Cypress CY7C1312AV18 18-mb qdr-ii sram 2-word burst architecture Datasheet

CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
18-Mb QDR™-II SRAM 2-Word Burst Architecture
Features
Functional Description
• Separate independent Read and Write data ports
— Supports concurrent transactions
• 167-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate (DDR) interfaces on both Read and
Write ports (data transferred at 333 MHz) @ 167MHz
• Two input clocks (K and K) for precise DDR timing
— SRAM uses rising edges only
• Two output clocks (C and C) account for clock skew
and flight time mismatching
• Echo clocks (CQ and CQ) simplify data capture in high
speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x18, and x36 configurations
• Full data coherancy , providing most current data
• Core Vdd=1.8V(+/-0.1V);I/O Vddq=1.4V to Vdd
• 13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball
(11x15 matrix)
• Variable drive HSTL output buffers
• JTAG 1149.1 compatible test access port
• Delay Lock Loop (DLL) for accurate data placement
Configurations
CY7C1310AV18 – 2M x 8
CY7C1312AV18 – 1M x 18
CY7C1314AV18 – 512K x 36
The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are
1.8V Synchronous Pipelined SRAMs, equipped with QDR-II
architecture. QDR-II architecture consists of two separate
ports to access the memory array. The Read port has
dedicated Data Outputs to support Read operations and the
Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data
outputs to completely eliminate the need to “turn-around” the
data bus required with common I/O devices. Access to each
port is accomplished through a common address bus. The
Read address is latched on the rising edge of the K clock and
the Write address is latched on the rising edge of the K clock.
Accesses to the QDR-II Read and Write ports are completely
independent of one another. In order to maximize data
throughput, both Read and Write ports are equipped with
Double Data Rate (DDR) interfaces. Each address location is
associated with two 8-bit words (CY7C1310AV18) or 18-bit
words (CY7C1312AV18) or 36-bit words (CY7C1314AV18)
that burst sequentially into or out of the device. Since data can
be transferred into and out of the device on every rising edge
of both input clocks (K and K and C and C), memory bandwidth
is maximized while simplifying system design by eliminating
bus “turn-arounds.”
Depth expansion is accomplished with Port Selects for each
port. Port selects allow each port to operate independently.
All synchronous inputs pass through input registers controlled
by the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Logic Block Diagram (CY7C1310AV18)
Write Add. Decode
20
K
K
CLK
Gen.
DOFF
VREF
WPS
BWS[1:0]
Write
Reg
1M x 8 Array
Address
Register
Write
Reg
1M x 8 Array
A(19:0)
8
Address
Register
Read Add. Decode
D[7:0]
RPS
Control
Logic
C
C
Read Data Reg.
16
8
Reg.
8
8
Reg.
8
Cypress Semiconductor Corporation
Document #: 38-05497 Rev. *A
•
3901 North First Street
•
CQ
CQ
8
Reg.
Control
Logic
A(19:0)
20
Q[7:0]
San Jose, CA 95134
•
408-943-2600
Revised June 1, 2004
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Logic Block Diagram (CY7C1312AV18)
D[17:0]
K
K
CLK
Gen.
DOFF
BWS[1:0]
RPS
Control
Logic
C
C
CQ
CQ
18
Reg.
Control
Logic
A(18:0)
19
Read Data Reg.
36
VREF
WPS
Address
Register
Read Add. Decode
19
Write
Reg
512K x 18 Array
A(18:0)
Write
Reg
512K x 18 Array
Address
Register
Write Add. Decode
18
18
Reg.
18
18
Reg.
Q[17:0]
18
Logic Block Diagram (CY7C1314AV18)
D[35:0]
CLK
Gen.
DOFF
VREF
WPS
BWS[3:0]
Address
Register
Read Add. Decode
K
K
Write Add. Decode
18
Write
Reg
256K x 36 Array
Address
Register
Write
Reg
256K x 36 Array
A(17:0)
36
18
RPS
Control
Logic
C
C
Read Data Reg.
72
36
CQ
CQ
36
Reg.
Control
Logic
A(17:0)
Reg.
36
Reg.
36
36
Q[35:0]
Selection Guide
167 MHz
133 MHz
Unit
Maximum Operating Frequency
167
133
MHz
Maximum Operating Current
800
700
mA
Document #: 38-05497 Rev. *A
Page 2 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Pin Configurations
CY7C1310AV18 (2M × 8) – 11 × 15 BGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
CQ
NC
VSS/72M
A
NC
NC
NC
NC
NC
D4
NC
NC
NC
Q4
VDDQ
NC
NC
NC
VDDQ
NC
DOFF
NC
D5
VREF
NC
Q5
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
NC
NC
NC
VDDQ
VDD
4
NC
8
9
10
11
RPS
A
A
VSS/36M
CQ
NC
NC
Q3
VSS
VSS
NC
NC
NC
D3
NC
VSS
VDDQ
NC
D2
Q2
VDDQ
VDDQ
VDDQ
VDDQ
NC
NC
VDDQ
NC
NC
VSS
VSS
VSS
VDD
VDD
VDD
VDD
NC
VREF
Q1
NC
NC
ZQ
D1
VSS
VDD
VDDQ
NC
NC
NC
5
6
7
K
NC/144M
K
A
VSS
BWS0
A
VSS
VSS
VSS
VDD
VSS
WPS
A
BWS1
NC/288M
VSS
VSS
VSS
A
NC
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
NC
NC
NC
D7
NC
NC
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
NC
NC
D0
NC
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1312AV18 (1M × 18) – 11 × 15 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
VSS/144M NC/36M
4
5
6
7
K
NC/288M
8
9
10
11
VSS/72M
CQ
BWS0
RPS
A
A
NC
NC
Q8
A
VSS
VSS
VSS
NC
Q7
NC
D8
D7
WPS
A
BWS1
NC
VSS
VSS
VSS
K
A
VSS
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
Q13
VDDQ
D14
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
VDDQ
NC
NC
VREF
Q4
D5
ZQ
D4
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
NC
NC
NC
D17
D16
Q16
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
NC
NC
Q1
NC
D2
D1
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CQ
NC
Q9
D9
NC
D11
Q10
NC
NC
NC
Q12
NC
DOFF
NC
D13
VREF
NC
NC
NC
NC
Document #: 38-05497 Rev. *A
D10
A
NC
Page 3 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Pin Configurations (continued)
CY7C1314AV18 (512k × 36) – 11 × 15 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
Q27
D27
D28
2
3
4
VSS/288M NC/72M
Q18
D18
Q28
D20
Q19
D19
WPS
A
VSS
VSS
5
6
7
BWS2
K
BWS1
BWS3
A
K
A
VSS
BWS0
A
VSS
VSS
8
RPS
A
9
10
11
NC/36M VSS/144M
CQ
D17
Q17
Q8
D16
Q7
D15
D8
D7
VSS
VSS
Q16
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
D30
DOFF
D31
D22
VREF
Q31
Q22
VDDQ
D23
VDDQ
VDDQ
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
Q13
VDDQ
D12
D13
VREF
Q4
D5
ZQ
D4
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
D33
D34
Q34
D26
D25
Q25
VSS
VSS
VSS
A
VSS
A
VSS
A
VSS
VSS
D10
Q10
Q1
D9
D2
D1
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
InputSynchronous
Data input signals, sampled on the rising edge of K and K clocks during valid write
operations.
CY7C1310AV18 - D[7:0]
CY7C1312AV18 - D[17:0]
CY7C1314AV18 - D[35:0]
WPS
InputSynchronous
Write Port Select, active LOW. Sampled on the rising edge of the K clock. When
asserted active, a write operation is initiated. Deasserting will deselect the Write port.
Deselecting the Write port will cause D[x:0] to be ignored.
BWS0, BWS1,
BWS2, BWS3
InputSynchronous
Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and
K clocks during write operations. Used to select which byte is written into the device
during the current portion of the write operations. Bytes not written remain unaltered.
CY7C1310AV18 − BWS0 controls D[3:0] and BWS1 controls D[7:4].
CY7C1312AV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1314AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]
and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte
Write Select will cause the corresponding byte of data to be ignored and not written into
the device.
A
InputSynchronous
Address Inputs. Sampled on the rising edge of the K (read address) and K (write
address) clocks during active read and write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8
(2 arrays each of 1M x 8) for CY7C1310AV18, 1M x 18 (2 arrays each of 512K x 18) for
CY7C1312AV18 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314AV18.
Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1310AV18, 19 address inputs for CY7C1312AV18 and 18 address inputs for
CY7C1314AV18. These inputs are ignored when the appropriate port is deselected.
Document #: 38-05497 Rev. *A
Page 4 of 21
PRELIMINARY
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
Pin Definitions (continued)
I/O
Pin Description
Q[x:0]
Pin Name
OutputsSynchronous
Data Output signals. These pins drive out the requested data during a Read operation.
Valid data is driven out on the rising edge of both the C and C clocks during Read
operations or K and K when in single clock mode. When the Read port is deselected,
Q[x:0] are automatically tri-stated.
CY7C1310AV18 − Q[7:0]
CY7C1312AV18 − Q[17:0]
CY7C1314AV18 − Q[35:0]
RPS
InputSynchronous
Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).
When active, a Read operation is initiated. Deasserting will cause the Read port to be
deselected. When deselected, the pending access is allowed to complete and the output
drivers are automatically tri-stated following the next rising edge of the C clock. Each
read access consists of a burst of two sequential transfers.
C
Input-Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
C
Input-Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various
devices on the board back to the controller. See application example for further details.
K
Input-Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs
to the device and to drive out data through Q[x:0] when in single clock mode. All accesses
are initiated on the rising edge of K.
K
Input-Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented
to the device and to drive out data through Q[x:0] when in single clock mode.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
CQ
Echo Clock
CQ is referenced with respect to C. This is a free running clock and is synchronized
to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with
respect to K. The timings for the echo clocks are shown in the AC timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the
system data bus impedance. CQ,CQ and Q[x:0] output impedance are set to 0.2 x RQ,
where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to VDD, which enables the minimum impedance mode. This pin cannot
be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off – Active LOW. Connecting this pin to ground will turn off the DLL inside
the device. The timings in the DLL turned off operation will be different from those listed
in this data sheet. More details on this operation can be found in the application note,
“DLL Operation in the QDR-II.”
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/36M
N/A
Address expansion for 36M. This is not connected to the die and so can be tied to any
voltage level.
NC/72M
N/A
Address expansion for 72M. This is not connected to the die and so can be tied to any
voltage level.
VSS/72M
Input
Address expansion for 72M. This must be tied LOW on the 18M devices.
VSS/144M
Input
Address expansion for 144M. This must be tied LOW on the 18M devices.
VSS/288M
Input
Address expansion for 288M. This must be tied LOW on the 18M devices.
Document #: 38-05497 Rev. *A
Page 5 of 21
PRELIMINARY
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
Pin Definitions (continued)
Pin Name
I/O
VREF
InputReference
VDD
Power Supply
VSS
VDDQ
Ground
Power Supply
Pin Description
Reference Voltage Input. Static input used to set the reference level for HSTL inputs
and Outputs as well as AC measurement points.
Power supply inputs to the core of the device.
Ground for the device.
Power supply inputs for the outputs of the device.
Introduction
Functional Overview
The CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 are
synchronous pipelined Burst SRAMs equipped with both a
Read port and a Write port. The Read port is dedicated to
Read operations and the Write port is dedicated to Write
operations. Data flows into the SRAM through the Write port
and out through the Read Port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate Read and Write ports, the QDR-II
completely eliminates the need to “turn-around” the data bus
and avoids any possible data contention, thereby simplifying
system design. Each access consists of two 8-bit data
transfers in the case of CY7C1310AV18, two 18-bit data
transfers in the case of CY7C1312AV18 and two 36-bit data
transfers in the case of CY7C1314AV18, in one clock cycles.
Accesses for both ports are initiated on the rising edge of the
positive Input Clock (K). All synchronous input timings are
referenced from the rising edge of the input clocks (K and K)
and all output timings are referenced to the rising edge of
output clocks (C and C or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) inputs pass through input
registers controlled by the input clocks (K and K). All
synchronous data outputs (Q[x:0]) outputs pass through output
registers controlled by the rising edge of the output clocks (C
and C or K and K when in single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the
input clocks (K and K).
CY7C1312AV18 is described in the following sections. The
same basic descriptions apply to CY7C1310AV18 and
CY7C1314AV18.
Read Operations
The CY7C1312AV18 is organized internally as two arrays of
512Kx18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the Positive Input Clock (K).
The address is latched on the rising edge of the K Clock. The
address presented to Address inputs is stored in the Read
address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto
the Q[17:0]. The requested data will be valid 0.45 ns from the
rising edge of the output clock (C and C or K and K when in
single clock mode).
Synchronous internal circuitry will automatically tri-state the
outputs following the next rising edge of the Output Clocks
(C/C). This will allow for a seamless transition between
Document #: 38-05497 Rev. *A
devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the Positive Input Clock (K). On the same K
clock rise, the data presented to D[17:0] is latched and stored
into the lower 18-bit Write Data register provided BWS[1:0] are
both asserted active. On the subsequent rising edge of the
Negative Input Clock (K), the address is latched and the information presented to D[17:0] is stored into the Write Data
Register provided BWS[1:0] are both asserted active. The 36
bits of data are then written into the memory array at the
specified location. When deselected, the write port will ignore
all inputs after the pending Write operations have been
completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1312AV18.
A write operation is initiated as described in the Write
Operation section above. The bytes that are written are determined by BWS0 and BWS1 which are sampled with each 18-bit
data word. Asserting the appropriate Byte Write Select input
during the data portion of a write will allow the data being
presented to be latched and written into the device.
Deasserting the Byte Write Select input during the data portion
of a write will allow the data stored in the device for that byte
to remain unaltered. This feature can be used to simplify
Read/Modify/Write operations to a Byte Write operation.
Single Clock Mode
The CY7C1312AV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device will recognize only a single pair of input clocks (K and
K) that control both the input and output registers. This
operation is identical to the operation if the device had zero
skew between the K/K and C/C clocks. All timing parameters
remain the same in this mode. To use this mode of operation,
the user must tie C and C HIGH at power on. This function is
a strap option and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1312AV18 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user
can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started
in the same clock cycle. If the ports access the same location
at the same time, the SRAM will deliver the most recent information associated with the specified address location. This
includes forwarding data from a Write cycle that was initiated
on the previous K clock rise.
Page 6 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Depth Expansion
Echo Clocks
The CY7C1312AV18 has a Port Select input for each port.
This allows for easy depth expansion. Both Port Selects are
sampled on the rising edge of the Positive Input Clock only (K).
Each port select input can deselect the specified port.
Deselecting a port will not affect the other port. All pending
transactions (Read and Write) will be completed prior to the
device being deselected.
Echo clocks are provided on the QDR-II to simplify data
capture on high-speed systems. Two echo clocks are
generated by the QDR-II. CQ is referenced with respect to C
and CQ is referenced with respect to C. These are
free-running clocks and are synchronized to the output
clock(C/C) of the QDR-II. In the single clock mode, CQ is
generated with respect to K and CQ is generated with respect
to K. The timings for the echo clocks are shown in the AC
Timing table.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ
pin on the SRAM and VSS to allow the SRAM to adjust its
output driver impedance. The value of RQ must be 5x the
value of the intended line impedance driven by the SRAM. The
allowable range of RQ to guarantee impedance matching with
a tolerance of ±15% is between 175Ω and 350Ω, with
VDDQ = 1.5V.The output impedance is adjusted every 1024
cycles upon powerup to account for drifts in supply voltage and
temperature.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed
to function between 80 MHz and the specified maximum clock
frequency. The DLL may be disabled by applying ground to the
DOFF pin. The DLL can also be reset by slowing the cycle time
of input clocks K and K to greater than 30 ns.
\
Application Example[1]
SRAM #1
Vt
D
A
R
R
P
S
#
W
P
S
#
B
W
S
#
R = 250ohms
ZQ
CQ/CQ#
Q
C C# K K#
SRAM #4
R
P
S
#
D
A
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
R
W
P
S
#
B
W
S
#
ZQ R = 250ohms
CQ/CQ#
Q
C C# K K#
Vt
Vt
Delayed K
Delayed K#
R
R = 50ohms Vt = Vddq/2
Truth Table[ 2, 3, 4, 5, 6, 7]
Operation
K
RPS
WPS
Write Cycle:
Load address on the rising edge of K clock; input write data
on K and K rising edges.
L-H
X
L
D(A + 0)at K(t) ↑
Read Cycle:
Load address on the rising edge of K clock; wait one and a
half cycle; read data on C and C rising edges.
L-H
L
X
Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑
NOP: No Operation
L-H
H
H
D=X
Q=High-Z
D=X
Q=High-Z
Stopped
X
X
Previous State
Previous State
Standby: Clock Stopped
DQ
DQ
D(A + 1) at K(t) ↑
Notes:
1. The above application shows 4 QDRII being used.
2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a
write cycle, as long as the set-up and hold requirements are achieved.
Document #: 38-05497 Rev. *A
Page 7 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Write Cycle Descriptions (CY7C1310AV18 and CY7C1312AV18) [2, 8]
BWS0 BWS1
K
K
–
L
L
L-H
L
L
–
L
H
L-H
L
H
–
H
L
L-H
H
L
–
H
H
L-H
H
H
–
Comments
During the Data portion of a Write sequence :
CY7C1310AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1312AV18 − both bytes (D[17:0]) are written into the device.
L-H During the Data portion of a Write sequence :
CY7C1310AV18 − both nibbles (D[7:0]) are written into the device,
CY7C1312AV18 − both bytes (D[17:0]) are written into the device.
During the Data portion of a Write sequence :
CY7C1310AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1312AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
–
L-H During the Data portion of a Write sequence :
CY7C1310AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,
CY7C1312AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.
During the Data portion of a Write sequence :
CY7C1310AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,
CY7C1312AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.
–
L-H During the Data portion of a Write sequence :
CY7C1310AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,
CY7C1312AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.
–
No data is written into the devices during this portion of a write operation.
L-H No data is written into the devices during this portion of a write operation.
Write Cycle Descriptions (CY7C1314AV18) [2, 8]
BWS0 BWS1 BWS2 BWS3
K
K
Comments
L
L
L
L
L-H
-
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
-
L-H
During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
H
L-H
-
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
L
H
H
H
-
L-H
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] will remain unaltered.
H
L
H
H
L-H
-
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H
L
H
H
-
L-H
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] will remain unaltered.
H
H
L
H
L-H
-
During the Data portion of a Write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] will remain unaltered.
H
H
L
H
-
L-H
During the Data portion of a Write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] will remain unaltered.
H
H
H
L
L-H
H
H
H
L
-
L-H
H
H
H
H
L-H
-
No data is written into the device during this portion of a write operation.
H
H
H
H
-
L-H
No data is written into the device during this portion of a write operation.
Document #: 38-05497 Rev. *A
During the Data portion of a Write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] will remain unaltered.
During the Data portion of a Write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] will remain unaltered.
Page 8 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which useful life may be impaired.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
DC Voltage Applied to Outputs
in High-Z State .................................... –0.5V to VDDQ + 0.5V
DC Input Voltage[12] ............................ –0.5V to VDDQ + 0.5V
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Com’l
Ambient
Temperature(TA)
VDD[14]
VDDQ[14]
0°C to +70°C
1.8 ± 0.1 V
1.4V to VDD
DC Electrical Characteristics Over the Operating Range[9,14]
Parameter
Description
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
VOL
VOH(LOW)
Test Conditions
Min.
Typ.
Max.
Unit
1.7
1.8
1.9
V
1.4
1.5
VDD
V
[10]
VDDQ/2 –0.12
VDDQ/2 + 0.12
V
Output LOW Voltage
[11]
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
Output HIGH Voltage
IOH = −0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VREF + 0.1
VDDQ+0.3
V
VOL(LOW)
Output LOW Voltage
VIH
Input HIGH Voltage[12]
VIL
Input LOW Voltage[12, 13]
–0.3
VREF – 0.1
V
VIN
Clock Input Voltage
–0.3
VDDQ + 0.3
V
−5
5
µA
−5
5
µA
GND ≤ VI ≤ VDDQ
IX
Input Load Current
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
VREF
Input Reference Voltage[15]
Typical Value = 0.75V
0.95
V
IDD
VDD Operating Supply
VDD = Max., IOUT = 0 mA, 133 MHz
f = fMAX = 1/tCYC
167 MHz
700
mA
800
mA
ISB1
Automatic
Power-down Current
Max. VDD, Both Ports
133 MHz
Deselected, VIN ≥ VIH or 167 MHz
VIN ≤ VIL f = fMAX = 1/tCYC,
Inputs Static
450
mA
470
mA
0.68
0.75
AC Electrical Characteristics Over the Operating Range
Min.
Typ.
Max.
Unit
VIH
Parameter
Input High (Logic 1) Voltage
Description
Test Conditions
VREF + 0.2
–
–
V
VIL
Input Low (Logic 0) Voltage
–
–
VREF – 0.2
V
Notes:
9. All Voltage referenced to Ground.
10. Output are impedance controlled. Ioh=-(Vddq/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
11. Output are impedance controlled. Iol=(Vddq/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
12. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > -1.5V (Pulse width less than tCYC/2).
13. This spec is for all inputs except C and C clocks. For C and C clocks, VIL(Max.) = VREF – 0.2V.
14. Power-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD
15. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
Document #: 38-05497 Rev. *A
Page 9 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Switching Characteristics Over the Operating Range[16,17]
Cypress
Parameter
Consortium
167 MHz
Parameter
Description
133 MHz
Min.
Max.
Min.
Max.
Unit
tCYC
tKHKH
K Clock and C Clock Cycle Time
6.0
7.9
7.5
8.4
ns
tKH
tKHKL
Input Clock (K/K and C/C) HIGH
2.4
–
3.0
–
ns
tKL
tKLKH
Input Clock (K/K and C/C) LOW
2.4
–
3.0
–
ns
tKHKH
tKHKH
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising
edge to rising edge)
2.7
–
3.38
–
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
0.0
2.8
0.0
3.55
ns
Set-up Times
tSA
tSA
Address Set-up to K Clock Rise
0.5
–
0.5
–
ns
tSC
tSC
Control Set-up to Clock (K, K) Rise (RPS, WPS)
0.5
–
0.5
–
ns
tSCDDR
tSC
Double Data Rate Control Set-up to Clock (K, K) Rise
(BWS0, BWS1, BWS3, BWS4)
0.5
–
0.5
–
ns
tSD
tSD
D[X:0] Set-up to Clock (K and K) Rise
0.5
–
0.5
–
ns
Hold Times
tHA
tHA
Address Hold after Clock (K and K) Rise
0.5
–
0.5
–
ns
tHC
tHC
Control Hold after Clock (K and K) Rise (RPS, WPS)
0.5
–
0.5
–
ns
tHCDDR
tHC
Double Data Rate Control Hold after Clock (K and K) Rise
(BWS0, BWS1 , BWS3, BWS4)
0.5
–
0.5
–
ns
tHD
tHD
D[X:0] Hold after Clock (K and K) Rise
0.5
–
0.5
–
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise (Active to
Active)
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
–
0.50
–
0.50
ns
–0.50
–
–0.50
–
ns
–
0.50
–
0.50
ns
–0.50
–
–0.50
–
ns
–
0.40
–
0.40
ns
–0.40
–
–0.40
–
ns
–
0.50
–
0.50
ns
–0.50
–
–0.50
–
ns
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock Rise
tCQD
tCQHQV
Echo Clock High to Data Valid
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
tCHZ
tCHZ
Clock (C and C) Rise to High-Z (Active to High-Z)[18,19]
tCLZ
tCLZ
Clock (C and C) Rise to Low-Z[18,19]
tKC Var
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
ns
tKC lock
tKC lock
DLL Lock Time (K, C)
1024
–
1024
-
cycl
es
tKC Reset
tKC Reset
K Static to DLL Reset
30
DLL Timing
30
ns
Thermal Resistance[20]
Parameter
ΘJA
ΘJC
Description
Test Conditions
Thermal Resistance Test conditions follow standard test methods and
(Junction to Ambient) procedures for measuring thermal impedence, per
Thermal Resistance EIA / JESD51.
(Junction to Case)
165 FBGAPackage
Unit
16.7
°C/W
2.5
°C/W
Notes:
16. All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequncy,
it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.
17. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.
18. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
19. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document #: 38-05497 Rev. *A
Page 10 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Capacitance[20]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CO
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 1.8V
VDDQ = 1.5V
Max.
Unit
5
pF
6
pF
7
pF
AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
ZQ
RL = 50Ω
VREF = 0.75V
RQ =
250Ω
(a)
0.75V
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under ZQ
Test
INCLUDING
JIG AND
SCOPE
5 pF
0.25V
[12]
Slew Rate = 2V / ns
RQ =
250Ω
(b)
Note:
20. Tested initially and after any design or process change that may affect these parameters.
Document #: 38-05497 Rev. *A
Page 11 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Switching Waveforms[21,22,23]
Read/Write/Deselect Sequence
READ
WRITE
1
READ
2
WRITE
3
4
READ
WRITE
6
5
NOP
7
WRITE
NOP
8
9
10
Q40
Q41
K
tKH
tKL
tCYC
tKHKH
K
RPS
tSC
tHC
WPS
A
A0
A1
tSA
D
D10
tHA
A3
A4
A5
D31
D50
D51
A2
tSA
D11
tHA
D30
tSD
tCLZ
C
tKL
D60
tSD
tHD
Q
tKHCH
A6
Q00
Q01
tDOH
tDOH
tCO
D61
tHD
Q20
Q21
tCHZ
tCQD
tCO
tKH
tKHCH
tKHKH
t CYC
C
tCCQO
tCQOH
CQ
tCCQO
tCQOH
CQ
DON’T CARE
UNDEFINED
Notes:
21. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0+1.
22. Output are disabled (High-Z) one clock cycle after a NOP.
23. In this example , if address A2=A1,then data Q20=D10 and Q21=D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.,
Document #: 38-05497 Rev. *A
Page 12 of 21
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant
with IEEE Standard #1149.1-1900. The TAP operates using
JEDEC standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Test Access Port–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see Instruction codes). The
output changes on the falling edge of TCK. TDO is connected
to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
Document #: 38-05497 Rev. *A
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
TDI and TDO pins as shown in TAP Controller Block Diagram.
Upon power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and
Output ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instructions are described in detail below.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
Page 13 of 21
PRELIMINARY
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE / PRELOAD is a 1149.1 mandatory instruction.
When the SAMPLE / PRELOAD instructions are loaded into
the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins
is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will
undergo a transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not harm the
device, but there is no guarantee as to the value that will be
captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE / PRELOAD instruction. If
this is an issue, it is still possible to capture all other signals
and simply ignore the value of the CK and CK# captured in the
boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation.
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the "extest output bus tristate", is
latched into the preload register during the "Update-DR" state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the "Shift-DR" state. During "Update-DR", the
value loaded into that shift-register cell will latch into the
preload register. When the EXTEST instruction is entered, this
bit will directly control the output Q-bus pins. Note that this bit
is pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
"Test-Logic-Reset" state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05497 Rev. *A
Page 14 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
TAP Controller State Diagram[24]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
SELECT
DR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
SHIFT-IR
0
1
1
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
SELECT
IR-SCAN
0
UPDATE-IR
1
0
Note:
24. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05497 Rev. *A
Page 15 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30 29
.
.
2
Identification Register
106 .
.
.
.
2
1
0
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics Over the Operating Range[9,12,25]
Parameter
Description
Test Conditions
Min.
Max.
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 µA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 µA
0.2
V
VIH
Input HIGH Voltage
0.65VDD
VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.35VDD
V
IX
Input and OutputLoad Current
GND ≤ VI ≤ VDD
−5
5
Note:
25. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
Document #: 38-05497 Rev. *A
µA
Page 16 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[26, 27]
Parameter
Description
Min.
Max.
Unit
10
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
40
ns
tTL
TCK Clock LOW
40
ns
100
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
10
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
ns
tCS
Capture Set-up to TCK Rise
10
ns
tTMSH
TMS Hold after TCK Clock Rise
10
ns
tTDIH
TDI Hold after Clock Rise
10
ns
tCH
Capture Hold after Clock Rise
10
ns
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
20
0
ns
ns
TAP Timing and Test Conditions[27]
0.9V
50Ω
ALL INPUT PULSES
TDO
1.8V
Z0 = 50Ω
0.9V
CL = 20 pF
0V
GND
tTH
tTL
(a)
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
26. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
27. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05497 Rev. *A
Page 17 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Identification Register Definitions
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
2M x 8
1M x 18
512K x 36
000
000
000
Instruction Field
Revision Number (31:29)
Description
Version number.
Cypress Device ID (28:12) 11010011010000101 11010011010010101 11010011010100101 Defines the type of SRAM.
Cypress JEDEC ID (11:1)
00000110100
00000110100
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
1
Indicates the presence of an
ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
107
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Boundary Scan Order
Boundary Scan Order (continued)
Bit #
Bump ID
Bit #
Bump ID
0
6R
15
9M
1
6P
16
9N
2
6N
17
11L
3
7P
18
11M
4
7N
19
9L
5
7R
20
10L
6
8R
21
11K
7
8P
22
10K
8
9R
23
9J
9
11P
24
9K
10
10P
25
10J
11
10N
26
11J
12
9P
27
11H
13
10M
28
10G
14
11N
29
9G
Document #: 38-05497 Rev. *A
Page 18 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Boundary Scan Order (continued)
Boundary Scan Order (continued)
Bit #
Bump ID
Bit #
Bump ID
30
11F
74
2D
31
11G
75
2E
32
9F
76
1E
33
10F
77
2F
34
11E
78
3F
35
10E
79
1G
36
10D
80
1F
37
9E
81
3G
38
10C
82
2G
39
11D
83
1J
40
9C
84
2J
41
9D
85
3K
42
11B
86
3J
43
11C
87
2K
44
9B
88
1K
45
10B
89
2L
46
11A
90
3L
47
Internal
91
1M
48
9A
92
1L
49
8B
93
3N
50
7C
94
3M
51
6C
95
1N
52
8A
96
2M
53
7A
97
3P
54
7B
98
2N
55
6B
99
2P
56
6A
100
1P
57
5B
101
3R
58
5A
102
4R
59
4A
103
4P
60
5C
104
5P
61
4B
105
5N
62
3A
106
5R
63
1H
64
1A
65
2B
66
3B
67
1C
68
1B
69
3D
70
3C
71
1D
72
2C
73
3E
Document #: 38-05497 Rev. *A
Page 19 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Ordering Information
Speed
(MHz)
167
Ordering Code
CY7C1310AV18-167BZC
Package
Name
Operating
Range
Package Type
BB165D
13 x 15 x 1.4 mm FBGA
Commercial
BB165D
13 x 15 x 1.4 mm FBGA
Commercial
CY7C1312AV18-167BZC
CY7C1314AV18-167BZC
133
CY7C1310AV18-133BZC
CY7C1312AV18-133BZC
CY7C1314AV18-133BZC
Package Diagram
165 FBGA 13 x 15 x 1.40 mm BB165D
51-85180-**
QDR SRAMs and Quad Data Rate SRAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC and
Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05497 Rev. *A
Page 20 of 21
CY7C1310AV18
CY7C1312AV18
CY7C1314AV18
PRELIMINARY
Document History Page
Document Title: CY7C1310AV18/CY7C1312AV18/CY7C1314AV18 18-Mb QDR™-II SRAM 2-Word Burst Architecture
Document Number: 38-05497
Issue Date
Orig. of
Change
REV.
ECN No.
**
208405
see ECN
DIM
New Data Sheet
*A
230396
see ECN
VBL
Upload datasheet to the internet
Document #: 38-05497 Rev. *A
Description of Change
Page 21 of 21