GSI GS8182S18GD-267I 18mb burst of 2 ddr sigmasio-ii sram Datasheet

GS8182S18D-267/250/200/167
18Mb Burst of 2
DDR SigmaSIO-II SRAM
165-Bump BGA
Commercial Temp
Industrial Temp
267 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
routed internally to fire the output registers instead. Each Burst
of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,
CQ and CQ, which are synchronized with read data output.
When used in a source synchronous clocking scheme, the Echo
Clock outputs can be used to fire input registers at the data’s
destination.
SigmaRAM™ Family Overview
GS8182S18 are built in compliance with the SigmaSIO-II
SRAM pinout standard for Separate I/O synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. These are the first in
a family of wide, very low voltage HSTL I/O SRAMs designed
to operate at the speeds needed to implement economical high
performance networking systems.
Because Separate I/O Burst of 2 RAMs always transfer data in
two packets, A0 is internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a Burst of 2 RAM is always one address pin less than
the advertised index depth (e.g., the 1M x 18 has a 512K
addressable index).
Clocking and Addressing Schemes
A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It
employs dual input register clock inputs, K and K. The device
also allows the user to manipulate the output register clock
input quasi independently with dual output register clock
inputs, C and C. If the C clocks are tied high, the K clocks are
Parameter Synopsis
Rev: 1.08a 8/2005
-267
-250
-200
-167
tKHKH
3.75 ns
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.45 ns
0.45 ns
0.5 ns
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
1M x 18 SigmaQuad SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
CQ
VSS/SA
(144Mb)
NC/SA
(36Mb)
R/W
BW1
K
NC
LD
SA
VSS/SA
(72Mb)
CQ
B
NC
Q9
D9
SA
NC
K
BW0
SA
NC
NC
Q8
C
NC
NC
D10
VSS
SA
SA
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 1.08a 8/2005
2/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
NC
No Connect
—
—
R/W
Synchronous Read/Write
Input
BW0–BW1
Synchronous Byte Writes
Input
Active Low
K
Input Clock
Input
Active High
C
Output Clock
Input
Active High
TMS
Test Mode Select
Input
—
TDI
Test Data Input
Input
—
TCK
Test Clock Input
Input
—
TDO
Test Data Output
Output
—
VREF
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
K
Input Clock
Input
Active Low
C
Output Clock
Output
Active Low
DOFF
DLL Disable
—
Active Low
LD
Synchronous Load Pin
—
Active Low
CQ
Output Echo Clock
Output
Active Low
CQ
Output Echo Clock
Output
Active High
D
Synchronous Data Inputs
Input
Q
Synchronous Data Outputs
Output
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
—
Notes:
1. C, C, K, or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDD, output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. NC = Not Connected to die or any other pin
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the
other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are
needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a
separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control
protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at
the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write
addresses like SigmaCIO SRAMs, but in a separate I/O configuration.
Rev: 1.08a 8/2005
3/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Like a SigmaQuad SRAM, a SigmaSIO-II SRAM can execute an alternating sequence of reads and writes. However, doing so
results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep
both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands
and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from
loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random
address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs
offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore,
SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two
electrically independent busses is desired.
Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaCIO, and SigmaSIO—supports similar address rates because
random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are
based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how
the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to
the application at hand.
Burst of 2 SigmaSIO-II SRAM DDR Read
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on
the R/W pin begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C
are tied high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high).
SigmaSIO-II Double Data Rate SRAM Read First
Read A
Write B
Read C
Write D
NOP
Read E
Read F
NOP
K
K
Address
A
B
C
D
E
F
LD
R/W
BWx
B
B+1
D
D+1
D
B
B+1
D
D+1
C
C
Q
A
A+1
C
C+1
E
E+1
F
CQ
CQ
Rev: 1.08a 8/2005
4/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Burst of 2 SigmaSIO-II SRAM DDR Write
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the
R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.
SigmaSIO-II Double Data Rate SRAM Write First
Write A
Read B
NOP
Read C
Write D
NOP
Read E
Read F
NOP
K
K
Address
A
B
C
D
E
F
LD
R/W
BWx
A
A+1
D
D+1
D
A
A+1
D
D+1
C
C
Q
B
B+1
C
C+1
E
E+1
F
CQ
CQ
Rev: 1.08a 8/2005
5/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample
Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Resulting Write Operation
Beat 1
Beat 2
D0–D8
D9–D17
D0–D8
D9–D17
Written
Unchanged
Unchanged
Written
Output Register Control
SigmaSIO-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output
Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the
output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K
and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.
Rev: 1.08a 8/2005
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Example Four Bank Depth Expansion Schematic
R3
W3
R2
W2
R1
W1
R0
W0
A0–An
K
D1–Dn
Bank 0
Bank 1
Bank 2
Bank 3
A
A
A
A
W
W
W
W
R
R
R
R
K
D
CQ
Q
C
K
D
CQ
Q
C
K
D
CQ
K
CQ
Q
D
Q
C
C
C
Q1–Qn
CQ0
CQ1
CQ2
CQ3
Note:
For simplicity BWn is not shown.
Rev: 1.08a 8/2005
7/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Burst of 2 SigmaSIO-II SRAM Depth Expansion
Write A
Read B
Write C
Read D
Write E
Read F
Read G
Read H
NOP
K
K
Address
A
B
C
D
E
F
G
H
LD(Bank_1)
LD(Bank_2)
R/W(Bank_1)
R/W(Bank_2)
BWx(Bank_1)
A
A+1
C
BWx(Bank_2)
D(Bank_1)
A
C
E+1
E
E+1
D
D+1
C+1
A+1
D(Bank_2)
E
C+1
C(Bank_1)
C(Bank_1)
Q(Bank_1)
G
CQ(Bank)1
CQ(Bank_1)
C(Bank_2)
C(Bank_2)
B
Q(Bank_2)
B+1
F
F+1
CQ(Bank_2)
CQ(Bank_2)
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the
value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a
vendor-specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the
impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts
in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets
and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum
level. The output driver is implemented with discrete binary weighted impedance steps.
Rev: 1.08a 8/2005
8/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Separate I/O Burst of 2 SigmaSIO-II SRAM Truth Table
A
LD
R/W
Current
Operation
D
D
Q
Q
K↑
(tn)
K↑
(tn)
K↑
(tn)
K↑
(tn)
K↑
(tn+1)
K↑
(tn+1)
K↑
(tn+1)
K↑
(tn+1)
X
1
X
Deselect
X
—
Hi-Z
—
V
0
1
Read
X
—
Q0
Q1
V
0
0
Write
D0
D1
Hi-Z
—
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
4. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
5. Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when preceded by a Read command.
6. CQ is never tristated.
7. Users should not clock in metastable addresses.
Rev: 1.08a 8/2005
9/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
x18 Byte Write Clock Truth Table
BW
BW
Current Operation
D
D
K↑
(tn+1)
K↑
(tn+2)
K↑
(tn)
K↑
(tn+1)
K↑
(tn+2)
T
T
Write
Dx stored if BWn = 0 in both data transfers
D1
D2
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D1
X
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D2
F
F
Write Abort
No Dx stored in either data transfer
X
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
x18 Byte Write Enable (BWn) Truth Table
BW1 BW0
D9–D17
D0–D8
1
1
Don’t Care
Don’t Care
0
1
Don’t Care
Data In
1
0
Data In
Don’t Care
0
0
Data In
Data In
Rev: 1.08a 8/2005
10/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
State Diagram
Power-Up
LOAD
NOP
LOAD
Load New Address
LOAD
LOAD
LOAD
READ
WRITE
DDR Read
Rev: 1.08a 8/2005
LOAD
DDR Write
11/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 2.9
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
V
VREF
Voltage in VREF Pins
–0.5 to VDDQ
V
VI/O
Voltage on I/O Pins
–0.5 to VDDQ +0.3 (≤ 2.9 V max.)
V
VIN
Voltage on Other Input Pins
–0.5 to VDDQ +0.3 (≤ 2.9 V max.)
V
IIN
Input Current on Any Pin
+/–100
mA dc
IOUT
Output Current on Any I/O Pin
+/–100
mA dc
TJ
Maximum Junction Temperature
125
oC
TSTG
Storage Temperature
–55 to 125
o
C
TSUB
Storage Under Bias
–50 to 100
o
C
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Supply Voltage
VDD
1.7
1.8
1.95
V
1.5 V I/O Supply Voltage
VDDQ
1.4
1.5
1.65
V
1
1.8 V I/O Supply Voltage
VDDQ
1.7
1.8
1.95
V
1
Reference Voltage
VREF
0.68
—
0.95
V
1
Notes:
1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ VDDQ ≤ 1.6 V (i.e., 1.5 V I/O)
and 1.7 V ≤ VDDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.
2. The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The
power down sequence must be the reverse. VDDQ must not exceed VDD.
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
Ambient Temperature
(Commercial Range Versions)
TA
0
25
70
°C
2
Ambient Temperature
(Industrial Range Versions)
TA
–40
25
85
°C
2
Rev: 1.08a 8/2005
12/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
DC Input Logic High
VIH (dc)
VREF + 0.1
VDDQ + 0.3
mV
1
DC Input Logic Low
VIL (dc)
–0.3
VREF – 0.1
mV
1
Note:
Compatible with both 1.8 V and 1.5 V I/O drivers
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
AC Input Logic High
VIH (ac)
VREF + 0.2
—
mV
3,4
AC Input Logic Low
VIL (ac)
—
VREF – 0.2
mV
3,4
VREF (ac)
—
5% VREF (DC)
mV
1
VREF Peak to Peak AC Voltage
Notes:
1. The peak to peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
4. See AC Input Definition drawing below.
HSTL I/O AC Input Definitions
VIH (ac)
VREF
VIL (ac)
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKHKH
VDD + 1.0 V
VSS
50%
50%
VDD
VSS – 1.0 V
20% tKHKH
Rev: 1.08a 8/2005
VIL
13/31
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© 2003, GSI Technology
GS8182S18D-267/250/200/167
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Output Capacitance
COUT
VOUT = 0 V
6
7
pF
Notes
Note:
This parameter is sample tested.
AC Test Conditions
Parameter
Conditions
Input high level
VDDQ
Input low level
0V
Max. input slew rate
2 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
RQ = 250 Ω (HSTL I/O)
VREF = 0.75 V
50Ω
VT = VDDQ/2
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–2 uA
2 uA
Output Leakage Current
IOL
Output Disable,
VOUT = 0 to VDDQ
–2 uA
2 uA
Rev: 1.08a 8/2005
14/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
Min.
Max.
Units
Notes
Output High Voltage
VOH1
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
1, 3
Output Low Voltage
VOL1
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
2, 3
Output High Voltage
VOH2
VDDQ – 0.2
VDDQ
V
4, 5
Output Low Voltage
VOL2
Vss
0.2
V
4, 6
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175Ω ≤ RQ ≤ 350Ω).
3. Parameter tested with RQ = 250Ω and VDDQ = 1.5 V or 1.8 V
4. Minimum Impedance mode, ZQ = VSS
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Operating Currents
-267
-250
-200
-167
Parameter
Org
Symbol
0°C
to
70°C
–40°C
to
+85°C
0°C
to
70°C
–40°C
to
+85°C
0°C
to
70°C
–40°C
to
+85°C
0°C
to
70°C
–40°C
to
+85°C
Test Conditions
Operating
Current
x18
IDD
475 mA
485 mA
450 mA
460 mA
400 mA
410 mA
350 mA
360 mA
VDD =max.; IOUT = 0 mA;
Cycle Time ≥ tKHKH min.
Standby
Current (NOP)
x18
ISB1
230 mA
235 mA
220 mA
225 mA
205 mA
210 mA
195 mA
200 mA
Device deselected;
IOUT = 0 mA; f = max;
All inputs ≤ 0.2 V or ≥ VDD – 0.2 V
Notes:
1. Power measured with output pins floating.
2. All inputs (except ZQ, VREF) are held at either VIH or VIL.
3. Operating supply currents are measured at 100% buss utilization.
4. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed.
Rev: 1.08a 8/2005
15/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
AC Electrical Characteristics
Parameter
Symbol
-267
-250
-200
-167
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes
K Clock Cycle Time
C Clock Cycle Time
tKHKH
tCHCH
3.75
6.3
4.0
6.3
5.0
7.88
6.0
8.4
ns
K Clock High Pulse Width
C Clock High Pulse Width
tKHKL
tCHCL
1.6
—
1.6
—
2.0
—
2.4
—
ns
K Clock Low Pulse Width
C Clock Low Pulse Width
tKLKH
tCLCH
1.6
—
1.6
—
2.0
—
2.4
—
ns
Clock to Clock Delay
tKHKH
tCHCH
1.8
—
1.8
—
2.3
—
2.8
—
ns
Address Input Setup Time
tAVKH
0.5
—
0.5
—
0.6
—
0.7
—
ns
Address Input Hold Time
tKHAX
0.5
—
0.5
—
0.6
—
0.7
—
ns
Control Input Setup Time
tBVKH
0.5
—
0.5
—
0.6
—
0.7
—
ns
1
Control Input Hold Time
tKHBX
0.5
—
0.5
—
0.6
—
0.7
—
ns
1
Data and Byte Write Input Setup Time
tDVKH
0.35
—
0.35
—
0.4
—
0.5
—
ns
Data and Byte Write Input Hold Time
tKHDX
0.35
—
0.35
—
0.4
—
0.5
—
ns
K Clock High to Data Output Valid
C Clock High to Data Output Valid
tKHQV
tCHQV
—
0.45
—
0.45
—
0.45
—
0.5
ns
K Clock High to Data Output Hold
C Clock High to Data Output Hold
tKHQX
tCHQX
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
2
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
tKHQX1
tCHQX1
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
2,3
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
tKHQZ
tCHQZ
—
0.45
—
0.45
—
0.45
—
0.5
ns
2,3
K Clock High to CQ Clock High
C Clock High to CQ Clock High
tKHCQV
tCHCQV
—
0.45
—
0.45
—
0.45
—
0.5
ns
K Clock High to CQ Clock Hold
C Clock High to CQ Clock Hold
tKHCQX
tCHCQX
–0.45
—
–0.45
—
–0.45
—
–0.5
—
ns
2
CQ Clock High to Data Output Valid
tCQHQV
—
0.3
—
0.3
—
0.35
—
0.4
ns
2
CQ Clock High to Data Output Hold
tCQHQX
–0.3
—
–0.3
—
–0.35
—
–0.4
—
ns
2
Notes:
1. These parameters apply to control inputs R and W.
2. These parameters are guaranteed by design through extensive corner lot characterization.
3. These parameters are measured at ±50 mV from steady state voltage.
Rev: 1.08a 8/2005
16/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
K Controlled Read-First Timing Diagram
Read A
Write B
Read C
Read E
Deselect
Deselect
KHKL
KHKH
KLKH
K
KH#KH
K
AVKH
KHAX
Address
A
B
C
IVKH
KHIX
IVKH
KHIX
D
E
LD
R/W
IVKH
KHIX
B
BWx
B+1
DVKH
KHDX
B
D
B+1
KHQX1
A
Q
KHQZ
A+1
KHQV
C
C+1
KHQX
D
D+1
CQ
KHCQV
KHCQX
CQHQV
CQHQX
CQ
Rev: 1.08a 8/2005
17/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
K Controlled Write-First Timing Diagram
NOP
Write A
Read B
Read C
Write D
Write E
Deselect
KHKL
KHKH
KLKH
K
KH#KH
K
AVKH
KHAX
A
Address
IVKH
B
C
D
E
KHIX
LD
IVKH
KHIX
R/W
KHIX
IVKH
A
BWx
A+1
D
D+1
E
E+1
D
D+1
E
E+1
KHDX
DVKH
A
D
A+1
KHQV
KHQX1
B
Q
KHQX
B+1
C
KHQZ
C+1
KHCQX
KHCQV
CQ
KHCQX
KHCQV
CQHQX
CQHQV
CQ
Rev: 1.08a 8/2005
18/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
C Controlled Read-First Timing Diagram
Read A
Write B
Read C
Read D
Deselect
Deselect
KHKL
KHKH
KLKH
K
KHKH#
K
AVKH
KHAX
A
Address
B
C
D
IVKH
KHIX
LD
IVKH
KHIX
R/W
KHIX
IVKH
B
BWx
B+1
KHDX
DVKH
B
D
B+1
CLCH
KHCH
CHCL
CHCH
C
CHCH#
C
CHQX1
A
Q
CHQZ
A+1
CHQV
C
CHQX
C+1
D
D+1
CQ
CHCQX
CHCQV
CQHCV
CQHQX
CQ
Rev: 1.08a 8/2005
19/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
C Controlled Write-First Timing Diagram
NOP
Write A
Read B
Write C
Write D
Read E
Deselect
KHKL
KHKH
KLKH
K
KH#KH
K
KHAX
AVKH
A
Addr
IVKH
B
C
D
E
KHIX
LD
IVKH
KHIX
R/W
KHIX
IVKH
A
BWx
A+1
C
C+1
D
D+1
C
C+1
D
D+1
KHDX
DVKH
A
D
A+1
KHKL
KHKH
KLKH
C
KH#KH
C
CHQZ
CHQX1
CHQX
CHQV
B
Q
B+1
CQ
CQHQV
CQHQX
CQ
Rev: 1.08a 8/2005
20/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDDQ.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Port Registers
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDI
Test Data In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
Overview
The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.08a 8/2005
21/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
Boundary Scan Register
·
·
0
Bypass Register
0
108
·
1
·
·
2 1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
·
· · ·
2 1 0
Control Signals
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents TBD for this part.
Rev: 1.08a 8/2005
22/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Die
Revision
Code
GSI Technology
JEDEC Vendor
ID Code
I/O
Configuration
Not Used
Presence Register
Tap Controller Instruction Set
ID Register Contents
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
x18
X
1
X
X
X
0
0
0
X
1
0
0
0
1
0
0
0
1
0
1
0
0
0 0 1 1 0 1 1 0 0 1
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.08a 8/2005
23/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
JTAG Tap Controller State Diagram
1
0
Test Logic Reset
0
Run Test Idle
1
Select DR
1
Select IR
0
0
1
1
Capture DR
Capture IR
0
0
Shift DR
1
1
Shift IR
0
1
1
Exit1 DR
0
Exit1 IR
0
0
Pause DR
1
Exit2 DR
1
Update DR
1
1
0
0
Pause IR
1
Exit2 IR
0
1
0
0
Update IR
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 1.08a 8/2005
24/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.
Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
RFU
These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction.
Rev: 1.08a 8/2005
25/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
JTAG Port AC Test Load
DQ
50Ω
30pF*
VDDQ/2
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
1
RFU
011
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.08a 8/2005
26/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
Test Port Input High Voltage
VIHJ
0.6 * VDD
VDD2 +0.3
V
1
Test Port Input Low Voltage
VILJ
–0.3
0.3 * VDD
V
1
TMS, TCK and TDI Input Leakage Current
IINHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
–1
100
uA
3
TDO Output Leakage Current
IOLJ
–1
1
uA
4
Test Port Output High Voltage
VOHJ
1.7
—
V
5, 6
Test Port Output Low Voltage
VOLJ
—
0.4
V
5, 7
Test Port Output CMOS High
VOHJC
VDDQ – 100 mV
—
V
5, 8
Test Port Output CMOS Low
VOLJC
—
100 mV
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDD + 1V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V ≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDDQ supply.
6. IOHJ = –4 mA
7. IOLJ = + 4 mA
8. IOHJC = –100 uA
9. IOHJC = +100 uA
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
tTH
tTS
TDI
tTH
tTS
TMS
tTKQ
TDO
tTH
tTS
Parallel SRAM input
Rev: 1.08a 8/2005
27/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
JTAG Port AC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
50
—
ns
TCK Low to TDO Valid
tTKQ
—
20
ns
TCK High Pulse Width
tTKH
20
—
ns
TCK Low Pulse Width
tTKL
20
—
ns
TDI & TMS Set Up Time
tTS
10
—
ns
TDI & TMS Hold Time
tTH
10
—
ns
Rev: 1.08a 8/2005
28/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Package Dimensions—165-Bump FPBGA (Package D; Variation 3)
A1 CORNER
TOP VIEW
BOTTOM VIEW
Ø0.10 M C
Ø0.25 M C A B
Ø0.44~0.64 (165x)
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1.0
14.0
15±0.05
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
1.0
1.0
0.20 C
B
C
Rev: 1.08a 8/2005
SEATING PLANE
13±0.05
0.20(4x)
0.36~0.46
1.40 MAX.
0.36 REF
0.53 REF
0.35 C
10.0
29/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
Ordering Information—GSI SigmaSIO-II SRAM
Org
Part Number1
Type
Package
Speed
(MHz)
TA3
Status
1M x 18
GS8182S18D-267
SigmaSIO-II SRAM
1 mm Pitch, 165-Pin BGA (var. 3)
267
C
MP
1M x 18
GS8182S18D-250
SigmaSIO-II SRAM
1 mm Pitch, 165-Pin BGA (var. 3)
250
C
MP
1M x 18
GS8182S18D-200
SigmaSIO-II SRAM
1 mm Pitch, 165-Pin BGA (var. 3)
200
C
MP
1M x 18
GS8182S18D-167
SigmaSIO-II SRAM
1 mm Pitch, 165-Pin BGA (var. 3)
167
C
MP
1M x 18
GS8182S18D-267I
SigmaSIO-II SRAM
1 mm Pitch, 165-Pin BGA (var. 3)
267
I
MP
1M x 18
GS8182S18D-250I
SigmaSIO-II SRAM
1 mm Pitch, 165-Pin BGA (var. 3)
250
I
MP
1M x 18
GS8182S18D-200I
SigmaSIO-II SRAM
1 mm Pitch, 165-Pin BGA (var. 3)
200
I
MP
1M x 18
GS8182S18D-167I
SigmaSIO-II SRAM
1 mm Pitch, 165-Pin BGA (var. 3)
167
I
MP
1M x 18
GS8182S18GD-267
SigmaSIO-II SRAM
RoHS-compliant
1 mm Pitch, 165-Pin BGA (var. 3)
267
C
PQ
1M x 18
GS8182S18GD-250
SigmaSIO-II SRAM
RoHS-compliant
1 mm Pitch, 165-Pin BGA (var. 3)
250
C
PQ
1M x 18
GS8182S18GD-200
SigmaSIO-II SRAM
RoHS-compliant
1 mm Pitch, 165-Pin BGA (var. 3)
200
C
PQ
1M x 18
GS8182S18GD-167
SigmaSIO-II SRAM
RoHS-compliant
1 mm Pitch, 165-Pin BGA (var. 3)
167
C
PQ
1M x 18
GS8182S18GD-267I
SigmaSIO-II SRAM
RoHS-compliant
1 mm Pitch, 165-Pin BGA (var. 3)
267
I
PQ
1M x 18
GS8182S18GD-250I
SigmaSIO-II SRAM
RoHS-compliant
1 mm Pitch, 165-Pin BGA (var. 3)
250
I
PQ
1M x 18
GS8182S18GD-200I
SigmaSIO-II SRAM
RoHS-compliant
1 mm Pitch, 165-Pin BGA (var. 3)
200
I
PQ
1M x 18
GS8182S18GD-167I
SigmaSIO-II SRAM
RoHS-compliant
1 mm Pitch, 165-Pin BGA (var. 3)
167
I
PQ
Notes:
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8182S18D-250T.
2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
3. MP = Mass Production. PQ = Pre-Qualification.
Rev: 1.08a 8/2005
30/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology
GS8182S18D-267/250/200/167
SigmaSIO-II Revision History
File Name
Format/Content
8182Sxx_r1
Description of changes
Creation of datasheet
8182Sxx_r1; 8182Sxx_r1_01
Content
• Changed 330 MHz to 333MHz
• Removed any references to 133 MHz or 100 MHz
8182Sxx_r1_01; 8182Sxx_r1_02
Content
• Updated AC spec information
8182Sxx_r1_02; 8182Sxx_r1_03
Content
• Comprehensive rewrite, including (but not limited to)
tables, pinouts, and timing diagrams
8182Sxx_r1_03; 8182Sxx_r1_04
Content
• Removed x36 configuration
• Removed 333 and 300 MHz speed bins
• Updated format
Content
• Updated timing diagrams
• Corrected erroneous VDD information in pin description
table
• Deleted erroneous sentent in FLXDrive section
8182Sxx_r1_05; 8182Sxx_r1_06
Content
• Added 165 BGA Pb-Free information
• Added Storage Under Bias information
• Incorporated IDD information into Operating Currents table
• Updated Test Conditions for Operating Currents table
• Added max numbers for tKHKH and tCHCH in AC Char.
table
• Added Clock to /Clock Delay timing to AC Char. table
8182Sxx_r1_06; 8182Sxx_r1_07
Content
• Updated timing diagrams
8182Sxx_r1_07; 8182Sxx_r1_08
Content
• Added 267 MHz speed bin
8182Sxx_r1_04; 8182Sxx_r1_05
Rev: 1.08a 8/2005
31/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2003, GSI Technology