Rochester ICM7170AIDG Microprocessor-compatible, real-time clock 8-bit, up bus compatible Datasheet

ICM7170
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November 2003
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© 2013w
Rochester
Electronics, LLC. All Rights Reserved 03132013
contac ERSIL or ww
INT
1-888®
Microprocessor-Compatible,
Real-Time Clock
FN3019.6
ICM7170
Features
The ICM7170 real time clock is a microprocessor bus
compatible peripheral, fabricated using Intersil’s silicon gate
CMOS LSl process. An 8-bit bidirectional bus is used for the
data I/O circuitry. The clock is set or read by accessing the 8
internal separately addressable and programmable counters
from 1/100 seconds to years. The counters are controlled by
a pulse train divided down from a crystal oscillator circuit,
and the frequency of the crystal is selectable with the
on-chip command register. An extremely stable oscillator
frequency is achieved through the use of an on-chip
regulated power supply.
The device access time (tACC) of 300ns eliminates the need
for wait states or software overhead with most
microprocessors. Furthermore, an ALE (Address Latch
Enable) input is provided for interfacing to microprocessors
with a multiplexed address/data bus. With these two special
features, the ICM7170 can be easily interfaced to any
available microprocessor.
The ICM7170 generates two types of interrupts, periodic and
alarm. The periodic interrupt (100Hz, 10Hz, etc.) can be
programmed by the internal interrupt control register to
provide 6 different output signals. The alarm interrupt is set
by loading an on-chip 51-bit RAM that activates an interrupt
output through a comparator. The alarm interrupt occurs
when the real time counter and alarm RAM time are equal. A
status register is available to indicate the interrupt source.
An on-chip Power Down Detector eliminates the need for
external components to support the battery back-up
function. When a power down or power failure occurs,
internal logic switches the on-chip counters to battery backup operation. Read/write functions become disabled and
operation is limited to time-keeping and interrupt generation,
resulting in low power consumption.
Internal latches prevent clock roll-over during a read cycle.
Counter data is latched on the chip by reading the
100th-seconds counter and is held indefinitely until the
counter is read again, assuring a stable and reliable time
value.
• 8-Bit, µP Bus Compatible
- Multiplexed or Direct Addressing
• Regulated Oscillator Supply Ensures Frequency Stability
and Low Power
• Time From 1/100 Seconds to 99 Years
• Software Selectable 12/24 Hour Format
• Latched Time Data Ensures No Roll Over During Read
• Full Calendar with Automatic Leap Year Correction
• On-Chip Battery Backup Switchover Circuit
• Access Time Less than 300ns
• 4 Programmable Crystal Oscillator Frequencies Over
Industrial Temperature Range
• 3 Programmable Crystal Oscillator Frequencies Over
Military Temperature Range
• On-Chip Alarm Comparator and RAM
• Interrupts from Alarm and 6 Selectable Periodic Intervals
• Standby Micro-Power Operation: 1.2µA Typical at 3.0V
and 32kHz Crystal
Applications
• Portable and Personal Computers
• Data Logging
• Industrial Control Systems
• Point Of Sale
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Part Number Information
PART NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG.
NO.
ICM7170IPG
-40× to 85×
24 Ld PDIP
E24.6
ICM7170IBG
-40× to 85×
24 Ld SOIC
M24.3
ICM7170AIPG
-40× to 85×
24 Ld PDIP
E24.6
For complete Rochester ordering guide,
please-40×
refer
to page
2
ICM7170AIBG
to 85×
24 Ld SOIC
Please consult factory for specific
availability
NOTE: package
“A” Parts Screened
to <5µA ISTBY at 32kHz.
M24.3
Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes
only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. Rochester Electronics reserves
the right to make changes without further notice to any specification herein.
Specification Number
REV -These devices are sensitive to electrostatic discharge; follow proper
Page
1 ofProcedures.
14
IC Handling
1 ICM7170_IM (IL) CAUTION:
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1-888-INTERSIL or 321-724-7143
ICM7170
Rochester Ordering Guide
*Most products can also be offered as RoHS compliant, designated by a –G suffix. Please contact factory for more information.
Package
Temperature
ICM7170AIBG
Rochester Part Number
ICM7170AIBG
Intersil Part Number
SOP-24, Plastic
-40° to +85°C
ICM7170AIBGT
ICM7170AIBGT
SOP-24, Plastic
-40° to +85°C
ICM7170AIDG
ICM7170AIDG
CDIP-24
-40° to +85°C
ICM7170AIPG
ICM7170AIPG
PDIP-24
-40° to +85°C
ICM7170AMDG
ICM7170AMDG
CDIP-24
-55° to +125°C
ICM7170IBG
ICM7170IBG
SOP-24, Plastic
-40° to +85°C
ICM7170IBGT
ICM7170IBGT
SOP-24, Plastic
-40° to +85°C
ICM7170IDG
ICM7170IDG
CDIP-24
-40° to +85°C
ICM7170IPG
ICM7170IPG
PDIP-24
-40° to +85°C
ICM7170MDG
ICM7170MDG
CDIP-24
-55° to +125°C
Specification Number ICM7170_IM (IL) REV -
Page 2 of 14
ICM7170
ICM7170
Pinouts
ICM7170 (PDIP)
TOP VIEW
ICM7170 (SOIC)
TOP VIEW
WR 1
24 RD
ALE 2
23 VDD
A1 1
24 A2
A0 2
23 A3
CS 3
22 D7
OSC OUT 3
22 A4
A4 4
21 D6
OSC IN 4
21 CS
A3 5
20 D5
INT SOURCE 5
A2 6
19 D4
INT 6
19 WR
A1 7
18 D3
VSS 7
18 RD
A0 8
17 D2
VBACKUP 8
OSC OUT 9
16 D1
D0 9
16 D7
OSC IN 10
15 D0
D1 10
15 D6
INT SOURCE 11
14 VBACKUP
D2 11
14 D5
INTERRUPT 12
13 VSS (GND)
D3 12
13 D4
20 ALE
17 VDD
Functional Block Diagram
OSCILLATOR
CRYSTAL
OSC
OUT
9
RD
WR
ALE
CS
2
3
10
INTERRUPTS
LOW
POWER
OSC
24
1
OSC
IN
µP
COMPARE
PERIODIC
12
CONTROL
INT
11 SOURCE
TIME COUNTERS
0.01
VDD
VBACKUP
VSS
SEC
MIN
HOUR
DAY
DATE
INT
MON
YEAR
23
14
13
POWER
SUPPLY
CONTROL
8
THREE-STATE
I/O
DRIVERS
8-BIT BUS
8
DATA I/O
D0 - D7
15 - 22
8
ADDRESS
INPUTS
A0 - A4
5
8-4
ADDRESS
LATCHES
0.01
SEC
MIN
HOUR
DAY
DATE
COMPARE RAM
Specification Number ICM7170_IM (IL) REV 2
MON
YEAR
CMD
REG
STATUS
REG
INTER
MASK
REG
Page 3 of 14
ICM7170
ICM7170
Absolute Maximum Ratings TA = 25oC
Thermal Information
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Power Dissipation (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . .500mW
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . .300oC
Input Voltage (Any Terminal) (Note 2) . . . . VDD +0.3V to VSS -0.3V
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
50
N/A
SOIC Package . . . . . . . . . . . . . . . . . . .
75
N/A
Maximum Junction Temperature
Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Due to the SCR structure inherent in the CMOS process, connecting any terminal at voltages greater than VDD or less than VSS may cause destructive
device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same power supply be applied to the
device before its supply is established, and that in multiple supply systems, the supply to the ICM7170 be turned on first.
TA = -40oC to 85oC, VDD +5V ±10%, VBACKUP VDD , VSS = 0V Unless Otherwise Specified
All IDD specifications include all input and output leakages (ICM7170 and ICM7170A)
Electrical Specifications
PARAMETER
TEST CONDITIONS
VDD Supply Range, VDD
Standby Current, ISTBY(1)
MIN
TYP
MAX
UNITS
fOSC = 32kHz
1.9
-
5.5
V
fOSC = 1, 2, 4MHz
2.6
-
5.5
V
fOSC = 32kHz
Pins 1 - 8,15 - 22 and 24 = VDD
ICM7170
-
1.2
20.0
µA
VDD = VSS ; VBACKUP = VDD - 3.0V
For ICM7170A See General Notes 5
ICM7170A
-
1.2
5.0
µA
Standby Current, ISTBY(2)
fOSC = 4MHz Pins 1 - 8,15 - 22 and 24 = VDD
VDD = VSS ; VBACKUP = VDD - 3.0V
-
20
150
µA
Operating Supply Current, IDD(1)
fOSC = 32kHz, Read/Write Operation at 100Hz
-
0.3
1.2
mA
Operating Supply Current, IDD(2)
fOSC = 32kHz, Read/Write Operation at 1MHz
-
1.0
2.0
mA
Input Low Voltage (Except Osc.), VIL
VDD = 5.0V
-
-
0.8
V
Input High Voltage (Except Osc.), VIH
VDD = 5.0V
2.4
-
-
V
Output Low Voltage (Except Osc.), VOL
IOL = 1.6mA
-
-
0.4
V
Output High Voltage Except
INTERRUPT (Except Osc.), VOH
IOH = -400µA
2.4
-
-
V
Input Leakage Current, IIL
VIN = VDD or VSS
-10
0.5
+10
µA
Three-State Leakage Current
(D0 - D7), IOL(1)
VO = VDD or VSS
-10
0.5
+10
µA
Backup Battery Voltage, VBATTERY
fOSC = 1, 2, 4MHz
2.6
-
VDD - 1.3
V
Backup Battery Voltage, VBATTERY
fOSC = 32kHz
1.9
-
VDD - 1.3
V
Leakage Current INTERRUPT, IOL(2)
VO = VDD
-
0.5
10
µA
Capacitance D0 - D7, CI/O
-
8
-
pF
Capacitance A0 - A4, CADDRESS
-
6
-
pF
Specification Number ICM7170_IM (IL) REV 3
INT SOURCE
Connected to VSS
Page 4 of 14
ICM7170
ICM7170
AC Electrical Specifications
TA = -40oC to 85oC, VDD = +5V ± 10%, VBACKUP = VDD ,
D0 - D7 Load Capacitance = 150pF, VIL = 0.4V, VlH = 2.8V, Unless Otherwise Specified
PARAMETER
MIN
MAX
UNITS
READ to DATA Valid, tRD
-
250
ns
ADDRESS Valid to DATA Valid, tACC
-
300
ns
READ Cycle Time, tCYC
400
-
ns
Read High Time, tRH
150
-
ns
-
25
ns
ADDRESS to READ Set Up Time, tAS
50
-
ns
ADDRESS HOLD Time After READ, tAR
0
-
ns
ADDRESS Valid to WRITE Strobe, tAD
50
-
ns
ADDRESS Hold Time for WRITE, tWA
0
-
ns
WRITE Pulse Width, Low, tWL
100
-
ns
WRITE High Time, tWH
300
-
ns
DATA IN to WRITE Set Up Time, tDW
100
-
ns
DATA IN Hold Time After WRITE, tWD
30
-
ns
WRITE Cycle Time, tCYC
400
-
ns
ALE Pulse Width, High, tLL
50
-
ns
ADDRESS to ALE Set Up Time, tAL
30
-
ns
ADDRESS Hold Time After ALE, tLA
30
-
ns
READ CYCLE TIMING
RD High to Bus Three-State, tRH
WRITE CYCLE TIMING
MULTIPLEXED MODE TIMING
Timing Diagrams
ADDRESS VALID, CS LOW
A0 - A4, CS
tAS
tAR
tCYC
RD
tRD
D0 - D7
OUTPUT DATA VALID
tACC
tRX
FIGURE 1. READ CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = VIH , WR = VIH)
Specification Number ICM7170_IM (IL) REV 4
Page 5 of 14
ICM7170
ICM7170
Timing Diagrams
(Continued)
A0 - A4, CS
ADDRESS VALID, CS LOW
tAD
tWA
tCYC
tWL
WR
tDW
D0 - D7
tWD
INPUT DATA VALID
FIGURE 2. WRITE CYCLE TIMING FOR NON-MULTIPLEXED BUS (ALE = VIH , RD = VIH)
A0 - A4, D0 - D7, CS
ADDRESS VALID, CS LOW
OUTPUT DATA VALID
tLA
tLL
tAR
tACC
ALE
tAL
tCYC
RD
tAS
tRD
FIGURE 3. READ CYCLE TIMING FOR MULTIPLEXED BUS (WR = VIH)
A0 - A4, D0 - D7, CS
ADDRESS VALID, CS LOW
INPUT DATA VALID
tLA
tDW
tWD
tLL
tWA
ALE
tAL
tAD
tCYC
tWL
WR
FIGURE 4. WRITE CYCLE TIMING FOR MULTIPLEXED BUS (RD = VIH)
Specification Number5ICM7170_IM (IL) REV -
Page 6 of 14
ICM7170
ICM7170
Pin Descriptions
PIN NUMBER
SOIC PIN NUMBER
WR
SIGNAL
1
19
Write Input
ALE
2
20
Address Latch Enable Input
CS
A4-A0
OSC OUT
3
21
4-8
22 - 2
9
3
DESCRIPTION
Chip Select Input
Address Inputs
Oscillator Output
OSC IN
10
4
Oscillator Input
INT SOURCE
11
5
Interrupt Source
INTERRUPT
12
6
Interrupt Output
VSS (GND)
13
7
Digital Common
VBACKUP
14
8
Battery Negative Side
15 - 22
9 - 16
VDD
23
17
Positive Digital Supply
RD
24
18
Read Input
D0 - D7
Data I/O
TABLE 1. COMMAND REGISTER FORMAT
COMMAND REGISTER ADDRESS (10001b, 11h) WRITE-ONLY
D7
D6
D5
D4
D3
D2
D1
D0
n/a
n/a
Normal/Test
Mode
Interrupt
Enable
Run/Stop
12/24 Hour
Format
Crystal
Frequency
Crystal
Frequency
TABLE 2. COMMAND REGISTER BIT ASSIGNMENTS
D5
TEST BIT
D4
INTERRUPT
ENABLE
D3
RUN/STOP
D2
24/12 HOUR
FORMAT
D1
D0
CRYSTAL
FREQUENCY
0
Normal Mode
0
Interrupt disabled
0
Stop
0
12-Hour Mode
0
0
32.768kHz
1
Test Mode
1
Interrupt enable
1
Run
1
24-Hour Mode
0
1
1.048576MHZ
1
0
2.097152MHz
1
1
4.194304MHz
TABLE 3. ADDRESS CODES AND FUNCTIONS
ADDRESS
DATA
A4
A3
A2
A1
A0
HEX
FUNCTION
D7
D6
D5
0
0
0
0
0
00
Counter-1/100 seconds
-
0
0
0
0
1
01
Counter-hours
-
-
-
12 Hour Mode
†
-
-
D3
D2
D1
D0
VALUE
0 - 99
0
0
0
1
0
02
Counter-minutes
-
-
0
0
0
1
1
03
Counter-seconds
-
-
0
0
1
0
0
04
Counter-month
-
-
-
0
0
1
0
1
05
Counter-date
-
-
-
0
0
1
1
0
06
Counter-year
-
0
0
1
1
1
07
Counter-day of week
-
-
-
0
1
0
0
0
08
RAM-1/100 seconds
M
0
1
0
0
1
09
RAM-hours
-
M
-
†
M
-
12 Hour Mode
D4
0 - 23
-
1 - 12
0 - 59
0 - 59
-
1 - 12
1 - 31
0 - 99
-
-
0-6
0 - 99
0 - 23
-
1 - 12
0
1
0
1
0
0A
RAM-minutes
M
-
.
.
0 - 59
0
1
0
1
1
0B
RAM-seconds
M
-
.
.
0 - 59
-
0
1
1
0
0
0C
RAM-month
M
-
-
0
1
1
0
1
0D
RAM-date
M
-
-
0
1
1
1
0
0E
RAM-year
M
6
Specification Number ICM7170_IM (IL) REV -
1 - 12
1 - 31
0 - 99
Page 7 of 14
ICM7170
ICM7170
TABLE 3. ADDRESS CODES AND FUNCTIONS (Continued)
ADDRESS
DATA
A4
A3
A2
A1
A0
HEX
0
1
1
1
1
0F
1
0
0
0
0
1
0
0
0
1
FUNCTION
D7
D6
D5
D4
D3
RAM-day of week
M
-
-
-
-
10
Interrupt Status and Mask
Register
+
11
Command register
-
D2
D1
D0
VALUE
0-6
-
NOTES:
Addresses 10010 to 11111 (12h to 1Fh) are unused.
‘+’ Unused bit for interrupt Mask Register, MSB bit for interrupt Status Register.
‘-’ Indicates unused bits.
‘†’ AM/PM indicator bit in 12 hour format Logic “0” indicates AM, logic “1” indicates PM.
‘M’ Alarm compare for particular counter will be enabled if bit is set to logic “0”.
TABLE 4. INTERRUPT AND STATUS REGISTERS FORMAT
INTERRUPT MASK REGISTER ADDRESS (10000b, 10h) WRITE-ONLY
D7
D6
D5
D4
D3
D2
D1
D0
NOT USED
DAY
HOUR
MIN
SEC
1/10 SEC
1/100 SEC
ALARM
→
Alarm/Compare Mask Bit
Periodic Interrupt Mask Bits
←
INTERRUPT STATUS REGISTER ADDRESS (10000b, 10h) READ-ONLY
D7
D6
D5
GLOBAL INTERRUPT
DAY
HOUR
Periodic and Alarm Flags
←
D4
D3
D2
D1
MIN
SEC
1/10 SEC
1/100 SEC
ALARM
→
Alarm Compare Flag
Periodic Interrupt Flags
Detailed Description
Oscillator
The ICM7170 has an onboard CMOS Pierce oscillator with an
internally regulated voltage supply for maximum accuracy,
stability, and low power consumption. It operates at any of
four popular crystal frequencies: 32.768kHz, 1.046576MHz,
2.097152MHz, and 4.194304MHz (Note 1). The crystal
should be designed for the parallel resonant mode of
oscillation. In addition to the crystal, 2 or 3 load capacitors are
required, depending on the circuit topology used.
The oscillator output is divided down to 4000Hz by one of
four divider ratios, determined by the two frequency
selection bits in the Command Register (D0 and D1 at
address 11H). This 4000Hz is then divided down to 100Hz,
which is used as the clock for the counters.
Time and calendar information is provided by 8 consecutive,
programmable counters: 100ths of, seconds, minutes,
hours, day of week, date, month, and year. The data is in
binary format with 8 bits per digit. See Table 3 for address
information. Any unused bits are held to a logic “0” during a
read and ignored during a write operation.
NOTE:
1. 4.94304MHz is not available over military temperature range.
Alarm Compare RAM
On the chip are 51 bits of Alarm Compare RAM grouped into
words of different lengths. These are used to store the time,
ranging from 10ths of seconds to years, for comparison to the
real-time counters. Each counter has a corresponding RAM
Specification Number7 ICM7170_IM (IL) REV -
D0
word. In the Alarm Mode an interrupt is generated when the
current time is equal to the alarm time. The RAM contents are
compared to the counters on a word by word basis. If a
comparison to a particular counter is unnecessary, then the
appropriate ‘M’ bit in Compare RAM should be set to logic “1”.
The ‘M’ bit, referring to Mask bit, causes a particular RAM
word to be masked off or ignored during a compare. Table 3
shows addresses and Mask bit information.
Periodic Interrupts
The interrupt output can be programmed for 6 periodic
signals: 100Hz, 10Hz, once per second, once per minute,
once per hour, or once per day. The 100Hz and 10Hz
interrupts have instantaneous errors of ±2.5% and ±0.15%
respectively. This is because non-integer divider circuitry is
used to generate these signals from the crystal frequency,
which is a power of 2. The time average of these errors over
a 1 second period, however, is zero. Consequently, the
100Hz or 10Hz interrupts are not suitable as an aid in tuning
the oscillator; the 1 second interrupt must be used instead.
See General Notes, Note 6.
The periodic interrupts can occur concurrently and in
addition to alarm interrupts. The periodic interrupts are
controlled by bits in the interrupt mask register, and are
enabled by setting the appropriate bit to a “1” as shown in
Table 4. Bits D1 through D6 in the mask register, in
conjunction with bits D1 through D6 of the status register,
control the generation of interrupts according to Figure 5.
Page 8 of 14
ICM7170
ICM7170
ALARM MASK BIT
PERIODIC INT’ MASK BITS
INTERRUPT MASK
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
NOT
USED
PIN 12
INT
VIG
INT
SOURCE
PIN 11
INTERRUPT STATUS
REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
PERIODIC INT’ FLAGS
RD OF ADD HEX 10 = >RESET
ALARM FLAG BIT
GLOBAL INTERRUPT FLAG BIT
INTERRUPT
ENABLE
COMMAND
REGISTER
BIT D4
FIGURE 5. INTERRUPT OUTPUT CIRCUIT
The interrupt status register, when read, indicates the cause
of the interrupt and resets itself on the rising edge of the RD
signal. When any of the counters having a corresponding bit
in the status register increments, that bit is set to a “1”
regardless of whether the corresponding bit in the interrupt
mask register is set or not.
Consequently, when the status register is read it will always
indicate which counters have increments and if an alarm
compare occurred, since the last time it was read. This
requires some special software considerations. If a slow
interrupt is enabled (i.e., hourly or daily), the program must
always check the slowest interrupt that has been enabled
first, because all the other lower order bits in the status
register will be set to “1” as well.
Bit D7 is the global interrupt bit, and when set to a “1”,
indicates that the ICM7170 did indeed generate a hardware
interrupt. This is useful when other interrupting devices in
addition to the ICM7170 are attached to the system
microprocessor, and all devices must be polled to determine
which one generated the interrupt.
See General Notes, Note 6.
Interrupt Operation
The Interrupt Output N-channel MOSFET (Figure 4) is enabled
whenever both the Interrupt Enable bit (D4 of the Command
Register) and a mask bit (D0 - D6 of the Interrupt Mask
Register) are set. The transistor is turned ON when a flag bit is
set that corresponds to one of the set mask bits. This also sets
the Global Interrupt Flag Bit (D7 of the Interrupt Status
Register). It is turned OFF when the Interrupt Status Register is
8
Specification Number ICM7170_IM (IL) REV -
read. An interrupt can occur in both the operational and standby
modes of operation.
Since system power is usually applied between VDD and VSS ,
the user can connect the Interrupt Source (pin 11) to VSS . This
allows the Interrupt Output to turn on only while system powers
applied and will not be pulled to VSS during standby operation.
If interrupts are required only during standby operation, then the
interrupt source pin should be connected to the battery’s
negative side (VBACKUP). In this configuration, for example,
the interrupt could be used to turn on power for a cold boot.
Power Down Detector
The ICM7170 contains an on-chip power down detector that
eliminates the need for external components to support the
battery-backup switchover function, as shown in Figure 6.
Whenever the voltage from the VSS pin to the VBACKUP pin is
less than approximately 1.0V (the VTH of the N-channel
MOSFET), the data bus I/O buffers in the ICM7170 are
automatically disabled and the chip cannot be read or written
to. This prevents random data from the microprocessor being
written to the clock registers as the power supply is going down.
Actual switchover to battery operation occurs when the voltage
on the VBACKUP pin is within ±50mV of VSS . This switchover
uncertainty is due to the offset voltage of the CMOS
comparator that is used to sense the battery voltage. During
battery backup, device operation is limited to timekeeping and
interrupt generation only, thus achieving micro- power current
drain. If an external battery-backup switch-over circuit is being
used with the ICM7170, or if standby battery operation is not
required, the VBACKUP pin should be pulled up to VDD through
a 2K resistor.
Page 9 of 14
ICM7170
ICM7170
POSITIVE SUPPLY RAIL
(+5V)
VDD
VDD
PIN 23
BATTERY
VTH
R2
VBACK
2K
VSS
VIG
INTERNAL GROUND
VDD
+
-
PIN 14
I/O DISABLE
≅ 1.0V
CMOS COMPARATOR
VIG
PIN 13
DIGITAL GROUND
FIGURE 6. SIMPLIFIED ICM7170 BATTERY BACKUP CIRCUIT
Time Synchronization
Time synchronization is achieved through bit D3 of the
Command Register, which is used to enable or disable the
100Hz clock from the counters. A logic “1” allows the counters
to function and a logic “0” disables the counters. To accurately
set the time, a logic “0” should be written into D3 and then the
desired times entered into the appropriate counters. The clock
is then started at the proper time by writing a logic “1” into D3 of
the Command Register.
Latched Data
To prevent ambiguity while the processor is gathering data from
the registers, the ICM7170 incorporates data latches and a
transparent transition delay circuit.
By accessing the 100ths of seconds counter an internal
store signal is generated and data from all the counters is
transferred into a 36-bit latch. A transition delay circuit will
delay a 100Hz transition during a READ cycle. The data
stored by the latches is then available for further processing
until the 100ths of seconds counter is read again. If a RD
signal is wider than 0.01s, 100Hz counts will be ignored.
falling edge, the address and CS information is read into the
address latch and buffer. RD and WR are used in the same
way as on a non-multiplexed bus. If a non-multiplexed bus is
used, ALE should be connected to VDD .
Test Mode
The test mode is entered by setting D5 of the Command
Register to a logic “1”. This connects the 100Hz counter
directly to the oscillator’s output.
Oscillator Considerations
Load Design: A new oscillator load configuration, shown in
Figure 7, has been found that eliminates start-up problems
sometimes encountered with 32kHz tuning fork crystals.
VDD
C1
C2
X1
OSC IN
C3
OSC OUT
9
10
VDD
Control Lines
The RD, WR, and CS signals are active low inputs. Data is
placed on the bus from counters or registers when RD is a
logic “0”. Data is transferred to counters or registers when
WR is a logic “0”. RD and WR must be accompanied by a
logical “0” CS as shown in Figures 2 and 3. The ICM7170
will also work satisfactorily with CS grounded. In this mode,
access to the ICM7170 is controlled by RD and WR only.
With the ALE (Address Latch Enable) input, the ICM7170
can be interfaced directly to microprocessors that use a
multiplexed address/data bus by connecting the address
lines A0 - A4 to the data lines D0 - D4. To address the chip,
the address is placed on the bus and ALE is strobed. On the
9
Specification Number ICM7170_IM (IL) REV -
23
ICM7170
FIGURE 7. NEW OSCILLATOR CONFIGURATION
Two conditions must be met for best oscillator performance:
the capacitive load must be matched to both the inverter and
crystal to provide the ideal conditions for oscillation, and the
resonant frequency of the oscillator must be adjustable to
the desired frequency. In the original design (Figure 8),
these two goals were often at odds with each other; either
the oscillator was trimmed to frequency by detuning the load
circuit, or stability was increased at the expense of absolute
frequency accuracy.
Page 10 of 14
ICM7170
ICM7170
on a single layer of the PCB. Avoid putting a ground plane
above or below this layer. The traces between the crystal,
the capacitors, and the ICM7170 OSC pins should be as
short as possible. Completely surround the oscillator
components with a thick trace of VDD to minimize coupling
with any digital signals. The final assembly must be free from
contaminants such as solder flux, moisture, or any other
potential sources of leakage. A good solder mask will help
keep the traces free of moisture and contamination over
time.
VDD
C1
C2
X1
OSC OUT
OSC IN
10
9
VDD
23
C1 ≈ 2 x LOAD
ICM7170
C2 ≈ 5pF - 35pF
FIGURE 8. ORIGINAL OSCILLATOR CONFIGURATION
The new load configuration (Figure 6) allows these two
conditions to be met independently. The two load capacitors,
C1 and C2, provide a fixed load to the oscillator and crystal.
C3 adjusts the frequency that the circuit resonates at by
reducing the effective value of the crystal's motional
capacitance, C0. This minute adjustment does not
appreciably change the load of the overall system, therefore,
stability is no longer affected by tuning. Typical values for
these capacitors are shown in Table 5. C1 and C2 must
always be greater than twice the crystal’s recommended load
capacitance in order for C3 to be able to trim the frequency.
Some experimentation may be necessary to determine the
ideal values of C1 and C2 for a particular crystal.
TABLE 5. TYPICAL LOAD CAPACITOR VALUES
CRYSTAL
FREQUENCY
LOAD CAPS
(C1, C2)
TRIMMER CAP
(C3)
32kHz
33pF
5 - 50pF
1MHz
33pF
5 - 50pF
2MHz
25pF
5 - 50pF
4MHz
22pF
5 - 100pF
This three capacitor tuning method will be more stable than
the original design and is mandatory for 32kHz tuning fork
crystals: without it they may leap into an overtone mode
when power is initially applied.
The original two-capacitor circuit (Figure 8) will continue to
work as well as it always has, and may continue to be used
in applications where cost or space is a critical
consideration. It is also easier to tune to frequency since one
end of the trimmer capacitor is fixed at the AC ground of the
circuit (VDD), minimizing the disturbance cause by contact
between the adjustment tool and the trimmer capacitor. Note
that in both configurations the load capacitors are connected
between the oscillator pins and VDD - do not use VSS as an
AC ground.
Layout: Due to the extremely low current (and therefore high
impedance) design of the ICM7170s oscillator, special
attention must be given to the layout of this section. Stray
capacitance should be minimized. Keep the oscillator traces
10
Specification Number ICM7170_IM (IL) REV -
Oscillator Tuning
Trimming the oscillator should be done indirectly. Direct
monitoring of the oscillator frequency by probing OSC IN or
OSC OUT is not accurate due to the capacitive loading of
most probes. One way to accurately trim the ICM7170 is by
turning on the 1 second periodic interrupt and trimming the
oscillator until the interrupt period is exactly one second.
This can be done as follows:
1.Turn on the system. Write a 00H to the Interrupt Mask Register
(location 10H) to clear all interrupts.
2. Set the Command Register (location 11H) for the appropriate
crystal frequency, set the Interrupt Enable and Run/Stop bits to
1, and set the Test bit to 0.
3. Write a 08H to the Interrupt Mask Register to turn on the 1s
interrupt.
4. Write an interrupt handler to read the Interrupt Status Register
after every interrupt. This resets the interrupt and allows it to be
set again. A software loop that reads the Interrupt Status
Register several times each second will accomplish this also.
5. Connect a precision period counter capable of measuring 1s
within the accuracy desired to the interrupt output. If the interrupt
is configured as active low, trigger on the falling edge. If the
interrupt is active high, trigger on the rising edge. Be sure to
measure the period between when the transistor turns ON, and
when the transistor turns ON a second later.
6. Adjust C3 (C2 for the two-capacitor load configuration) for an
interrupt period of exactly 1.000000 seconds.
Application Notes
Digital Input Termination During Backup
To ensure low current drain during battery backup operation,
none of the digital inputs to the ICM7170 should be allowed
to float. This keeps the input logic gates out of their transition
region, and prevents crossover current from flowing which
will shorten battery life. The address, data, CS, and ALE pins
should be pulled to either VDD or VSS , and the RD and WR
inputs should be pulled to VDD . This is necessary whether
the internal battery switchover circuit is used or not.
IBM/PC Evaluation Circuit
Figure 9 shows the schematic of a board that has been
designed to plug into an IBM PC/XT (Note 1) or compatible
computer. In this example CS is permanently tied low and
access to the chip is controlled by the RD and WR pins.
These signals are generated by U1, which gates the IBM’s
lOR and lOW with a device select signal from U3, which is
Page 11 of 14
ICM7170
ICM7170
functioning as an I/O block address decoder. DS1 selects
the interrupt priority.
When trimming the oscillator, the frequency counter must be
triggered on the rising edge of the interrupt signal.
U5 is used to isolate the ICM7170 from the PC databus for
test purposes. It is only required on heavily-loaded TTL
databuses - the ICM7170 can drive most TTL and CMOS
databuses directly.
TABLE 6.
BATTERIES
Since the IBM PC/XT (Note 1) requires a positive interrupt
transition, the ICM7170s interrupt output transistor has been
configured as a source follower. As a source follower, the
interrupt output signal will swing between 0V and 2.5V.
A11 AEN
S1
S2
Saronix
32kHz
NTF3238
Rayovac
Statek
32kHz
CX - 1V
Seiko
2MHz
GT - 38
NOTE:
1.IBM, IBM PC, and IBM XT are trademarks of IBM Corp.
C5
20
1
16
2
19
2
15
3
18
4
17
3
14
IOR B14
13
IOW B13
6
S4
Panasonic
1
5
S3
CRYSTALS
U3
74LS688
4
16
5
15
7
14
8
13
A26 A5
9
12
A25 A6
10
11
U1
74LS139
C6
12
6
11
7
10
8
9
A24 A7
A23 A8
A22 A9
J1
A31 A0
A30 A1
C4
C7
1
24
2
23
1
3
22
2
19
4
21
3
18
D7 A2
20
4
17
D6 A3
19
5
16
D5 A4
18
6
15
D4 A5
5
20
A29 A2
6
A28 A3
7
A27 A4
8
17
7
14
D3 A6
9
16
8
13
D2 A7
10
15
9
12
D1 A8
11
14
10
11
D0 A9
12
13
C3
C2
B4 IRQ2
B23 IRQ5
B24 IRQ4
B25 IRQ3
X1
C1
U2
ICM7170
S1
S2
S3
S4
+
R2
-
B1
SR2
D1 OPTIONAL DIODE AND
RESISTOR SEE NOTE 8
POSITIVE INTERRUPT
TP1
R1
U5
74LS245
5V B3.B29
GND B1.B31
1K
DSI
INTERRUPT
SELECT
FIGURE 9. IBM PC INTERFACE FOR ICM7170Y
11 ICM7170_IM (IL) REV Specification Number
Page 12 of 14
ICM7170
ICM7170
Dual-In-Line Plastic Packages (PDIP)
E24.6 (JEDEC MS-011-AA ISSUE B)
N
24 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-A-
E
D
BASE
PLANE
-C-
SEATING
PLANE
A
L
D1
B1
A2
e
D1
B
0.010 (0.25) M
A1
eC
C A B S
MILLIMETERS
SYMBOL
MIN
MAX
MIN
A
-
0.250
-
MAX
6.35
A1
0.015
-
0.39
A2
0.125
0.195
3.18
4.95
NOTES
4
4
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.030
0.070
0.77
1.77
8
eA
C
0.008
0.015
C
D
1.150
1.290
D1
0.005
-
0.13
E
0.600
0.625
15.24
15.87
6
E1
0.485
0.580
12.32
14.73
5
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
e
0.204
29.3
0.100 BSC
0.381
32.7
-
2.54 BSC
5
5
-
eA
0.600 BSC
15.24 BSC
6
eB
-
0.700
-
17.78
7
L
0.115
0.200
2.93
5.08
4
N
24
24
9
Rev. 0 12/93
7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
Specification Number ICM7170_IM (IL) REV 13
Page 13 of 14
ICM7170
ICM7170
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
0.25(0.010) M
H
E
M24.3 (JEDEC MS-013-AD ISSUE C)
B M
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
-B1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
µα
e
A1
B
C
0.25(0.010) M
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
NOTES:
MAX
A1
e
0.10(0.004)
MIN
α
24
0o
24
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Rochester Electronics guarantees performance of its semiconductor products to the original OEM specifications. “Typical” values are for reference purposes
Intersil only.
products
are minimum
sold by description
only.
Intersil
Corporation
reserves
right to make changes
in circuit design,
software
and/or
specifications
at any
time without
Certain
or maximum
ratings
may
be based on
productthe
characterization,
design, simulation,
or sample
testing.
Rochester
Electronics
reserves
notice. the
Accordingly,
the reader
is cautioned
to verify
thattodata
sheets are current
right to make
changes
without further
notice
any specification
herein.before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information
regarding Intersil
Specification Number
ICM7170_IM
(IL)Corporation
REV - and its products, see www.intersil.com Page 14 of 14
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