DDU8F data 3 delay devices, inc. 5-TAP, TTL-INTERFACED FIXED DELAY LINE (SERIES DDU8F) FEATURES • • • • • • PACKAGES Five equally spaced outputs Fits standard 8-pin DIP socket Low profile Auto-insertable Input & outputs fully TTL interfaced & buffered 10 T2L fan-out capability IN 1 8 VCC T2 2 7 T1 T4 3 6 T3 GND 4 5 T5 DDU8F-xx DDU8F-xxA1 DDU8F-xxB1 DDU8F-xxM FUNCTIONAL DESCRIPTION IN N/C N/C T2 N/C T4 GND DIP Gull-Wing J-Lead Military DIP 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD N/C T1 N/C T3 N/C T5 Military SMD DDU8F-xxMD1 DDU8F-xxMD4 PIN DESCRIPTIONS The DDU8F-series device is a 5-tap digitally buffered delay line. The IN Signal Input signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an T1-T5 Tap Outputs amount determined by the device dash number (See Table). For dash VCC +5 Volts numbers less than 5025, the total delay of the line is measured from T1 to GND Ground T5. The nominal tap-to-tap delay increment is given by one-fourth of the total delay, and the inherent delay from IN to T1 is nominally 3.5ns. For dash numbers greater than or equal to 5025, the total delay of the line is measured from IN to T5. The nominal tap-to-tap delay increment is given by one-fifth of this number. SERIES SPECIFICATIONS • • • • • • DASH NUMBER SPECIFICATIONS Minimum input pulse width: 40% of total delay Output rise time: 2ns typical Supply voltage: 5VDC ± 5% Supply current: ICCL = 32ma typical ICCH = 7ma typical Operating temperature: 0° to 70° C Temp. coefficient of total delay: 100 PPM/°C 3.5ns VCC IN 25% T1 25% T2 25% T3 25% T4 T5 GND Functional diagram for dash numbers < 5025 20% VCC IN 20% T1 20% T2 20% T3 20% T4 T5 GND Part Number DDU8F-5004 DDU8F-5006 DDU8F-5008 DDU8F-5010 DDU8F-5012 DDU8F-5016 DDU8F-5020 DDU8F-5025 DDU8F-5030 DDU8F-5035 DDU8F-5040 DDU8F-5045 DDU8F-5050 DDU8F-5060 DDU8F-5075 DDU8F-5100 DDU8F-5125 DDU8F-5150 DDU8F-5175 DDU8F-5200 DDU8F-5250 Total Delay (ns) 4 ± 1.0 * 6 ± 1.0 * 8 ± 2.0 * 10 ± 2.0 * 12 ± 2.0 * 16 ± 2.0 * 20 ± 3.0 * 25 ± 3.0 30 ± 3.0 35 ± 3.0 40 ± 3.0 45 ± 3.0 50 ± 3.0 60 ± 3.0 75 ± 4.0 100 ± 5.0 125 ± 6.5 150 ± 7.5 175 ± 8.0 200 ± 10.0 250 ± 12.5 Delay Per Tap (ns) 1.0 ± 0.5 1.5 ± 0.5 2.0 ± 1.0 2.5 ± 1.0 3.0 ± 1.0 4.0 ± 1.5 5.0 ± 2.0 5.0 ± 2.0 6.0 ± 2.0 7.0 ± 2.0 8.0 ± 2.0 9.0 ± 3.0 10.0 ± 3.0 12.0 ± 3.0 15.0 ± 3.0 20.0 ± 3.0 25.0 ± 3.0 30.0 ± 3.0 35.0 ± 4.0 40.0 ± 4.0 50.0 ± 5.0 * Total delay is referenced to first tap output Input to first tap = 3.5ns ± 1ns Functional diagram for dash numbers >= 5025 1997 Data Delay Devices Doc #97012 1/28/97 NOTE: Any dash number between 5004 and 5250 not shown is also available. DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 1 DDU8F APPLICATION NOTES Delay Devices if your application requires device testing at a specific input condition. HIGH FREQUENCY RESPONSE The DDU8F tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data POWER SUPPLY BYPASSING The DDU8F relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended. A wide VCC trace and a clean ground plane should be used. DEVICE SPECIFICATIONS TABLE 1: ABSOLUTE MAXIMUM RATINGS PARAMETER DC Supply Voltage Input Pin Voltage Storage Temperature Lead Temperature SYMBOL VCC VIN TSTRG TLEAD MIN -0.3 -0.3 -55 MAX 7.0 VDD+0.3 150 300 UNITS V V C C NOTES 10 sec TABLE 2: DC ELECTRICAL CHARACTERISTICS (0C to 70C, 4.75V to 5.25V) PARAMETER High Level Output Voltage SYMBOL VOH Low Level Output Voltage VOL High Level Output Current Low Level Output Current High Level Input Voltage Low Level Input Voltage Input Clamp Voltage Input Current at Maximum Input Voltage High Level Input Current Low Level Input Current Short-circuit Output Current Output High Fan-out Output Low Fan-out IOH IOL VIH VIL VIK IIHH Doc #97012 1/28/97 IIH IIL IOS MIN 2.5 TYP 3.4 MAX UNITS V 0.35 0.5 V -1.0 20.0 0.8 -1.2 0.1 mA mA V V V mA 20 -0.6 -150 25 12.5 µA mA mA Unit Load 2.0 -60 NOTES VCC = MIN, IOH = MAX VIH = MIN, VIL = MAX VCC = MIN, IOL = MAX VIH = MIN, VIL = MAX VCC = MIN, II = IIK VCC = MAX, VI = 7.0V VCC = MAX, VI = 2.7V VCC = MAX, VI = 0.5V VCC = MAX DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 2 DDU8F PACKAGE DIMENSIONS 8 7 6 5 Lead Material: Nickel-Iron alloy 42 TIN PLATE 8 1 2 3 7 6 5 .440 MAX. 4 .280 MAX. .500 MAX. 1 2 3 4 .500 MAX. .290 MAX. .020 .290 TYP. MAX. .015 TYP. .010±.002 .018 TYP. .070 MAX. .180 TYP. .350 MAX. .300±.010 3 Equal spaces each .100±.010 Non-Accumulative .300 TYP. .040 TYP. 8 7 6 .010 TYP. .020 TYP. 5 2 3 7 6 .300 MAX. .050 TYP. DDU8F-xxA1 (Commercial Gull-Wing) .320 TYP. .270 TYP. 1 .110 .050 TYP. 5 .430 TYP. 4 .100 .300 .520 MAX. .040 TYP. 8 .270 TYP. 1 .300 TYP. DDU8F-xxM (Military DIP) DDU8F-xx (Commercial DIP) .020 TYP. .010 TYP. .020 TYP. 2 3 4 .100 .300 .520 MAX. .110 .350 MAX. .110 TYP. DDU8F-xxB1 (Commercial J-Lead) .650 .100 1 .100 .017 14 1 .510 MAX. .300 TYP. 7 .510 MAX. .360 TYP. .008 .065 TYP. DDU8F-xxD1 (Commercial SMD) DDU8F-xxMD1 (Military SMD) Doc #97012 1/28/97 .050 .510 MAX. .080 .025 8 .100 .300 .200 MAX. (Com) .225 MAX. (Mil) .065 TYP. .510 MAX. 7 .050 .045 .017 .300 TYP. 8 .100 .300 14 .200 MAX. (Com) .225 MAX. (Mil) .005 .080 .008 .360 TYP. .065 TYP. .065 TYP. DDU8F-xxD4 (Commercial SMD) DDU8F-xxMD4 (Military SMD) DATA DELAY DEVICES, INC. 3 Mt. Prospect Ave. Clifton, NJ 07013 3 DDU8F DELAY LINE AUTOMATED TESTING TEST CONDITIONS INPUT: Ambient Temperature: 25oC ± 3oC Supply Voltage (Vcc): 5.0V ± 0.1V Input Pulse: High = 3.0V ± 0.1V Low = 0.0V ± 0.1V Source Impedance: 50Ω Max. Rise/Fall Time: 3.0 ns Max. (measured between 0.6V and 2.4V ) Pulse Width: PWIN = 1.5 x Total Delay Period: PERIN = 10 x Total Delay OUTPUT: Load: Cload: Threshold: 1 FAST-TTL Gate 5pf ± 10% 1.5V (Rising & Falling) NOTE: The above conditions are for test only and do not in any way restrict the operation of the device. PRINTER COMPUTER SYSTEM REF PULSE GENERATOR OUT IN TRIG DEVICE UNDER TEST (DUT) T1 IN T2 TRIG TIME INTERVAL COUNTER T3 T4 T5 Test Setup PERIN PWIN TRISE INPUT SIGNAL TFALL VIH 2.4V 1.5V 0.6V 2.4V 1.5V 0.6V TRISE OUTPUT SIGNAL VIL TFALL VOH 1.5V 1.5V VOL Timing Diagram For Testing Doc #97012 1/28/97 DATA DELAY DEVICES, INC. Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com 4