LTC1150 ±15V Zero-Drift Operational Amplifier with Internal Capacitors DESCRIPTIO U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1150 is a high-voltage, high-performance zero-drift operational amplifier. The two sample-and-hold capacitors usually required externally by other chopper amplifiers are integrated on-chip. Further, LTC’s proprietary high-voltage CMOS structures allow the LTC1150 to operate at up to 32V total supply voltage. High Voltage Operation: ±16V No External Components Required Maximum Offset Voltage: 10µV Maximum Offset Voltage Drift: 0.05µV/°C Low Noise 1.8µVP-P (0.1Hz to 10Hz) Minimum Voltage Gain: 135dB Minimum PSRR: 120dB Minimum CMRR: 110dB Low Supply Current: 0.8mA Single Supply Operation: 4.75V to 32V Input Common Mode Range Includes Ground 200µA Supply Current with Pin 1 Grounded Typical Overload Recovery Time 20ms The LTC1150 has an offset voltage of 0.5µV, drift of 0.01µV/°C, 0.1Hz to 10Hz input noise voltage of 1.8µVP-P and a typical voltage gain of 180dB. The slew rate of 3V/µs and a gain bandwidth product of 2.5MHz are achieved with 0.8mA of supply current. Overload recovery times from positive and negative saturation conditions are 3ms and 20ms, respectively. U APPLICATIO S ■ ■ ■ ■ ■ For applications demanding low power consumption, Pin 1 can be used to program the supply current. Pin 5 is an optional AC-coupled clock input, useful for synchronization. Strain Gauge Amplifiers Electronic Scales Medical Instrumentation Thermocouple Amplifiers High Resolution Data Acquisition The LTC1150 is available in standard 8-lead, plastic dualin-line package, as well as an 8-lead SO package. The LTC1150 can be a plug-in replacement for most standard bipolar op amps with significant improvement in DC performance. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO Single Supply Instrumentation Amplifier Noise Spectrum 160 VOLTAGE NOISE DENSITY (nV√Hz) 1k 1M V+ 1M V+ 2 – 7 LTC1150 –VIN 3 + 6 1k 2 – 7 LTC1150 4 VIN 3 + 6 VOUT GAIN = 1000V/V 4 OUTPUT OFFSET ≤ 5mV TOTAL SUPPLY CURRENT DECREASES TO 400µA WHEN BOTH PIN 1s ARE GROUNDED 140 120 100 80 60 40 20 0 10 LTC1150 •TA01 100 1k 10k FREQUENCY (Hz) 100k LTC1150 •TA02 1150fb 1 LTC1150 W W W AXI U U ABSOLUTE RATI GS (Note 1) Total Supply Voltage (V + to V –) ............................... 32V Input Voltage (Note 2) .............. (V + 0.3V) to (V– –0.3V) Output Short Circuit Duration .......................... Indefinite Burn-In Voltage ....................................................... 32V Operating Temperature Range LTC1150M (OBSOLETE).....................–55°C to 125°C LTC1150C .......................................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U U W PACKAGE/ORDER I FOR ATIO TOP VIEW ORDER PART NUMBER 8 CLOCK OUT ISUPPLY 1 –IN 2 7 V+ +IN 3 6 OUT EXT CLOCK 5 IN V– 4 LTC1150CN8 TOP VIEW ISUPPLY 1 –IN 2 +IN 3 N8 PACKAGE 8-LEAD PDIP TJMAX = 110°C, θJA = 130°C/W V OBSOLETE PACKAGE – – + 4 8 CLOCK OUT 7 V+ 6 OUT 5 EXT CLOCK IN LTC1150CS8 S8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 110°C, θJA = 200°C/W LTC1150MJ8 LTC1150CJ8 J8 PACKAGE 8-LEAD CERDIP ORDER PART NUMBER 1150 Consider the N8 or S8 Package as an Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range otherwise specifications are at TA = 25°C. VS = ±15V, Pin 1 = Open, unless otherwise noted. PARAMETER CONDITIONS Input Offset Voltage (Note 3) Average Input Offset Drift (Note 3) MIN ● Long Term Offset Voltage Drift LTC1150M TYP MAX ±10 ±0.5 ±10 ±0.01 ±0.05 ±0.01 ±0.05 µV µV/°C nV/√mo ±60 ±1.5 ±20 ±200 ±0.5 pA nA ±10 ±50 ±2.5 ±10 ±100 ±1.0 pA nA ● Input Noise Current 50 UNITS ±20 ● Input Bias Current LTC1150C TYP MAX ±0.5 50 Input Offset Current Input Noise Voltage MIN RS = 100Ω, 0.1Hz to 10Hz, TC2 1.8 1.8 RS = 100Ω, 0.1Hz to 1Hz, TC2 0.6 0.6 f = 10Hz (Note 4) 1.8 1.8 fA/√Hz V– Common Mode Rejection Ratio VCM = ● 110 130 110 130 dB Power Supply Rejection Ratio VS = ±2.375V to ±16V ● 120 145 120 145 dB Large-Signal Voltage Gain RL = 10kΩ, VOUT = ±10V ● 135 180 135 180 dB ±13.5 ±14.5 ±13.5 ±14.5 V Maximum Output Voltage Swing to 12V µVP-P RL = 10kΩ RL = 10kΩ RL = 100kΩ ● 10.5/ –13.5 10.5/ –13.5 ±14.95 ±14.95 1150fb 2 LTC1150 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±15V, Pin 1 = Open, unless otherwise noted. PARAMETER CONDITIONS Slew Rate RL = 10kΩ, CL = 50pF MIN Gain Bandwidth Product Supply Current No Load No Load, Pin 1 = V – No Load LTC1150M TYP MAX MIN LTC1150C TYP MAX 3 3 V/µs 2.5 2.5 MHz 0.8 0.2 1.5 0.8 0.2 2 ● Internal Sampling Frequency UNITS 1.5 mA 2 550 550 Hz The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = 5V, Pin 1 = Open, unless otherwise noted. PARAMETER CONDITIONS Input Offset Voltage (Note 3) Average Input Offset Drift (Note 3) MIN LTC1150M TYP MAX ±0.5 ● MIN ±10 ±0.01 ±0.05 LTC1150C TYP MAX ±0.05 ±10 ±0.01 ±0.05 µV µV/°C Long Term Offset Voltage Drift 50 Input Offset Current ±10 ±60 ±10 ±60 pA Input Bias Current ±5 ±30 ±5 ±30 pA Input Noise Voltage RS = 100Ω, 0.1Hz to 10Hz, TC2 RS = 100Ω, 0.1Hz to 1Hz, TC2 50 UNITS 2.0 0.7 1.3 µV/√mo 2.0 0.7 µVP-P Input Noise Current f = 10Hz (Note 4) 1.3 fA/√Hz Common Mode Rejection Ratio VCM = 0V to 2.7V ● 106 130 106 130 dB Power Supply Rejection Ratio VS = ±2.375V to ±16V ● 120 145 120 145 dB Large-Signal Voltage Gain RL = 10kΩ, VOUT = 0.3V to 4.5V ● 115 180 115 Maximum Output Voltage Swing RL = 10kΩ RL = 100kΩ Slew Rate RL = 10kΩ, CL = 50pF Gain Bandwidth Product Supply Current No Load 180 dB 0.15 to 4.85 0.02 to 4.97 0.15 to 4.85 0.02 to 4.97 V 1.5 1.5 V/µs 1.8 1.8 MHz 0.4 ● Internal Sampling Frequency Note 1: Absolute Maximum Ratings are those values beyond which life of the device may be impaired. Note 2: Connecting any terminal to voltages greater than V + or less than V – may cause destructive latch-up. It is recommended that no sources operating from external supplies be applied prior to power-up of the LTC1150. 300 1 1.5 0.4 300 1 1.5 mA Hz Note 3: These parameters are guaranteed by design. Thermocouple effects preclude measurement of these voltage levels in high-speed automatic test systems. VOS is measured to a limit determined by test equipment capability. Note 4: Current Noise is calculated from the formula: IN = √(2q • Ib) where q = 1.6 • 10 –19 Coulomb. 1150fb 3 LTC1150 TEST CIRCUITS Offset Voltage Test Circuit DC-10Hz Noise Test Circuit 475k 1M 1k 2 – V+ 7 100k 0.1µF 6 LTC1150 3 + OUTPUT – 158k 316k 475k – LTC1150 RL 4 V 10Ω + – TO X-Y RECORDER LT1012 0.1µF 0.1µF + LTC1150 •TC01 FOR 1Hz NOISE BW, INCREASE ALL THE CAPACITORS BY A FACTOR OF 10 LTC1150 •TC02 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 1000 Supply Current vs Temperature 1400 TA = 25°C 100 700 600 500 400 80 1000 800 600 400 300 4 200 –55 8 12 16 20 24 28 32 36 TOTAL SUPPLY VOLTAGE, V+ TO V – (V) 95 5 35 65 –25 AMBIENT TEMPERATURE (°C) 1000 PIN 1 = OPEN PIN 1 = V – 0 –3 –6 VOUT = V + ISINK –9 –12 –15 PIN 1 = V – VS = ± 15V TA = 25°C 0 180 –20 200 1k 220 10M 1M 10k 100k FREQUENCY (Hz) VS = ± 15V CL = 100pF PIN 1 = –15V 100 80 60 80 100 PHASE 800 600 400 0 LTC1150 • TPC04 160 Gain/Phase vs Frequency 200 8 12 16 20 24 28 32 36 TOTAL SUPPLY VOLTAGE, V+ TO V – (V) 20 120 PIN 1 = OPEN 4 140 LTC1150 • TPC03 GAIN (dB) TA = 25°C 2 40 Supply Current vs RSET 1200 SUPPLY CURRENT (µA) 4 120 –40 100 125 100 GAIN 60 1k 10k 100k RSET, PIN 1 TO V – (Ω) 1M LTC1150 • TPC05 60 120 GAIN 40 140 20 160 0 180 –20 200 –40 100 1k 10k 100k FREQUENCY (Hz) 1M PHASE (DEGREES) SHORT-CIRCIUT OUTPUT CURRENT, IOUT (mA) Output Short-Circuit Current vs Supply Voltage VOUT = V – ISOURCE 80 LTC1150 • TPC02 LTC1150 • TPC01 6 60 VS = ± 15V CL = 100pF PHASE GAIN (dB) SUPPLY CURRENT (µA) 1200 800 200 VS = ± 15V PHASE (DEGREES) SUPPLY CURRENT (µA) 900 Gain/Phase vs Frequency 120 220 10M LTC1150 • TPC06 1150fb 4 LTC1150 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Bias Current vs Supply Voltage TA = 25°C VCM = OV 120 4 2 15 80 GAIN (dB) 6 20 PIN 1 = FLOATING RL = 100k 10 5 0 0 ±2 0 100 ± 4 ± 6 ± 8 ± 10 ± 12 ± 14 ± 16 SUPPLY VOLTAGE (V) 1k 10k 100k FREQUENCY (Hz) LTC1150 • TPC07 –1000 INPUT BIAS CURRENT (pA) 20 –IB 10 0 –10 +IB –20 140 20 160 0 180 –20 200 10k 100k FREQUENCY (Hz) 1k 220 10M 15 VCM = 0 VS = ± 15V TA = 25°C 10 –100 –IB +IB –10 5 0 –5 –10 –15 5 10 –10 –5 0 INPUT COMMON MODE VOLTAGE (V) –1 –50 –25 15 0 25 50 75 100 –15 125 0 TEMPERATURE (°C) ±2.5 ±5 ±7.5 ±10 ±12.5 SUPPLY VOLTAGE (V) LTC1150 • TPC11 CMRR vs Frequency Offset Voltage vs Sampling Frequency PSRR vs Frequency 160 160 10 POSITIVE SUPPLY, PIN 1 = OPEN 120 120 100 100 80 60 POSITIVE SUPPLY, PIN 1 = V – 80 60 40 40 20 20 NEGATIVE SUPPLY, PIN 1 = OPEN 1 10 100 1k FREQUENCY (Hz) 10k 100k LTC1150 • TPC13 PIN 1 = V – 6 4 PIN 1 = OPEN 2 NEGATIVE SUPPLY, PIN 1 = V – 0 0 0 VA = ± 15V TA = 25°C 8 OFFSET VOLTAGE (µV) 140 PSRR (dB) 140 ±15 LTC1150 • TPC12 LTC1150 • TPC10 CMRR (dB) 1M Common Mode Input Range vs Supply Voltage –30 –40 40 Input Bias Current vs Temperature VS = ± 15V TA = 25°C 30 120 LTC1150 • TPC09 COMMON MODE RANGE (V) 40 60 LTC1150 • TPC08 Input Bias Current vs Input Common Mode Voltage 100 GAIN –40 100 1M 80 PHASE PHASE (DEGREES) 8 PIN 1 = V – RL = 10k 60 VS = ±2.5V CL = 100pF 100 25 OUTPUT VOLTAGE (Vp-p) 10 INPUT BIAS CURRENT (pA) Gain/Phase vs Frequency 30 12 INPUT BIAS CURRENT (pA) Undistorted Output Swing vs Frequency 1 10 100 1k FREQUENCY (Hz) 10k 100k LTC1150 • TPC14 0 2k 1k SAMPLING FREQUENCY, fS (Hz) 3k LTC1150 • TPC15 1150fb 5 LTC1150 U W TYPICAL PERFOR A CE CHARACTERISTICS Offset Voltage Drift vs Sampling Frequency 4 VS = ± 15V 80 70 60 50 40 PIN 1 = OPEN 30 20 Sampling Frequency vs Temperature 900 VS = ± 15V TA = 25°C SAMPLING FREQUENCY (Hz) OFFSET VOLTAGE DRIFT (nV/C°) 90 10Hz PEAK-TO-PEAK NOISE (µV) 100 10Hz p-p Noise vs Sampling Frequency 3 2 1 VS = ± 15V 800 700 600 500 400 10 0 100 1k SAMPLING FREQUENCY, fS (Hz) 10k LTC1150 • TPC16 0 100 1k SAMPLING FREQUENCY, fS (Hz) 10k LTC1150 • TPC17 300 –55 95 5 35 65 –25 AMBIENT TEMPERATURE (°C) 125 LTC1150 • TPC18 Large-Signal Transient Response Large-Signal Transient Response, Pin 1 = V – Small-Signal Transient Response VS = ±15V, AV = 1, CL = 100pF, RL = 10kΩ VS = ±15V, AV = 1, CL = 100pF, PIN 1 = V – VS = ±15V, AV = 1, CL = 100pF, RL = 10kΩ Small-Signal Transient Response, Pin 1 = V – Overload Recovery from Negative Saturation Overload Recovery from Positive Saturation VS = ±15V, AV = 1, CL = 100pF, RL = 10kΩ, PIN 1 = V – VS = ±15V, AV = –100, 2ms/DIV VS = ±15V, AV = –100, 2ms/DIV 1150fb 6 LTC1150 U W TYPICAL PERFOR A CE CHARACTERISTICS 0.1Hz to 10Hz Noise, V = ±15V, TA = 25°C, Internal Clock 2.0µVP-P 1µV 1s 10s LTC1150 • TPC25 0.1Hz to 10Hz Noise, V = ±15V, TA = 25°C, fS = 1800Hz 1.0µVP-P 1µV 1s 10s LTC1150 • TPC26 0.1Hz to 1Hz Noise, V = ±15V, TA = 25°C, Internal Clock 700nVP-P 500nV 10s 100s LTC1150 • TPC27 1150fb 7 LTC1150 U W TYPICAL PERFOR A CE CHARACTERISTICS 0.1Hz to 1Hz Noise, V = ±15V, TA = 25°C, fS = 1800Hz 300nVP-P 500nV 100s 10s U U PI DESCRIPTIO S LTC1150 • TPC28 8-Pin Packages ISUPPLY (Pin 1): Supply Current Programming. The supply current can be programmed through Pin 1. When Pin 1 is left open or tied to V+, the supply current defaults to 800µA. Tying a resistor between Pin 1 and Pin 4, the negative supply pin, will reduce the supply current. The supply current, as a function of the resistor value, is shown in Typical Performance Characteristics. –IN (Pin 2): Inverting Input. simplified interface requirements. The amplitude of the clock input signal needs to be greater than 2V and the voltage level has to be within the supply voltage range. Duty cycle is not critical. The internal chopping frequency is the external clock frequency divided by four. When frequency of the external clock falls below 100Hz (internal chopping at 25Hz), the internal oscillator takes over and the circuit chops at 550Hz. +IN (Pin 3): Noninverting Input. OUT (Pin 6): Output. V– (Pin 4): Negative Supply. V+ (Pin 7): Positive Supply. EXT CLOCK IN (Pin 5): Optional External Clock Input. The LTC1150 has an internal oscillator to control the circuit operation of the amplifier if Pin 5 is left open or biased at any DC voltage in the supply voltage range. When an external clock is desirable, it can be applied to Pin 5. The applied clock is AC-coupled to the internal circuitry to CLOCK OUT (Pin 8): Clock Output. The signal coming out of this pin is at the internal oscillator frequency of about 2.2kHz (four times the chopping frequency) and has voltage levels at VH = VS and VL = VS – 4.6. If the circuit is driven by an external clock, Pin 8 is pulled up to VS. 1150fb 8 LTC1150 U W U U APPLICATIO S I FOR ATIO ACHIEVING PICOAMPERE/MICROVOLT PERFORMANCE Picoamperes In order to realize the picoampere level of accuracy of the LTC1150, proper care must be exercised. Leakage currents in circuitry external to the amplifier can significantly degrade performance. High quality insulation should be used (e.g., Teflon, Kel-F); cleaning of all insulating surfaces to remove fluxes and other residues will probably be necessary–particularly for high temperature performance. Surface coating may be necessary to provide a moisture barrier in high humidity environments. Board leakage can be minimized by encircling the input connections with a guard ring operated at a potential close to that of the inputs: in inverting configurations the guard ring should be tied to ground; in noninverting connections to the inverting input. Guarding both sides of the printed circuit board is required. Bulk leakage reduction depends on the guard ring width. number of junctions in the amplifier’s input signal path. Avoid connectors, sockets, switches, and relays where possible. In instances where this is not possible, attempt to balance the number and type of junctions so that differential cancellation occurs. Doing this may involve deliberately introducing junctions to offset unavoidable junctions. Figure 1 is an example of the introduction of an unnecessary resistor to promote differential thermal balance. Maintaining compensating junctions in close physical proximity will keep them at the same temperature and reduce thermal EMF errors. NOMINALLY UNNECESSARY RESISTOR USED TO THERMALLY BALANCE OTHER INPUT RESISTOR LEAD WIRE/SOLDER COPPER TRACE JUNCTION + LTC1150 RESISTOR LEAD, SOLDER, COPPER TRACE JUNCTION OUTPUT – Microvolts Thermocouple effects must be considered if the LTC1150’s ultralow drift is to be fully utilized. Any connection of dissimilar metals forms a thermoelectric junction producing an electric potential which varies with temperature (Seebeck effect). As temperature sensors, thermocouples exploit this phenomenon to produce useful information. In low drift amplifier circuits the effect is a primary source of error. Connectors, switches, relay contacts, sockets, resistors, solder, and even copper wire are all candidates for thermal EMF generation. Junctions of copper wire from different manufacturers can generate thermal EMFs of 200nV/°C—four times the maximum drift specification of the LTC1150. The copper/kovar junction, formed when wire or printed circuit traces contact a package lead, has a thermal EMF of approximately 35µV/°C—700 times the maximum drift specification of the LTC1150. Minimizing thermal EMF-induced errors is possible if judicious attention is given to circuit board layout and component selection. It is good practice to minimize the LTC1150 •AI01 Figure 1. Extra Resistors Cancel Thermal EMF When connectors, switches, relays and/or sockets are necessary, they should be selected for low thermal EMF activity. The same techniques of thermally-balancing and coupling the matching junctions are effective in reducing the thermal EMF errors of these components. Resistors are another source of thermal EMF errors. Table 1 shows the thermal EMF generated for different resistors. The temperature gradient across the resistor is important, not the ambient temperature. There are two junctions formed at each end of the resistor and if these junctions are at the same temperature, their thermal EMFs will cancel each other. The thermal EMF numbers are approximate and vary with resistor value. High values give higher thermal EMF. 1150fb 9 LTC1150 U W U U APPLICATIO S I FOR ATIO LEVEL SHIFTING THE CLOCK Table 1. Resistor Thermal EMF RESISTOR TYPE THERMAL EMF/°C GRADIENT Tin Oxide ~mV/°C Carbon Composition ~450µV/°C Metal Film ~20µV/°C WireWound Evenohm Manganin ~2µV/°C ~2µV/°C Level shifting is needed if the clock output of the LTC1150 in ±15V operation must interface to regular 5V logic circuits. Figures 2 and 3 show some typical level shifting circuits. When operated from single 5V or ±5V supplies, the LTC1150 clock output at Pin 8 can interface to TTL or CMOS inputs directly. PACKAGE-INDUCED OFFSET VOLTAGE Package-induced thermal EMF effects are another important source of errors. It arises at the copper/kovar junctions formed when wire or printed circuit traces contact a package lead. Like all the previously mentioned thermal EMF effects, it is outside the LTC1150’s offset nulling loop and cannot be cancelled. Metal can H packages exhibit the worst warm-up drift. The input offset voltage specification of the LTC1150 is actually set by the package-induced warm-up drift rather than by the circuit itself. The thermal time constant ranges from 0.5 to 3 minutes, depending on package type. LOW SUPPLY OPERATION The minimum supply for proper operation of the LTC1150 is typically below 4.0V (±2.0V). In single supply applications, PSRR is guaranteed down to 4.7V (±2.35V) to ensure proper operation down to the minimum TTL specified voltage of 4.75V. 15V 10k 2 ALIASING 7 – 5V 8 6 LTC1150 3 Like all sampled data systems, the LTC1150 exhibits aliasing behavior at input frequencies near the sampling frequency. The LTC1150 includes a high-frequency correction loop which minimizes this effect; as a result, aliasing is not a problem for most applications. LOGIC CIRCUIT + 4 10k –15V LTC1150 • AI02 Figure 2. Output Level Shift (Option 1) For a complete discussion of the correction circuitry and aliasing behavior, please refer to the LTC1051/53 data sheet. 5V 15V 5V 100pF SYNCHRONIZATION OF MULTIPLE LTC115O’S When synchronization of several LTC1150’s is required, one of the LTC1150’s can be used to provide the “master” clock to control over 100 “slave” LTC1150’s. The master clock, coming from Pin 8 of the master LTC1150, can directly drive Pin 5 of the slaves. Note that Pin 8 of the slave LTC1150’s will be pulled up to VS. 10k 2 – 7 8 LTC1150 3 LOGIC CIRCUIT 6 + 4 10k –15V GND LTC1150 • AI03 Figure 3. Output Level Shift (Option 2) If all the LTC1150’s are to be synchronized with an external clock, then the external clock should drive Pin 5 of all the LTC1150’s. 1150fb 10 LTC1150 U TYPICAL APPLICATIO S Low Level Photodetector 15pF 1M 10Ω V+ HP 5082-4204 2 IP – LTC1150 3 + 10k 7 6 OUTPUT = IP • 10 9Ω 4 LTC1150 • TA03 Ground Force Reference 1k 15V 2 – 7 LTC1150 3 SINGLE POINT SENSE GROUND + 15V 1000pF 6 LT1010 4 –15V –15V FORCED GROUND LTC1150 • TA04 APPLICATION: TO FORCE TWO GROUND POINTS IN A SYSTEM WITHIN 5µV 1150fb 11 LTC1150 U TYPICAL APPLICATIO S Paralleling to Improve Noise CLK IN 10k MEASURED NOISE VOS = 1.1µV CLK 10Ω – 10k LTC1150 + 10k 10Ω – 10k FREE RUN 10Hz = 700nVP-P 1Hz = 200nVP-P CLK DRIVEN 1800Hz 10Hz = 360nVP-P 1Hz = 160nVP-P VOS = 10µV 25k LTC1150 + 10k 10Ω – – LTC1150 10k VOUT = 10k VIN + LTC1150 + IN 10k 10Ω – 10k LTC1150 + LTC1150 • TA05 Battery Discharge Monitor OPEN AT t = 0 C + R2 2 – LTC1150 3 6 + VOUT = ERROR ≤ I LOAD 5µV IR1 + –IR1 t R2C 30pA R2 I R1 R1 LTC1150 • TA06 1150fb 12 LTC1150 U PACKAGE DESCRIPTIO J8 Package 8-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) CORNER LEADS OPTION (4 PLCS) .023 – .045 (0.584 – 1.143) HALF LEAD OPTION .045 – .068 (1.143 – 1.650) FULL LEAD OPTION .005 (0.127) MIN .405 (10.287) MAX 8 7 6 5 .025 (0.635) RAD TYP .220 – .310 (5.588 – 7.874) 1 2 .300 BSC (7.62 BSC) 3 4 .200 (5.080) MAX .015 – .060 (0.381 – 1.524) .008 – .018 (0.203 – 0.457) 0° – 15° NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS .045 – .065 (1.143 – 1.651) .014 – .026 (0.360 – 0.660) .100 (2.54) BSC .125 3.175 MIN J8 0801 OBSOLETE PACKAGE 1150fb 13 LTC1150 U PACKAGE DESCRIPTIO N8 Package 8-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .400* (10.160) MAX 8 7 6 5 1 2 3 4 .255 ± .015* (6.477 ± 0.381) .300 – .325 (7.620 – 8.255) .008 – .015 (0.203 – 0.381) +.035 .325 –.015 ( 8.255 +0.889 –0.381 ) .045 – .065 (1.143 – 1.651) .130 ± .005 (3.302 ± 0.127) .065 (1.651) TYP .100 (2.54) BSC .120 (3.048) .020 MIN (0.508) MIN .018 ± .003 (0.457 ± 0.076) N8 1002 NOTE: 1. DIMENSIONS ARE INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) 1150fb 14 LTC1150 U PACKAGE DESCRIPTIO S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) .189 – .197 (4.801 – 5.004) NOTE 3 .045 ±.005 .050 BSC 8 7 6 5 N N .245 MIN .160 ±.005 .150 – .157 (3.810 – 3.988) NOTE 3 .228 – .244 (5.791 – 6.197) 1 2 3 N/2 N/2 .030 ±.005 TYP RECOMMENDED SOLDER PAD LAYOUT .010 – .020 × 45° (0.254 – 0.508) .008 – .010 (0.203 – 0.254) .053 – .069 (1.346 – 1.752) 0°– 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. DIMENSIONS IN 1 .014 – .019 (0.355 – 0.483) TYP INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 2 3 4 .004 – .010 (0.101 – 0.254) .050 (1.270) BSC SO8 0502 1150fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LTC1150 U TYPICAL APPLICATIO DC Stabilized, Low Noise Amplifier 15V 3 INPUT 7 + 6 LTC1150 2 – 4 –15V 0.01µF 15V 130Ω 3 100k 68Ω 1 + 8 LT1028 2 – 15V 7 4 6 OUTPUT 10k –15V (A = 1000) 10Ω LTC1150 • TA07 1150fb 16 Linear Technology Corporation LW/TP 1202 1K REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 1991