Fujitsu MB90F809S 16-bit microcontroller Datasheet

FUJITSU MICROELECTRONICS
DATA SHEET
DS07-13733-6E
16-bit Microcontroller
CMOS
F2MC-16LX MB90800 Series
MB90803/803S/F803/F803S/F804-101/
MB90F804-201/F809/F809S/V800
■ DESCRIPTION
The MB90800 series is a general-purpose 16-bit microcontroller that has been developed for high-speed realtime processing required for industrial and office automation equipment and process control, etc. The LCD
controller of 48 segment four common is built into.
Instruction set has taken over the same AT architecture as in the F2MC-8L and F2MC-16L, and is further enhanced
to support high level languages, extend addressing mode, enhanced divide/multiply instructions with sign and
enrichment of bit processing. In addition, long word processing is now available by introducing a 32-bit accumulator.
Note: F2MC is the abbreviation of Fujitsu Flexible Microcontroller.
■ FEATURES
• Clock
• Built-in PLL clock frequency multiplication circuit
• Operating clock (PLL clock) : divided-by-2 of oscillation (at oscillation of 6.25 MHz) or
1 to 4 times the oscillation (at oscillation of 6.25 MHz to 25 MHz).
• Minimum instruction execution time of 40.0 ns (at oscillation of 6.25 MHz, four times the PLL clock, operation
at Vcc = 3.3 V)
• The maximum memory space:16 Mbytes
• 24-bit internal addressing
• Bank addressing
(Continued)
For the information for microcontroller supports, see the following web site.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2005-2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.9
MB90800 Series
(Continued)
• Optimized instruction set for controller applications
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• High code efficiency
• Enhanced high-precision computing with 32-bit accumulator
• Enhanced Multiply/Divide instructions with sign and the RETI instruction
• Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Instruction set has symmetry and barrel shift instructions
• Program Patch Function (2 address pointer)
• 4-byte instruction queue
• Interrupt function
• The priority level can be set to programmable.
• Interrupt function with 32 factors
• Data transfer function
• Expanded intelligent I/O service function (EI2OS): Maximum of 16 channels
• Low Power Consumption Mode
• Sleep mode (a mode that halts CPU operating clock)
• Time-base timer mode (a mode that operates oscillation clock and time-base timer)
• Watch mode (mode in which only the subclock and watch timers operate)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking mode (operating CPU at each set cycle)
• Package
• QFP-100 (FPT-100P-M06 : 0.65 mm lead pitch)
• Process : CMOS technology
2
DS07-13733-6E
MB90800 Series
■ PRODUCT LINEUP
Part number
Item
Type
System clock
Sub clock
MB90V800101/201
MB90F804101/201
MB90803/
MB90803S
Evaluation
product
Flash
memory
products
Mask ROM products
MB90F803/
MB90F803S
MB90F809/
MB90F809S
Flash memory products
On-chip PLL clock multiplication method( × 1, × 2, × 3, × 4, 1/2 when PLL stops)
Minimum instruction execution time of 40.0 ns
(at oscillation of 6.25 MHz, four times the PLL clock)
With sub clock:
201 option
Without sub clock: 101 option
With sub clock:
Part number of products without "S" suffix
Without sub clock: Part number of products with "S" suffix
ROM capacity
No
256 Kbytes
128 Kbytes
128 Kbytes
dual
operation
192 Kbytes
RAM capacity
28 Kbytes
16 Kbytes
4 Kbytes
4 Kbytes
10 Kbytes
CPU functions
Number of basic instructions
: 351
Minimum instruction execution time : 40.0 ns/6.25 MHz oscillator
(When four times is used : machine clock
25 MHz, Power supply voltage : 3.3 V ± 0.3 V)
Addressing type
: 23 types
Program Patch Function
: 2 address pointers
The maximum memory space
: 16 Mbytes
Ports
I/O port (CMOS) 68 ports (shared with resources), (70 ports when the subclock is not used)
LCD
controller/driver
Segment driver that can drive the LCD panel (liquid crystal display) directly, and common driver 48 SEG × 4 COM
16-bit
input/
output
timer
16-bit
free-run
timer
1 channel
Overflow interrupt
Output
compare
(OCU)
2 channels
Pin input factor: matching of the compare register
Input
capture
(ICU)
2 channels
Rewriting a register value upon a pin input (rising edge, falling edge, or both edges)
16-bit
Reload Timer
16-bit reload timer operation (toggle output, single shot output selectable)
The event count function is optional. The event count function is optional.
Three channels are built in.
16-bit
PPG timer
Output pin × 2 ports
Operating clock frequency : fcp, fcp/22, fcp/24, fcp/26
Two channels are built in.
Time-base timer
1 channel
Watchdog timer
1 channel
Timer clock
output
circuit
Clock with a frequency of external input clock divided by 16/32/64/128 can be
output externally.
I2C bus
I2C Interface. 1 channel is built-in.
(Continued)
DS07-13733-6E
3
MB90800 Series
(Continued)
Part number
Item
MB90V800101/201
MB90F804101/201
MB90803/
MB90803S
MB90F803/
MB90F803S
8/10-bit
A/D converter
12 channels (input multiplex)
The 8-bit resolution or 10-bit resolution can be set.
Conversion time : 5.9 μs (When machine clock 16.8 MHz works).
UART
Full-duplex double buffer
Asynchronous/synchronous transmit (with start/stop bits) are supported.
Two channels are built in.
Extended I/O serial
interface
MB90F809/
MB90F809S
Two channels are built in.
Interrupt delay
interrupt
One channel
DTP/External
interrupt
4 channels
Interrupt causes : “L”→“H” edge/“H”→“L” edge/“L” level/“H” level selectable
Low Power
Sleep mode/Time-base timer mode/Watch mode/Stop mode/CPU intermittent mode
Consumption Mode
Process
Operating voltage
4
CMOS
2.7 V to 3.6 V
DS07-13733-6E
MB90800 Series
■ PIN ASSIGNMENT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P23/SEG31
P22/SEG30
P21/SEG29
P20/SEG28
P17/SEG27
P16/SEG26
P15/SEG25
X0
X1
VSS
VCC
P14/SEG24
P13/SEG23
P12/SEG22
P11/SEG21
P10/SEG20
P07/SEG19
P06/SEG18
P05/SEG17
P04/SEG16
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
QFP-100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P03/SEG15
P02/SEG14
P01/SEG13
P00/SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
VSS
VCC
SEG1
SEG0
P84/COM3
P83/COM2
COM1
COM0
V3
V2/P82
V1/P81
V0/P80
RST
MD0
MD1
MD2
P56/SO0
AVCC
P57/SI1
P76
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5/INT0
P66/AN6/INT1
P67/AN7/INT2
VSS
P70/AN8/INT3
P71/AN9/SC1
P72/AN10/SO1
P73/AN11/SI2
P74/SDA/SC2
P75/SCL/SO2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P24/SEG32
P25/SEG33
P26/SEG34
P27/SEG35
P30/SEG36/SO3
P31/SEG37/SC3
P32/SEG38/SI3
P33/SEG39/TMCK
P34/SEG40/IC0
P35/SEG41/IC1
P36/SEG42/OCU0
P37SEG43/OCU1
X0A/P90
X1A/P91
VCC
VSS
P40/LED0
P41/LED1
P42/LED2
P43/LED3
P44/LED4
P45/LED5/TOT0
P46/LED6/TOT1
P47/LED7/TOT2
P50/SEG44/TIN0
P51/SEG45/TIN1
P52/SEG46/TIN2/PPG0
P53/SEG47/PPG1
P54/SI0
P55/SC0
(FPT-100P-M06)
DS07-13733-6E
5
MB90800 Series
■ PIN DESCRIPTION
I/O
Status/function
Circuit
at reset
Type*
Pin No.
Pin Name
92, 93
X1, X0
A
Oscillation
status
It is a terminal which connects the oscillator.
When connecting an external clock, leave the x1 pin
unconnected.
X0A, X1A
B
Oscillation
status
It is 32 kHz oscillation pin.
(Dual-line model)
P90, P91
G
Port input
(High-Z)
General purpose input/output port.
(Single-line model)
51
MD2
M
Mode Pins
Input pin for selecting operation mode.
Connect directly to Vss.
52, 53
MD1, MD0
L
Mode Pins
Input pin for selecting operation mode.
Connect directly to Vcc.
54
RST
K
Reset input
External reset input pin.
63, 64,
67 to 76
SEG0
to
SEG11
D
LCD SEG
output
13, 14
77 to 84
SEG12
to
SEG19
85 to 89,
94 to 96
E
General purpose input/output port.
A segment output terminal of the LCD controller/
driver.
E
P10 to P17
97 to 100,
1 to 4
SEG28
to
SEG35
General purpose input/output port.
Port input
(High-Z)
SEG36
6
P30
A segment output terminal of the LCD controller/
driver.
E
P20 to P27
5
A segment output terminal of the LCD controller/
driver.
A segment output terminal of the LCD controller/
driver.
P00 to P07
SEG20
to
SEG27
Function
E
General purpose input/output port.
A segment output terminal of the LCD controller/
driver.
General purpose input/output port.
SO3
Serial data output pin of serial I/O ch.3.
Valid when serial data output of serial I/O ch.3 is
enabled.
SEG37
A segment output terminal of the LCD controller/
driver.
P31
SC3
E
General purpose input/output port.
Serial clock I/O pin of serial I/O ch.3.
Valid when serial clock output of serial I/O ch.3 is
enabled.
(Continued)
6
DS07-13733-6E
MB90800 Series
Pin No.
Pin Name
I/O
Status/function
Circuit
at reset
Type*
A segment output terminal of the LCD controller/
driver.
SEG38
7
P32
General purpose input/output port.
E
Serial data input pin of serial I/O ch.3.
This pin may be used during serial I/O ch.3 in input
mode, so it cannot use as other pin function.
SI3
A segment output terminal of the LCD controller/
driver.
SEG39
8
9, 10
11, 12
P33
E
Timer clock output pin.
It is effective when permitting the power output.
SEG40,
SEG41
A segment output terminal of the LCD controller/
driver.
P34, P35
E
External trigger input pin of input capture ch.0/ch.1.
SEG42,
SEG43
A segment output terminal of the LCD controller/
driver.
P36, P37
E
LED0
to
LED4
P45 to P47
General purpose input/output port.
Port input
(High-Z)
F
Output terminal for the output compares ch.0/ch.1.
It is a output terminal for LED (IOL = 15 mA).
General purpose input/output port.
LED5
to
LED7
25, 26
General purpose input/output port.
IC0, IC1
P40 to P44
22 to 24
General purpose input/output port.
TMCK
OCU0,
OCU1
17 to 21
Function
It is a output terminal for LED (IOL = 15 mA).
F
General purpose input/output port.
TOT0
to
TOT2
External event output pin of reload timer ch.0 to
ch.2.
It is effective when permitting the external event
output.
SEG44,
SEG45
A segment output terminal of the LCD controller/
driver.
P50, P51
TIN0,
TIN1
E
General purpose input/output port.
External clock input pin of reload timer ch.0, ch.1.
It is effective when permitting the external clock
input.
(Continued)
DS07-13733-6E
7
MB90800 Series
Pin No.
Pin Name
I/O
Status/function
Circuit
at reset
Type*
A segment output terminal of the LCD controller/
driver.
SEG46
P52
27
28
General purpose input/output port.
E
TIN2
External clock input pin of reload timer ch.2.
It is effective when permitting the external clock
input.
PPG0
PPG timer (ch.0) output pin.
SEG47
A segment output terminal of the LCD controller/
driver.
P53
E
General purpose input/output port.
PPG1
29
SIO
PPG (ch.1) timer output pin.
Serial data input pin of UART ch.0.
This pin may be used during UART ch.0 in receiving
mode, so it cannot use as other pin function.
G
P54
30
31
33
Function
SC0
General purpose input/output port.
Port input
(High-Z)
G
Serial clock input/output pin of UART ch.0.
It is effective when permitting the serial clock output
of UART ch.0.
P55
General purpose input/output port.
SO0
Serial data output pin of UART ch.0.
It is effective when permitting the serial clock output
of UART ch.0.
G
P56
General purpose input/output port.
SI1
Serial data input pin of UART ch.1.
This pin may be used during UART ch.1 in receiving
mode, so it cannot use as other pin function.
G
P57
34
P76
36 to 40
AN0
to
AN4
P60 to P64
General purpose input/output port.
G
General purpose input/output port.
I
Analog input pin ch.0 to ch.4 of A/D
converter. Enabled when analog input setting is
“enabled”(set by ADER).
General purpose input/output port.
(Continued)
8
DS07-13733-6E
MB90800 Series
Pin No.
Pin Name
I/O
Circuit
Type*
Status/function
at reset
AN5
to
AN7
41 to 43
P65 to P67
Analog input pin ch.5 to ch.7 of A/D
converter. Enabled when analog input setting is
“enabled”.
I
INT0
to
INT2
General purpose input/output port.
Analog input
(High-Z)
46
47
48
P70
Functions as an external interrupt ch.0 to ch.2 input
pin.
Analog input pin ch.8 of A/D converter.
Enabled when analog input setting is “enabled”.
AN8
45
Function
I
General purpose input/output port.
INT3
Functions as an external interrupt ch.3 input pin.
AN9
Analog input pin ch.9 of A/D converter.
Enabled when analog input setting is “enabled”.
P71
General purpose input/output port.
I
SC1
Serial clock input/output pin of UART ch.1.
It is effective when permitting the serial clock output
of UART ch.1.
AN10
Analog input pin ch.10 of A/D converter.
Enabled when analog input setting is “enabled”.
P72
I
Port input
(High-Z)
General purpose input/output port.
SO1
Serial data output pin of serial I/O ch.1.
Valid when serial data output of serial I/O ch.1 is
enabled.
AN11
Analog input pin ch.11 of A/D converter.
Enabled when analog input setting is “enabled”.
P73
SI2
I
General purpose input/output port.
Serial data input pin of serial I/O ch.2.
This pin may be used during serial I/O ch.2 in input
mode, so it cannot use as other pin function.
(Continued)
DS07-13733-6E
9
MB90800 Series
(Continued)
Pin No.
Pin Name
I/O
Status/function
Circuit
at reset
Type*
Data input/output pin of I2C Interface.
This pin is enabled when the I2C interface is operated.
While the I2C interface is running, the port must be set
for input use.
SDA
49
P74
General purpose input/output port.
(N-ch open-drain, withstand voltage of 5 V.)
H
SC2
Port input
(High-Z)
SCL
50
P75
H
55 to 57
COM0,
COM1
Clock input/output pin of I2C Interface.
This pin is enabled when the I2C interface is operated.
While the I2C interface is running, the port must be set
for input use.
Serial data output pin of serial I/O ch.2.
Valid when serial data output of serial I/O ch.2 is
enabled.
J
P80 to P82
59, 60
Serial clock input pin of serial I/O ch.2.
Valid when serial clock output of serial I/O ch.2 is
enabled.
General purpose input/output port.
(N-ch open-drain, withstand voltage of 5 V.)
SO2
V0 to V2
Function
LCD controller/driver.
LCD drive power Reference power terminals of LCD controller/driver.
supply input
General purpose input/output port.
D
LCD COM
output
Port input
(High-Z)
P83, P84
A common output terminal of the LCD controller/
driver.
General purpose input/output port.
61, 62
COM2,
COM3
E
32
AVCC
C
A/D converter exclusive power supply input pin.
35
AVSS
C
A/D converter-exclusive GND power supply pin.
58
V3
J
15, 65, 90
VCC
⎯
These are power supply input pins.
16, 44,
66, 91
VSS
⎯
GND power supply pin.
Power supply
A common output terminal of the LCD controller/
driver.
LCD controller/driver
Reference power terminals of LCD controller/driver.
* : Refer to “■ I/O CIRCUIT TYPE” for details on the I/O circuit types.
10
DS07-13733-6E
MB90800 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
X1
Clock input
Oscillation feedback resistance :
1 MΩ approx.
P-ch N-ch
X0
Standby control signal
B
X1A
Clock input
Low-rate oscillation feedback resistor,
approx.10 MΩ
P-ch N-ch
X0A
Standby control signal
C
Analog power supply input protection
circuit
P-ch
AVP
N-ch
D
LCDC output
P-ch
R
LCDC output
N-ch
E
• CMOS output
• LCDC output
• CMOS hysteresis input
(With input interception function at
standby)
P-ch
N-ch
R
LCDC output
R
CMOS hysteresis input
Standby control signal
(Continued)
DS07-13733-6E
11
MB90800 Series
Type
Circuit
Remarks
F
• CMOS output
(Heavy-current IOL =15 mA for LED
drive)
• CMOS hysteresis input
(With input interception function at
standby)
P-ch
N-ch
R
CMOS hysteresis input
Standby control signal
G
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
P-ch
N-ch
R
CMOS hysteresis input
Standby control signal
H
N-ch
Notes : • The I/O port and internal resources
share one output buffer for their
outputs.
• The I/O port and internal resources
share one input buffer for their
input.
• CMOS hysteresis input
(With input interception function at
standby)
• N-ch open drain output
Nout
R
CMOS hysteresis input
Standby control signal
I
P-ch
N-ch
R
CMOS hysteresis input
Standby control signal
A/D converter
Analog input
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
• Analog input
(If the bit of analog input enable
register = 1, the analog input of A/D
converter is enabled.)
Notes : • The I/O port and internal resources
share one output buffer for their
outputs.
• The I/O port and internal resources
share one input buffer for their
inputs.
(Continued)
12
DS07-13733-6E
MB90800 Series
(Continued)
Type
Circuit
Remarks
J
• CMOS output
• CMOS hysteresis input
(With input interception function at
standby)
• LCD drive power supply input
P-ch
N-ch
R
CMOS hysteresis input
Standby control signal
LCD drive power supply
K
R
CMOS hysteresis input with pull-up
resistor.
R
Reset input
L
CMOS hysteresis input
R
CMOS hysteresis input
M
R
CMOS hysteresis input
CMOS hysteresis input with pull-down
resistor
R
DS07-13733-6E
13
MB90800 Series
■ HANDLING DEVICES
1. Preventing Latch-up, Turning on Power Supply
Latch-up may occur on CMOS IC under the following conditions:
• If a voltage higher than VCC or lower than VSS is applied to input and output pins,
• A voltage higher than the rated voltage is applied between VCC pin and VSS pin.
• If the AVCC power supply is turned on before the VCC voltage.
Ensure that you apply a voltage to the analog power supply at the same time as VCC or after you turn on the
digital power supply (when you perform power-off, turn off the analog power supply first or at the same time as
VCC and the digital power supply).
When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When
using CMOS IC, take great care to prevent the occurrence of latch-up.
2. Treatment of unused pins
If unused input pins are left open, they may cause abnormal operation or latch-up which may lead to permanent
damage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least
2 kΩ.
Any unused input/output pins should be left open in output status, or if found set to input status, they should be
treated in the same way as input pins.
Any unused output pins should be left open.
3. Treatment of A/D converter power supply pins
Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = VSS.
4. About the attention when the external clock is used
In using an external clock, drive pin X0 only and leave pin X1 open.
The example of using an external clock is shown below.
X0
MB90800 Series
OPEN
X1
Please set X0A = GND and X1A = open without subclock mode.
The following figure shows the using sample.
X0A
MB90800 Series
OPEN
14
X1A
DS07-13733-6E
MB90800 Series
5. Treatment of power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device
to avoid abnormal operations including latch-up. However, you must connect all power supply pins to external
power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of
strobe signals caused by the rise in the ground level, and to conform to the total output current rating.
Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance.
It is also advisable to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between VCC
and VSS near this device.
6. About Crystal oscillators circuit
Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1 pins and X0A/X1A pins, the crystal oscillator (or the ceramic oscillator) and the bypass
capacitor to ground are located as close to the device as possible.
It is strongly recommended to design the PC board artwork with the X0/X1 pins and X0A/X1A pins surrounded
by ground plane because stable operation can be expected with such a layout.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
7. Caution on Operations during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
8. Stabilization of Supply Power Supply
A sudden change in the supply voltage may cause the device to malfunction even within the VCC supply voltage
operating range.Therefore, the VCC supply voltage should be stabilized. For reference, the supply voltage should
be controlled so that VCC ripple variations (peak- to-peak values) at commercial frequencies (50 Hz/60 Hz) fall
below 10% of the standard VCC supply voltage and the coefficient of fluctuation does not exceed 0.1 V/ms at
instantaneous power switching.
9. Note on Using the two-subsystem product as one-subsystem product
If you are using only one subsystem of the MB90800 series that come in one two-subsystem product, use it with
X0A = VSS and X1A = OPEN.
10. Write to FLASH
Ensure that you must write to FLASH at the operating voltage VCC = 3.0 V to 3.6 V.
DS07-13733-6E
15
MB90800 Series
■ BLOCK DIAGRAM
X0, X1
X0A*, X1A*
RST
Clock control
circuit
RAM
(2/4/10/16/28 Kbytes)
V0/P80
V1/P81
V2/P82
V3
COM0
COM1
P83/COM2
P84/COM3
P10 to P17/
SEG20 to SEG27
P20 to P27/
SEG28 to SEG35
P30/SEG36/SO3
P31/SEG37/SC3
P32/SEG38/SI3
P33/SEG39/TMCK
P34/SEG40/IC0
P35/SEG41/IC1
P36/SEG42/OCU0
P37/SEG43/OCU1
ROM/Flash
(128/192/256 Kbytes)
F2MC-16LX bus
Port
8
12
SEG0 to SEG11
P00 to P07/
SEG12 to SEG19
8
8
8
Port
0
LCD
Controller/
Driver
P50/SEG44/TIN0
P51/SEG45/TIN1
P52/SEG46/TIN2/PPG0
P53/SEG47/PPG1
P54/SI0
P55/SC0
P56/SO0
P57/SI1
16
Interrupt controller
Port
1
I2C
Port
2
Port
6
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5/INT0
P66/AN6/INT1
P67/AN7/INT2
Port
7
P70/AN8/INT3
P71/AN9/SC1
P72/AN10/SO1
P73/AN11/SI2
P74/SDA/SC2
P75/SCL/SO2
P76
Port
9
P90*
P91*
8/10 bits PPG
A/D converter
External interrupt
(4 channels)
Serial I/O 2/3
Port
3
Prescaler
2/3
OCU0/OCU1
Free-run timer
P40/LED0
P41/LED1
P42/LED2
P43/LED3
P44/LED4
P45/LED5/TOT0
P46/LED6/TOT1
P47/LED7/TOT2
CPU F2MC-16LX
core
ICU0/ICU1
Port
4
Timer clock output
Reload timer
0/1/2
* : X0A/X1A and P90/P91 can be
switched by the option.
X0A/X1A: With sub clock
Part number of products without “S” suffix/
201 option
P90/P91: Without sub clock
Part number of products with “S” suffix/
101 option
PPG0/PPG1
Port
5
UART0/UART1
Notes:
• Built-in ROM of MB90V800 (evaluation) is not
exist.
• The device has built-in RAM of 28 Kbytes.
Prescaler
0/1
DS07-13733-6E
MB90800 Series
■ MEMORY MAP
ROM mirror function
FFFFFFH
ROM area
Address #2
00FFFFH
ROM mirror area
32 Kbytes
008000H
007917H
007900H
Extended I/O area 2
Address #1
RAM area
Register
000100H
0000CFH
0000C0H
0000BFH
000000H
Extended I/O area 1
I/O area
Part number
Address #1
Address #2
MB90803/S,
MB90F803/S
0010FFH
FE0000H
MB90F809/S
0028FFH
FD0000H
MB90F804-101/201
0040FFH
FC0000H
MB90V800-101/201
0070FFH
F80000H*
* : ROM is not built into MB90V800.
F80000H is ROM decipherment region on the tool side.
Memory Map of MB90800 Series
Notes : • When the ROM mirror function register has been set, the mirror image data at higher addresses
( “FF4000H to FFFFFFH” ) of bank FF is visible from the higher addresses ( “008000H to 00FFFFH”) of
bank 00.
• The ROM mirror function is for using the C compiler small model.
• The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Note that because the ROM
area of bank FF exceeds.
32 Kbytes, all data in the ROM area cannot be shown in mirror image in bank 00.
• When the C compiler small model is used, the data table can be shown as mirror image at “008000H to
00FFFFH ”by storing the data table at “FF8000H to FFFFFFH”. Therefore, data tables in the ROM area
can be referenced without declaring the far addressing with the pointer.
DS07-13733-6E
17
MB90800 Series
■ F2MC-16L CPU Programming model
• Dedicated Registers
AH
Accumulator
AL
USP
User stack pointer
SSP
System stack pointer
PS
Processor status
PC
Program counter
DPR
Direct page register
PCB
Program bank register
DTB
Data bank register
USB
User stack bank register
SSB
System stack bank register
ADB
Additional data bank register
8-bit
16-bit
32-bit
• General purpose registers
MSB
LSB
16-bit
000180H + RP × 10H
RW0
RL0
RW1
RW2
RL1
RW3
R1
R0
RW4
R3
R2
RW5
R5
R4
RW6
R7
R6
RW7
RL2
RL3
• Processor status
bit
PS
18
15
13 12
ILM
8 7
RP
0
CCR
DS07-13733-6E
MB90800 Series
■ I/O MAP
Address
Register
abbreviation
Read/
Write
Resource name
Initial Value
000000H
PDR0
Port 0 data register
R/W
Port 0
XXXXXXXXB
000001H
PDR1
Port 1 data register
R/W
Port 1
XXXXXXXXB
000002H
PDR2
Port 2 data register
R/W
Port 2
XXXXXXXXB
000003H
PDR3
Port 3 data register
R/W
Port 3
XXXXXXXXB
000004H
PDR4
Port 4 data register
R/W
Port 4
XXXXXXXXB
000005H
PDR5
Port 5 data register
R/W
Port 5
XXXXXXXXB
000006H
PDR6
Port 6 data register
R/W
Port 6
XXXXXXXXB
000007H
PDR7
Port 7 data register
R/W
Port 7
- XXXXXXXB
000008H
PDR8
Port 8 data register
R/W
Port 8
- - - XXXXXB
000009H
PDR9
Port 9 data register
R/W
Port 9
- - - - - - XXB
Register
00000AH
to
00000FH
Prohibited
000010H
DDR0
Port 0 direction register
R/W
Port 0
0 0 0 0 0 0 0 0B
000011H
DDR1
Port 1 direction register
R/W
Port 1
0 0 0 0 0 0 0 0B
000012H
DDR2
Port 2 direction register
R/W
Port 2
0 0 0 0 0 0 0 0B
000013H
DDR3
Port 3 direction register
R/W
Port 3
0 0 0 0 0 0 0 0B
000014H
DDR4
Port 4 direction register
R/W
Port 4
0 0 0 0 0 0 0 0B
000015H
DDR5
Port 5 direction register
R/W
Port 5
0 0 0 0 0 0 0 0B
000016H
DDR6
Port 6 direction register
R/W
Port 6
0 0 0 0 0 0 0 0B
000017H
DDR7
Port 7 direction register
R/W
Port 7
- 0 0 0 0 0 0 0B
000018H
DDR8
Port 8 direction register
R/W
Port 8
- - - 0 0 0 0 0B
000019H
DDR9
Port 9 direction register
R/W
Port 9
- - - - - - 0 0B
00001AH
to
00001DH
Prohibited
00001EH
ADER0
Analog input enable 0 register
R/W
Port 6, A/D
1 1 1 1 1 1 1 1B
00001FH
ADER1
Analog input enable 1 register
R/W
Port 7, A/D
- - - - 1 1 1 1B
000020H
SMR0
Serial mode register
R/W
000021H
SCR0
Serial control register
R/W
000022H
SIDR0/
SODR0
000023H
SSR0
000024H
000025H
Serial input/output register
R/W
Serial data register
0 0 0 0 0 - 0 0B
0 0 0 0 0 1 0 0B
UART0
R/W
XXXXXXXXB
0 0 0 0 1 0 0 0B
Prohibited
CDCR0
000026H
000027H
Communication prescaler control
register
R/W
Prescaler 0
0 0 - - 0 0 0 0B
Prohibited
(Continued)
DS07-13733-6E
19
MB90800 Series
Address
000028H
000029H
00002AH
00002BH
00002CH
00002DH
Register
abbreviation
SMR1
SCR1
SIDR1/
SODR1
SSR1
CDCR1
00002EH
00002FH
000030H
000031H
000032H
000033H
000034H
000035H
000036H
000037H
000038H
000039H
00003AH
00003BH
00003CH
00003DH
ADCS0
ADCS1
ADCR0
ADCR1
00003EH
TCCSL
00003FH
TCCSH
000040H
to
000043H
000044H
000045H
000046H
000047H
000048H
000049H
00004AH
00004BH
00004CH
00004DH
Read/
Write
R/W
R/W, W
Register
Serial mode register
Serial control register
Serial input/output register
R/W
Serial data register
Resource name
0 0 0 0 0 - 0 0B
0 0 0 0 0 1 0 0B
UART1
R/W, R
Prohibited
Communication prescaler control
R/W
register
Initial Value
XXXXXXXXB
0 0 0 0 1 0 0 0B
Prescaler 1
0 0 - - 0 0 0 0B
External interrupt
- - - - 0 0 0 0B
- - - - XXXXB
0 0 0 0 0 0 0 0B
A/D converter
00------B
0 0 0 0 0 0 0 0B
XXXXXXXXB
0 0 1 0 1 - XXB
Prohibited
ENIR
EIRR
ELVR
Interrupt/DTP enable
Interrupt/DTP source
Request level set register
R/W
R/W
R/W
Prohibited
ADMR
R/W
W, R/W
R
R, W
Prohibited
A/D conversion channel set register
R/W
CPCLR
Compare clear register
R/W
Timer counter data register
R/W
TCDT
Control status register (lower)
Control status register (upper)
Data register (lower)
Data register (upper)
Timer counter control/status register
(lower)
Timer counter control/status register
(upper)
A/D converter
16-bit free-run
timer
0 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
R/W
0 - - 0 0 0 0 0B
Prohibited
IPCP0
Input capture data register 0
IPCP1
Input capture data register 1
ICS01
Control status register
R/W
XXXXXXXXB
XXXXXXXXB
Input Capture 0/1 XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
Output compare 0
R
Prohibited
OCCP0
Compare register 0
R/W
OCCP1
Compare register 1
R/W
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
Output compare 1
0 0 0 0 0 0 0 0B
(Continued)
20
DS07-13733-6E
MB90800 Series
Address
Register
abbreviation
00004EH
OCSL
Control status register (lower)
R/W
00004FH
OCSH
Control status register (upper)
R/W
000050H
TMCSR0L
Timer control status register (lower)
R/W
000051H
TMCSR0H
Timer control status register (upper)
R/W
000052H
TMR0/
TMRLR0
16-bit timer register/Reload register
R/W
000054H
TMCSR1L
Timer control status register (lower)
R/W
000055H
TMCSR1H
Timer control status register (upper)
R/W
000056H
000057H
TMR1/
TMRLR1
16-bit timer register/Reload register
R/W
000058H
TMCSR2L
Timer control status register (lower)
R/W
000059H
TMCSR2H
Timer control status register (upper)
R/W
00005AH
TMR2/
TMRLR2
16-bit timer register/Reload register
R/W
000053H
00005BH
Read/
Write
Register
00005CH
LCRL
LCDC control register (lower)
R/W
00005DH
LCRH
LCDC control register (upper)
R/W
00005EH
LCRR
LCDC range register
R/W
00005FH
000060H
000061H
SMCS0
SDR0
000063H
000065H
R/W
R/W
SDCR0
Communication prescaler control
register
R/W
SMCS1
Serial mode control status register
SDR1
000067H
SDCR1
R, R/W
R/W
Serial Data Register
R/W
Communication prescaler control
register
R/W
000068H
Output Compare
0/1
0 0 0 0 - - 0 0B
- - - 0 0 0 0 0B
0 0 0 0 0 0 0 0B
16-bit reload
timer 0
- - - - 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
16-bit reload
timer 1
- - - - 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
0 0 0 0 0 0 0 0B
16-bit reload
timer 2
- - - - 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
0 0 0 1 0 0 0 0B
LCD controller/
driver
0 0 0 0 0 0 0 0B
0 0 0 0 0 0 0 0B
SIO
(Extended Serial
I/O)
Communication
prescaler (SIO)
SIO
(Extended Serial
I/O)
Communication
prescaler (SIO)
0 0 0 0 0 0 1 0B
- - - - 0 0 0 0B
XXXXXXXXB
0 - - - 0 0 0 0B
0 0 0 0 0 0 1 0B
- - - - 0 0 0 0B
XXXXXXXXB
0 - - - 0 0 0 0B
Prohibited
000069H
00006BH
R, R/W
Serial mode control status register
Serial Data Register
000066H
00006AH
Initial Value
Prohibited
000062H
000064H
Resource name
IBSR
IBCR
I2C status register
2
I C control register
2
R
0 0 0 0 0 0 0 0B
R/W
0 0 0 0 0 0 0 0B
2
IC
00006CH
ICCR
I C clock control register
R/W
00006DH
IADR
I2C address register
R/W
XXXXXXXXB
00006EH
IDAR
I2C data register
R/W
XXXXXXXXB
00006FH
ROMM
ROM mirror function select register
R/W, W
ROM mirror
XX0XXXXXB
XXXXXXX1B
(Continued)
DS07-13733-6E
21
MB90800 Series
Address
Register
abbreviation
000070H
PDCRL0
000071H
PDCRH0
000072H
PCSRL0
000073H
PCSRH0
000074H
PDUTL0
000075H
PDUTH0
000076H
PCNTL0
000077H
PCNTH0
000078H
PDCRL1
000079H
PDCRH1
00007AH
PCSRL1
00007BH
PCSRH1
00007CH
PDUTL1
00007DH
PDUTH1
00007EH
PCNTL1
00007FH
PCNTH1
Register
Read/
Write
PDCRL0/PDCRH0 PPG down counter
register
R
PCSRL0/PCSRH0 PPG cycle set
register
W
PDUTL0/PDUTH0 PPG duty setting
register
W
PCNTL0/PCNTH0 PPG control status
register
R/W
PDCRL1/PDCRH1 PPG down counter
register
R
PCSRL1/PCSRH1 PPG cycle set
register
W
PDUTL1/PDUTH1 PPG duty setting
register
W
000096H
Prohibited
000097H
(Reserved)
000098H
to
00009DH
Prohibited
00009FH
DIRR
0000A0H
LPMCR
0000A1H
CKSCR
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
- - 0 0 0 0 0 0B
0 0 0 0 0 0 0 -B
1 1 1 1 1 1 1 1B
1 1 1 1 1 1 1 1B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
- - 0 0 0 0 0 0B
R/W
(Reserved)
PACSR
1 1 1 1 1 1 1 1B
16-bit
PPG1
PCNTL1/PCNTH1 PPG control status
register
Initial Value
1 1 1 1 1 1 1 1B
16-bit
PPG0
000080H
to
000095H
00009EH
Resource name
0 0 0 0 0 0 0 -B
ROM correction control register
R/W
ROM Correction
0 0 0 0 0 0 0 0B
Delayed interrupt source generated/
release register
R/W
Delayed interrupt
- - - - - - - 0B
Low power consumption mode control
register
R/W, W
0 0 0 1 1 0 0 0B
Clock selector register
R/W, R
Low power
consumption
control circuit
1 1 1 1 1 1 0 0B
0000A2H
to
0000A7H
Prohibited
0000A8H
WDTC
Watchdog timer control register
R, W
Watchdog timer
XXXXX 1 1 1B
0000A9H
TBTC
Time-base timer control register
R/W, W
Time-base timer
1 - - 0 0 1 0 0B
0000AAH
WTC
Watch timer control register
R/W, R
Watch timer
(Sub clock)
1 X0 1 1 0 0 0B
0000ABH
to
0000ADH
Prohibited
(Continued)
22
DS07-13733-6E
MB90800 Series
(Continued)
Address
Register
abbreviation
Read/
Write
Resource
name
Initial Value
0000AEH
FMCS
Flash control register
R/W
Flash I/F
0 0 0 X 0 0 0 0B
0000AFH
TMCS
Timer clock output control register
R/W
Timer clock
divide
XXXXX 0 0 0B
0000B0H
ICR00
Interrupt control register 00
R/W, W, R
0 0 0 0 0 1 1 1B
0000B1H
ICR01
Interrupt control register 01
R/W, W, R
0 0 0 0 0 1 1 1B
0000B2H
ICR02
Interrupt control register 02
R/W, W, R
0 0 0 0 0 1 1 1B
0000B3H
ICR03
Interrupt control register 03
R/W, W, R
0 0 0 0 0 1 1 1B
0000B4H
ICR04
Interrupt control register 04
R/W, W, R
0 0 0 0 0 1 1 1B
0000B5H
ICR05
Interrupt control register 05
R/W, W, R
0 0 0 0 0 1 1 1B
0000B6H
ICR06
Interrupt control register 06
R/W, W, R
0 0 0 0 0 1 1 1B
0000B7H
ICR07
Interrupt control register 07
R/W, W, R
0000B8H
ICR08
Interrupt control register 08
R/W, W, R
0000B9H
ICR09
Interrupt control register 09
R/W, W, R
0 0 0 0 0 1 1 1B
0000BAH
ICR10
Interrupt control register 10
R/W, W, R
0 0 0 0 0 1 1 1B
Register
Interrupt
controller
0 0 0 0 0 1 1 1B
0 0 0 0 0 1 1 1B
0000BBH
ICR11
Interrupt control register 11
R/W, W, R
0 0 0 0 0 1 1 1B
0000BCH
ICR12
Interrupt control register 12
R/W, W, R
0 0 0 0 0 1 1 1B
0000BDH
ICR13
Interrupt control register 13
R/W, W, R
0 0 0 0 0 1 1 1B
0000BEH
ICR14
Interrupt control register 14
R/W, W, R
0 0 0 0 0 1 1 1B
0000BFH
ICR15
Interrupt control register 15
R/W, W, R
0 0 0 0 0 1 1 1B
0000CAH
FWR0
Flash Program Control Register 0
0000CBH
FWR1
Flash Program Control Register 1
R/W
0000CCH
SSR0
Sector Conversion Setting Register
R/W
R/W
Flash I/F
(MB90F803/S
only object)
PADR0
Program address detection register 0
R/W
001FF2H
001FF3H
001FF4H
PADR1
Program address detection register 1
R/W
Address
matching
detection
function
001FF5H
007900H
to
007917H
0 0 0 0 0 0 0 0B
0 0 XXXXX 0B
XXXXXXXXB
001FF0H
001FF1H
0 0 0 0 0 0 0 0B
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
XXXXXXXXB
VRAM
LCD display RAM
R/W
LCD controller/
driver
XXXXXXXXB
• Read/Write
R/W : Readable and Writable
R
: Read only
W : Write only
• Initial values
0
: Initial Value is “0”.
1
: Initial Value is “1”.
X
: Initial Value is Indeterminate.
: Unused bit
DS07-13733-6E
23
MB90800 Series
■ INTERRUPT SOURCES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS
Interrupt source
EI2OS
readiness
Interrupt vector
Number*
Interrupt control register
Address
ICR
Address
Reset
×
#08
08H
FFFFDCH
⎯
⎯
INT 9 instruction
×
#09
09H
FFFFD8H
⎯
⎯
Exceptional treatment
×
#10
0AH
FFFFD4H
⎯
⎯
DTP/External interrupt ch.0
#11
0BH
FFFFD0H
ICR00
0000B0H
DTP/External interrupt ch.1
#13
0DH
FFFFC8H
ICR01
0000B1H
#15
0FH
FFFFC0H
#16
10H
FFFFBCH
ICR02
0000B2H
#17
11H
FFFFB8H
#18
12H
FFFFB4H
ICR03
0000B3H
#19
13H
FFFFB0H
ICR04
0000B4H
16-bit Reload Timer ch.2
#21
15H
FFFFA8H
ICR05
0000B5H
16-bit Reload Timer ch.0
#23
17H
FFFFA0H
16-bit Reload Timer ch.1
#24
18H
FFFF9CH
ICR06
0000B6H
Input capture ch.0
#25
19H
FFFF98H
Input capture ch.1
#26
1AH
FFFF94H
ICR07
0000B7H
PPG timer ch.0 counter-borrow
#27
1BH
FFFF90H
ICR08
0000B8H
Output compare match
#29
1DH
FFFF88H
ICR09
0000B9H
PPG timer ch.1 counter-borrow
#31
1FH
FFFF80H
ICR10
0000BAH
#33
21H
FFFF78H
ICR11
0000BBH
UART0 reception end
#35
23H
FFFF70H
UART0 transmission end
#36
24H
FFFF6CH
ICR12
0000BCH
A/D converter conversion termination
#37
25H
FFFF68H
#38
26H
FFFF64H
ICR13
0000BDH
UART1 : Reception
#39
27H
FFFF60H
UART1 : Transmission
#40
28H
FFFF5CH
ICR14
0000BEH
ICR15
0000BFH
Serial I/O ch.2
×
DTP/External interrupt ch.2/ch.3
Serial I/O ch.3
×
16-bit free-run timer
Watch timer
Time-base timer
2
I C Interface
×
×
×
Flash memory status
×
#41
29H
FFFF58H
Delayed interrupt output module
×
#42
2AH
FFFF54H
Priority
High
Low
: Available
× : Unavailable
: Available El2OS function is provided.
: Available when a cause of interrupt sharing a same ICR is not used.
* : When interrupts of the same level are output at the same time, the interrupt with the smallest interrupt vector
number has the priority.
• For a resource that has two interrupt causes in the same interrupt control register (ICR), use of EI2OS is
enabled, EI2OS is started upon detection of one of the interrupt causes. As interrupts other than the start
cause are masked during EI2OS start, masking one of the interrupt causes is recommended when using EI2OS.
• For a resource that has two interrupt causes in the same interrupt control register (ICR), the interrupt flag is
cleared by an EI2OS interrupt clear signal.
24
DS07-13733-6E
MB90800 Series
■ PERIPHERAL RESOURCES
1. I/O port
The I/O ports function to output data from the CPU to I/O pins by setting their port data register (PDR) and send
signals input to I/O pins to the CPU. In addition, the port can randomly set the direction of the input/output of
the port in bit by the port direction register (DDR).
The MB90800 series has 68 (70 ports when the subclock is not used) input/output pins. Port0 to port8 (port0 to
port9 when product without the subclock is used) are input/output port.
(1) Port data register
PDR0
7
6
5
4
3
2
1
0
Initial Value
Access
Address : 000000H
P07
P06
P05
P04
P03
P02
P01
P00
Indeterminate
R/W*
PDR1
bit
15
14
13
12
11
10
9
8
Address : 000001H
P17
P16
P15
P14
P13
P12
P11
P10
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
Indeterminate
R/W*
PDR2
bit
bit
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
bit
15
14
13
12
11
10
9
8
Address : 000003H
P37
P36
P35
P34
P33
P32
P31
P30
7
6
5
4
3
2
1
0
P47
P46
P45
P44
P43
P42
P41
P40
Address : 000002H
PDR3
PDR4
bit
Address : 000004H
PDR5
bit
15
14
13
12
11
10
9
8
Address : 000005H
P57
P56
P55
P54
P53
P52
P51
P50
7
6
5
4
3
2
1
0
P67
P66
P65
P64
P63
P62
P61
P60
bit
15
14
13
12
11
10
9
8
Address : 000007H
⎯
P76
P75
P74
P73
P72
P71
P70
PDR8
bit
7
6
5
4
3
2
1
0
Address : 000008H
⎯
⎯
⎯
P84
P83
P82
P81
P80
PDR9
bit
15
14
13
12
11
10
9
8
Address : 000009H
⎯
⎯
⎯
⎯
⎯
⎯
P91
P90
PDR6
bit
Address : 000006H
PDR7
- : Unused
* : R/W access to I/O ports is a bit different in behavior from R/W access to memory as follows
• Input mode
When reading : Read the corresponding pin level.
When writing : Write into the latch for the output.
• Output mode
When reading : Read the value of the data register latch.
When writing : Write into the corresponding pin.
DS07-13733-6E
25
MB90800 Series
(2) Port direction register
DDR0
bit
Address : 000010H
DDR1
bit
Address : 000011H
DDR2
bit
Address : 000012H
DDR3
bit
Address : 000013H
DDR4
bit
Address : 000014H
DDR5
bit
Address : 000015H
DDR6
bit
Address : 000016H
DDR7
bit
Address : 000017H
DDR8
bit
Address : 000018H
DDR9
bit
Address : 000019H
7
6
5
4
3
2
1
0
Initial Value
Access
D07
D06
D05
D04
D03
D02
D01
D00
00000000B
R/W
15
14
13
12
11
10
9
8
D17
D16
D15
D14
D13
D12
D11
D10
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
00000000B
R/W
- 0000000B
R/W
- - - 00000B
R/W
- - - - - - 00B
R/W
7
6
5
4
3
2
1
0
D27
D26
D25
D24
D23
D22
D21
D20
15
14
13
12
11
10
9
8
D37
D36
D35
D34
D33
D32
D31
D30
7
6
5
4
3
2
1
0
D47
D46
D45
D44
D43
D42
D41
D40
15
14
13
12
11
10
9
8
D57
D56
D55
D54
D53
D52
D51
D50
7
6
5
4
3
2
1
0
D67
D66
D65
D64
D63
D62
D61
D60
15
14
13
12
11
10
9
8
⎯
D76
D75
D74
D73
D72
D71
D70
7
6
5
4
3
2
1
0
⎯
⎯
⎯
D84
D83
D82
D81
D80
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
⎯
D91
D90
- : Unused
When each terminal functions as a port, each correspondent pin are controlled by the port direction register to
following;
0 : Input mode
1 : Output mode This bit becomes “0” after a reset.
Note : When accessing this register by using the instruction of the read modify write system (instructions such as
bit set) is mode, the bit targeted by an instruction becomes the defined value. However, the content of the
output register set to input with the other changes to input value of the pin at that time. Therefore, be sure
to write an expected value into PDR firstly, and then set DDR and finally change to the output when changing
the input pin to the output pin is made.
26
DS07-13733-6E
MB90800 Series
(3) Analog Input Enable register
ADER0
bit
Address : 00001EH
ADER1
bit
Address : 00001FH
7
6
5
4
3
2
1
0
ADE7
ADE6
ADE5
ADE4
ADE3
ADE2
ADE1
ADE0
15
14
13
12
11
10
9
8
⎯
⎯
⎯
⎯
ADE11
ADE10
ADE9
ADE8
Initial Value Access
11111111B
R/W
- - - -1111B
R/W
- : Unused
Each pin of port 6 is controlled by the analog input enable register as follow.
0 : Port input/output mode.
1 : Analog input mode.This bit becomes “1” after a reset.
DS07-13733-6E
27
MB90800 Series
2. UART
UART is a serial I/O port for asynchronous (start-stop synchronization) communication or CLK synchronous
communications.
• With full-duplex double buffer
• Clock asynchronous (start-stop synchronization) , CLK synchronous communications (no start-bit/stop-bit)
can be used.
• Supports multi-processor mode
• Built-in dedicated baud rate generator
•
•
•
•
•
28
Asynchronous
: 120192/60096/30048/15024/781.25 K/390.625 kbps
CLK synchronous : 25 M/12.5 M/6.25 M/3.125 M/1.5627 M/781.25 kbps
Variable baud rate can be set by an external clock.
7 bits data length (only asynchronous normal mode) /8 bits length
Master/slave type communication function (at multiprocessor mode) : The communication between one (master) to n (slave) can be operating.
Error detection functions(parity, framing, overrun)
Transmission signal format is NRZ
DS07-13733-6E
MB90800 Series
(1) Register list
bit
8 7
15
Serial mode register (SMR0, SMR1)
bit
7
000020H
MD1
Address :
000028H
R/W
Serial control register(SCR0, SCR1)
bit
15
000021H
Address :
PEN
000029H
R/W
0
CDCR
⎯
SCR
SMR
SSR
SIDR (R)/SODR (W)
8-bit
8-bit
5
4
3
2
1
0
MD0
CS2
CS1
CS0
⎯
SCKE
SOE
00000 - 00B
R/W
R/W
R/W
R/W
⎯
R/W
R/W
Read/Write
14
13
12
11
10
9
8
P
SBL
CL
A/D
REC
RXE
TXE
00000100B
R/W
R/W
R/W
R/W
W
R/W
R/W
Read/Write
2
1
0
D2
D1
D0
Serial input/output register (SIDR0, SIDR1/SODR0, SODR1)
bit
7
6
5
4
3
000022H
Address :
D7
D6
D5
D4
D3
00002AH
R/W
Serial Data Register (SSR0, SSR1)
bit
15
000023H
Address :
PE
00002BH
R
Initial Value
Initial Value
XXXXXXXXB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
14
13
12
11
10
9
8
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
00001000B
R
R
R
R
R/W
R/W
R/W
Read/Write
10
9
8
DIV2
DIV1
DIV0
00 - - 0000B
R/W
R/W
R/W
Read/Write
Communication prescaler control register (CDCR0, CDCR1)
bit
15
14
13
12
11
000025H
Address :
Reserved
MD
URST
⎯
⎯
00002DH
R/W
Initial Value
6
R/W
⎯
⎯
R/W
Initial Value
Initial Value
- : Unused
DS07-13733-6E
29
MB90800 Series
(2) Block Diagram
Control signal
Special-purpose
baud-rate generator
16-bit reload timer 0
RX interrupt
(to CPU)
Clock
selection
circuit
Transmission clock
Reception clock
TX interrupt
(to CPU)
SC Pin
SI Pin
Reception control
circuit
Transmission
control circuit
Start bit
detection circuit
Transmission
start circuit
Reception bit
counter
Transmission bit
counter
Reception
parity counter
Transmission
parity counter
SO Pin
Receive status
decision circuit
Reception error
occurrence signal
for EI2OS (to CPU)
RX shifter
TX shifter
Reception
control
circuit
Start
transmission
SIDR
SODR
F2MC-16LX bus
SMR
Register
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR
Register
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR
Register
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
Control signal
30
DS07-13733-6E
MB90800 Series
3. I2C Interface
I2C interface is the serial input/output port that support Inter IC BUS and functions as the master/slave device
on the I2C bus. MB90800 series have 1 channel of the built-in I2C interface.
It has the features of I2C interface below.
• Master/slave sending and receiving
• Arbitration function
• Clock synchronization function
• Slave address and general call address detection function
• Detecting transmitting direction function
• Repeat generating and detecting function of the start conditions
• Bus error detection function
• The forwarding rate can be supported to 100 kbps.
(1) Register list
I2C status register (IBSR)
bit
Address :00006AH
I2C control register (IBCR)
bit
Address :00006BH
Initial Value
00000000B
7
6
5
4
3
2
1
0
BB
RSC
AL
LRB
TRX
AAS
GCA
FBT
R
R
R
R
R
R
R
R
Read/Write
15
14
13
12
11
10
9
8
BER
BEIE
SCC
MSS
ACK
GCAA
INTE
INT
Initial Value
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
5
4
3
2
1
0
I2C clock control register (ICCR)
bit
7
Address :00006CH
⎯
⎯
EN
CS4
CS3
CS2
CS1
CS0
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
Initial Value
XX0XXXXXB
Read/Write
I2C data register(IDAR)
bit
Address :00006EH
I2C address register (IADR)
bit
Address :00006DH
15
14
13
12
11
10
9
8
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
⎯
A6
A5
A4
A3
A2
A1
A0
⎯
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
XXXXXXXXB
Read/Write
Initial Value
XXXXXXXXB
Read/Write
- : Unused
DS07-13733-6E
31
MB90800 Series
(2) Block Diagram
ICCR
EN
I2C Enable
Machine clock
Clock divide 1
ICCR
5
6
7
8
CS4
Clock selector 1
CS3
Clock divide 2
CS2
Internal data bus
CS1
2 4 8
CS0
16
32
64
128 256
RSC
LRB
TRX
Generating shift clock
Clock selector 2
Change timing of
shift clock edge
IBSR
BB
Sync
Bus busy
Repeat start
Last Bit
Start • stop Condition detection
Transfer/
reception
Error
First Byte
FBT
AL
Arbitration lost detection
IBCR
BER
SCL
BEIE
Interrupt request
INTE
IRQ
SDA
INT
End
IBCR
SCC
MSS
ACK
GCAA
Start
Master
ACK enable
Start • stop Condition detection
GC-ACK enable
IDAR
IBSR
AAS
Slave
GCA
Global call
Slave address
compare
IADR
32
DS07-13733-6E
MB90800 Series
4. Extended I/O serial interface
The extended I/O serial interface is a serial I/O interface that can transfer data through the adoption of 8-bit ×
2 channels configured clock synchronization scheme. The extended I/O serial interface also has two alternatives
in data transfer called LSB first and MSB first.
The serial I/O interface operates in two modes:
• Internal shift clock mode : Transfer data in sync with the internal clock.
• External shift clock mode : Transfers data in sync with the clock input through an external pin (SC) . In this
mode, transfer operation performed by the CPU instruction is also available by
operating the general-use port sharing an external pin (SC) .
(1) Register list
Serial mode control status register (SMCS0, SMCS1)
bit
15
14
13
12
000060H
Address :
SMD2 SMD1 SMD0
SIE
000064H
R/W
bit
000061H
Address :
000065H
R/W
R/W
R/W
11
10
9
8
Initial Value
SIR
BUSY
STOP
STRT
00000010B
R/W
R
R/W
R/W
Read/Write
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
MODE
BDS
SOE
SCOE
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial Data Register (SDR0, SDR1)
bit
7
000062H
Address :
D7
000066H
R/W
Communication Prescaler control register (SDCR0, SDCR1)
bit
15
14
13
12
11
000063H
Reserved
Address :
MD
⎯
⎯
⎯
000067H
R/W
⎯
⎯
⎯
R/W
----0000B
Read/Write
XXXXXXXXB
Read/Write
10
9
8
DIV2
DIV1
DIV0
0---0000B
R/W
R/W
R/W
Read/Write
- : Unused
DS07-13733-6E
33
MB90800 Series
(2) Block Diagram
Internal data bus
Initial Value
(LSB fast) D7 to D0
Transfer direction selection
(MSB fast) D0 to D7
SI2, SI3
Read
Write
SDR (Serial Data Register)
SO2, SO3
SC2, SC3
Control circuit
Shift clock counter
Internal clock
2
1
0
SMD2 SMD1 SMD0
SIE
SIR
BUSY STOP STRT MODE BDS
SOE SCOE
Interrupt
request
Internal data bus
34
DS07-13733-6E
MB90800 Series
5. 8/10-bit A/D converter
The feature of 8/10-bit A/D converter is shown as follows.
• conversion time : 3.1 μs minimum per 1 channel
(78 machine cycle/at machine clock 25 MHz/including the sampling time)
• Sampling time : 2.0 μs minimum per 1channel
(50 machine cycle/at machine clock 25 MHz)
• Uses RC-type successive approximation conversion method with a sample & hold circuit
• 8-bit resolution or 10-bit resolution can be select.
• 12 channel program-selectable analog inputs.
Single conversion mode
: Convert specified 1 channel
Scan conversion mode
: Continuous plural channels (maximum 12 channels can be programmed) are
converted.
Continuous conversion mode : Selected channel converted continuously.
Stop conversion time
: Perform conversion for one channel, then pause it to wait for the next activation
trigger (synchronizes the conversion start timing)
2
• EI OS can be activated by outputting the interrupt request when the A/D conversion completes.
• If the A/D conversion is performed under the condition of the interrupt enable, the converting data will be
protected.
• Selectable conversion activation trigger : Software, or reload timer (rising edge)
(1) Register list
ADCS1, ADCS0 (Control status register)
ADCS0
bit
7
6
5
Address : 000034H MD1
MD0
⎯
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
ADCS1
bit
Address : 000035H
R/W
R/W
⎯
⎯
⎯
⎯
⎯
⎯
Read/Write
15
14
13
12
11
10
9
8
BUSY
INT
INTE
PAUS
STS1
STS0
STRT
Reserved
Initial Value
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
W
R/W
Read/Write
6
5
4
3
2
1
0
D6
D5
D4
D3
D2
D1
D0
Initial Value
XXXXXXXXB
R
R
R
R
R
R
R
R
Read/Write
15
14
13
12
11
10
9
8
S10
ST1
ST0
CT1
CT0
⎯
D9
D8
Initial Value
00101 - XXB
W
W
W
W
W
⎯
R
R
Read/Write
ADCR1, ADCR0 (Data register)
ADCR0
bit
7
Address : 000036H
D7
ADCR1
bit
Address : 000037H
Initial Value
00 - - - - - - B
- : Unused
DS07-13733-6E
35
MB90800 Series
(2) Block Diagram
AVCC
AVR
MPX
AVSS
D/A converter
Input
circuit
Sequential compare
register
Comparator
Data bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
Sample & hold circuit
Data register
Decoder
ADCR0, ADCR1
A/D conversion channel set
register
ADCS0 A/D control status
register 0 (lower)
ADCS1 A/D control status
register 1 (upper)
Timer start-up
16-bit Reload Timer
Operation clock
φ
36
ADCS0, ADCS1,
ADMR
Prescaler
DS07-13733-6E
MB90800 Series
6. 16 bits PPG
The PPG timer consists of the following:
• Prescaler
• 16-bit down-counter: 1
• 16-bit data register with a cycle setting buffer
• 16-bit compare register with a duty setting buffer
• Pin control unit
The PPG timer can output pulses synchronized to the software trigger.
The output pulse can be changed to any cycle and duty freely by updating the PCSRL, PCSRH/PDUTL, PDUTH
registers.
• PWM function
The PPG timer can output pulses programmably by updating the PCSR and PDUT registers described above
in synchronization to the trigger.
Can also be used as a D/A converter by an external circuit.
• Single shot function
By detecting an edge of the trigger input, a single pulse can be output.
• 16-bit down counter
The counter operation clock comes from eight kinds optional. There are eight kinds of internal clocks.
(φ, φ2, φ4, φ8, φ16, φ32, φ64, φ128) φ : machine clock
The counter can be initialized to “FFFFH” at a reset or counter borrow.
• Interrupt request
The PPG timer generates an interrupt request when :
• Timer start-up
• Counter borrow occurrence (cycle match)
• Duty match occurrence
DS07-13733-6E
37
MB90800 Series
(1) Register list
PCNTH (PCNTH0/PCNTH1 PPG Control Status register)
000077H
00007FH
bit
15
14
13
12
11
10
9
8
CNTE
STGR
MDSE
RTRG
CKS2
CKS1
CKS0
PGMS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0000000-B
Read/Write
PCNTL (PCNTL0/PCNTL1 PPG Control Status register)
000076H
00007EH
bit
7
6
5
4
3
2
1
0
⎯
⎯
IREN
IRQF
IRS1
IRS0
POEN
OSEL
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
- - 000000B
Read/Write
PDCRH (PDCRH0/PDCRH1 PPG Down Counter Register)
000071H
000079H
bit
15
14
13
12
11
10
9
8
DC15
DC14
DC13
DC12
DC11
DC10
DC09
DC08
R
R
R
R
R
R
R
R
Initial Value
11111111B
Read/Write
PDCRL (PDCRL0/PDCRL1 PPG Down Counter Register)
000070H
000078H
bit
7
6
5
4
3
2
1
0
DC07
DC06
DC05
DC04
DC03
DC02
DC01
DC00
R
R
R
R
R
R
R
R
Initial Value
11111111B
Read/Write
PCSRH (PCSRH0/PCSRH1 PPG cycle set register)
000073H
00007BH
bit
15
14
13
12
11
10
9
8
CS15
CS14
CS13
CS12
CS11
CS10
CS09
CS08
W
W
W
W
W
W
W
W
Initial Value
XXXXXXXXB
Read/Write
PCSRL (PCSRL0/PCSRL1 PPG cycle set register)
000072H
00007AH
bit
7
6
5
4
3
2
1
0
CS07
CS06
CS05
CS04
CS03
CS02
CS01
CS00
W
W
W
W
W
W
W
W
Initial Value
XXXXXXXXB
Read/Write
PDUTH (PDUTH0/PDUTH1 PPG duty set register)
000075H
00007DH
bit
15
14
13
12
11
10
9
8
DU15
DU14
DU13
DU12
DU11
DU10
DU09
DU08
W
W
W
W
W
W
W
W
Initial Value
XXXXXXXXB
Read/Write
PDUTL (PDUTL0/PDUTL1 PPG duty set register)
000074H
00007CH
bit
7
6
5
4
3
2
1
0
DU07
DU06
DU05
DU04
DU03
DU02
DU01
DU00
W
W
W
W
W
W
W
W
Initial Value
XXXXXXXXB
Read/Write
- : Unused
38
DS07-13733-6E
MB90800 Series
(2) Block Diagram
• 16-bit PPG ch.0/ch.1 block diagram
Prescaler
1/1
PCSR
1/2
PDUT
1/4
1/8
1/16
Clock
1/32
Load
CMP
PCNT
16-bit down counter
1/64
1/128
Start
Borrow
PPG mask
Machine clock φ
S
PPG output
Q
R
Reverse bit
Enable
Interrupt
select
Interrupt
Soft trigger
DS07-13733-6E
39
MB90800 Series
7. Delay interrupt generator module
The delayed interrupt generation module outputs an interrupt request for task switching. The hardware interrupt
request can be generated by software.
(1) Register list
Delayed Interrupt/release register(DIRR)
DIRR
bit
15
14
Address : 00009FH
⎯
⎯
⎯
⎯
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
R0
Initial Value
- - - - - - - 0B
⎯
⎯
⎯
⎯
⎯
R/W
Read/Write
- : Unused
(2) Block diagram
F2MC-16LX bus
Delay interruption factor generation/
release decoder
Factor latch
40
DS07-13733-6E
MB90800 Series
8. DTP/External interrupt
DTP (Data Transfer Peripheral)/External interrupt circuit detects the interrupt request input from the external
interrupt input terminal, and outputs the interrupt request.
(1) Register list
Interrupt/DTP enable register (ENIR)
ENIR
bit
7
6
Address : 000030H
⎯
⎯
5
4
3
2
1
0
⎯
⎯
EN3
EN2
EN1
EN0
Initial Value
- - - - 0000B
⎯
⎯
⎯
R/W
R/W
R/W
R/W
Read/Write
Interrupt/DTP source register (EIRR)
EIRR
bit
15
14
Address : 000031H
⎯
⎯
13
12
11
10
9
8
⎯
⎯
ER3
ER2
ER1
ER0
Initial Value
- - - - XXXXB
⎯
⎯
R/W
R/W
R/W
R/W
Read/Write
5
4
3
2
1
0
LB2
LA2
LB1
LA1
LB0
LA0
Initial Value
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
⎯
⎯
⎯
Request level setting register (ELVR)
ELVR
bit
7
6
Address : 000032H
LB3
LA3
R/W
R/W
- : Unused
(2) Block diagram
F2MC-16LX bus
4
4
4
8
DS07-13733-6E
Interrupt/DTP enable register
Gate
Source F/F
Edge detection circuit
4
Request input
Interrupt/DTP source register
Request level setting register
41
MB90800 Series
9. 16-bit input/output timer
The 16-bit I/O timer consists of one 16-bit free-run timer, two output compare and two input capture. This function
enables six independent waveforms to be output based on the 16-bit free-run timer, and input pulse widths and
external clock frequencies to be measured.
• Register list
• 16-bit free-run timer
bit 15
0
00003BH/00003AH
CPCLR
00003DH/00003CH
TCDT
00003FH/00003EH
TCCSH
Compare clear register
Timer counter data register
Timer counter
control/status register
TCCSL
• 16-bit Output Compare
bit 15
0
00004AH/00004BH,
00004CH/00004DH
Compare register
OCCP0, OCCP1
00004FH/00004EH
OCSH
Control status register
OCSL
• 16-bit Input Capture
bit
000044H/000045H,
000046H/000047H
000048H
42
15
0
Input capture data register
IPCP0, IPCP1
ICS01
Control status register
DS07-13733-6E
MB90800 Series
• Block diagram
Control logic
Interrupt
16-bit free-run timer
To each
block
16-bit timer
Bus
Clear
Output
compare 0
Compare register 0
TQ
OCU0
Output
compare 1
Compare register 1
TQ
OCU1
Input capture 0
Capture register 0
Edge select
IC0
Capture register 1
Edge select
IC1
Input capture 1
DS07-13733-6E
43
MB90800 Series
(1) 16-bit free-run timer
The 16-bit free-run timer consists of a 16-bit up-down counter and control status register.
Counter value of 16-bit free-run timer is available as base timer for input capture and output compare.
• Clock for the counter operation can be selected from eight types.
• The counter overflow interruption can be generated.
• Setting the mode enables initialization of the counter through compare-match operation with the value of the
compare clear register in the output compare and that of the free-run timer counter.
• Register list
Compare clear register (CPCLR)
bit
15
14
00003BH
CL15
CL14
bit
00003AH
12
11
10
9
8
CL13
CL12
CL11
CL10
CL09
CL08
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CL07
CL06
CL05
CL04
CL03
CL02
CL01
CL00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
13
12
11
10
9
8
T13
T12
T11
T10
T09
T08
Initial Value
00000000B
Initial Value
XXXXXXXXB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
7
6
5
4
3
2
1
0
T07
T06
T05
T04
T03
T02
T01
T00
Initial Value
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
12
11
10
9
8
MSI2
MSI1
MSI0
ICLR
ICRE
Initial Value
0--00000B
Timer counter control/status register (TCCS)
bit
15
14
13
00003FH ECKE
⎯
⎯
bit
00003EH
Initial Value
XXXXXXXXB
R/W
Timer counter data register (TCDT)
bit
15
14
00003DH
T15
T14
bit
00003CH
13
R/W
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Read/Write
7
6
5
4
3
2
1
0
IVF
IVFE
STOP
MODE
SCLR
CLK2
CLK1
CLK0
Initial Value
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
- : Unused
44
DS07-13733-6E
MB90800 Series
• Block diagram
φ
Interrupt request
IVF
Divider
IVFE STOP MODE SCLR CLK2 CLK1 CLK0
Bus
Clock
16-bit free-run timer
Count value output T15 to T00
16-bit compare clear register
Compare circuit
MSI2 to MSI0
ICLR
ICRE
Interrupt request
DS07-13733-6E
45
MB90800 Series
(2) Output compare
The output compare consists of 16-bit compare registers, compare output pin part and a control register. It can
reverse the output level for the pin and at the same time, generate an interrupt when the 16-bit free-run timer
value matches a value set in one of the 16-bit compare registers of this module.
• It has a total of six compare registers that can operate independently. In addition, the output can be set to be
controlled by using two compare registers.
• An interrupt can be set by a comparing match.
• Register list
Compare register (OCCP0, OCCP1)
bit
15
14
00004BH OP15 OP14
00004DH
bit
00004AH
00004CH
Control register (OCSH)
bit
00004FH
Control register (OCSL)
bit
00004EH
13
12
11
10
9
8
OP13
OP12
OP11
OP10
OP09
OP08
Initial Value
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
7
6
5
4
3
2
1
0
OP07
OP06
OP05
OP04
OP03
OP02
OP01
C00
Initial Value
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
15
14
13
12
11
10
9
8
⎯
⎯
⎯
CMOD
OTE1
OTE0
OTD1
OTD0
Initial Value
---00000B
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
Read/Write
7
6
5
4
3
2
1
0
IOP1
IOP0
IOE1
IOE0
⎯
⎯
CST1
CST0
Initial Value
0000--00B
R/W
R/W
R/W
R/W
⎯
⎯
R/W
R/W
Read/Write
- : Unused
46
DS07-13733-6E
MB90800 Series
• Block diagram
16-bit timer counter value (T15 to T00)
Compare control
TQ
OTE0
Compare register 0
CMOD
Bus
16-bit timer counter value (T15 to T00)
Compare control
TQ
OTE1
Compare register 1
ICP1
Control logic
Each control blocks
DS07-13733-6E
ICP0
ICE0
ICE0
Interrupt
#29
#29
47
MB90800 Series
(3) Input capture
The input capture consists of input capture and control registers. Each input capture has its corresponding
external input pin.
This module has a function that detects a rising edge, falling edge or both edges and holds a value of the 16bit free-run timer in a register at the time of detection. It can also generate an interrupt when detecting an edge.
• The detection edge of an external input can be selected from among three types. Rising edge/falling edge/
both edges.
• It can generate an interrupt when it detects the valid edge of the external input.
• Register list
Input capture data register (IPCP0, IPCP1)
000045H
000047H
000044H
000046H
bit
bit
Initial Value
XXXXXXXXB
15
14
13
12
11
10
9
8
CP15
CP14
CP13
CP12
CP11
CP10
CP09
CP08
R
R
R
R
R
R
R
R
Read/Write
7
6
5
4
3
2
1
0
CP07
CP06
CP05
CP04
CP03
CP02
CP01
CP00
Initial Value
XXXXXXXXB
R
R
R
R
R
R
R
R
Read/Write
7
6
5
4
3
2
1
0
ICP1
ICP0
ICE1
ICE0
EG11
EG10
EG01
EG00
Initial Value
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Control status register (ICS01)
bit
000048H
48
Read/Write
DS07-13733-6E
MB90800 Series
• Block diagram
Capture data register 0
Edge detection
16-bit timer counter value (T15 to T00)
IC0
Bus
EG11 EG10 EG01 EG00
Capture data register 1
ICP1
Edge detection
ICP0
ICE1
IC1
ICE0
Interrupt #25
Interrupt #25
DS07-13733-6E
49
MB90800 Series
10. 16-bit reload timer
The 16-bit reload timer provides two functions either one which can be selected, the internal clock mode that
performs the count down by synchronizing with 3-type internal clocks and the event count mode that performs
the count down by detecting the arbitration. This timer defines an underflow as a transition of the count value
from 0000H to FFFFH. Therefore, when the equation (counted value = reload register setting value+1) holds, an
underflow occurs. Either mode can be selected for the count operation from the reload mode which repeats the
count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the
count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as
to correspond to the DTC.
(1) Register list
• TMCSR Timer control status register
Timer control status register (upper) (TMCSR0H to TMCSR2H)
bit
15
14
13
12
11
10
9
000051H
⎯
⎯
⎯
⎯
CSL1
CSL0
MOD2
000055H
⎯
⎯
⎯
⎯
R/W
R/W
R/W
000059H
Timer control status register (lower) (TMCSR0L to TMCSR2L)
bit
7
6
5
4
3
2
000050H
MOD0 OUTE OUTL
RELD
INTE
UF
000054H
R/W
R/W
R/W
R/W
R/W
R/W
000058H
MOD1
Initial Value
- - - - 0000B
R/W
Read/Write
1
0
CNTE
TRG
Initial Value
00000000B
R/W
R/W
Read/Write
8
• 16-bit timer register/16-bit reload register TMR0 to TMR2/TMRLR0 to TMRLR2 (upper)
bit
Initial Value
15
14
13
12
11
10
9
8
XXXXXXXX
B
000053H
D15
D14
D13
D12
D11
D10
D9
D8
000057H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
00005BH
TMR0 to TMR2/TMRLR0 to TMRLR2 (lower)
bit
7
6
5
4
000052H
000056H
00005AH
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
XXXXXXXXB
Read/Write
- : Unused
50
DS07-13733-6E
MB90800 Series
(2) Block diagram
Internal data bus
TMRLR
16-bit reload register
Reload signal
TMR
16-bit timer register
(down counter)
Reload control
circuit
UF
CLK
Count clock generation circuit
Machine
clock φ
3
Prescaler
Gate
input
Valid clock
identification circuit
Clear
Wait signal
CLK
Output signal
generation circuit
Pin
Input control
circuit
Clock
selector
Reverse
Output signal
generation circuit
EN
External clock
OUTL
Select
function
3
Select signal
Pin
2
RELD
Operation
control circuit
OUTE
Timer control status register (TMCSR)
DS07-13733-6E
51
MB90800 Series
11. Watch timer
The watch timer is a 15-bit timer using the subclock. It can generate the interrupt request for each interval time.
The watch timer can also be used as the clock source of the watchdog timer by setting so.
(1) Register list
Watch timer control register (WTC)
bit
7
6
5
0000AAH
WDCS
SCE
WTIE
R/W
R
4
3
2
1
0
WTOF
WTR
WTC2
WTC1
WTC0
Initial Value
1X011000B
R/W
R/W
R/W
R/W
R/W
Read/Write
WTC1
WTC0
R/W
(2) Block diagram
Watch timer control register (WTC)
WDCS
SCE
WTIE
WTOF
WTR
WTC2
Clear
28
29
Sub clock
Watch counter
210
211
Interval
selector
Interrupt
generation
circuit
Watch timer
interrupt
212
213
210 213 214 215
214
To watchdog timer
52
DS07-13733-6E
MB90800 Series
12. Watchdog timer
The watchdog timer is a timer counter provided for preventing program malfunction. The watchdog timer is a 2bit counter operating with an output of the timebase timer or watch timer as count clock and resets the CPU
when the counter is not cleared within the interval time.
(1) Register list
Watchdog timer control register (WDTC)
bit
7
6
5
0000A8H
PONR
⎯
WRST
⎯
R
R
4
3
2
1
0
ERST
SRST
WTE
WT1
WT0
Initial Value
XXXXX111B
R
R
W
W
W
Read/Write
− : Unused
(2) Block diagram
Watchdog timer control register (WDTC)
PONR
Watch mode start
Time-base timer mode start
Sleep mode start
Hold status start
WRST ERST SRST WTE
WT1
WT0
WDCS bit of watch timer
control register (WTC)
SCM bit of clock selection
register (CKSCR)
2
CLR and start-up
Watchdog timer
Counter
clear control
circuit
Count
clock
selector
Stop mode start
2-bit
counter
CLR
Watchdog reset
generation
circuit
CLR
Internal
reset
generation
circuit
4
4
Clear
Time base counter
Dividing HCLK by 2
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
SCLK
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
HCLK: Oscillation clock
SCLK: Sub clock
DS07-13733-6E
53
MB90800 Series
13. Time-base timer
The time-base timer has a function that enables a selection of four interval times using 18-bit free-run counter
(time-base counter) with synchronizing to the internal count clock (two division of original oscillation). Furthermore, the function of timer output of oscillation stabilization wait or function supplying operation clocks for
watchdog timer are provided.
(1) Register list
Time-base timer control register (TBTC)
bit
15
14
13
0000A9H Reserved ⎯
⎯
⎯
R/W
⎯
12
11
10
9
8
TBIE
TBOF
TBR
TBC1
TBC0
Initial Value
1 - - 00100B
R/W
R/W
W
R/W
R/W
Read/Write
- : Unused
(2) Block diagram
To PPG timer
To watchdog timer
Time-base timer counter
Dividing HCLK by 2
× 21 × 22
× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218
Power-on reset
Stop mode start
Hold status start
CKSCR : MCS = 1→0*1
CKSCR : SCS = 0→1*2
OF
OF
OF
OF
To clock controller
Oscillation stabilizing
Wait time selector
Counter
clear
control
circuit
Interval timer selector
TBOF set
TBOF clear
Time-base timer control register (TBTC)
Reserved
⎯
⎯
TBIE TBOF TBR TBC1 TBC0
Time-base timer interrupt signal
⎯
OF
HCLK
*1
*2
54
: Unused
: Overflow
: Oscillation clock
: The machine clock is switched from main/sub clock to PLL clock.
: The machine clock is switched from sub clock to main clock.
DS07-13733-6E
MB90800 Series
14. Clock generator
The clock generator controls operation of the internal clock which is the operation clock for the CPU and peripheral
devices. This internal clock is used as machine clock and its one cycle as machine cycle. In addition, the clock
generated by original oscillation is used as oscillation clock and that by internal PLL oscillation as PLL clock.
(1) Register list
Clock selection register (CKSCR)
bit
15
14
13
0000A1H
SCM
MCM
WS1
R
DS07-13733-6E
R
R/W
12
11
10
9
8
WS0
SCS
MCS
CS1
CS0
Initial Value
11111100B
R/W
R/W
R/W
R/W
R/W
Read/Write
55
MB90800 Series
(2) Block diagram
Standby control circuit
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0 Reserved
Pin High-Z
control circuit
RST
Pin
Pin High-Z control
Internal reset
generation circuit
CPU intermittent
operation selector
Internal reset
Intermittent cycle selection
CPU clock
control circuit
Standby control
circuit
Release
interrupting
CPU clock
Stop, sleep signal
Stop signal
Peripheral clock
control circuit
Machine clock
Oscillation stabilization wait
Clock generation block
Clock
selector
Oscillation
stabilization
wait time
selector
2
Dividing
by 4
SCLK
2
PLL multiplying
circuit
Sub clock
generation
circuit
X0A
Pin
X1A
Pin
Peripheral clock
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
System
clock
generation
circuit
Dividing
by 2
HCLK
X0
Pin
X1
Pin
Dividing
by
1024
Dividing
by 2
Dividing
by 4
Dividing
by 4
Dividing
by 4
Dividing
by 2
MCLK
Time-base timer
To watchdog timer
HCLK : Oscillation clock
MCLK : Main clock
SCLK : Sub clock
56
DS07-13733-6E
MB90800 Series
(3) Clock supply map
Clock generation circuit
Timer clock divider
X0
Watch timer
Oscillation
circuit
X1
Watchdog timer
Internal resources
X0A
Selector
Oscillation
circuit
X1A
Time-base timer
1
2
3
LCD controller
16-bit Reload Timer
8/10-bit A/D converter
Serial I/O
Free-run timer
Input capture
Output compare
4
PLL multiplying circuit
PCLK
CPU (F2MC-16LX)
2 division circuit
Selector
HCLK
MCLK
2 division circuit
HCLK
MCLK
PCLK
SCLK
ROM/RAM (memory)
SCLK
: Oscillation clock
: Main clock
: PLL clock
: Sub clock
DS07-13733-6E
57
MB90800 Series
15. Low power consumption mode
The low-power consumption mode has the following CPU operation modes by selecting the operation clock and
operating the control of the clock.
• Clock mode
(PLL clock mode, main clock mode and sub clock mode)
• CPU intermittent operation mode
(PLL clock intermittent operation mode, main clock intermittent operation mode and subclock intermittent
operation mode)
• Standby mode
(Sleep mode, time base timer mode, stop mode and watch mode)
(1) Register list
Low power consumption mode control register (LPMCR)
bit
7
6
5
4
3
2
0000A0H
STP
SLP
SPL
RST
TMD
CG1
W
58
W
R/W
W
R/W
R/W
1
0
CG0
Reserved
Initial Value
00011000B
R/W
R/W
Read/Write
DS07-13733-6E
MB90800 Series
(2) Block diagram
Standby control circuit
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD CG1 CG0 Reserved
Pin High-Z
control circuit
RST
Pin High-Z control
Internal reset
generation
circuit
Pin
CPU intermittent
operation selector
Internal reset
Intermittent cycle selection
CPU clock
control circuit
Standby control
circuit
Release of
interrupt
CPU clock
Stop, sleep signal
Stop signal
Peripheral
clock control
Machine clock
Release of oscillation stabilization wait
Clock generation block
Clock
selector
Oscillation
stabilization
wait time
selector
2
Dividing
by 4
SCLK
X0A
Pin
X1A
Pin
2
PLL multiplying
circuit
Sub
clock
generation
circuit
Peripheral clock
SCM MCM WS1 WS0 SCS MCS CS1 CS0
Clock selection register (CKSCR)
System
clock
generation
circuit
Dividing
by 2
HCLK
X0
Pin
X1
Pin
Dividing
by 1024
Dividing
by 2
Dividing
by 4
Dividing
by 4
Dividing
by 4
Dividing
by 2
MCLK
Time-base timer
To watchdog timer
HCLK
MCLK
SCLK
DS07-13733-6E
: Oscillation clock
: Main clock
: Sub clock
59
MB90800 Series
(3) Figure of status transition
External reset, watchdog timer reset, software reset
Power supply
Reset
SCS = 0
Power-on reset
End of oscillation
stabilization wait
SCS = 1
MCS = 0
Main clock mode
SLP = 1
MCS = 1
Interrupt
Main sleep mode
TMD = 0
Interrupt
Time-base
timer mode
STP = 1
End of oscillation
stabilization wait
Main clock Oscillation
stabilization wait
60
SCS = 0
SCS = 1
SLP = 1
Interrupt
PLL sleep mode
TMD = 0
Interrupt
Time-base
timer mode
STP = 1
Main stop mode
Interrupt
PLL clock mode
SLP = 1
Interrupt
Sub sleep mode
TMD = 0
Interrupt
Watch mode
STP = 1
PLL stop mode
Interrupt
Sub clock mode
End of oscillation
stabilization wait
PLL clock Oscillation
stabilization wait
Sub stop mode
Interrupt
End of oscillation
stabilization wait
Sub clock Oscillation
stabilization wait
DS07-13733-6E
MB90800 Series
16. Timer clock output
The timer clock output circuit divides the oscillation clock by the time-base timer and generates and outputs the
set division clock. Selectable from 32/64/128/256 division of the oscillation clock.
The timer clock output circuit is inactive in reset or stop mode. It is active in normal run, sleep, or pseudo-timer
mode.
PLL_Run
Main_Run
Pseudo
clock
Sleep
Operation status
STOP
Reset
×
×
Note : When the time-base timer is cleared while using the timer clock output circuit, the clock is not correctly output.
For detail of the time-base timer’s clear condition, see the section of time-base timer in the MB90800
Hardware Manual.
(1) Register list
Watch clock output control register (TMCS)
bit
15
14
0000AFH
13
12
11
10
9
8
⎯
⎯
⎯
⎯
⎯
TEN
TS1
TS0
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
Initial Value
XXXXX000B
Read/Write
- : Unused
(2) Block diagram
Timer clock selection circuit
X0
X1
Oscillation
circuit
Selector
Timer clock output
Time-base timer
Dividing by 2
DS07-13733-6E
61
MB90800 Series
17. ROM mirroring function selection module
ROM mirroring function selection module provides the setting so that ROM data located in FF bank can be read
by access to 00 bank.
(1) Register list
ROM mirror function select register (ROMM)
bit
15
14
00006FH
13
12
11
10
9
8
MI
R/W
Initial Value
XXXXXXX1B
Read/Write
- : Unused
(2) Block diagram
F2MC-16LX bus
ROM mirroring function selection
Address area
Address
Data
FF bank
00 bank
ROM
Note : Do not access to ROM mirroring function selection register in the middle of the operation of the address
008000H to 00FFFFH.
62
DS07-13733-6E
MB90800 Series
18. Interrupt controller
Interrupt control register is in the interrupt controller. The register corresponds to all I/O of interrupt function. The
register has following functions;
• Setting of Interrupt level at correspondent peripheral circuit.
(1) Register list (at writing)
Interrupt control register
Address :
ICR01
ICR03
ICR05
ICR07
ICR09
ICR11
ICR13
ICR15
0000B1H
0000B3H
0000B5H
0000B7H
0000B9H
0000BBH
0000BDH
0000BFH
Initial Value
bit 15
14
13
12
11
10
9
8
00000111B
ICS3
ICS2
W
W
ICS1
ICS0
W
W
ISE
IL2
IL1
IL0
R/W
R/W
R/W
R/W
Read/Write
Interrupt control register
Address :
ICR00
ICR02
ICR04
ICR06
ICR08
ICR10
ICR12
ICR14
0000B0H
0000B2H
0000B4H
0000B6H
0000B8H
0000BAH
0000BCH
0000BEH
Initial Value
bit
7
6
5
4
3
2
1
0
ICS3
ICS2
ICS1
ICS0
ISE
IL2
IL1
IL0
W
W
W
W
R/W
R/W
R/W
R/W
00000111B
Read/Write
Note : Do not access using read modify write instruction because it causes the malfunction.
DS07-13733-6E
63
MB90800 Series
(2)Register list (at reading)
Interrupt control register
Address :
ICR01
ICR03
ICR05
ICR07
ICR09
ICR11
ICR13
ICR15
Initial Value
0000B1H
0000B3H
bit 15
0000B5H
0000B7H
⎯
0000B9H
0000BBH
0000BDH
0000BFH
Read/Write
⎯
Initial Value
14
13
12
11
10
9
8
00000111B
⎯
S1
S0
ISE
IL2
IL1
IL0
⎯
R
R
R/W
R/W
R/W
R/W
Read/Write
Interrupt control register
Address :
ICR00
ICR02
ICR04
ICR06
ICR08
ICR10
ICR12
ICR14
0000B0H
0000B2H
0000B4H
0000B6H
0000B8H
0000BAH
0000BCH
0000BEH
Read/Write
Initial Value
Initial Value
bit
7
6
5
4
3
2
1
0
00000111B
⎯
⎯
S1
S0
ISE
IL2
IL1
IL0
⎯
⎯
R
R
R/W
R/W
R/W
R/W
Read/Write
- : Unused
Note : Do not access using read modify write instruction because it causes the malfunction.
64
DS07-13733-6E
MB90800 Series
(3) Block diagram
F2MC-16LX bus
3
IL2
IL1
IL0
Interrupt request
(Peripheral resources)
3
32
Judging the priority
of interrupt
3
DS07-13733-6E
(CPU)
Interrupt level
65
MB90800 Series
19. LCD controller/driver
The LCD controller/driver contains 24 × 8-bit display data memory and controls the LCD display with four common
output lines and 48 segment output lines. Three duty outputs can be selected to directly drive the LCD panel
(liquid crystal display).
• Contains an LCD driving voltage split resistor. Moreover, the external division resistance can be connected.
• A maximum of four common output lines (COM0 to COM3) and 48 segment output lines (SEG0 to SEG47)
are available.
• Contains 24-byte display data memory (display RAM).
• For the duty, 1/2, 1/3, or 1/4 can be selected (restricted by bias setting).
• The LCD can directly be driven.
Bias
1/2 duty
1/3 duty
1/4 duty
×
×
1/2 bias
×
1/3 bias
: Recommended mode
× : Disable
(1) Register list
• LCDC control register (upper) (LCRH)
bit
15
14
13
00005DH
9
8
Initial Value
CS1
CS0
SS3
SS2
SS1
SS0
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
4
3
2
1
0
Initial Value
CSS
LCEN
VSEL
BK
MS1
MS0
FP1
FP0
00010000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
5
4
3
2
1
0
Initial Value
SE4
SE3
SE2
SE1
SE0
LCR
00000000B
R/W
R/W
R/W
R/W
R/W
R/W
Read/Write
Reserved Reserved
R/W
66
10
VS0
• LCDC range register (LCRR)
bit
7
6
00005EH
11
SS4
• LCDC control register (lower) (LCRL)
bit
7
6
5
00005CH
12
R/W
DS07-13733-6E
MB90800 Series
(2) Block diagram
LCDC range register
(LCRR)
V0
LCD control register
(LCRL)
Main
Clock
V2
V3
Division resistor
4
Prescaler
Internal data bus
V1
Timing
controller
Common
driver
Sub clock
(32 kHz)
Circuit
of
making
to
exchange
48
Segment
driver
Display RAM
24 × 8-bit
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
to
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
LCD control register
(LCRH)
Controller
DS07-13733-6E
Driver
67
MB90800 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1
Symbol
Rating
Unit
Remarks
Min
Max
VCC
VSS − 0.3
VSS + 4.0
V
AVCC
VSS − 0.3
VSS + 4.0
V
VCC ≥ AVCC*2
VSS − 0.3
VSS + 4.0
V
*3
VSS − 0.3
VSS + 6.0
V
N-ch open-drain
(5 V withstand voltageI/O) *4
*3
Input voltage*1
VI
Output voltage*1
VO
VSS − 0.3
VSS + 4.0
V
IOL11
⎯
10
mA
Other than P74, P75,
P40 to P47*5
IOL12
⎯
30
mA
P74, P75, P40 to P47
(Heavy-current output port) *5
IOLAV1
⎯
3
mA
Other than P74, P75,
P40 to P47*6
IOLAV2
⎯
15
mA
P74, P75, P40 to P47
(Heavy-current output port) *6
“L” level maximum total output current
ΣIOL
⎯
120
mA
“L” level average total output current
ΣIOLAV
⎯
60
mA
*7
IOH11
⎯
− 10
mA
Other than P74, P75,
P40 to P47*5
IOH12
⎯
− 12
mA
P40 to P47
(Heavy-current output port) *5
“H” level average output current
IOHAV
⎯
−3
mA
*6
“H” level maximum total output
current
ΣIOH
⎯
− 120
mA
ΣIOHAV
⎯
− 60
mA
Power consumption
Pd
⎯
351
mW
Operating temperature
TA
− 40
+ 85
°C
TSTG
− 55
+ 150
°C
“L” level maximum output current
“L” level average output current
“H” level maximum output current
“H” level average total output current
Storage temperature
*7
*1 : The parameter is based on VSS = AVSS = 0.0 V.
*2 : AVCC should not be exceeding VCC at power-on etc.
*3 : VI, VO, should not exceed Vcc + 0.3 V.
*4 : Applicable to pins : P74, P75
*5 : A peak value of an applicable one pin is specified as a maximum output current.
*6 : An average current value of an applicable one pin within 100 ms is specified as an average output current.
(Average value is found by multiplying operating current by operating rate.)
*7 : An average current value of all pins within 100 ms is specified as an average total output current.
(Average value is found by multiplying operating current by operating rate.)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
68
DS07-13733-6E
MB90800 Series
2. Recommended Operating Conditions
( VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
“H” level input voltage
“L” level input voltage
Operating temperature
Symbol
Value
Unit
Remarks
Min
Max
2.7
3.6
V
At normal operating
1.8
3.6
V
Stop operation state maintenance
VIH
0.7 VCC
VCC + 0.3
V
CMOS input pin
VIHS
0.8 VCC
VCC + 0.3
V
CMOS hysteresis input pin
(Resisting pressure of 5 V is VCC = 5.0 V)
VIHM
VCC − 0.3
VCC + 0.3
V
MD pin input
VIL
VSS − 0.3
0.3 VCC
V
CMOS input pin
VILS
VSS − 0.3
0.2 VCC
V
CMOS hysteresis input pin
VILM
VSS − 0.3
VSS + 0.3
V
MD pin input
TA
− 40
+ 85
°C
VCC
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS07-13733-6E
69
MB90800 Series
3. DC Characteristics
Parameter
Symbol
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin name
Conditions
Unit
Remarks
Min
Typ
Max
VOH
Output pins
other than
P40 to P47,
P74, P75
IOH = − 4.0 mA
VCC − 0.5
⎯
Vcc
V
VOH1
P40 to P47 IOH = − 8.0 mA
VCC − 0.5
⎯
Vcc
V
VOL
Output pins
other than
P40 to P47,
P74, P75
IOL = 4.0 mA
Vss
⎯
Vss + 0.4
V
VOL1
P40 to P47
IOL = 15.0 mA
Vss
⎯
Vss + 0.6
V
Heavy-current
output port
VOL2
P74, P75
IOL = 15.0 mA
⎯
0.5
Vss + 0.8
V
Open-drain pin
Open-drain output
application voltage
VD1
P74, P75
⎯
Vss − 0.3
⎯
Vss + 5.5
V
Input leak current
IIL
All output
pins
VCC = 3.3 V,
VSS < VI < VCC
− 10
⎯
+ 10
μA
RUP
RST
Vcc = 3.3 V,
TA = + 25 °C
25
50
100
kΩ
Pull-down resistor
RDOWN
MD2
Vcc = 3.3 V,
TA = + 25 °C
25
50
100
kΩ
Open drain output
current
Ileak
P74, P75
⎯
⎯
0.1
10
μA
VCC = 3.3 V,
Internal frequency 25 MHz
At normal operating
⎯
48
60
mA
VCC = 3.3 V,
Internal frequency 25 MHz
At Flash writing
⎯
60
75
mA
Flash memory
products
VCC = 3.3 V,
Internal frequency 25 MHz
At Flash erasing
⎯
60
75
mA
Flash memory
products
VCC = 3.3 V,
Internal frequency 25 MHz
at sleep mode
⎯
22.5
30
mA
“H” level output
voltage
“L” level output
voltage
Pull-up resistor
ICC
Power
supply
current
VCC
ICCS
Heavy-current
output port
Except
Flash memory
products
(Continued)
70
DS07-13733-6E
MB90800 Series
(Continued)
Parameter
Power
supply
current
LCD division
resistance
Symbol
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin name
Conditions
Unit Remarks
Min
Typ Max
ICCTS
VCC = 3.3 V,
Internal frequency 3 MHz
at timer mode
ICCL
VCC = 3.3 V,
Internal frequency 8 kHz
at subclock operation,
(TA = + 25 °C)
⎯
0.75
7
mA
⎯
15
140
μA
⎯
0.5
0.9
Flash
mA memory
products
ICCLS
VCC = 3.3 V,
Internal frequency 8 kHz
at subclock sleep operation,
(TA = + 25 °C)
⎯
13
40
μA
ICCT
VCC = 3.3 V,
Internal frequency 8 kHz
at watch mode
(TA = + 25 °C)
⎯
1.8
40
μA
ICCH
At Stop mode,
(TA = + 25 °C)
⎯
0.8
40
μA
VCC − V3
At LCR = 0 setting
100
200
400
VCC − V3
At LCR = 1 setting
12.5
25
50
V0 − V1,
V1 − V2,
V2 − V3
At LCR = 0 setting
50
100
200
V0 − V1,
V1 − V2,
V2 − V3
At LCR = 1 setting
6.25
12.5
25
⎯
⎯
2.5
kΩ
⎯
⎯
15
kΩ
−5
⎯
+5
μA
VCC
RLCD
COM0 to COM3
RVCOM
output impedance
COM0
to
COM3
SEG0 to SEG47
RVSEG
output impedance
SEG0
to
SEG47
LCD leak current
ILCDC
V0 to V3,
COM0
to
COM3,
SEG0
to
SEG47
kΩ
MASK ROM
products
*
V1 to V3 = 3.3 V
⎯
* : LCD internal divided resistor can be select two type resistor by internal divided resistor selecting bit (LCR) of
LCDC range register (LCRR) .
DS07-13733-6E
71
MB90800 Series
4. AC Characteristics
(1) Clock timing
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Sym
CondiPin name
Unit
Remarks
bol
tions
Min
Typ
Max
3
16
External crystal
oscillation
3
16
× 1/2 (at PLL stop)
At oscillation circuit
4
16
Multiply by 1
At oscillation circuit
4
12.5
Multiply by 2
At oscillation circuit
4
8.33
Multiply by 3
At oscillation circuit
X0, X1
Clock frequency
4
fCH
X0
⎯
⎯
6.25
MHz
Multiply by 4
At oscillation circuit
3
25
× 1/2 (at PLL stop)
At external clock
4
25
Multiply by 1
At external clock
4
12.5
Multiply by 2
At external clock
4
8.33
Multiply by 3
At external clock
4
6.25
Multiply by 4
At external clock
fCL
X0A, X1A
⎯
32.768
⎯
kHz
tHCYL
X0, X1
40
⎯
333
ns
tLCYL X0A, X1A
⎯
30.5
⎯
μs
PWH
PWL
X0
5
⎯
⎯
ns
Set duty ratio 50% ± 3%
PWLH
PWLL
X0A
⎯
15.2
⎯
μs
Set duty ratio at 30% to
70% as a guideline.
Input clock rise time and
fall time
tcr
tcf
X0
⎯
⎯
5
ns
At external clock
Internal operating clock
frequency
fCP
⎯
1.5
⎯
25
MHz
fCP1
⎯
⎯
8.192
⎯
kHz When sub clock is used
tCP
⎯
40
⎯
666
ns
When main clock is
used
tCP1
⎯
⎯
122.1
⎯
μs
When sub clock is used
Clock cycle time
Input clock pulse width
Internal operating clock
cycle time
72
When main clock is
used
DS07-13733-6E
MB90800 Series
• X0, X1 clock timing
tC
0.8 VCC
0.2 VCC
PWH
PWL
tcr
tcf
• X0A, X1A clock timing
tCL
0.8 VCC
0.2 VCC
PWLH
PWLL
tcf
DS07-13733-6E
tcr
73
MB90800 Series
• PLL operation guarantee range
Relation between internal operation clock frequency and power supply voltage
PLL operation guarantee range
Power voltage V CC (V)
3.6
3.0
2.7
Normal operation
assurance range
1.5
4.5
16
25
Internal operation clock fCP (MHz)
Relation between oscillation clock frequency and internal operating clock frequency
Multiply by 4 Multiply by 3
Internal operation clock fCP (MHz)
25
Multiply by 1
Multiply by 2
16
× 1/2
(PLL off)
12
External clock
8
6
4.5
4
3
4.5
4
6
8
12
16
25
Original oscillation clock fCH (MHz)
Rating values of alternating current is defined by the measurement reference voltage values shown below :
74
• Input signal waveform
• Output signal waveform
Hysteresis input pin
Output pin
0.8 VCC
2.4 V
0.2 VCC
0.8 V
DS07-13733-6E
MB90800 Series
(2) Reset input timing
Symbol
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
CondiPin name
Unit
Remarks
tions
Min
Max
⎯
500
Reset input time
tRSTL
RST
ns
At normal operating,
at time base timer mode,
at main sleep mode,
at PLL sleep mode
μs
At stop mode,
at sub clock mode,
at sub sleep mode,
at watch mode
⎯
Oscillation time
of oscillator*+
500 ns
⎯
* : Oscillation time of oscillator is time until oscillation reaches 90% of amplitude. It takes several milliseconds to
several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds
on a ceramic oscillator, and 0 milliseconds on an external clock.
• In normal operating, time base timer mode, main sleep mode and PLL sleep mode
tRSTL
RST
0.2 VCC
0.2 VCC
• In stop mode, sub clock mode, sub sleep mode and watch mode
tRSTL
RST
0.2 VCC
X0
Internal operating
clock
0.2 VCC
90% of
amplitude
Oscillation time
of oscillator
500 ns
Wait time for stabilization oscillator
Execute instruction
Internal reset
DS07-13733-6E
75
MB90800 Series
(3) Power-on reset
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
CondiSymbol Pin name
Unit
Remarks
tions
Min
Max
Power supply rising time
tR
VCC
Power supply shutdown
time
tOFF
VCC
⎯
⎯
30
ms
At normal operating
1
⎯
ms
Wait time until power
on
Notes : • VCC should be set under 0.2 V before power-on rising up.
• These value are for power-on reset.
• In the device, there are internal registers which is initialized only by a power-on reset. If these initialization
is executing, power-on procedure must be obeyed by these value.
tR
VCC
2.7 V
0.2 V
0.2 V
0.2 V
tOFF
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing power
supply voltages during operation, raise the power smoothly by suppressing variation of voltages as shown
below.
VCC
Limiting the slope of rising within
50 mV/ms is recommended.
2.7 ± 0.3 V
RAM data hold
VSS
76
DS07-13733-6E
MB90800 Series
(4) Serial I/O
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Symbol
Pin name
Conditions
Unit
Min
Max
Parameter
Serial clock cycle time
tSCYC
SC0 to SC3
SCK ↓ → SOT delay time
tSLOV
SC0 to SC3,
SO0 to SO3
Valid SIN → SCK ↑
tIVSH
SCK ↑ → Valid
SIN hold time
tSHIX
Serial clock “H” pulse width
tSHSL
Serial clock “L” pulse width
tSLSH
SCK ↓ → SOT delay time
tSLOV
Valid SIN → SCK ↑
tIVSH
SCK ↑ → valid
SIN hold time
tSHIX
Internal shift clock
mode output pin :
CL = 80 pF + 1TTL
SC0 to SC3,
SI0 to SI3
SC0 to SC3
External shift clock
mode output pin :
CL = 80 pF + 1TTL
SC0 to SC3,
SO0 to SO3
SC0 to SC3,
SI0 to SI3
8 tCP
⎯
ns
−80
+ 80
ns
100
⎯
ns
60
⎯
ns
4 tCP
⎯
ns
4 tCP
⎯
ns
⎯
150
ns
60
⎯
ns
60
⎯
ns
Notes : • The above rating is in CLK synchronous mode.
• C L is a load capacitance value on pins for testing.
• tCP is machine cycle frequency (ns) . Refer to “ (1) Clock timing”.
• Internal shift clock mode
tSCYC
2.4 V
SC
0.8 V
0.8 V
tSLOV
2.4 V
SO
0.8 V
tIVSH
SI
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
• External shift clock mode
tSLSH
SC
0.2 VCC
tSHSL
0.8 VCC
0.8 VCC
0.2 VCC
tSLOV
2.4 V
SO
0.8 V
tIVSH
SI
DS07-13733-6E
tSHIX
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
77
MB90800 Series
(5) Timer input timing
Parameter
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin name
Conditions
Unit
Min
Max
Symbol
tTIWH
tTIWL
Input pulse width
TIN0 to TIN2,
IC0, IC1
⎯
4 tCP
⎯
ns
Note : tCP is machine cycle frequency (ns) . Refer to “ (1) Clock timing”.
• Timer Input Timing
0.8 VCC
0.8 VCC
TINx
ICx
0.2 VCC
tTIWH
0.2 VCC
tTIWL
(6) Timer output timing
Parameter
Symbol
CLK ↑ → TOUT change time
tTO
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
Pin name
Conditions
Unit
Min
Max
TOT0 to TOT2,
PPG0, PPG1,
OCU0, OCU1
⎯
30
⎯
ns
• Timer Output Timing
2.4 V
CLK
tTO
TOTx
PPGx
OCUx
2.4 V
0.8 V
(7) Trigger input timing
Parameter
Symbol
Input pulse width
tTRGH
tTRGL
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Value
CondiUnit
Remarks
Pin name
tions
Min
Max
INT0 to INT3
⎯
5 tCP
⎯
ns
At normal operating
1
⎯
μs
In Stop mode
Note : tCP is machine cycle frequency (ns) . Refer to “ (1) Clock timing”.
• Trigger Input Timing
0.8 VCC
0.8 VCC
INTx
0.2 VCC
tTRGH
78
0.2 VCC
tTRGL
DS07-13733-6E
MB90800 Series
(8) I2C timing
Parameter
(AVCC = VCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40 °C to + 85 °C)
Standardmode
Symbol
Conditions
Unit
Min Max
SCL clock frequency
Hold time (repeated) START condition
SDA ↓ → SCL ↓
tHDSTA
“L” width of the SCL clock
tLOW
“H” width of the SCL clock
tHIGH
Set-up time for a repeated START condition
SCL ↑ → SDA ↓
tSUSTA
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT
Data set-up time
SDA ↓ ↑ → SCL ↑
Set-up time for STOP condition
SCL ↑ → SDA ↑
Bus free time between a STOP and START
condition
0
100
kHz
4.0
⎯
μs
4.7
⎯
μs
4.0
⎯
μs
4.7
⎯
μs
0
3.45
*3
μs
When power supply voltage of external
pull-up resistor is 5.0 V
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2 250
*4
When power supply voltage of external
pull-up resistor is 3.6 V
fCP*1 ≤ 20 MHz, R = 1.0 kΩ, C = 50 pF*2
⎯
ns
When power supply voltage of external
pull-up resistor is 5.0 V
fCP*1 > 20 MHz, R = 1.0 kΩ, C = 50 pF*2 200
*4
When power supply voltage of external
pull-up resistor is 3.6 V
fCP*1 > 20 MHz, R = 1.0 kΩ, C = 50 pF*2
⎯
ns
4.0
⎯
μs
4.7
⎯
μs
fSCL
tSUDAT
tSUSTO
tBUS
When power supply voltage of external
pull-up resistor is 5.0 V
R = 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 3.6 V
R = 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 5.0 V
R = 1.0 kΩ, C = 50 pF*2
When power supply voltage of external
pull-up resistor is 3.6 V
R = 1.0 kΩ, C = 50 pF*2
*1 : fCP is internal operation clock frequency. Refer to “ (1) Clock timing”.
*2 : R, C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*3 : The maximum tHDDAT only has to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.
*4 : Refer to “• Note of SDA and SCL set-up time”.
DS07-13733-6E
79
MB90800 Series
• Note of SDA and SCL set-up time
SDA
Input data set-up time
SCL
6 tcp
Note : The rating of the input data set-up time in the device connected to the bus cannot be satisfied depending on
the load capacitance or pull-up resistor.
Be sure to adjust the pull-up resistor of SDA and SCL if the rating of the input data set-up time cannot be
satisfied.
• Timing definition
SDA
tBUS
tLOW
tHDSTA
tSUDAT
SCL
tHDSTA
80
tHIGH
tHDDAT
fSCL
tSUSTA
tSUSTO
DS07-13733-6E
MB90800 Series
5. A/D Converter
(1) A/D Converter Electrical Characteristics
(VCC = AVCC = 3.3 V ± 0.3 V, VSS = AVSS = 0.0 V, TA = − 40°C to + 85 °C)
Symbol
Pin
name
Resolution
⎯
Total error
Parameter
Conditions
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
± 3.0
LSB
Nonlinear error
⎯
⎯
⎯
⎯
± 2.5
LSB
Differential linear
error
⎯
⎯
⎯
⎯
± 1.9
LSB
Zero transition
voltage
VOT
AN0
to
AN11
AVSS − 1.5LSB AVss + 0.5LSB AVSS + 2.5LSB
V
Full-scale
transition
voltage
VFST
AN0
to
AN11
AVcc − 3.5LSB AVcc − 1.5LSB AVcc + 0.5LSB
V
Conversion time
⎯
⎯
8.64*1
⎯
⎯
μs
Sampling time
⎯
⎯
2
⎯
⎯
μs
Analog port input
current
IAIN
AN0
to
AN11
⎯
⎯
10
μA
Analog input
voltage
VAIN
AN0
to
AN11
0
⎯
AVcc
V
Reference
voltage
⎯
AVcc
3.0
⎯
AVcc
V
Power supply
current
IA
AVcc
⎯
1.4
3.5
mA
IAH
AVcc
⎯
⎯
5*2
μA
⎯
Reference
voltage supplying
current
IR
AVcc
⎯
94
150
μA
IRH
AVcc
⎯
⎯
5*2
μA
Interchannel
disparity
⎯
AN0
to
AN11
⎯
⎯
4
LSB
Remarks
1 LSB =
(AVCC - AVSS)/
1024
*1 : At operating, main clock 25 MHz.
*2 : If A/D converter is not operating, a current when CPU is stopped is applicable (at Vcc − CPU = AVcc = 3.3 V)
DS07-13733-6E
81
MB90800 Series
(2) Notes on Using A/D Converter
• About the external impedance of analog input and its sampling time
A/D converter with sample & hold circuit. If the external impedance is too high to keep sufficient sampling time,
the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relation-ship
between the external impedance and minimum sampling time and either adjust the resistor value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
And, if the sampling time cannot be sufficient, connect a capacitor of about 0.1 μF to the analog input pin.
• Analog input circuit model
R
Analog input
Comparator
C
During sampling : ON
R
C
MB90803 (S)
1.9 kΩ (Max)
32.3 pF (Max)
MB90F804-201(101)/F803(S)/F809(S)
1.9 kΩ (Max)
25.0 pF (Max)
MB90V800
1.9 kΩ (Max)
32.3 pF (Max)
Note : The values are reference values.
• The relationship between external impedance and minimum sampling time
(External impedance = 0 kΩ to 20 kΩ)
(External impedance = 0 kΩ to 100 kΩ)
MB90F804-201(101)/
MB90F803(S)/
MB90803(S)/
MB90F809(S)
MB90V800
90
20
External impedance [kΩ]
External impedance [kΩ]
100
80
70
60
50
40
30
20
10
MB90F804-201(101)/
MB90803(S)/
MB90F803(S)/
MB90V800
MB90F809(S)
18
16
14
12
10
8
6
4
2
0
0
0
5
10
15
20
25
30
Minimum sampling time [μs]
35
0
1
2
3
4
5
6
7
8
Minimum sampling time [μs]
• About errors
As | AVCC − AVSS | becomes smaller, values of relative errors grow larger.
82
DS07-13733-6E
MB90800 Series
6. Definition of A/D Converter Terms
Resolution
Analog variation that is recognized by an A/D converter.
The 10-bit can resolve analog voltage into 210 = 1024.
Total error
This shows the difference between the actual voltage and the ideal value and means a total of error because of
offset error, gain error, non-linearity error and noise.
Linearity error
Deviation between a line across zero-transition line (00 0000 0000↔00 0000 0001) and full-scale transition line
(11 1111 1110↔11 1111 1111) and actual conversion characteristics.
Differential linear error
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
Total error
3FFH
3FEH
1.5 LSB
Actual conversion
characteristic
Digital output
3FDH
{1 LSB × (N − 1) + 0.5 LSB}
004H
VNT
(measurement value)
003H
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB
AVSS
(AVRL)
Total error of digital output N =
1LSB(Ideal value) =
Analog input
AVCC
(AVRH)
VNT − {1 LSB × (N − 1) + 0.5 LSB}
[LSB]
1 LSB
AVCC − AVSS
1024
[V]
N : A/D converter digital output value
VOT(Ideal value) = AVSS + 0.5 LSB [V]
VFST(Ideal value) = AVCC − 1.5 LSB [V]
VNT: A voltage at which digital output transitions from (N − 1)H to NH.
(Continued)
DS07-13733-6E
83
MB90800 Series
(Continued)
Linearity error
3FFH
Actual conversion characteristic
Actual conversion
characteristics
(N + 1)H
{1 LSB × (N − 1) + VOT}
Digital output
Ideal characteristics
VFST
3FDH
(measurement value)
Digital output
3FEH
Differential linear error
VNT
(measurement value)
004H
Actual conversion
characteristics
003H
NH
V(N + 1)T
(measurement value)
(N − 1)H
VNT
002H
(measurement value)
Ideal characteristics
001H
Actual conversion
characteristics
(N − 2)H
VOT (actual measurement value)
AVCC
(AVRH)
AVSS
(AVRL)
AVSS
(AVRL)
AVCC
(AVRH)
Analog input
Analog input
Linear error in digital output N =
Differential linear error in digital output N =
1 LSB =
VNT − {1 LSB × (N − 1) + VOT}
1 LSB
V (N + 1) T − VNT
1 LSB
VFST − VOT
1022
− 1LSB
[LSB]
[LSB]
[V]
N : A/D converter digital output value
VOT : Voltage at which digital output transits from 000H to 001H.
VFST : Voltage at which digital output transits from 3FEH to 3FFH.
84
DS07-13733-6E
MB90800 Series
7. Flash Memory (MB90F804-101/201, MB90F809/S)
Parameter
Conditions
Min
Typ
Max
⎯
1
15
⎯
9
⎯
⎯
16
⎯
10000
Average
TA = + 85 °C
20
Sector erase time
Chip erase time
Word (16-bit width)
programming time
Program/erase cycle
Flash memory data
retention time
Value
TA = + 25 °C
Vcc = 3.0 V
Unit
Remarks
s
Excludes 00H programming
prior to erasure.
3600
μs
Except for the over head time
of the system.
⎯
⎯
cycle
⎯
⎯
year
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C).
8. Dual Operation Flash Memory (MB90F803/S)
Parameter
Conditions
Value
Min
Typ
Max
Sector erase time
(4 Kbytes sector )
⎯
0.2
0.5
Sector erase time
(16 Kbytes sector)
⎯
0.5
7.5
⎯
4.6
⎯
⎯
64
⎯
10000
Average
TA = + 85 °C
20
Chip erase time
TA = +25 °C
Vcc = 3.0 V
Word (16-bit width)
programming time
Program/erase cycle
Flash memory data
retention time
Unit
Remarks
s
Excludes 00H programming
prior to erasure.
3600
μs
Except for the over head time
of the system.
⎯
⎯
cycle
⎯
⎯
year
*
* : This value comes from the technology qualification (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C).
DS07-13733-6E
85
MB90800 Series
■ ORDERING INFORMATION
Part number
MB90F804-101PF-G
MB90F804-201PF-G
MB90F803PF-G
MB90F803SPF-G
MB90F809PF-G
MB90F809SPF-G
MB90803PF-G
MB90803SPF-G
86
Package
100-pin plastic QFP
(FPT-100P-M06)
Remarks
With sub clock:
Products without "S" suffix
201 option products
Without sub clock:
Products with "S" suffix
101 option products
DS07-13733-6E
MB90800 Series
■ PACKAGE DIMENSION
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14×20-0.65
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
50
81
0.10(.004)
17.90±0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8˚
31
100
1
30
0.65(.026)
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
"A"
©2002-2008
FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
C
2002 FUJITSU LIMITED F100008S-c-5-5
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest Package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
DS07-13733-6E
87
MB90800 Series
■ MAIN CHANGES IN THIS EDITION
Page
17
Section
■ MEMORY MAP
Change Results
Corrected “Address #2” for part number MB90F809/S.
FC8000H → FD0000H
The vertical lines marked in the left side of the page show the changes.
88
DS07-13733-6E
MB90800 Series
MEMO
DS07-13733-6E
89
MB90800 Series
MEMO
90
DS07-13733-6E
MB90800 Series
MEMO
DS07-13733-6E
91
MB90800 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
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Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
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Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
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The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
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