TI LM25019SDX/NOPB 48v, 100ma constant on-time synchronous buck regulator Datasheet

LM25019
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SNVS952 – DECEMBER 2012
LM25019 48V, 100mA Constant On-Time Synchronous Buck Regulator
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FEATURES
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Wide 9V to 48V Input Range
Integrated 48V, High and Low Side Switches
No Schottky Required
Constant On-Time Control
No Loop Compensation Required
Ultra-Fast Transient Response
Nearly Constant Operating Frequency
Intelligent Peak Current Limit
Adjustable Output Voltage from 1.225V
Precision 2% Feedback Reference
Frequency Adjustable to 1MHz
Adjustable Undervoltage Lockout
Remote Shutdown
Thermal Shutdown
APPLICATIONS
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Industrial Equipments
Smart Power Meters
Telecommunication Systems
Isolated Bias Supply
DESCRIPTION
The LM25019 is a 48V, 100mA synchronous step-down regulator with integrated high side and low side
MOSFETs. The constant-on-time (COT) control scheme employed in the LM25019 requires no loop
compensation, provides excellent transient response, and enables very low step-down ratios. The on-time varies
inversely with the input voltage resulting in nearly constant frequency over the input voltage range. A high voltage
startup regulator provides bias power for internal operation of the IC and for integrated gate drivers.
A peak current limit circuit protects against overload conditions. The undervoltage lockout (UVLO) circuit allows
the input undervoltage threshold and hysteresis to be independently programmed. Other protection features
include thermal shutdown and bias supply undervoltage lockout.
The LM25019 is available in LLP-8 and PSOP-8 plastic packages.
Packages
•
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LLP-8
PSOP-8
Typical Application
LM25019
CIN
2
+
4
RUV2
RON
SD
3
BST
VIN
SW
RON
+
8
CBST
L1
VOUT
CVCC
VCC
UVLO
FB
RUV1
7
RTN
1
+
9V-48V
VIN
6
RFB2
5
RC
+
RFB1
COUT
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM25019
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Connection Diagram
RTN
1
VIN
2
8
SW
7
BST
6
VCC
5
FB
PSOP-8
UVLO
3
RON
4
Exp Pad
Figure 1. Top View (Connect Exposed Pad to RTN)
RTN
1
VIN
2
UVLO
3
RON
4
8 SW
LLP-8
Exp Pad
7 BST
6 VCC
5 FB
Figure 2. Top View (Connect Exposed Pad to RTN)
Pin Functions
Table 1. Pin Descriptions
Pin
Name
1
RTN
2
VIN
3
UVLO
4
Description
Application Information
Ground
Ground connection of the integrated circuit.
Input Voltage
Operating input range is 9V to 48V.
Input Pin of Undervoltage Comparator
Resistor divider from VIN to UVLO to GND programs the
undervoltage detection threshold. An internal current
source is enabled when UVLO is above 1.225V to
provide hysteresis. When UVLO pin is pulled below
0.66V externally, the parts goes in shutdown mode.
RON
On-Time Control
A resistor between this pin and VIN sets the switch ontime as a function of VIN. Minimum recommended ontime is 100ns at max input voltage.
5
FB
Feedback
This pin is connected to the inverting input of the internal
regulation comparator. The regulation level is 1.225V.
6
VCC
Output From the Internal High Voltage Series Pass
Regulator. Regulated at 7.6V
The internal VCC regulator provides bias supply for the
gate drivers and other internal circuitry. A 1.0μF
decoupling capacitor is recommended.
7
BST
Bootstrap Capacitor
An external capacitor is required between the BST and
SW pins (0.01μF ceramic). The BST pin capacitor is
charged by the VCC regulator through an internal diode
when the SW pin is low.
8
SW
Switching Node
Power switching node. Connect to the output inductor
and bootstrap capacitor.
EP
Exposed Pad
Exposed pad must be connected to RTN pin. Connect to
system ground plane on application board for reduced
thermal resistance.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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Absolute Maximum Ratings
(1)
VIN, UVLO to RTN
-0.3V to 53V
SW to RTN
-1.5V to VIN +0.3V
BST to VCC
53V
BST to SW
13V
RON to RTN
-0.3V to 53V
VCC to RTN
-0.3V to 13V
FB to RTN
-0.3V to 5V
ESD Rating (Human Body Model
Lead Temperature
(2)
2kV
(3)
200°C
Storage Temperature Range
(1)
(2)
(3)
-55°C to +150°C
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. The RTN
pin is the GND reference electrically connected to the substrate.
The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.
For detailed information on soldering plastic PSOP package, refer to the Packaging Data Book available from National Semiconductor
Corporation. Max solder time not to exceed 4 seconds.
Operating Ratings
(1)
VIN Voltage
9V to 48V
−40°C to +125°C
Operating Junction Temperature
(1)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. The RTN
pin is the GND reference electrically connected to the substrate.
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Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VIN = 48V, unless otherwise stated. See (1).
Symbol
Parameter
Conditions
Min
Typ
Max
6.25
7.6
8.55
Units
VCC Supply
VCC Reg
VCC Regulator Output
VIN = 48V, ICC = 20mA
VCC Current Limit
VIN = 48V (2)
VCC Undervoltage Lockout Voltage
(VCC Increasing)
26
4.15
VCC Undervoltage Hysteresis
V
mA
4.5
4.9
300
V
mV
VCC Drop Out Voltage
VIN = 9V, ICC = 20mA
2.3
V
IIN Operating Current
Non-Switching, FB = 3V
1.75
mA
IIN Shutdown Current
UVLO = 0V
50
225
µA
Buck Switch RDS(ON)
ITEST = 100mA, BST-SW =
7V
0.8
1.8
Ω
Synchronous RDS(ON)
ITEST = 200mA
0.45
1
Ω
Gate Drive UVLO
VBST − VSW Rising
3
3.6
Switch Characteristics
2.4
Gate Drive UVLO Hysteresis
260
V
mV
Current Limit
Current Limit Threshold
150
Current Limit Response Time
Time to Switch Off
Off-Time Generator (Test 1)
Off-Time Generator (Test 2)
270
370
mA
150
ns
FB = 0.1V, VIN = 48V
12
µs
FB = 1V, VIN = 48V
2.5
µs
On-Time Generator
TON Test 1
VIN = 32V, RON = 100k
270
TON Test 2
VIN = 48V, RON = 100k
188
TON Test 4
VIN = 10V, RON = 250k
1880
350
460
ns
250
336
ns
3200
4425
ns
Minimum Off-Time
Minimum Off-Timer
FB = 0V
144
ns
Regulation and Overvoltage Comparators
FB Regulation Level
Internal Reference Trip Point
for Switch ON
FB Overvoltage Threshold
Trip Point for Switch OFF
1.2
FB Bias Current
1.225
1.25
V
1.62
V
60
nA
Undervoltage Sensing Function
UV Threshold
UV Rising
1.19
1.225
1.26
V
UV Hysteresis Input Current
UV = 2.5V
-10
-20
-29
µA
Remote Shutdown Threshold
Voltage at UVLO Falling
0.32
0.66
V
110
mV
Thermal Shutdown Temp.
165
°C
Thermal Shutdown Hysteresis
20
°C
PSOP-8
40
°C/W
LLP-8
40
°C/W
Remote Shutdown Hysteresis
Thermal Shutdown
Tsd
Thermal Resistance
θJA
(1)
(2)
4
Junction to Ambient
All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.
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Typical Performance Characteristics
8
100
VOUT=10V, fsw=240 kHz
7
90
5
VCC (V)
Efficiency (%)
6
80
70
4
3
60
2
15V
24V
36V
48V
50
40
20
40
60
80
1
VCCvsVIN
0
0
100
2
4
6
Load Current (mA)
8
10
12
C004
C011
Figure 3. Efficiency at 240kHz, 10V
Figure 4. VCC vs VIN
8
8
7
VIN=48V
VIN=24V
VIN=48V
VIN=24V
7
6
6
ICC (mA)
5
VCC (V)
14
VIN (V)
4
3
1 MHz
5
4
450 kHz
2
3
1
VIN=15V
0
2
0
10
20
30
40
50
60
8
9
10
ICC (mA)
11
12
13
C012
C013
Figure 5. VCC vs ICC
Figure 6. ICC vs External VCC
20
Current Limit Off-Time (µs)
10,000
On-Time (ns)
14
VCC (V)
1,000
100
RON=499KOhms
VIN=48V
VIN=36V
VIN=24V
VIN=14V
16
12
8
4
RON=250kOhms
RON=100kOhms
10
10
20
30
40
50
VIN (V)
0
0.00
0.25
0.50
0.75
1.00
1.25
VFB (V)
C014
Figure 7. TON vs VIN and RON
C015
Figure 8. TOFF (ILIM) vs VFB and VIN
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Typical Performance Characteristics (continued)
1.84
120
UVLO=VIN, FB=3V
UVLO=0
100
Shutdown Current (µA)
Operating Current (mA)
1.80
1.76
1.72
1.68
1.64
80
60
40
20
1.60
0
0
10
20
30
40
50
0
10
VIN (V)
20
30
40
50
VIN (V)
C016
C017
Figure 9. IIN vs VIN (Operating, Non Switching)
Figure 10. IIN vs VIN (Shutdown)
300
Frequency (kHz)
250
200
150
100
RON=499kOhms,
VOUT=10V
50
10
15
20
25
30
35
40
45
50
VIN (V)
C010
Figure 11. Switching Frequency vs VIN
6
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Block Diagram
LM25019
START-UP
REGULATOR
VIN
VCC
V UVLO
20 µA
4.5V
UVLO
THERMAL
SHUTDOWN
UVLO
1.225V
SD
VDD REG
BST
0.66V
SHUTDOWN
BG REF
VIN
DISABLE
ON/OFF
TIMERS
RON
1.225V
SW
COT CONTROL
LOGIC
FEEDBACK
FB
ILIM
COMPARATOR
OVER-VOLTAGE
1.62V
CURRENT
LIMIT
ONE-SHOT
+
-
RTN
VILIM
Figure 12. Functional Block Diagram
Functional Description
The LM25019 step-down switching regulator features all the functions needed to implement a low cost, efficient,
buck converter capable of supplying up to 100mA to the load. This high voltage regulator contains 48V, Nchannel buck and synchronous switches, is easy to implement, and is provided in thermally enhanced PSOP-8
and LLP-8 packages. The regulator operation is based on a constant on-time control scheme using an on-time
inversely proportional to VIN. This control scheme does not require loop compensation. The current limit is
implemented with a forced off-time inversely proportional to VOUT. This scheme ensures short circuit protection
while providing minimum foldback. The simplified block diagram of the LM25019 is shown in Figure 12,
Functional Block Diagram.
The LM25019 can be applied in numerous applications to efficiently regulate down higher voltages. This
regulator is well suited for 12V and 24V rails. Protection features include: thermal shutdown, undervoltage
lockout, minimum forced off-time, and an intelligent current limit.
Control Overview
The LM25019 buck regulator employs a control principle based on a comparator and a one-shot on-timer, with
the output voltage feedback (FB) compared to an internal reference (1.225V). If the FB voltage is below the
reference the internal buck switch is turned on for the one-shot timer period, which is a function of the input
voltage and the programming resistor (RON). Following the on-time the switch remains off until the FB voltage
falls below the reference, but never before the minimum off-time forced by the minimum off-time one-shot timer.
When the FB pin voltage falls below the reference and the minimum off-time one-shot period expires, the buck
switch is turned on for another on-time one-shot period. This will continue until regulation is achieved and the FB
voltage is approximately equal to 1.225V (typ).
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In a synchronous buck converter, the low side (sync) FET is ‘on’ when the high side (buck) FET is ‘off’. The
inductor current ramps up when the high side switch is ‘on’ and ramps down when the high side switch is ‘off’.
There is no diode emulation feature in this IC, and therefore, the inductor current may ramp in the negative
direction at light load. This causes the converter to operate in continuous conduction mode (CCM) regardless of
the output loading. The operating frequency remains relatively constant with load and line variations. The
operating frequency can be calculated as follows:
gsw =
VOUT
10-10 x RON
(1)
The output voltage (VOUT) is set by two external resistors (RFB1, RFB2). The regulated output voltage is calculated
as follows:
VOUT = 1.225V x
RFB2 + RFB1
RFB1
(2)
L1
VOUT
SW
LM25019
RFB2
FB
RC
+
RFB1
VOUT
(low ripple)
COUT
(3)
This regulator regulates the output voltage based on ripple voltage at the feedback input, requiring a minimum
amount of ESR for the output capacitor (COUT). A minimum of 25mV of ripple voltage at the feedback pin (FB) is
required for the LM25019. In cases where the capacitor ESR is too small, additional series resistance may be
required (RC in Figure 13 Low Ripple Output Configuration).
For applications where lower output voltage ripple is required the output can be taken directly from a low ESR
output capacitor, as shown in Figure 13 Low Ripple Output Configuration. However, RC slightly degrades the
load regulation.
VCC Regulator
The LM25019 contains an internal high voltage linear regulator with a nominal output of 7.6V. The input pin (VIN)
can be connected directly to the line voltages up to 48V. The VCC regulator is internally current limited to 30mA.
The regulator sources current into the external capacitor at VCC. This regulator supplies current to internal circuit
blocks including the synchronous MOSFET driver and the logic circuits. When the voltage on the VCC pin
reaches the undervoltage lockout threshold of 4.5V, the IC is enabled.
The VCC regulator contains an internal diode connection to the BST pin to replenish the charge in the gate drive
boot capacitor when SW pin is low.
At high input voltages, the power dissipated in the high voltage regulator is significant and can limit the overall
achievable output power. As an example, with the input at 48V and switching at high frequency, the VCC
regulator may supply up to 7mA of current resulting in 48V x 7mA = 336mW of power dissipation. If the VCC
voltage is driven externally by an alternate voltage source, between 8V and 13V, the internal regulator is
disabled. This reduces the power dissipation in the IC.
L1
VOUT
SW
LM25019
RFB2
FB
RC
+
RFB1
VOUT
(low ripple)
COUT
Figure 13. Low Ripple Output Configuration
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Regulation Comparator
The feedback voltage at FB is compared to an internal 1.225V reference. In normal operation, when the output
voltage is in regulation, an on-time period is initiated when the voltage at FB falls below 1.225V. The high side
switch will stay on for the on-time, causing the FB voltage to rise above 1.225V. After the on-time period, the
high side switch will stay off until the FB voltage again falls below 1.225V. During start-up, the FB voltage will be
below 1.225V at the end of each on-time, causing the high side switch to turn on immediately after the minimum
forced off-time of 144ns. The high side switch can be turned off before the on-time is over, if the peak current in
the inductor reaches the current limit threshold.
Overvoltage Comparator
The feedback voltage at FB is compared to an internal 1.62V reference. If the voltage at FB rises above 1.62V
the on-time pulse is immediately terminated. This condition can occur if the input voltage and/or the output load
changes suddenly. The high side switch will not turn on again until the voltage at FB falls below 1.225V.
On-Time Generator
The on-time for the LM25019 is determined by the RON resistor, and is inversely proportional to the input voltage
(VIN), resulting in a nearly constant frequency as VIN is varied over its range. The on-time equation for the
LM25019 is:
TON =
10-10 x RON
VIN
(4)
See figure “TON vs VIN and RON” in the section “Performance Curves”. RON should be selected for a minimum ontime (at maximum VIN) greater than 100ns, for proper operation. This requirement limits the maximum switching
frequency for high VIN.
Current Limit
The LM25019 contains an intelligent current limit off-timer. If the current in the buck switch exceeds 240mA the
present cycle is immediately terminated, and a non-resetable off-timer is initiated. The length of off-time is
controlled by the FB voltage and the input voltage VIN. As an example, when FB = 0V and VIN = 48V, the
maximum off-time is set to 16μs. This condition occurs when the output is shorted, and during the initial part of
start-up. This amount of time ensures safe short circuit operation up to the maximum input voltage of 48V.
In cases of overload where the FB voltage is above zero volts (not a short circuit) the current limit off-time is
reduced. Reducing the off-time during less severe overloads reduces the amount of foldback, recovery time, and
start-up time. The off-time is calculated from the following equation:
TOFF(ILIM) =
0.07 x VIN
Ps
VFB + 0.2V
(5)
The current limit protection feature is peak limited. The maximum average output will be less than the peak.
N-Channel Buck Switch and Driver
The LM25019 integrates an N-Channel Buck switch and associated floating high voltage gate driver. The gate
driver circuit works in conjunction with an external bootstrap capacitor and an internal high voltage diode. A
0.01uF ceramic capacitor connected between the BST pin and the SW pin provides the voltage to the driver
during the on-time. During each off-time, the SW pin is at approximately 0V, and the bootstrap capacitor charges
from VCC through the internal diode. The minimum off-timer, set to 144ns, ensures a minimum time each cycle to
recharge the bootstrap capacitor.
Synchronous Rectifier
The LM25019 provides an internal synchronous N-Channel MOSFET rectifier. This MOSFET provides a path for
the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier has no diode emulation mode, and is designed to keep the regulator in continuous
conduction mode even during light loads which would otherwise result in discontinuous operation.
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Undervoltage Detector
The LM25019 contains a dual level Undervoltage Lockout (UVLO) circuit. When the UVLO pin voltage is below
0.66V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.66V but
less than 1.225V, the controller is in standby mode. In standby mode the VCC bias regulator is active while the
regulator output is disabled. When the VCC pin exceeds the VCC undervoltage threshold and the UVLO pin
voltage is greater than 1.225V, normal operation begins. An external set-point voltage divider from VIN to GND
can be used to set the minimum operating voltage of the regulator.
UVLO hysteresis is accomplished with an internal 20μA current source that is switched on or off into the
impedance of the set-point divider. When the UVLO threshold is exceeded, the current source is activated to
quickly raise the voltage at the UVLO pin. The hysteresis is equal to the value of this current times the resistance
RUV2.
UVLO
Mode
Description
<0.66V
VCC
Shutdown
VCC Regulator Disabled.
Switcher Disabled.
0.66V – 1.225V
Standby
VCC Regulator Enabled
Switcher Disabled.
VCC <4.5V
Standby
VCC Regulator Enabled.
Switcher Disabled.
VCC >4.5V
Operating
VCC enabled.
Switcher enabled.
>1.225V
If the UVLO pin is wired directly to the VIN pin, the regulator will begin operation once the VCC undervoltage is
satisfied.
VIN
CIN
2
VIN
+
RUV2
LM25019
3
UVLO
RUV1
Figure 14. UVLO Resistor Setting
Thermal Protection
The LM25019 should be operated so the junction temperature does not exceed 150°C during normal operation.
An internal Thermal Shutdown circuit is provided to protect the LM25019 in the event of a higher than normal
junction temperature. When activated, typically at 165°C, the controller is forced into a low power reset state,
disabling the buck switch and the VCC regulator. This feature prevents catastrophic failures from accidental
device overheating. When the junction temperature reduces below 145°C (typical hysteresis = 20°C), the VCC
regulator is enabled, and normal operation is resumed.
Application Information
SELECTION OF EXTERNAL COMPONENTS
Selection of external components is illustrated through a design example. The design example specifications are
as follows:
Buck Converter Design Specifications
Input Voltage Range
12.5V to 48V
Output Voltage
10V
Maximum Load Current
100mA
Switching Frequency
400kHz
10
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RFB1, RFB2:
VOUT = VFB x (RFB2/RFB1 + 1), and since VFB = 1.225V, the ratio of RFB2 to RFB1 calculates as 7:1. Standard
values of 6.98kΩ and 1.00kΩ are chosen. Other values could be used as long as the 7:1 ratio is maintained.
Frequency Selection:
At the minimum input voltage, the maximum switching frequency of LM25019 is restricted by the forced minimum
off-time (TOFF(MIN)) as given by:
gSW(MAX) =
1 - DMAX
1 - 10/12.5
=
= 1 MHz
200 ns
TOFF(MIN)
(6)
Similarly, at maximum input voltage, the maximum switching frequency of LM25019 is restricted by the minimum
TON as given by:
gSW(MAX) =
DMIN
10/48
=
= 2.1 MHz
TON(MIN) 100 ns
(7)
Resistor RON sets the nominal switching frequency based on the following equations:
gSW =
VOUT
K x RON
(8)
–10
where K = 1 x 10 . Operation at high switching frequency results in lower efficiency while providing the smallest
solution. For this example a 400kHz was selected, resulting in RON = 246kΩ. Selecting a standard value for RON
= 237kΩ results in a nominal frequency of 416kHz.
Inductor Selection:
The inductance selection is a compromise between solution size, output ripple, and efficiency. The peak inductor
current at maximum load current should be smaller than the minimum current limit of 150mA. The maximum
permissible peak to peak inductor ripple is:
ΔIL = 2*(ILIM(min) - IOUT(max) = 2*50 = 100mA
The minimum inductance is given by:
ûIL =
VIN - VOUT VOUT
x
VIN
L1 x gSW
(9)
Resulting in L=190µH. A standard value of 220µH is selected. For proper operation the inductor saturation
current should be higher than the peak encountered in the application. For robust short circuit protection, the
inductor saturation current should be higher than the maximum current limit of 300mA.
LM25019
CIN
2
+
+
4
CBYP
RUV2
Shutdown
RON
3
BST
VIN
SW
RON
+
8
CBST
L1
VOUT
CVCC
VCC
UVLO
FB
RUV1
7
RTN
1
+
9V-48V
VIN
6
RC
RFB2
5
RFB1
+
COUT
Figure 15. Reference Schematic for Selection of External Components
Output Capacitor:
The output capacitor is selected to minimize the capacitive ripple across it. The maximum ripple is observed at
maximum input voltage and is given by:
COUT =
ûIL
8 x gsw x ûVripple
(10)
where ΔVripple is the voltage ripple across the capacitor. Substituting ΔVripple = 10mV gives COUT = 2.94μF. A
4.7μF standard value is selected. An X5R or X7R type capacitor with a voltage rating 16V or higher should be
selected.
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Series Ripple Resistor RC:
The series resistor should be selected to produce sufficient ripple at the feedback node. The ripple produced by
RC is proportional to the inductor current ripple, and therefore RC should be chosen for minimum inductor current
ripple which occurs at minimum input voltage. The RC is calculated by the equation:
(11)
This gives an RC of greater than or equal to 10.8Ω. Selecting RC = 11Ω results in ~1V of maximum output
voltage ripple. For applications requiring lower output voltage ripple, Type II or Type III ripple injection circuits
should be used as described in the section “Ripple Configuration”.
VCC and Bootstrap Capacitor:
The VCC capacitor provides charge to bootstrap capacitor as well as internal circuitry and low side gate driver.
The Bootstrap capacitor provides charge to high side gate driver. A good value for CVCC is 1μF. A good value for
CBST is 0.01μF.
Input Capacitor:
Input capacitor should be large enough to limit the input voltage ripple:
CIN >
IOUT(MAX)
8 x gSW x ûVIN
(12)
choosing a ΔVIN = 0.5V gives a minimum CIN = 0.12μF. A standard value of 1μF is selected. The input capacitor
should be rated for the maximum input voltage under all conditions. A 50V, X7R dielectric should be selected for
this design.
Input capacitor should be placed directly across VIN and RTN (pin 2 and 1) of the IC. If it is not possible to place
all of the input capacitor close to the IC, a 0.1μF capacitor should be placed near the IC to provide a bypass path
for the high frequency component of the switching current. This helps limit the switching noise.
UVLO Resistors:
The UVLO resistors RFB1 and RFB2 set the UVLO threshold and hysteresis according to the following relationship:
VIN(HYS) = IHYS x RUV2
(13)
and
VIN (UVLO,rising) = 1.225V x (
RUV2
+ 1)
RUV1
(14)
where IHYS = 20μA. Setting UVLO hysteresis of 2.5V and UVLO rising threshold of 12V results in RUV1 = 14.53kΩ
and RUV2 = 125kΩ. Selecting standard value of RUV1 = 14kΩ and RUV2 = 125kΩ results in UVLO thresholds and
hysteresis of 12.4V and 2.5V respectively.
APPLICATION CIRCUIT: 12V TO 48V INPUT AND 10V, 100mA OUTPUT BUCK CONVERTER
The application schematic of a buck supply is shown in Figure 16 below. For output voltage (VOUT) above the
maximum regulation threshold of VCC (8.3V, see electrical characteristics), the VCC pin can be connected to VOUT
through a diode (D2), as shown below, for higher efficiency and lower power dissipation in the IC.
12
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SW
(TP6)
12V-48V
VIN
(TP1)
LM25019
2
C4
1 F
+
C5 +
R5
0.1 F 127 NŸ
GND
(TP2)
(TP4)
UVLO/SD
4
R3
237 NŸ 3
BST
VIN
SW
RON
7 0.01 F
+
C1
8
VCC
R7
14 NŸ
FB
RTN
1
6
0Ÿ
R8
VOUT
(TP3)
R2
0Ÿ
C6
3300 pF
C8
0.1 F
R1
6.98 NŸ
R4
46.4 NŸ
UVLO
EXP
220 H
L1
D2
+ C9
4.7 F
5
+
U1
R6
1 NŸ
C7
1 F
GND
(TP5)
Figure 16. Final Schematic for 12V to 48V Input, and 10V, 100mA Output Buck Converter
ISOLATED DC-DC CONVERTER USING LM25019
An isolated supply using LM25019 is shown in Figure 17 below. Inductor (L) in a typical buck circuit is replaced
with a coupled inductor (X1). A diode (D1) is used to rectify the voltage on a secondary output. The nominal
voltage at the secondary output (VOUT2) is given by:
VOUT2 = VOUT1 x
NS
- VF
NP
(15)
where VF is the forward voltage drop of D1, and NP, NS are the number of turns on the primary and secondary
of coupled inductor X1. For output voltage (VOUT1) above the maximum VCC (8.55V), the VCC pin can be diode
connected to VOUT1 for higher efficiency and low dissipation in the IC. See AN-2292 for a complete isolated bias
design.
VOUT2
D1
+
NS
LM25019
VIN
20V-48V
BST
CIN
+
X1
CBST
SW
VIN
COUT2
VOUT1
Rr NP
+
+
RON
RUV2
RON
Cac
RFB2
VCC
UVLO
COUT1
Cr
D2
RUV1
RTN
FB
+
CVCC
RFB1
Figure 17. Typical Isolated Application Schematic
RIPPLE CONFIGURATION
LM25019 uses Constant-On-Time (COT) control scheme, in which the on-time is terminated by an on-timer, and
the off-time is terminated by the feedback voltage (VFB) falling below the reference voltage (VREF). Therefore, for
stable operation, the feedback voltage must decrease monotonically, in phase with the inductor current during
the off-time. Furthermore, this change in feedback voltage (VFB) during off-time must be large enough to
suppress any noise component present at the feedback node.
Table 1 shows three different methods for generating appropriate voltage ripple at the feedback node. Type 1
and Type 2 ripple circuits couple the ripple at the output of the converter to the feedback node (FB). The output
voltage ripple has two components:
1. Capacitive ripple caused by the inductor current ripple charging/discharging the output capacitor.
2. Resistive ripple caused by the inductor current ripple flowing through the ESR of the output capacitor.
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The capacitive ripple is not in phase with the inductor current. As a result, the capacitive ripple does not
decrease monotonically during the off-time. The resistive ripple is in phase with the inductor current and
decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at the output
node (VOUT) for stable operation. If this condition is not satisfied unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off-time.
Type 3 ripple method uses Rr and Cr and the switch node (SW) voltage to generate a triangular ramp. This
triangular ramp is ac coupled using Cac to the feedback node (FB). Since this circuit does not use the output
voltage ripple, it is ideally suited for applications where low output voltage ripple is required. See application note
AN-1481 for more details for each ripple generation method.
Type 1
Lowest Cost Configuration
Type 2
Reduced Ripple Configuration
Type 3
Minimum Ripple Configuration
VOUT
VOUT
L1
VOUT
L1
L1
R FB2
Cac
RC
To FB
R FB2
Rr
RC
COUT
R FB2
Cac
To FB
R FB1
Cr
GND
C OUT
R FB1
GND
C OUT
To FB
R FB1
GND
C>
5
gsw (RFB2||RFB1)
25 mV
RC >
ûIL(MIN)
(16)
Cr = 3300 pF
Cac = 100 nF
(VIN(MIN) ± VOUT) x TON
RrCr <
25 mV
(17)
(18)
SOFT START
A soft-start feature can be implemented to the LM25019 using an external circuit. As shown in , the soft-start
circuit consists of one capacitor, C1, two resistors, R1 and R2, and a diode, D. During the initial start-up, the VCC
voltage is established prior to the VOUT voltage. D is thereby forward biased and the FB voltage is pulled up
above the reference voltage (1.225V). The switcher is disabled. With the charging of the capacitor C1, the voltage
at node B gradually decreases. Due to the action of the control circuit, VOUT will gradually rise to maintain the FB
voltage at the reference voltage. Once the voltage at node B is lower than the FB voltage, plus the voltage drop
of D, the soft-start is finished and D is reverse biased.
During the initial part of the start-up, the FB voltage can be approximated as follows. Please note that the effect
of R1 has been ignored to simplify the calculation:
VFB = (VCC - VD) x
RFB1 x RFB2
R2 x (RFB1 + RFB2) + RFB1 x RFB2
(19)
To achieve the desired soft-start, the following design guidance is recommended:
(1) R2 is selected so that VFB is higher than 1.225V for a VCC of 4.5V, but is lower than 5V when VCC is 8.55V. If
an external VCC is used, VFB should not exceed 5V at maximum VCC.
(2) C1 is selected to achieve the desired start-up time that can be determined as follows:
tS = C1 x (R2 +
RFB1 x RFB2
)
RFB1 + RFB2
(20)
(3) R1 is used to maintain the node B voltage at zero after the soft-start is finished. A value larger than the
feedback resistor divider is preferred.
Based on the schematic shown in , selecting C1=1uF, R2=1kΩ, R1=30kΩ results in a soft-start time of about 2ms.
14
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VCC
VOUT
C1
RFB2
R2
To FB
D
B
RFB1
R1
Figure 18. Soft-Start Circuit
LAYOUT RECOMMENDATION
A proper layout is essential for optimum performance of the circuit. In particular, the following guidelines should
be observed:
1. CIN: The loop consisting of input capacitor (CIN), VIN pin, and RTN pin carries switching currents. Therefore,
the input capacitor should be placed close to the IC, directly across VIN and RTN pins and the connections to
these two pins should be direct to minimize the loop area. In general it is not possible to accommodate all of
input capacitance near the IC. A good practice is to use a 0.1μF or 0.47μF capacitor directly across the VIN
and RTN pins close to the IC, and the remaining bulk capacitor as close as possible (Refer to Figure 19
Placement of Bypass Capacitors).
2. CVCC and CBST: The VCC and bootstrap (BST) bypass capacitors supply switching currents to the high and
low side gate drivers. These two capacitors should also be placed as close to the IC as possible, and the
connecting trace length and loop area should be minimized (See Figure 19 Placement of Bypass
Capacitors).
3. The Feedback trace carries the output voltage information and a small ripple component that is necessary for
proper operation of LM25019. Therefore, care should be taken while routing the feedback trace to avoid
coupling any noise to this pin. In particular, feedback trace should not run close to magnetic components, or
parallel to any other switching trace.
4. SW trace: The SW node switches rapidly between VIN and GND every cycle and is therefore a possible
source of noise. The SW node area should be minimized. In particular, the SW node should not be
inadvertently connected to a copper plane or pour.
RTN
1
VIN
2
8
SW
7
BST
CIN
PSOP-8
UVLO
3
6
VCC
RON
4
5
FB
CVCC
Figure 19. Placement of Bypass Capacitors
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PACKAGE OPTION ADDENDUM
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9-Feb-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
(3)
Top-Side Markings
(4)
LM25019MR/NOPB
PREVIEW SO PowerPAD
DDA
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LM25019MRE/NOPB
PREVIEW SO PowerPAD
DDA
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LM25019MRX/NOPB
PREVIEW SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 125
LM25019SD/NOPB
ACTIVE
WSON
NGU
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM25019SDE/NOPB
ACTIVE
WSON
NGU
8
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM25019SDX/NOPB
ACTIVE
WSON
NGU
8
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Feb-2013
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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