Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM Document Title 4M x 16Bit Asynchronous / Page Mode StRAM Revision History Revision No. 0.0 History Draft Date Initial Draft Oct. 23 , 2007 Remark Preliminary Emerging Memory & Logic Solutions Inc. 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Zip Code : 690-717 The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM 4M x16 Bit Async./Page StRAM FEATURES GENERAL DISCRIPTION - Single power supply voltage of 2.6 to 3.3V - Direct TTL compativility for all inputs and outputs. - Deep power-down mode : Memory cell data invalid. - Supplied in KGD(Known Good Die) form. - Page operation mode Page read operation by 8 words. - Logic compatible with SRAM R/W pin. - Standby Current Standby 150 uA Deep power-down standby 10uA - Access Time The EM7643SU16H is a 64M-bit StRAM organized as 4M words by 16 bits. It provides high density, high speed and low power. The device operates single power supply. The device also features SRAM-like W/R timing whereby the device is controlled by CE1, OE and WE on asynchronous. The device has the page access operation. Page size is 8 words. The device also supports deep powerdown mode, realizing low-power standby. Access Time 65ns CE1 Access Time 65ns OE Access Time 25ns Page Access Time 20NS PAD DESCRIPTION SYMBOL DESCRIPTION A0~A21 Address input A0~A2 Page Address input CE1 Chip Enable Input1, Low : Enable CE2 Chip Enable Input2, High:Enable, Low:Enter Power Down mode WE Write Enable input, Low :Enable OE Output Enable input, Low :Enable LB Lower byte write control UB Upper byte write control DQ0~DQ15 Data inputs/outputs VDD Device Power supply VSS VSS must be connected ground VDDQ I/O Power supply VSSQ VSS must be connected ground NC Not Connection 2 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM FUNCTION BLOCK DIAGRAM VDD GND MEMORY CELL ARRAY DATA OUTPUT BUFFER ROW ADDRESS DECODER A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 ROW ADDRESS BUFFER DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DATA INPUT BUFFER CE DATA OUTPUT BUFFER DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DATA INPUT BUFFER Sense AMP COLUMN ADDRESS DECODER REFRESH CONTROL REFRESH ADDRESS COUNTER COLUMN ADDRESS BUFFER A0 A1 A2 A3 A4 A5 A6 A7 CONTROL SIGNAL GENERATOR CE WE OE UB LB CE1 CE CE2 3 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM OPERATION MODE CE1 CE2 OE WE LB UB Add DQ0 to DQ7 DQ8 to DQ15 L H L H L L X Data Out Data Out L H L H L H X Data Out L H L H H L X L H X L L L L H X L L L H X L L H H H H H L Mode Power Read(Word) IDD0 High-Z Read(Lower Byte) IDD0 High-Z Data Out Read(Upper Byte) IDD0 X Data In Data In Write(Word) IDD0 H X Data In Invalid Write(Lower Byte) IDD0 H L X Invalid Data In Write(Upper Byte) IDD0 H X X X High-Z High-Z Outputs Disabled IDD0 X X X X X High-Z High-Z Standby IDDS X X X X X High-Z High-Z Deep Power-down Standby IDDSD Note: X means don’t care. (Must be low or high state) ABSOLUTE MAXIMUM RATINGS (SEE NOTE1) SYMBOL VDD VIN VOUT Topr. Tstrg. PD IOUT RATING Device Power Supply Voltage Input Voltage Output Voltage Operating Temperature Stroage Temperature Power Dissipation Short Circuit Output Current VALUE -1.0 to 3.6 -1.0 to 3.6 -1.0 to 3.6 -25 to 85 -55 to 150 0.6 50 UNIT V V V ℃ ℃ W mA DC RECOMMENDED OPERATING CONDITIONS(Ta = -25℃ to 85 ℃) SYMBOL PARAMETER MIN TYP Max VDD Device Power Supply Voltage 2.6 2.75 3.3 VIH Input High Voltage 0.8*VDD - VDD + 0.3 VIL Input Low Voltage -0.3 - 0.15*VDD Unit V VIH(Max) VDD+1.0V with 10ns pulse width VIL(Min)-1.0V with 10ns pulse width 4 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM DC CHARACTERISTICS(Ta = -25℃ to 85 ℃, VDD=2.6 to 3.3V) (SEE NOTE 3 to 4) Parameter Symbol Test Conditions Min Typ Max Unit Input leakage current ILI VIN=0 to VDD -1 - 1 uA Output leakage current ILO Output disable, VOUT= 0V to VDD -1 - 1 uA Operating current IDDO1 tRC= Min, CE1=VIL , CE2=VIH , IOUT=0mA - - 50 mA Page Access Operating current IDDO2 tPC = Min, CE1=VIL, CE2=VIH , IOUT=0mA, Page add. cycling. - - 25 mA 0.8*VDD - - V Output high voltage VOH IOH = -0.5mA Output low voltage VOL IOL = 1.0mA, VCC=VCCmin - - 0.15*VCCQ V Standby Current (CMOS) IDDS CE1>VDD-0.2V, CE2=VDD -0.2V - - 150 uA - - 10 uA Deep Power-down Standby Curret VDDSD (*1, *2) CE2 = 0.2V Note *1. Max VIL of signals(i.e. A0~A21, DQ1~DQ16, CE1#, CE2, WE#, OE#, LB#, UB#) can be 0.2V to 0.616V. *2. For deep power-down, CE2<=0.2V is essential. If max VIL of CE2 is from 0.2V to 0.616V, the 10uA deep-power current will not be guaranteed, and the deep-power current might go high as 20uA. CAPACITANCE (f =1MHz, TA=25oC) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=VSS - 10 pF Ouput capacitance COUT VOUT=VSS - 30 pF Note : This parameter is sampled periodically and is not 100% tested 5 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM AC TEST CONDITIONS PARAMETER CONDITION Output load 50 ohm+0.5 * VDD Input pulse level VDD-0.2V, 0.2V Timing measurements VDD * 0.5 Reference level VDD * 0.5 tR, tF 5 ns AC CHARACTERISTICS (Vcc = 2.6 to 3.3V, Gnd = 0V, TA = -25oC to +85oC) (SEE NOTE 5-11) Speed Parameter List Symbol Min 65 Max 10000 Unit tRC Read Cycle Time ns tACC Address Access Time - 65 ns tCO Chip Enable(CE1) Access Time - 65 ns tOE Output Enable Access Time - 25 ns tBA Data Byte Control Access Time - 65 ns tCOE Chip Enable Low to Output Active 10 - ns tOEE Output Enable Low to Output Active 0 - ns tBE Data Byte Control Low to Output Active 0 - ns tOD Chip Enable High to Ouput High-Z - 20 ns Output Enable High to Output High-Z - 20 ns tBD Data Byte Control High to Output High-Z - 20 ns tOH Output Data Hold Time 5 - ns tPM Page Mode Time 65 10000 ns tPC Page Mode Cycle Time 20 - ns tODO tAA Page Mode Address Access Time - 20 ns tAOH Page Mode Output Data Hold Time 5 - ns tWC Write Cycle Time 65 10000 ns tWP Write Pulse Width 50 - ns tCW Chip Enable to End of Write 65 - ns tBW Data Byte Control to End of Write 60 - ns tAW Address Valid to End of Write 60 - ns tAS Address Set-up Time 0 - ns tWR Write Recovery Time 0 - ns tCEH Chip Enable High Pulse Width 10 - ns tWEH Write Enable High Pulse Width 6 - ns tODW WE Low to Output High-Z - 20 ns tOEW WE High to Output Active 0 - ns tDS Data Set-up Time 30 - ns tDH Data Hold Time 0 - ns tCS CE2 Set-up Time 0 - ns tCH CE2 Hold Time 300 - us tDPD CE2 Pulse Width 10 - ms tCHC CE2 Hold from CE1 0 - ns tCHP CE2 Hold from Power On 30 - us 6 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM TIMING WAVEFORM OF READ CYCLE tRC Address A0 to A21 tOH tACC tCO CE1 CE2 tOD OE tODO WE UB, LB Dout DQ0 ~ DQ15 tOEE tBE tBD Valid Data High-Z High-Z tCOE TIMING WAVEFORM OF PAGE READ CYCLE (8 words access) tPM Address A0 to A2 tRC tPC tPC Address A3 to A21 CE1 CE2 tOE OE WE tBA UB, LB Dout DQ0 ~ DQ15 tOEE tBE High-Z tCOE tACC tAOH Dout tAA tACC tAOH Dout tAOH Dout tAA tOD tBD Dout High-Z tOH tODO 7 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM TIMING WAVEFORM OF WRITE CYCLE1 (WE CONTROLLED) (SEE NOTE 8) tWC Address A0 to A21 tAW tWEH tWP WE tAS tCW tWR CE1 tCH CE2 tBW tWR UB, LB tODW Dout DQ0 ~ DQ15 tOEW High - Z (See Note 10) tDS Din DQ0 ~ DQ15 (See Note11) tDH Valid Data (See Note 9) (See Note 9) TIMING WAVEFORM OF WRITE CYCLE 2 (CE CONTROLLED) (SEE NOTE 8) tWC Address A0 to A21 tAW tWR tWP WE tCW CE1 tCH tWR tCEH tAS CE2 tBW tWR UB, LB tODW Dout DQ0 ~ DQ15 High - Z High - Z tBE tDS tCOE Din DQ0 ~ DQ15 tDH Valid Data (See Note9) 8 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM DEEP POWER-DOWN TIMING CE1 tDPD CE2 tCS tCH POWER_ON TIMING VDD VDD min CE1 tCHC CE2 tCHP tCH PROVISIONS OF ADDRESS SKEW Read In case, multiple invalid address cycles shorter than tRC_min sustain over 10us in a active status, as least one valid address cycle over tRC_min must be needed during 10us. over 10 us CE1 WE Address tRCmin Write In case, multiple invalid address cycles shorter than tWC_min sustain over 10us in a active status, as least one valid address cycle over tRC_min with tWP_min must be needed during 10us. over 10 us CE1 tWPmin WE Address tWCmin 9 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM Notes : 1. Stresses greater than listed under “Absolute Maximum Ratings” may cause permanet damage to the device. 2. All voltages are reference to VSS. 3. IDD0 depends on the cycle time. 4. IDD0 depends on output loading. Specified values are defined with the output open condition. 5. AC measurement are assumed tR, tF = 5ns. 6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels 7. Data cannot be retained at deep power-down stand-by mode. 8. If OE is high during the write cycle, the outputs will remain at high impedence. 9. During the output state of DQ signals, input signals of reverse polarity must not be applied. 10. If CE1 or LB / UB goes LOW coincident with or after WE goes LOW, the outputs will remain at high impedence. 11. If CE1 or LB./UB goes HIGH coincident with or before WE goes HIGH, the outputs will remain at high impedence. 10 Rev. 0.0 Preliminary EM7643SU16H 4Mx16 Async. / Page StRAM MEMORY FUNCTION GUIDE EM X XX X X X XX X X X - XX XX 1. EMLSI Memory 12. Power 2. Device Type 11. Speed 3. Density 10. PKG 9. Option 4. Function 8. Version 5. Technology 7. Organization 6. Operating Voltage 8. Version Blank ----------------- Mother die A ----------------------- 2’nd generation B ----------------------- 3’rd generation C ----------------------- 4’th generation D ----------------------- 5’th generation 1. Memory Component 2. Device Type 6 ---------------------- Low Power SRAM 7 ---------------------- STRAM C ---------------------- CellularRAM 9. Option Blank ---- No optional mode H ----------- Demultiplexed with DPD J ------------ Demultiplexed with DPD & RBC K ------------ Multiplexed with RBC L ------------ Multiplexed with DPD & RBC 3. Density 4 ----------------------- 4M 8 ----------------------- 8M 16 --------------------- 16M 32 --------------------- 32M 64 --------------------- 64M 28 --------------------- 128M 4. Function 2 ----Multiplexed async. 3-----Demultiplexed async. with page mode 4-----Demultiplexed async. with direct DPD 5-----Multiplexed sync. 6-----Optional mux/demuxed sync. 5. Technology S ----------------------- Single Transistor & Trench Cell 10. Package Blank ---------------------- Wafer S ---------------------- 32 sTSOP1 T ---------------------- 32 TSOP1 U ---------------------- 44 TSOP2 P ---------------------- 48 FPBGA Z ---------------------- 52 FPBGA Y ---------------------- 54 FPBGA V ---------------------- 90 FPBGA 11. Speed (@async.) 45 ---------------------- 45ns 55 ---------------------- 55ns 70 ---------------------- 70ns 85 ---------------------- 85ns 90 ---------------------- 90ns 10 --------------------- 100ns 12 --------------------- 120ns 6. Operating Voltage V ----------------------- 3.3V U ----------------------- 3.0V S ----------------------- 2.5V R ----------------------- 2.0V P ----------------------- 1.8V L ----------------------- 1.5V 7. Organization 8 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 12. Power LL ---------------------- Low Low Power LF ---------------------- Low Low Power (Pb-Free&Green) L ---------------------- Low Power 11 Rev. 0.0