LT6016/LT6017 Dual/Quad 3.2MHz, 0.8V/µs Low Power, Over-The-Top Precision Op Amp DESCRIPTION FEATURES n n n n n n n n n n n n n n Input Common Mode Range: V– to V– + 76V Rail-to-Rail Input and Output Low Power: 315μA/Amplifier Operating Temperature Range: –55°C to 150°C VOS: ±50μV (Maximum) CMRR, PSRR: 126dB Reverse Battery Protection to 50V Gain Bandwidth Product: 3.2MHz Specified on 5V and ±15V Supplies High Voltage Gain: 1000V/mV No Phase Reversal No Supply Sequencing Problems Dual 8-Lead MSOP Quad 22-Lead DFN (6mm × 3mm) APPLICATIONS n n n n n The LT®6016/LT6017 are dual and quad rail-to-rail input operational amplifiers with input offset voltage trimmed to less than 50μV. These amplifiers operate on single and split supplies with a total voltage of 3V to 50V and draw only 315μA per amplifier. They are reverse battery protected, drawing very little current for reverse supplies up to 50V. The Over-The-Top® input stage of the LT6016/LT6017 is designed to provide added protection in tough environments. The input common mode range extends from V– to V+ and beyond: these amplifiers operate with inputs up to 76V above V– independent of V+. Internal resistors protect the inputs against transient faults up to 25V below the negative supply. The LT6016/LT6017 can drive loads up to 25mA and are unity-gain stable with capacitive loads as large as 200pF. Optional external compensation can be added to extend the capacitive drive capability beyond 200pF. The LT6016 dual op amp is available in an 8-lead MSOP package. The LT6017 is offered in a 22-pin leadless DFN package. High Side or Low Side Current Sensing Battery/Power Supply Monitoring 4mA to 20mA Transmitters High Voltage Data Acquisition Battery/Portable Instrumentation L, LT, LTC, LTM, Linear Technology, Over-The-Top and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION Output Error vs Load Current Precision High Voltage High Side Load Current Monitor 0.2 0.1Ω 10W LOAD 200Ω 0.1μF + 100Ω 1% LT6016 BSP89 – 1V/A 0V TO 1V OUT 2k 60167 TA01a OUTPUT ERROR (%) 200Ω 0 5V VBAT = 1.5V TO 76V –0.2 –0.4 –0.6 VBAT = 1.5V VBAT = 5V VBAT = 20V VBAT = 75V –0.8 –1.0 0.01 0.1 LOAD CURRENT (A) 1 60167 TA01b 60167fa 1 LT6016/LT6017 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage (V+ to V–)................................60V, –50V Input Differential Voltage ........................................±80V Input Voltage (Note 2) .....................................80V, –25V Input Current (Note 2) .......................................... ±10mA Output Short Circuit Duration (Note 3) ......................................................... Continuous Temperature Range (Notes 4, 5) LT6016I/LT6017I ..................................–40°C to 85°C LT6016H/LT6017H ............................. –40°C to 125°C LT6016MP/LT6017MP(TJUNCTION) ..... –55°C to 150°C Storage Temperature Range .................. –65°C to 150°C Maximum Junction Temperature .......................... 150°C Lead Temperature (Soldering, 10sec).................... 300°C PIN CONFIGURATION TOP VIEW OUTA 1 –INA 2 22 OUTD 21 –IND A D +INA 3 N/C 4 19 N/C V– 5 18 V + N/C 6 V– 7 16 V + N/C 8 15 N/C +INB 9 14 +INC –INB 10 23 B 20 +IND TOP VIEW OUTA –INA +INA V– 17 N/C C OUTB 11 1 2 3 4 A B 8 7 6 5 V+ OUTB –INB +INB MS8 PACKAGE 8-LEAD PLASTIC MSOP TJMAX = 150°C, θJA = 273°C/W, θJC = 45°C/W 13 –INC 12 OUTC DJC PACKAGE 22-LEAD (6mm × 3mm) PLASTIC DFN TJMAX = 150°C, θJA = 31.8°C/W, θJC = 4.3°C/W UNDERSIDE METAL INTERNALLY CONNECTED TO V– ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT6016IMS8#PBF LT6016IMS8#TRPBF LTGFK 8-Lead Plastic MSOP –40°C to 85°C LT6016HMS8#PBF LT6016HMS8#TRPBF LTGFK 8-Lead Plastic MSOP –40°C to 125°C LT6016MPMS8#PBF LT6016MPMS8#TRPBF LTGFK 8-Lead Plastic MSOP –55°C to 150°C LT6017IDJC#PBF LT6017IDJC#TRPBF 6017 22-Lead Plastic DFN –40°C to 85°C LT6017HDJC#PBF LT6017HDJC#TRPBF 6017 22-Lead Plastic DFN –40°C to 125°C LT6017MPDJC#PBF LT6017MPDJC#TRPBF 6017 22-Lead Plastic DFN –55°C to 150°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 60167fa 2 LT6016/LT6017 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H–grade parts, otherwise specifications are at TA = 25°C, VS = 5V, VCM = VOUT = mid-supply. SYMBOL PARAMETER VOS ΔVOS ΔTEMP ΔVOS ΔTIME IB IOS Input Offset Voltage CONDITIONS MIN I-, H-GRADE TYP MAX –50 ±25 50 μV μV –80 –125 –135 –250 –350 ±45 ±50 ±50 ±45 ±50 80 125 135 250 350 μV μV μV μV μV < V+ – 1.75V 0 < VCM MS8 Package 0 < VCM < V+ – 1.75V DJC22 Package VCM = 5V VCM =76V 0 < VCM < V+ – 1.75V VCM = 5V to VCM = 76V l l UNITS Input Offset Voltage Drift 0.75 μV/°C Long Term Voltage Offset Stability 0.75 μV/Mo Input Bias Current Input Offset Current VCMR Common Mode Input Range CIN Differential Input Capacitance RIN Differential Input Resistance RINCM en 0.25V < VCM < V+ – 1.75V VCM = 0V VCM = 5V to 76V 0.25V < VCM < V+ – 1.75V VCM = 0V VCM = 5V to 76V VS = 0V, VCM = 0V to 76V 0.25V < VCM < V+ – 1.75V VCM = 0V VCM = 5V to 76V (Note 6) 0.25V < VCM < V+ – 1.75V VCM = 0V VCM = 5V to 76V (Note 6) –5 –30 11 –15 –150 7 ±2 –16.5 14 ±2 –16.5 14 0.001 5 0 17.5 15 0 23 1 nA nA μA nA nA μA μA l l l –5 –5 –500 –15 –15 –500 ±2 ±2 ±50 ±2 ±2 ±50 5 5 500 15 15 500 nA nA nA nA nA nA l 0 l l l l 76 V 5 pF 0 < VCM < V+ – 1.75V VCM > V+ 1 3.7 MΩ kΩ Common Mode Input Resistance 0 < VCM < V+ – 1.75V VCM > V+ >1 >100 GΩ MΩ Input Referred Noise Voltage Density f = 1kHz VCM < V+ – 1.75V VCM > V+ 18 25 nV/√Hz nV/√Hz 0.5 μVP-P 0.1 11.5 pA/√Hz pA/√Hz Input Referred Noise Voltage f = 0.1Hz to 10Hz VCM < V+ – 1.75V in Input Referred Noise Current Density f = 1kHz VCM < V+ – 1.75V VCM > V+ AVOL Open Loop Gain RL = 10kΩ ΔVOUT = 3V l 300 3000 V/mV PSRR Supply Rejection Ratio VS = ±1.65V to ±15V VCM = VOUT = Mid-Supply l 110 126 dB CMRR Input Common Mode Rejection Ratio VCM = 0V to 3.25V VCM = 5V to 76V l l 100 126 126 140 dB dB VOL Output Voltage Swing Low VS = 5V, No Load VS = 5V, 5mA l l 3 280 55 500 mV mV VOH Output Voltage Swing High VS = 5V, No Load VS = 5V, 5mA l l 450 1000 700 1250 mV mV ISC Short-Circuit Current VS = 5V, 50Ω to V+ VS = 5V, 50Ω to V– l l 10 10 25 25 mA mA 60167fa 3 LT6016/LT6017 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H–grade parts, otherwise specifications are at TA = 25°C, VS = 5V, VCM = VOUT = mid-supply. SYMBOL PARAMETER CONDITIONS GBW Gain Bandwidth Products fTEST = 10kHz SR Slew Rate ΔVOUT = 3V tS Settling Time Due to Input Step ΔVOUT = ±2V 0.1% Settling VS Supply Voltage Reverse Supply (Note 7) IS < –25μA/Amplifier IS Supply Current Per Amplifier VS = 5V RO Output Impedance ΔIO = ±5mA MIN I-, H-GRADE TYP l 2.85 2.5 3.2 3.2 MHz MHz l 0.55 0.45 0.75 0.75 V/μs V/μs 3.5 μs l l 3 3.3 l MAX UNITS –65 50 50 –50 V V V 315 315 335 500 μA μA 0.15 Ω The l denotes the specifications which apply over the specified temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H–grade parts, otherwise specifications are at TA = 25°C, VS = ±15V, VCM = VOUT = mid-supply. SYMBOL PARAMETER VOSI CONDITIONS Input Offset Voltage l VS = ±25V VS = ±25V ΔVOSI ΔTEMP Input Offset Voltage Drift IB Input Bias Current IOS Input Offset Current VCMR Common Mode Input Range CIN Differential Input Capacitance RIN Differential Input Resistance RINCM Common Mode Input Resistance en Input Referred Noise Voltage Density l MIN I-, H-GRADE TYP MAX UNITS –80 –250 –110 –250 ±55 ±55 ±75 ±75 80 250 110 250 μV μV μV μV 0.75 μV/°C l –5 –15 ±2 ±2 5 15 nA nA l –5 –15 ±2 ±2 5 15 nA nA l –15 61 V 0 < VCM < V+ – 1.75V VCM > V+ 0 < VCM < V+ – 1.75V VCM > V+ f = 1kHz VCM < V+ – 1.75V VCM > V+ 5 pF 1 3.7 MΩ kΩ >1 >100 GΩ MΩ 18 25 nV/√Hz nV/√Hz 0.5 μVP-P 0.1 11.5 pA/√Hz pA/√Hz Input Referred Noise Voltage f = 0.1Hz to 10Hz VCM < V+ – 1.25V in Input Referred Noise Current Density f = 1kHz VCM < V+ – 1.75V VCM > V+ AVOL Open Loop Gain RL = 10kΩ ΔVOUT = 27V l 200 1000 V/mV PSRR Supply Rejection Ratio VS = ±2.5V to ±25V VCM = VOUT = 0V l 114 126 dB CMRR Input Common Mode Rejection Ratio VCM = –15V to 13.25V l 110 126 dB VOL Output Voltage Swing Low VS = ±15V, No Load VS = ±15V, 5mA l l 3 280 55 500 mV mV VOH Output Voltage Swing High VS = ±15V, No Load VS = ±15V, 5mA l l 450 1000 700 1250 mV mV 60167fa 4 LT6016/LT6017 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H–grade parts, otherwise specifications are at TA = 25°C, VS = ±15V, VCM = VOUT = mid-supply. SYMBOL PARAMETER ISC Short-Circuit Current VS = ±15V, 50Ω to GND VS = ±15V, 50Ω to GND GBW Gain Bandwidth Product fTEST = 10kHz SR Slew Rate ΔVOUT = 3V tS Settling Time Due to Input Step 0.1% Settling ΔVOUT = ±2V VS Supply Voltage Reverse Supply IS IS = –25μA/Amplifier Supply Current Per Amplifier Output Impedance I-, H-GRADE TYP l l 10 10 30 32 mA mA l 2.9 2.55 3.3 3.3 MHz MHz l 0.6 0.5 0.8 0.8 V/μs V/μs 3.5 μs l l 3 3.3 l VS = ±25V VS = ±25V RO MIN CONDITIONS l ΔIO = ±5mA MAX UNITS –65 50 50 –30 V V V 325 325 340 340 350 525 360 550 μA μA μA μA 0.15 Ω The l denotes the specifications which apply over the specified temperature range, –55°C < TJUNCTION < 150°C for MP-grade parts, otherwise specifications are at TA = 25°C, VS = 5V, VCM = VOUT = mid-supply. SYMBOL PARAMETER VOS ΔVOS ΔTEMP ΔVOS ΔTIME IB IOS Input Offset Voltage CONDITIONS 0 < VCM < V+ – 1.75V MS8 Package 0 < VCM < V+ – 1.75V DJC22 Package VCM = 5V VCM = 76V 0 < VCM < V+ –1.75V VCM = 5V to VCM = 76V l l MIN MP-GRADE TYP MAX –50 ±25 50 μV μV –80 –125 –135 –500 –600 ±45 ±50 ±50 ±45 ±50 80 125 135 500 600 μV μV μV μV μV UNITS Input Offset Voltage Drift 0.75 μV/°C Long Term Voltage Offset Stability 0.75 μV/Mo Input Bias Current Input Offset Current VCMR Common Mode Input Range CIN Differential Input Capacitance RIN Differential Input Resistance RINCM Common Mode Input Resistance 0.25V < VCM < V+ – 1.75V VCM = 0V VCM = 5V to 76V 0.25V < VCM < V+ – 1.75V VCM = 0V VCM = 5V to 76V VS = 0V, VCM = 0V to 76V 0.25V < VCM < V+ – 1.75V VCM = 0V VCM = 5V to 76V (Note 6) 0.25V < VCM < V+ – 1.75V VCM = 0V VCM = 5V to 76V (Note 6) 0 < VCM < V+ – 1.75V VCM > V+ 0 < VCM < V+ – 1.75V VCM > V+ –5 –30 11 –100 –500 6.5 ±2 –16.5 14 ±2 –16.5 14 0.001 5 0 17.5 100 0 24 4 nA nA μA nA nA μA μA l l l –5 –5 –500 –50 –200 –500 ±2 ±2 ±50 ±2 ±2 ±150 5 5 500 50 200 500 nA nA nA nA nA nA l 0 76 V l l l l 5 pF 1 3.7 MΩ kΩ >1 >100 GΩ MΩ 60167fa 5 LT6016/LT6017 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified temperature range, –55°C < TJUNCTION < 150°C for MP-grade parts, otherwise specifications are at TA = 25°C, VS = 5V, VCM = VOUT = mid-supply. SYMBOL PARAMETER en Input Referred Noise Voltage Density CONDITIONS MIN f = 1kHz VCM < V+ – 1.75V VCM > V+ MP-GRADE TYP MAX UNITS 18 25 nV/√Hz nV/√Hz 0.5 μVP-P 0.1 11.5 pA/√Hz pA/√Hz Input Referred Noise Voltage f = 0.1Hz to 10Hz VCM < V+ – 1.75V in Input Referred Noise Current Density f = 1kHz VCM < V+ – 1.75V VCM > V+ AVOL Open Loop Gain RL = 10kΩ ΔVOUT = 3V l 200 3000 V/mV PSRR Supply Rejection Ratio VS = ±1.65V to ±15V VCM = VOUT = Mid-Supply l 106 126 dB CMRR Input Common Mode Rejection Ratio VCM = 0V to 3.25V VCM = 5V to 76V l l 90 120 126 140 dB dB VOL Output Voltage Swing Low VS = 5V, No Load VS = 5V, 5mA l l 3 280 75 550 mV mV VOH Output Voltage Swing High VS = 5V, No Load VS = 5V, 5mA l l 450 1000 750 1300 mV mV ISC Short-Circuit Current VS = 5V, 50Ω to V+ VS = 5V, 50Ω to V– l l 8 8 25 25 mA mA GBW Gain Bandwidth Product fTEST = 10kHz l 2.85 2.4 3.2 3.2 MHz MHz SR Slew Rate ΔVOUT = 3V l 0.55 0.4 0.75 0.75 V/μs V/μs tS Settling Time Due to Input Step 0.1% Settling ΔVOUT = ±2V 3.5 μs VS Supply Voltage Reverse Supply (Note 7) IS < –25VμA/Amplifier IS Supply Current Per Amplifier VS = 5V RO Output Impedance ΔIO = ±5mA l l 3 3.3 l –63 50 50 –50 V V V 315 315 335 540 μA μA 0.15 Ω The l denotes the specifications which apply over the specified temperature range, –55°C < TJUNCTION < 150°C for MP-grade parts, otherwise specifications are at TA = 25°C, VS = ±15V, VCM = VOUT = mid-supply. SYMBOL PARAMETER VOSI CONDITIONS Input Offset Voltage l VS = ±25V VS = ±25V ΔVOSI ΔTEMP Input Offset Voltage Drift IB Input Bias Current IOS Input Offset Current VCMR Common Mode Input Range CIN Differential Input Capacitance RIN Differential Input Resistance l MIN MP-GRADE TYP MAX UNITS –80 –500 –110 –500 ±55 ±55 ±75 ±75 80 500 110 500 μV μV μV μV 0.75 0 < VCM < V+ – 1.75V VCM > V+ μV/°C l –5 –300 ±2 ±2 5 300 nA nA l –5 –50 ±2 ±2 5 50 nA nA l –15 61 V 5 pF 1 3.7 MΩ kΩ 60167fa 6 LT6016/LT6017 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified temperature range, –55°C < TJUNCTION < 150°C for MP-grade parts, otherwise specifications are at TA = 25°C, VS = ±15V, VCM = VOUT = Mid-Supply. SYMBOL PARAMETER CONDITIONS MIN RINCM Common Mode Input Resistance 0 < VCM < V+ – 1.75V VCM > V+ en Input Referred Noise Voltage Density f = 1kHz VCM < V+ – 1.75V VCM > V+ MP-GRADE TYP MAX >1 >100 UNITS GΩ MΩ 18 25 nV/√Hz nV/√Hz 0.5 μVP-P 0.1 11.5 pA/√Hz pA/√Hz Input Referred Noise Voltage f = 0.1Hz to 10Hz VCM < V+ – 1.75V in Input Referred Noise Current Density f = 1kHz VCM < V+ – 1.75V VCM > V+ AVOL Open Loop Gain RL = 10kΩ ΔVOUT = 27V l 100 1000 V/mV PSRR Supply Rejection Ratio VS = ±2.5V to ±25V VCM = VOUT = 0V l 106 126 dB CMRR Input Common Mode Rejection Ratio VCM = –15V to 13.25V l 100 126 dB VOL Output Voltage Swing Low VS = ±15V, No Load VS = ±15V, 5mA l l 3 280 75 550 mV mV VOH Output Voltage Swing High VS = ±15V, No Load VS = ±15V, 5mA l l 450 1000 750 1300 mV mV ISC Short-Circuit Current VS = ±15V, 50Ω to GND VS = ±15V, 50Ω to GND l l 8 8 30 32 mA mA GBW Gain Bandwidth Product fTEST = 10kHz l 2.9 2.45 3.3 3.3 MHz MHz SR Slew Rate ΔVOUT = 3V l 0.6 0.45 0.8 0.8 V/μs V/μs tS Settling Time Due to Input Step 0.1% Settling ΔVOUT = ±2V 3.5 μs VS Supply Voltage Reverse Supply IS IS = –25μA/Amplifier Supply Current Per Amplifier l VS = ±25V VS = ±25V RO Output Impedance l l ΔIO = ±5mA Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Voltages applied are with respect to V–. The inputs are tested to the Absolute Maximum Rating by applying –25V (relative to V–) to each input for 10ms. In general, faults capable of sinking current from either input should be current limited to under 10mA. See the Applications Information section for more details. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum. This depends on the power supply voltage and how many amplifiers are shorted. Note 4: The LT6016I/LT6017 are guaranteed functional over the operating temperature range of –40°C to 85°C. The LT6016H/LT6017H are guaranteed functional over the operating temperature range of –40°C to 125°C. The LT6016MP/LT6017MP are guaranteed functional over the l 3 3.3 –65 50 50 –30 V V V 325 325 340 340 350 575 360 600 μA μA μA μA 0.15 Ω junction temperature range of –55°C to 150°C. Junction temperatures greater than 125°C will promote accelerated aging. The LT6016/LT6017 has a demonstrated typical performance beyond 1000 hours at TJ = 150°C. Note 5: The LT6016I/LT6017I are guaranteed to meet specified performance from –40°C to 85°C. The LT6016H/LT6017H are guaranteed to meet specified performance from –40°C to 125°C. The LT6016MP/ LT6017MP are guaranteed to meet specified performance with junction temperature ranging from –55°C to 150°C. Note 6: Test accuracy is limited by high speed test equipment repeatability. Bench measurements indicate the input offset current in the Over-The-Top configuration is typically controlled to under ±50nA at 25°C and ±150nA over temperature. Note 7: The Reverse Supply voltage is tested by pulling 25μA/Amplifier out of the V+ pin while measuring the V+ pin’s voltage with both inputs and V– grounded, verifying V+ < –50V. 60167fa 7 LT6016/LT6017 TYPICAL PERFORMANCE CHARACTERISTICS Typical Distribution of Input Offset Voltage Typical Distribution of Input Offset Voltage 600 150 100 350 965 UNITS 1930 CHANNELS 300 FROM TWO RUNS VS = ±15V VCM = 0V 500 TA = 25°C MS8 PACKAGE NUMBER OF CHANNELS VS = 5V 350 VCM = MID-SUPPLY TA = 25°C 300 MS8 PACKAGE 1285 UNITS 250 2570 CHANNELS FROM TWO RUNS 200 NUMBER OF CHANNELS 400 1285 UNITS 2570 CHANNELS FROM TWO RUNS 300 200 100 50 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 INPUT OFFSET VOLTAGE (μV) 0 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 INPUT OFFSET VOLTAGE (μV) Typical Distribution of Over-The-Top Input Offset Voltage 350 510 UNITS 2040 CHANNELS 300 FROM TWO RUNS VS = 5V VCM = 76V TA = 25°C MS8 PACKAGE 250 200 150 100 200 150 100 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 INPUT OFFSET VOLTAGE (μV) 60167 G03 Typical Distribution of Input Offset Voltage NUMBER OF CHANNELS 965 UNITS 1930 CHANNELS 300 FROM TWO RUNS 250 60167 G02 60167 G01 350 VS = 5V VCM = 5V TA = 25°C MS8 PACKAGE 50 Typical Distribution of Over-The-Top Input Offset Voltage VS = 5V VCM = MID-SUPPLY TA = 25°C DJC22 PACKAGE 250 200 150 100 500 510 UNITS 450 2040 CHANNELS FROM TWO RUNS 400 NUMBER OF CHANNELS NUMBER OF CHANNELS 400 NUMBER OF CHANNELS Typical Distribution of Over-The-Top Input Offset Voltage VS = 5V VCM = 5V TA = 25°C DJC22 PACKAGE 350 300 250 200 150 100 50 50 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 INPUT OFFSET VOLTAGE (μV) 50 60167 G04 60167 G06 60167 G05 Voltage Offset Shift vs Lead Free IR Reflow Over-The-Top Voltage Offset Shift vs Lead Free IR Reflow Voltage Offset Shift vs Lead Free IR Reflow 12 14 NUMBER OF CHANNELS 24 DEVICES 16 48 CHANNELS MS8 PACKAGE 14 VS = 5V VCM = MID-SUPPLY 12 10 8 6 24 DEVICES 48 CHANNELS 12 MS8 PACKAGE VS = 5V 10 VCM = 5V 10 DEVICES VS = 5V 40 CHANNELS VCM = MID-SUPPLY 10 DJC22 PACKAGE NUMBER OF CHANNELS 18 NUMBER OF CHANNELS 0 –100 –80 –60 –40 –20 0 20 40 60 80 100 INPUT OFFSET VOLTAGE (μV) 0 –50 –40 –30 –20 –10 0 10 20 30 40 50 INPUT OFFSET VOLTAGE (μV) 8 6 4 8 6 4 4 2 2 2 0 5 10 15 20 –20 –15 –10 –5 0 VOLTAGE OFFSET SHIFT (μV) 25 60167 G07 0 5 10 15 20 –20 –15 –10 –5 0 VOLTAGE OFFSET SHIFT (μV) 25 60167 G08 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 VOLTAGE OFFSET SHIFT (μV) 60167 G09 60167fa 8 LT6016/LT6017 TYPICAL PERFORMANCE CHARACTERISTICS Warm-Up Drift 2.5 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 CHANNEL A CHANNEL B –2.5 0 1 2 3 4 TIME AFTER POWER ON (MIN) 1.5 1.0 0.5 0.0 –0.5 –1.0 –2.5 0 1 2 3 4 TIME AFTER POWER ON (MIN) FOUR CYCLES –55°C TO 130°C VS = 5V, VCM = MID-SUPPLY 40 CHANNELS MEASURED MAXIMUM SHIFT MS8 PACKAGE MEASURED 25 TYPICAL 0 CHANNEL –25 –50 MINIMUM SHIFT MEASURED WORST-CASE CHANNEL –75 –100 –75 –50 –25 150 VS = 5V VCM = MID-SUPPLY 100 0 –50 –150 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) OFFSET VOLTAGE (μV) INPUT VOLTAGE OFFSET (μV) 75 TA = –45°C –10 –20 TA = 125°C –30 50 25 TA = 25°C 0 TA = –45°C –25 TA = 125°C –50 –75 –40 –50 0.01 0.1 1 VCM (V) 10 0 –50 –150 –50 –25 100 60167 G16 0 25 50 75 100 125 150 TEMPERATURE (°C) 60167 G15 Minimum Supply Voltage 30 TA = 25°C CHANNEL A CHANNEL B 60167 G14 VS = 5V 0 5 UNITS, 10 CHANNELS MS8 PACKAGE 50 Voltage Offset vs Supply Voltage 20 VS = 5V VCM = 50V –100 100 10 150 100 CHANNEL A CHANNEL B 50 Voltage Offset vs Input Common Mode Voltage 40 Over-The-Top Voltage Offset vs Temperature –100 0 25 50 75 100 125 150 TEMPERATURE (°C) –25 –20 –15 –10 –5 0 5 10 15 20 25 VOLTAGE OFFSET SHIFT (μV) 60167 G12 5 UNITS, 10 CHANNELS MS8 PACKAGE 60167 G13 50 0 5 Voltage Offset vs Temperature VOLTAGE OFFSET (μV) VOLTAGE OFFSET SHIFT (μV) 50 6 60167 G11 Voltage Offset Shift vs Temperature Cycling 75 8 2 CHANNEL A CHANNEL B 60167 G10 100 FOUR THERMAL CYCLES –55°C TO 130°C 16 TA = 25°C 20 DEVICES 14 40 CHANNELS MS8 PACKAGE 12 VS = 5V VCM = MID-SUPPLY 10 4 –1.5 –2.0 5 18 5 UNITS, 10 CHANNELS MS8 PACKAGE VOLTAGE OFFSET (μV) –2.0 VS = 5V VCM = 50V 2.0 NUMBER OF CHANNELS 5 UNITS, 10 CHANNELS MS8 PACKAGE –100 5 10 15 20 25 30 35 40 45 TOTAL SUPPLY VOLTAGE (V) 50 60167 G17 CHANGE IN INPUT OFFSET VOLTAGE OFFSET (μV) VS = ±15V VCM = 0V 2.0 CHANGE IN OFFSET VOLTAGE (μV) CHANGE IN OFFSET VOLTAGE (μV) 2.5 Voltage Offset Shift vs Thermal Cycling Over-The-Top Warm-Up Drift 20 TA = –45°C 15 10 TA = 125°C 5 TA = 25°C 0 –5 –10 –15 –20 0 1 3 2 4 TOTAL SUPPLY VOLTAGE (V) 5 60167 G18 60167fa 9 LT6016/LT6017 TYPICAL PERFORMANCE CHARACTERISTICS Long Term Stability of Five Representative Units 20 5 UNITS, 10 CHANNELS MS8 PACKAGE 2 15 1 0 –1 –2 10 5 CHANNEL A CHANNEL B –4 0 1 2 TIME (MONTHS) 3 TA = 125°C TA = 85°C TA = 25°C TA = –45°C TA = –55°C 0 –3 –5 –5 0.1 4 1 10 INPUT COMMON MODE VOLTAGE (V) Input Bias Current vs Supply Voltage 5.0 2.5 0.0 –2.5 10 0 20 30 40 SUPPLY VOLTAGE (V) 500 300 200 TA = –55°C PARAMETRIC SWEEP IN ~25°C INCREMENTS 100 0 0 10 20 30 40 SUPPLY VOLTAGE (V) 30 1.50 25 1.25 1.00 15 0.75 10 0.50 10 100 1000 FREQUENCY (Hz) 10k 0.25 0 100k 60167 G25 VOLTAGE NOISE DENSITY (nV/√Hz) VOLTAGE NOISE DENSITY (nV/√Hz) 1.75 CURRENT NOISE TA = –55°C TA = 130°C 0 TA = 150°C –5 TA = 25°C –10 –15 –60 –50 –40 –30 –20 SUPPLY VOLTAGE (V) –10 60 VS = 5V VCM = 5V 50 50 40 40 VOLTAGE NOISE 30 30 20 20 CURRENT NOISE 10 10 0 1 10 100 FREQUENCY (Hz) 0 60167 G24 0 1000 60167 G26 CURRENT NOISE DENSITY (pA/√Hz) 35 1 5 0.1Hz to 10Hz Noise 60 CURRENT NOISE DENSITY (pA/√Hz) 2.00 0 50 NON-INVERTING OP AMP CONFIGURATION +INA, +INB TIED TO V– Over-The-Top Noise Density vs Frequency 40 10 10 60167 G23 Noise Density vs Frequency 5 0.01 0.1 1 INPUT COMMON MODE VOLTAGE (V) Reverse Supply Current vs Reverse Supply Voltage 400 50 VOLTAGE NOISE TA = 125°C TA = 85°C TA = 25°C TA = –45°C TA = –55°C 60167 G21 TA = 150°C 60167 G22 20 –50 0.001 100 600 SUPPLY CURRENT PER AMPLIFIER (μA) INPUT BIAS CURRENT (nA) 7.5 –25 Supply Current vs Supply Voltage TA = 125°C TA = 85°C TA = 25°C TA = –45°C TA = –55°C 10.0 0 60167 G20 60167 G19 12.5 INPUT BIAS CURRENT (nA) 3 25 VS = 5V REVERSE SUPPLY CURRENT PER AMPLIFIER (μA) 4 Input Bias Current vs Input Common Mode Voltage VS = ±2.5V TO ±25V TA = 25°C NOISE VOLTAGE (100nV/DIV) VS = 5V INPUT BIAS CURRENT (μA) CHANGE IN OFFSET VOLTAGE (μV) 5 Input Bias Current vs Input Common Mode Voltage 0 2 4 6 TIME (SEC) 8 10 60167 G27 60167fa 10 LT6016/LT6017 TYPICAL PERFORMANCE CHARACTERISTICS Output Impedance vs Frequency PSRR vs Frequency 120 VS = ±2.5V 80 AV = +1 1 CMRR (dB) 80 AV = 100 10 60 AV = 10 1 10 100 FREQUENCY (kHz) 0 0.1 10k 1000 1 10 100 FREQUENCY (kHz) 60167 G28 157.5 GAIN (dB) 0 –10 VS = ±2.5V CLOAD = 20pF 10 1 100 1000 FREQUENCY (kHz) 10k –20 0.01 3.4 56 GBW 52 3.3 PM 3.2 48 3.1 44 3.0 0 Gain-Bandwidth vs Temperature VS = ±2.5V 40 50 10 20 30 40 TOTAL SUPPLY VOLTAGE (V) 60167 G33 Channel Separation vs Frequency 4.0 140 130 40.0 ISRC = 150μA 37.5 ISRC = 0 35.0 CHANNEL SEPARATION (dB) GAIN-BANDWIDTH (MHz) 42.5 3.5 VS = ±15V VS = 5V 3.0 2.5 32.5 30.0 60 CLOAD = 30pF 60167 G32 Phase Margin vs Capacitive Load 45.0 180.0 10 0.1 1 FREQUENCY (kHz) 60167 G31 1000 PHASE MARGIN (DEG) GAIN PHASE SHIFT (DEG) 135.0 20 1V/V 0 3.5 112.5 40 30 –20 90.00 PHASE 10 10 100 FREQUENCY (kHz) Gain Bandwidth Product and Phase Margin vs Supply Voltage 60 100V/V 10V/V 1 60167 G30 Gain and Phase Shift vs Frequency 50 20 0 0.1 1000 60167 G29 Closed-Loop Small Signal Frequency Response 40 40 20 20 GAIN BANDWIDTH PRODUCT (MHz) 0 60 NEGATIVE SUPPLY 40 0.01 PHASE MARGIN (DEG) VS = ±2.5V POSITIVE SUPPLY 0.10 GAIN (dB) CMRR vs Frequency 100 100 100 PSRR (dB) OUTPUT IMPEDANCE (Ω) 1000 120 RLOAD = OPEN RLOAD = 1kΩ 110 100 90 80 70 0 50 100 150 200 250 CAPACITIVE LOAD (pF) 300 60167 G34 2.0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 60167 G35 VS = ±15V 60 0.1 1 10 100 FREQUENCY (kHz) 1000 60167 G36 60167fa 11 LT6016/LT6017 TYPICAL PERFORMANCE CHARACTERISTICS Settling Time to 0.1% vs Output Step Slew Rate vs Temperature 2.0 VS = ±2.5V 4 AV = +1 OUTPUT STEP (V) 2 1 0 –1 AV = –1 –2 RISING EDGE 1.5 AV = –1 SLEW RATE (V/μs) 3 VS = ±15V VCM = 0V Short-Circuit vs Temperature 40 SHORT-CIRCUIT CURRENT (mA) 5 1.0 FALLING EDGE 0.5 –3 AV = +1 20 10 0 –10 SOURCING –20 –30 –4 –5 VS = 5V SINKING 30 2 3 4 5 SETTLING TIME (μs) 6 0 –50 –25 7 0 60167 G37 25 50 75 100 125 150 TEMPERATURE (°C) 60167 G39 Output Saturation Voltage vs Input Overdrive Large Signal Transient Response AV = 1V/V VS = ±2.5V CLOAD = 20pF 1000 OUTPUT SATURATION VOLTAGE (mV) AV = 1V/V VS = ±15 5V/DIV 25mV/DIV 0 60167 G38 Small Signal Transient Response 60167 G40 1μs/DIV –40 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 100 OUTPUT LOW 10 1 60167 G41 10μs/DIV OUTPUT HIGH VS = ±2.5V TA = 25°C NO LOAD 1 10 100 INPUT OVERDRIVE (mV) 1000 60167 G42 Output Saturation Voltage (VOL) vs Load Current Output Saturation Voltage (VOH) vs Load Current 10k Open-Loop Gain 200 10k VS = ±15V 150 100 10 1 0.001 OFFSET VOLTAGE (μV) 1000 VOH (mV) VOL (mV) 1000 100 0.01 0.1 1 SINKING LOAD CURRENT (mA) 10 60167 G43 1 0.001 RLOAD = 2kΩ RLOAD = 10kΩ 50 0 –50 RLOAD = 1MΩ –100 10 TA = 125°C TA = 25°C TA = –45°C 100 TA = 125°C TA = 25°C TA = –45°C 0.01 0.1 1 SOURCING LOAD CURRENT (mA) 10 60167 G44 –150 –200 –20 –15 –10 –5 0 5 10 OUTPUT VOLTAGE (V) 15 20 60167 G45 60167fa 12 LT6016/LT6017 APPLICATIONS INFORMATION Supply Voltage Inputs The positive supply pin of the LT6016/LT6017 should be bypassed with a small capacitor (typically 0.1μF) as close to the supply pins as possible. When driving heavy loads an additional 4.7μF electrolytic capacitor should be added. When using split supplies, the same is true for the V– supply pin. Referring to the Simplified Schematic, the LT6016/LT6017 has two input stages: a common emitter differential input stage consisting of PNP transistors Q1 and Q2 which operate when the inputs are biased between V– and 1.5V below V+, and a common base input stage consisting of PNP transistors Q3 to Q6 which operate when the common mode input is biased greater than V+ –1.5V. This results in two distinct operating regions as shown in Figure 2. The LT6017 consists of two dual amplifier dice assembled in a single DFN package which share a common substrate (V–). While the V– pins of the quad (pins 5 and 7) must always be tied together and to the exposed pad underneath, the V+ power supply pins (pins 16 and 18) may be supplied independently. The B and C channel amplifiers are supplied through V+ by pin 16, and the A and D channel amplifiers are supplied by pin 18. If pin 16 and pin 18 are not tied together and are biased independently, each V+ pin should have their own dedicated supply bypass to ground. For common mode input voltages approximately 1.5V or more below the V+ supply (Q1 and Q2 active), the common emitter PNP input stage is active and the input bias current is typically under ±2nA. When the common mode input is within approximately 1V of the V+ supply or higher –50V OK! + Shutdown While there are no dedicated shutdown pins for the LT6016/ LT6017, the amplifiers can effectively be shut down into a low power state by removing V+. In this condition the input bias current is typically less than 1nA with the inputs biased between V– and 76V above V–, and if the inputs are taken below V–, they appear as a diode in series with 1k of resistance. The output may be pulled up to 50V above the V+ power supply in this condition (See Figure 1). Pulling the output pin below V– will produce unlimited current and can damage the part. Reverse Battery The LT6016/LT6017 are protected against reverse battery voltages up to 50V. In the event a reverse battery condition occurs, the supply current is typically less than 5μA (assuming the inputs are biased within a diode drop from V–). For typical single supply applications with ground referred loads and feedback networks, no other precautions are required. If the reverse battery condition results in a negative voltage at the input pins, the current into the pin should be limited by an external resistor to less than 10mA. 5V OK! + – – + 80V REVERSE BATTERY TOLERANT 5V OK! 80V INPUTS DRIVEN ABOVE SUPPLY TOLERANT + 5V OK! + + – – – 25V TRANSIENT LARGE DIFFERENTIAL INPUT VOLTAGE TOLERANT INPUTS DRIVEN BELOW GROUND TOLERANT 0V OK! + + – 50V + 60167 F01 OUTPUT DRIVEN ABOVE THE V+ SUPPLY (IN SHUTDOWN) TOLERANT Figure 1. LT6016/LT6017 Fault Tolerant Conditions 60167fa 13 LT6016/LT6017 APPLICATIONS INFORMATION The inputs are protected against temporary excursions to as much as 25V below V– by internal 1k resistor in series with each input and a diode from the input to the negative supply. Adding additional external series resistance will extend the protection beyond 25V below V–. The input stage of the LT6016/LT6017 incorporates phase reversal protection to prevent the output from phase reversing for inputs below V–. There are no clamping diodes between the inputs. The inputs may be over-driven differentially to 80V without damage, or without drawing appreciable input current. Figure 1 summarizes the kind of faults that may be applied to the LT6016/LT6017 without damage. Over-The-Top Operation Considerations When the input common mode of the LT6016/LT6017 is biased near or above the V+ supply, the amplifier is said to be operating in the Over-The-Top configuration. The differential input pair which control amplifier operation is common base pair Q3 to Q6 (refer to the Simplified Schematic). If the input common mode is biased between V– and approximately 1.5V below V+, the amplifier is said to be operating in the normal configuration. The differential input pair which control amplifier operation is common emitter pair Q1 and Q2. A plot of the Over-The-Top Transition region vs Temperature (the region between normal operation and Over-The-Top operation) on a 5V single supply is shown in Figure 2. 5.0 4.5 VS = 5V 4.0 3.5 VCM (V) (Over-The-Top operation), Q9 begins to turn on diverting bias current away from the common emitter differential input pair to the current mirror consisting of Q11 and Q12. The current from Q12 will bias the common base differential input pair consisting of Q3 to Q6. Because the Over-The-Top input pair is operating in a common base configuration, the input bias current will increase to about, 14μA. Both input stages have their voltage offsets trimmed tightly and are specified in the Electrical Characteristics table. TYPICAL COMMON MODE VOLTAGE FOR ONSET OF OVER-THE-TOP OPERATION 3.0 2.5 2.0 TYPICAL COMMON MODE VOLTAGE WHERE OVER-THE-TOP OPERATION FULLY ON 1.5 1.0 TRANSISTION REGION 0.5 0 –50 –25 0 25 75 50 TEMPERATURE (°C) 100 125 150 60167 F02 Figure 2. LT6016/LT6017 Over-The-Top Transition Region vs Temperature Some implications should be understood about OverThe-Top operation. The first, and most obvious is the input bias currents change from under ±2nA in normal operation to 14μA in Over-The-Top operation as the input stage transitions from common emitter to common base. Even though the Over-The-Top input bias currents run around 14 μA, they are very well matched and their offset is typically under ±100nA. The second and more subtle change to amplifier operation is the differential input impedance which decreases from 1MΩ in normal operation, to approximately 3.7kΩ in Over-The-Top operation (specified as RIN in the Electrical Characteristics table). This resistance appears across the summing nodes in Over-The-Top operation and is due to the common base input stage configuration. Its value is easily derived from the specified input bias current flowing into the op amp inputs and is equal to 2 • k • T/(q • Ib) (k-Boltzmann’s constant, T – operating temperature, Ib-operating input bias current of the amplifier in the Over-The-Top region). And because the inputs are biased proportional to absolute temperature, it is relatively constant with temperature. The user may think this effective resistance is relatively harmless because it appears across the summing nodes which are forced 60167fa 14 LT6016/LT6017 APPLICATIONS INFORMATION to 0V differential by feedback action of the amplifier. However, depending on the configuration of the feedback around the amplifier, this input resistance can boost noise gain, lower overall amplifier loop gain and closed loop bandwidth, raise output noise, with one benevolent effect in increasing amplifier stability. In the normal mode of operation (where V– < VCM < V+ –1.5V), RIN is typically large compared to the value of the input resistor used, and RIN can be ignored (refer to Figure 3). In this case the noise gain is defined by the equation: R NOISE GAIN ≈ 1+ F RI Normal mode: BWCLOSED − LOOP ≈ GBW R 1+ F RI Over-The-Top mode: BWCLOSED − LOOP ≈ GBW RF 1+ RI || (RIN + RI || R F) And output noise is negatively impacted going from normal mode to Over-The-Top: However, when the amplifier transitions into Over-The-Top mode with the input common mode biased near or above the the V+ supply, RIN should be considered. The noise gain of the amplifier changes to: NOISE GAIN = 1+ Likewise the closed loop bandwidth of the amplifier will change going from normal mode operation to Over-TheTop operation: RF RI || (RIN + RI || R F) Normal mode: (neglecting resistor noise) ⎛ R ⎞ eno ≈ eni • ⎜1+ F ⎟ ⎝ RI ⎠ Over-The-Top mode: (neglecting resistor noise) RF 5V RI VIN VINCM RI + RIN 1/2 LT6016 VOUT ⎞ ⎛ RF ⎟⎟ eno ≈ eni • ⎜⎜1+ ⎝ RI || (RIN + RI || R F) ⎠ – Output RF 60167 F03 Figure 3. Difference Amplifier Configured for Both Normal and Over-The-Top Operation While it is true that the DC closed loop gain will remain mostly unaffected (= R F ), the loop gain of the amplifier RI A OL A OL RF has decreased from 1+ R F to 1+ RI || (RIN + RI || R F) RI The output of the LT6016/LT6017 can swing within a Schottky diode drop (~0.4V) of the V+ supply, and within 5mV of the negative supply with no load. The output is capable of sourcing and sinking approximately 25mA. The LT6016/LT6017 are internally compensated to drive at least 200pF of capacitance under any output loading conditions. For larger capacitive loads, a 0.22μF capacitor in series with a 150Ω resistor between the output and ground will compensate these amplifiers to drive capacitive loads greater than 200pF. 60167fa 15 LT6016/LT6017 APPLICATIONS INFORMATION Distortion In general, the die junction temperature (TJ) can be estimated from the ambient temperature TA, and the device power dissipation PD: There are two main contributors of distortion in op amps: output crossover distortion as the output transitions from sourcing to sinking current and distortion caused by nonlinear common mode rejection. If the op amp is operating in an inverting configuration there is no common mode induced distortion. If the op amp is operating in the noninverting configuration within the normal input common mode range (V– to V+ –1.5V) the CMRR is very good, typically over 120dB. When the LT6016 transitions input stages going from the normal input stage to the Over-The-Top input stage or vice-versa, there will be a significant degradation in linearity due to the change in input circuitry. The power dissipation in the IC is a function of supply voltage and load resistance. For a given supply voltage, the worst-case power dissipation PD(MAX) occurs at the maximum supply current with the output voltage at half of either supply voltage (or the maximum swing is less than one-half the supply voltage). PD(MAX) is given by: Lower load resistance increases distortion due to a net decrease in loop gain, and greater voltage swings internal to the amp necessary to drive the load, but has no effect on the input stage transition distortion. The lowest distortion can be achieved with the LT6016/LT6017 sourcing in class-A operation in an inverting configuration, with the input common mode biased mid-way between the supplies. PD(MAX) = 2 • 50 • 0.6mA + 2 • (12.5)2/2500 = 0.185W Power Dissipation Considerations Because of the ability of the LT6016/LT6017 to operate on power supplies up to ±25V and to drive heavy loads, there is a need to ensure the die junction temperature does not exceed 150°C. The LT6016 is housed in an 8-lead MSOP package (θJA = 273°C/W). The LT6017 is housed in a 22 pin leadless DFN package (DJC22, θJA = 31.8°C/W). TJ = TA + PD • θJA PD(MAX) = (VS • IS(MAX)) + (VS/2)2/RLOAD Example: An LT6016 in a MSOP package mounted on a PC board has a thermal resistance of 273°C/W. Operating on ±25V supplies with both amplifiers simultaneously driving 2.5kΩ loads, the worst-case IC power dissipation for the given load occurs when driving 12.5VPEAK and is given by: With a thermal resistance of 273°C/W, the die temperature will experience approximately a 50°C rise above ambient. This implies the maximum ambient temperate the LT6016 should ever operate under the assumed conditions: TA = 150°C – 50°C = 100°C To operate to higher ambient temperatures, use two channels of the LT6017 quad which has lower thermal resistance θJA = 31.8°C/W, and an exposed pad which may be soldered down to a copper plane (connected to V–) to further lower the thermal resistance below θJA = 31.8°C/W. 60167fa 16 LT6016/LT6017 SIMPLIFIED SCHEMATIC V+ Q10 PNP R5 40k I1 I3 I4 16μA 8μA 8μA M2 PMOS R1, 1k Q9 PNP –IN I2 R2, 1k 5μA Q2 PNP +IN Q6 PNP Q3 PNP Q4 PNP D3 Q5 PNP P CLASS AB ADJUST N Q1 PNP Q7 NPN M1 PMOS OUT Q8 NPN Q13 NPN Q11 NPN Q12 NPN D1 D2 R3 6k R4 6k D4 V– 60167 SS 60167fa 17 LT6016/LT6017 TYPICAL APPLICATIONS Gain of 100 High Voltage Difference Amplifier with –5V/75V Common Mode Range CMRR ADJUST 97.6k 5k 1k + VIN – + VCM – 1k 5V + 1/2 LT6016 VOUTt7IN – –5V 100k 60167 TA02 60167fa 18 LT6016/LT6017 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660 Rev F) 0.889 ±0.127 (.035 ±.005) 5.23 (.206) MIN 3.20 – 3.45 (.126 – .136) 3.00 ±0.102 (.118 ±.004) (NOTE 3) 0.65 (.0256) BSC 0.42 ± 0.038 (.0165 ±.0015) TYP 8 7 6 5 0.52 (.0205) REF RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ±0.102 (.118 ±.004) (NOTE 4) 4.90 ±0.152 (.193 ±.006) DETAIL “A” 0° – 6° TYP GAUGE PLANE 1 0.53 ±0.152 (.021 ±.006) DETAIL “A” 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.007) SEATING PLANE 0.22 – 0.38 (.009 – .015) TYP 0.65 (.0256) NOTE: BSC 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.1016 ±0.0508 (.004 ±.002) MSOP (MS8) 0307 REV F 60167fa 19 LT6016/LT6017 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. DJC Package 22-Lead Plastic DFN (6mm w 3mm) (Reference LTC DWG # 05-08-1714 Rev Ø) 0.889 0.70 ±0.05 R = 0.10 0.889 3.60 ±0.05 1.65 ±0.05 2.20 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 5.35 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 3. DRAWING IS NOT TO SCALE 6.00 ±0.10 (2 SIDES) 0.889 R = 0.10 TYP 3.00 ±0.10 (2 SIDES) R = 0.115 TYP 0.40 ±0.05 12 22 0.889 1.65 ±0.10 (2 SIDES) PIN 1 TOP MARK (NOTE 6) 11 0.200 REF 1 0.25 ±0.05 0.50 BSC 0.75 ±0.05 0.00 – 0.05 5.35 ±0.10 (2 SIDES) PIN #1 NOTCH R0.30 TYP OR 0.25mm w 45° CHAMFER (DJC) DFN 0605 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WXXX) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON TOP AND BOTTOM OF PACKAGE 60167fa 20 LT6016/LT6017 REVISION HISTORY REV DATE DESCRIPTION A 01/13 Corrected Block Diagram Q7 and Q8 PAGE NUMBER 17 60167fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 21 LT6016/LT6017 TYPICAL APPLICATION Extended Supply Current Boosted Gain of Three Amplifier Drives 100Ω Load to ±30V, with 600mA Current Limit 47nF 1k 0.1μF 35V 330pF 1k 820pF 35V 20k 10k – 100k 330Ω 1/2 LT6016** 1k VIN Q1 – 1/2 LT6016 1Ω 604Ω 1/2W + Q2 + VOUT = ±30V 24VZ* –35V 1k 10nF 24VZ* –35V 47nF 2 × 1N4148 OR EQUIVALENT *ZENER DIODES: CENTRAL SEMI CMZ5934 Q1, Q2: ON-SEMI D44VH10 NPN, D45VH10 PNP WITH HEAT SINK **BOTH HALVES OF LT6016 ON SAME SUPPLY 60167 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1490A/LT1491A Dual and Quad Micropower Rail-to-Rail Input and Output Op amp Over-The-Top Inputs, 50μA/Amplifier, Reverse Battery Protection to 18V LT1638/LT1639 1.2MHz, 0.4V/μs Over-The-Top Rail-to-Rail Input and Over-The-Top Inputs, 230μA/Amplifier, 1.2MHz GBW, 0.4V/μs Slew Rate Output Op Amp LT1494/LT1495/LT1496 1.5μA Max, Single, Dual, and Quad, Over-The-Top Precision Rail-to-Rail Input and Output Op Amps Over-The-Top Inputs, 1.5μA/Amplifier, 375μV Voltage Offset LT1112/LT1114 Dual/Quad Low Power Precision, pA Input Op Amp 60μV Offset Voltage, 400 μA/Amplifier LT1013/LT1014 Dual/Quad Precision Op Amp 150μV Offset Voltage, 500 μA/Amplifier 60167fa 22 Linear Technology Corporation LT 0113 REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2012