AKM AK5730 4-channel differential audio adc for line & mic input Datasheet

[AK5730]
AK5730
4-Channel Differential Audio ADC for Line & Mic Inputs
GENERAL DESCRIPTION
The AK5730 features a 4-channel Differential ADC with SAR ADC for DC measurement. Differential ADC
supports Line and Microphone-input, making it ideal for microphone array applications. TDM audio format
makes it easy to connect with DSP.
FEATURES
1. Audio ADC
- 4-Channel Audio ADC
- Full-differential Input
- Input Voltage:
Mic: 1.65Vrms,
LINE and Phone: 3Vrms(with external resistors) programmable
Boost input: 11.7Vrms(with external resistors) programmable
- ADC Performance:
S/(N+D): typ 92dB
DR, S/N: typ 100dB
- Digital HPF for DC-offset cancellation: fc=1Hz with individual on/off
2. SAR ADC
- 1ch SAR ADC with 9:1 MUX
- Reference Voltage: Ground
3. Sampling Rate: 8kHz ~ 48kHz
4. Master Clock: 256fs, 384fs, 512fs or Internal PLL
5. Master/Slave mode
6. Audio Interface Format: MSB First, 2’s complement
- 24bit I2S
- 24bit TDM interface up to 4 ICs cascade
7. Channel Independent Microphone Diagnostics
- open microphone
- shorts to battery
- shorts to ground
- shorts across inputs
- microphone bias over current
- over temperature
8. Programmable Microphone Bias: 5V to 9V with 0.5V step
9. μP I/F: I2C Bus (Ver 1.0, 400kHz Mode) or SPI
10. Power Supply:
VDD: 3.0 ∼ 3.6V
11. Ta = −40 ∼ 105°C
12. Package: 48pin LQFP
Rev 0.8
2013/06
-1-
[AK5730]
■ Block Diagram
max: 10mA x 4Mic
Mic
AVDD VSS1 VREF DVDD VSS2
+5.0~9.0V
CP1
CN1
CP2
CN2
CVP1
CVP2
Mic
Bias,
CP
SPI
MCLK
Amp.
IN1P
MCLKI
MUX
PLL
+
ADC1
IN1N
HPF,
LPF,
Gain
Amp.
Line
IIS/TDM
Out
IN4P
+
IN4N
ADC4
BICK(64-512fs)
LRLK
SDTO1
SDTO2
TDMI
MSN
-
PDN
INM1P
INM1N
1
2
MUX
Battery
INM4P
INM4N
SAR
ADC
7
8
9
Mic.
Diags
IIC or SPI
I/F
CAD0/CSN
CAD1/CDTO
SDA/CDTI
SCL/CCLK
INT
VBATM
Figure 1. Block Diagram
Rev 0.8
2013/06
-2-
[AK5730]
MPWR
NC
CVP1
CP1
CN1
DVDD
VSS2
NC
CN2
NC
SCL/CCLK
SDA/CDTI
36
35
34
33
32
31
30
29
28
27
26
25
■ Pin Layout
CP2
37
24
INT
CVP2
38
23
SDTO2
NC
39
22
SDTO1
INM1P
40
21
LRCK
IN1P
41
20
BICK
IN1N
AK5730VQ
42
19
MCLK
INM1N
43
18
TDMI
VREF
44
17
CAD1/CDTO
INM2P
45
16
CAD0/CSN
IN2P
Top View
8
9
10
11
12
IN4P
IN4N
INM4N
VSS1
VBATM
6
MSN
7
5
IN3N
INM3N
INM4P
4
AVDD
3
13
IN3P
SPI
48
2
47
INM2N
INM3P
PDN
14
1
15
VREFL
46
IN2N
Rev 0.8
2013/06
-3-
[AK5730]
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
Pin Name
VREFL
INM3P
IN3P
IN3N
INM3N
MSN
INM4P
IN4P
IN4N
INM4N
VSS1
VBATM
I/O
I
I
I
I
I
I
I
I
I
I
I
13
AVDD
-
14
SPI
I
15
PDN
I
CAD0
I
CSN
I
CAD1
I
CDTO
O
18
19
20
21
TDMI
MCLK
BICK
LRCK
I
I
I/O
I/O
22
SDTO1
O
23
SDTO2
O
24
INT
O
SDA
I/O
CDTI
I
SCL
I
CCLK
I
NC
-
16
17
25
26
27
Function
ADC Reference Pin. 0V
Ch3 Positive Input Monitor Pin
Ch3 Positive Input Pin (with DC cut capacitor)
Ch3 Negative Input Pin (with DC cut capacitor)
Ch3 Negative Input Monitor Pin
Master/Slave Control Pin
Ch4 Positive Input Monitor Pin
Ch4 Positive Input Pin (with DC cut capacitor)
Ch4 Negative Input Pin (with DC cut capacitor)
Ch4 Negative Input Monitor Pin
Ground Pin 1. 0V
Battery Power Monitor Pin
Analog Power Supply Pin, 3.0 ∼ 3.6V
Normally connected to VSS1 with a 0.1μF ceramic capacitor in
parallel with a 10μF electrolytic cap.
Control Mode Select Pin
“L”: I2C Bus or Parallel control mode, “H”: 4-wire serial control mode
Power-Down Mode Pin
When at “L”, the AK5730 is in the power-down mode and is held in reset. The AK5730
should always be reset upon power-up.
(SPI pin = “L”)
Chip Address 0 Pin
(SPI pin = “H”)
Chip Select Pin in serial control mode
(SPI pin = “L”)
Chip Address 1 Pin
(SPI pin = “H”)
Control Data Output Pin
TDM Data Input Pin
Master Clock Input Pin
Audio Serial Data Clock Pin
Channel Clock Pin
ADC Audio Serial Data Output1 Pin
Test Mode Digital Output Pin
ADC Audio Serial Data Output2 Pin
Test Mode Digital Output Pin
Interrupt Signal Output Pin
Normally connected to DVDD(3.3V) through 10kΩ resistor externally.
(SPI pin = “L”)
Control Data Input/Output Pin
(SPI pin = “H”)
Control Data Input Pin
(SPI pin = “L”)
Control Data Clock Pin
(SPI pin = “H”)
Control Data Clock Pin
This pin should be connected to VSS1.
Rev 0.8
2013/06
-4-
[AK5730]
No.
Pin Name
I/O
28
CN2
I
29
30
NC
VSS2
-
31
DVDD
-
32
CN1
I
33
CP1
I
34
CVP1
O
35
NC
-
36
MPWR
O
Function
Negative Charge Pump Capacitor Terminal Pin 2
Connect to CP2 with a 2.2μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the positive
polarity pin should be connected to the CP2 pin. Non polarity capacitors can also be
used.
* The maximum bias voltage of this pin is 7.2V. The capacitance variation of an external
capacitor should be in the range of 2.2μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
This pin should be connected to VSS1.
Digital Ground Pin and Charge Pump Ground Pin , 0V
Digital Power Supply Pin and Charge Pump Circuit Positive Power Supply Pin 3.0V∼3.6V
Normally connected to VSS2 with a 0.1μF ceramic capacitor in parallel with a 10μF
electrolytic cap.
Positive Charge Pump Capacitor Terminal Pin 1
Connect to CN1 with a 2.2μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the positive
polarity pin should be connected to the CN1 pin. Non polarity capacitors can also be
used.
* The maximum bias voltage of this pin is 3.6V. The capacitance variation of an external
capacitor should be in the range of 2.2μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
Negative Charge Pump Capacitor Terminal Pin 1
Connect to CP1 with a 2.2μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the positive
polarity pin should be connected to the CP1 pin. Non polarity capacitors can also be
used.
* The maximum bias voltage of this pin is 3.6V. The capacitance variation of an external
capacitor should be in the range of 2.2μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
Charge Pump Circuit Positive Voltage Output Pin 1
Connect to VSS2 with a 2.2μF capacitor that should have the low ESR (Equivalent Series
Resistance) over all temperature range. When this capacitor has the polarity, the positive
polarity pin should be connected to the VSS2 pin. Non polarity capacitors can also be
used.
* The maximum bias voltage of this pin is 7.2V. The capacitance variation of an external
capacitor should be in the range of 2.2μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
This pin should be connected to VSS1.
MIC Power Supply Pin
Normally connected to VSS1 with a 1μF ceramic capacitor.
* The maximum bias voltage of this pin is 10V. The capacitance variation of an external
capacitor should be in the range of 1μF +20% and -40% including the difference by a
tolerance, a rate of temperature change and a bias voltage.
Rev 0.8
2013/06
-5-
[AK5730]
No.
Pin Name
I/O
39
NC
-
Function
Positive Charge Pump Capacitor Terminal Pin 2
Connect to CN2 with a 2.2μF capacitor that should have the low ESR (Equivalent
Series Resistance) over all temperature range. When this capacitor has the polarity, the
positive polarity pin should be connected to the CN2 pin. Non polarity capacitors can
also be used.
* The maximum bias voltage of this pin is 7.2V. The capacitance variation of an
external capacitor should be in the range of 2.2μF +20% and -40% including the
difference by a tolerance, a rate of temperature change and a bias voltage.
Charge Pump Circuit Positive Voltage Output Pin 2
Connect to VSS2 with a 2.2μF capacitor that should have the low ESR (Equivalent
Series Resistance) over all temperature range. When this capacitor has the polarity, the
positive polarity pin should be connected to the VSS2 pin. Non polarity capacitors can
also be used.
* The maximum bias voltage of this pin is 7.2V. The capacitance variation of an
external capacitor should be in the range of 2.2μF +20% and -40% including the
difference by a tolerance, a rate of temperature change and a bias voltage.
This pin should be connected to VSS1.
37
CP2
I
38
CVP2
O
40
INM1P
I
Ch1 Positive Input Monitor Pin
41
IN1P
I
Ch1 Positive Input Pin (with DC cut capacitor)
42
IN1N
I
Ch1 Negative Input Pin (with DC cut capacitor)
43
INM1N
I
Ch1 Negative Input Monitor Pin
Voltage Reference Pin for MPWR.
44 VREF
O
Normally connected to VSS1 with a 1.0μF ceramic capacitor.
45 INM2P
I
Ch2 Positive Input Monitor Pin
46 IN2P
I
Ch2 Positive Input Pin (with DC cut capacitor)
47 IN2N
I
Ch2 Negative Input Pin (with DC cut capacitor)
48 INM2N
I
Ch2 Negative Input Monitor Pin
Note 1. All digital input pins should not be left floating.
NC Pin (No internal bonding).
Rev 0.8
2013/06
-6-
[AK5730]
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 2)
Parameter
Symbol
min
max
Unit
Power Supplies: Analog
AVDD
4.6
V
−0.3
Digital
DVDD
4.6
V
−0.3
Charge Pump
CVDD
4.6
V
-0.3
Input Current, Any Pin Except Supplies
IIN
mA
±10
Analog Input Voltage
(Note 3)
VINA
CVP1+0.3
V
−0.3
Digital Input Voltage
VIND
DVDD+0.3
V
−0.3
Ambient Temperature (powered applied)
Ta
105
−40
°C
Storage Temperature
Tstg
150
−65
°C
Note 2. All voltages with respect to ground. VSS1 and VSS2 must be connected to the same analog ground plane.
Note 3. CVP1: CVP1 pin voltage.
The internal positive power supply generating circuit provides positive power supply (CVP1).
Mode
Power-down (PDN pin and RSTN bit control)
Normal operation
CVP1 pin voltage
CVP1 pin Voltage
AVDD
1.67 x AVDD
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2 =0V; Note 2)
Parameter
Symbol
min
typ
max
Unit
Power Supplies Analog
AVDD
3.0
3.3
3.6
V
(Note 4) Digital, Charge Pump
DVDD
3.0
3.3
3.6
V
Note 2. All voltages with respect to ground. VSS1 and VSS2 must be connected to the same analog ground plane.
Note 4. The AVDD, DVDD must be the same voltage.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
Rev 0.8
2013/06
-7-
[AK5730]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=DVDD =3.3V; VSS1=VSS2=VSS3=0V; MCKI=512fs, fs=48kHz, BCLK=64fs; Signal
Frequency=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified; GAIN bit = “0”)
min
typ
max
Unit
Parameter
ADC Analog Characteristics (AC):
Resolution
24
Bits
Differential, Note 5
1.55
1.65
1.75
Vrms
Input Voltage
Single-ended, Note 6
0.77
0.82
0.87
Vrms
Gain mode, Note 7
0.51
0.55
0.59
Vrms
Input Impedance
1.0
1.4
MΩ
86
92
dB
−0.5dBFS Differential
S/(N+D)
86
92
dB
−0.5dBFS Single-ended
86
92
−0.5dBFS Gain mode
93
100
dB
−60dBFS, A-weighted Differential
Dynamic Range −60dBFS, A-weighted Single-ended
92
99
dB
92
98
−60dBFS, A-weighted Gain mode
A-weighted Differential
93
100
dB
S/N
A-weighted Single-ended
92
99
dB
10mVrms input, A-weighted Gain mode
57
63
dB
Interchannel Isolation
90
100
dB
Interchannel Gain Mismatch
0
0.3
dB
1kHz, Differential. Note 8
70
85
dB
20kHz, Differential. Note 8
70
85
dB
1kHz, Single-ended, Note 8
65
80
dB
CMRR
55
65
dB
20kHz, Single-ended, Note 8
1kHz, Gain mode, Note 9
65
80
dB
20kHz, Gain mode, Note 9
65
80
dB
PSRR (1kHz, Note 10)
50
dB
MIC Power Supply:
MBS3-0 bits= “0000”
4.90
5
5.10
V
MBS3-0 bits= “0001”
5.39
5.5
5.61
V
MBS3-0 bits= “0010”
5.88
6
6.12
V
MBS3-0 bits= “0011”
6.37
6.5
6.63
V
Output DC Voltage
MBS3-0 bits= “0100”
6.86
7
7.14
V
(Note 11)
MBS3-0 bits= “0101”
7.35
7.5
7.65
V
MBS3-0 bits= “0110”
7.84
8
8.16
V
MBS3-0 bits= “0111”
8.33
8.5
8.67
V
MBS3-0 bits= “1000”
8.78
9
9.22
V
Microphone Current (for 4 channels)
0.1
40
mA
Output Noise Level (A-weighted)
-100
-94
dBV
SAR ADC Characteristics (DC):
Resolution
12
Bits
Input Voltage (Note 12)
3.2
3.3
3.4
V
Integral Nonlinearity (INL) Error
-4
+5
LSB
Differential Nonlinearity (DNL) Error
-2
+2
LSB
Note 5. The voltage difference between IN*P and IN*N pins. Input Voltage should be adjusted with external resistors.
Input voltage is proportional to AVDD voltage. Vin = 0.5 × AVDD Vrms (typ). Full scale: -0.034dB
Note 6. Single-ended IN*P pin, IN*N pin must be connected to signal common. Input Voltage should be adjusted with
external resistors. When STD* bit = “1”, Input voltage is proportional to AVDD voltage.
Vin = 0.25 × AVDD Vrms (typ). Full scale: -0.034dB
Note 7. The voltage difference between IN*P and IN*N pins. Input Voltage should be adjusted with external resistors.
When GAIN* bit = “1”, Input Voltage = 0.55Vrms = 0.167 × AVDD Vrms (typ). Full scale: -0.034dB
Note 8. The 1kHz, 1.0Vpp signal is applied to IN*N and IN*P with same phase.
The CMRR is measured as the attenuation level from 0dB = -7.5dBFS(since the normal 1Vpp= -7.5dBFS).
Note 9. The 1kHz, 0.5Vpp signal is applied to IN+. IN- pin must be connected to be signal common.
The CMRR is measured as the attenuation level from 0dB = -4dBFS(since the normal 1Vpp=-4dBFS).
Rev 0.8
2013/06
-8-
[AK5730]
Note 10. The PSRR is applied to AVDD and DVDD with 1kHz, 100mVpp.
Note 11. When MBS3-0 bits = “0000” / “0001” / “0010” / “0011” / “0100” / “0101” / “0110” / “0111”/ “1000”,
Output DC Voltage(typ) is 1.52 / 1.67 / 1.82 / 1.97 / 2.12 / 2.27 / 2.42 / 2.58/ 2.73 × AVDD(V).
When MBS3-0 bits = “0000” / “0001” / “0010” / “0011” / “0100” / “0101” / “0110” / “0111”,
Output DC Voltage(min, max) is ±2.0% of Output DC Voltage(typ).
When MBS3-0 bits = “1000”, Output DC Voltage(min, max) is ±2.5% of Output DC Voltage (typ).
Note 12. Input Voltage should be adjusted with external resistors. The input voltage range is 0 to AVDD.
Vin = 1.00 × AVDD (Vpp). The SAR ADC operates at not less than 100 mV.
Rev 0.8
2013/06
-9-
[AK5730]
FILTER CHARACTERISTICS
(Ta=25°C ; AVDD=DVDD=3.0∼3.6V; fs=48kHz)
Parameter
Symbol
min
typ
max
Unit
ADC Digital Filter (Decimation LPF):
Passband
(Note 13)
PB
0
18.0
kHz
±0.13dB
20.0
kHz
-0.2dB
23.0
kHz
-3.0dB
Stopband
SB
28
kHz
Passband Ripple
PR
dB
±0.04
Stopband Attenuation
SA
68
dB
Group Delay
(Note 14)
GD
16.4
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response
(Note 13) -3dB
FR
1.0
Hz
-0.1dB
7.1
Hz
Note 13. The passband and stopband frequencies scale with fs.
For example, 21.8kHz at –0.1dB is 0.454 x fs.
Note 14. The calculating delay time which occurred by digital filtering. This time is from setting the input of analog signal
to setting the 24bit data of both channels to the output register.
1
1
1
DC CHARACTERISTICS
(Ta=-40°C ~+105°C; AVDD=DVDD=3.0∼3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage ( Iout=-400μA)
VOH
DVDD-0.4
Low-Level Output Voltage
VOL
(Iout= -400μA(except SDA, INT pin),
3mA(SDA, INT pin))
Input Leakage Current
Iin
(Ta=25°C; AVDD=DVDD=3.3V )
Power Supplies
Parameter
Power Supply Current
Normal Operation (PDN pin = “H”)
DVDD (Microphone Current=40mA)
DVDD (Microphone Current=100uA)
AVDD
Power-Down Mode (PDN pin = “L”; Note 15)
DVDD+AVDD
DVDD
AVDD
min
typ
-
max
30%DVDD
0.4
Unit
V
V
V
V
-
±10
μA
typ
max
Unit
180
18
9
220
27
13.5
mA
mA
mA
100
μA
μA
μA
3
0
Note 15. All digital inputs including clock pins (MCLK, BICK, LRCK and TDMI) are held at DVDD or VSS2.
Rev 0.8
2013/06
- 10 -
[AK5730]
SWITCHING CHARACTERISTICS
(Ta=-40∼+105°C; AVDD=DVDD=3.0∼3.6V; CL=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
Master Clock Timing
External Clock
fCLK
256fs:
2.048
tCLKL
Pulse Width Low
32
tCLKH
Pulse Width High
32
fCLK
384fs:
3.072
tCLKL
Pulse Width Low
22
tCLKH
Pulse Width High
22
fCLK
512fs:
4.096
tCLKL
Pulse Width Low
16
tCLKH
Pulse Width High
16
LRCK Timing (Slave mode)
Stereo mode
(TDM1/0 bit = “00”)
fs
8
frequency
Duty
45
Duty Cycle
TDM256 mode
(Note 16)
(TDM1/0 bit = “01”)
fsn
8
LRCK frequency
tLRH
1/256fs
“H” time
tLRL
1/256fs
“L” time
TDM512 mode
(Note 16)
(TDM1/0 bit = “10”)
fsn
8
LRCK frequency
tLRH
1/512fs
“H” time
tLRL
1/512fs
“L” time
LRCK Timing (Master Mode)
Stereo mode
(TDM1/0 bit = “00”)
fsn
8
Normal Speed Mode
Duty
Duty Cycle
TDM256 mode
(Note 16)
(TDM1/0 bit = “01”)
fsn
8
LRCK frequency
tLRH
“H” time
(Note 17)
TDM512 mode
(Note 16)
(TDM1/0 bit = “10”)
fsn
8
LRCK frequency
tLRH
“H” time
(Note 17)
Note 16. Master clock should be input the 256fs/512fs in Master mode.
Note 17. If the format is I2S, it is “L” time.
Rev 0.8
50
max
Unit
12.288
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
18.432
24.576
48
55
kHz
%
48
kHz
ns
ns
48
kHz
ns
ns
48
-
kHz
%
48
kHz
ns
48
kHz
ns
1/8fs
1/16fs
2013/06
- 11 -
[AK5730]
Parameter
Symbol
Audio Interface Timing (Slave mode)
Stereo mode (TDM1/0 bit = “00”)
BICK Period
tBCK
BICK Pulse Width Low
tBCKL
Pulse Width High
tBCKH
LRCK Edge to BICK “↑”
(Note 18)
tLRB
BICK “↑” to LRCK Edge
(Note 18)
tBLR
LRCK Edge to SDTO(MSB)(Except I2S mode)
tLRS
BICK “↓” to SDTO
tBSD
TDM256 mode (TDM1/0 bit = “01”)
BICK Period
tBCK
BICK Pulse Width Low
tBCKL
Pulse Width High
tBCKH
LRCK Edge to BICK “↑”
(Note 18)
tLRB
BICK “↑” to LRCK Edge
(Note 18)
tBLR
SDTO Setup time BICK “↑”
tBSS
SDTO Hold time BICK “↑”
tBSH
TDMI Hold Time
tSDH
TDMI Setup Time
tSDS
TDM512 mode (TDM1/0 bit = “10”)
BICK Period
tBCK
BICK Pulse Width Low
tBCKL
Pulse Width High
tBCKH
LRCK Edge to BICK “↑”
(Note 18)
tLRB
BICK “↑” to LRCK Edge
(Note 18)
tBLR
SDTO Setup time BICK “↑”
tBSS
SDTO Hold time BICK “↑”
tBSH
TDMI Hold Time
tSDH
TDMI Setup Time
tSDS
Audio Interface Timing (Master mode)
Stereo mode (TDM1/0 bit = “00”)
BICK Frequency
fBCK
BICK Duty
dBCK
BICK “↓” to LRCK
tMBLR
tBSD
BICK “↓” to SDTO
TDM256 mode (TDM1/0 bit = “01”)
BICK Frequency
fBCK
BICK Duty
dBCK
BICK “↓” to LRCK
tMBLR
tBSS
SDTO Setup time BICK “↑”
tBSH
SDTO Hold time BICK “↑”
tSDH
TDMI Hold Time
tSDS
TDMI Setup Time
TDM512 mode (TDM1/0 bit = “10”)
BICK Frequency
fBCK
BICK Duty
dBCK
BICK “↓” to LRCK
tMBLR
tBSS
SDTO Setup time BICK “↑”
tBSH
SDTO Hold time BICK “↑”
tSDH
TDMI Hold Time
tSDS
TDMI Setup Time
Note 18. BICK rising edge must not occur at the same time as LRCK edge.
Rev 0.8
min
typ
max
Unit
20
20
ns
ns
ns
ns
ns
ns
ns
320
128
128
20
20
80
32
32
20
20
12
10
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
16
16
10
10
6
5
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
−20
−20
64fs
50
-
20
20
Hz
%
ns
ns
-20
12
10
20
20
256fs
50
20
20
-
Hz
%
ns
ns
ns
ns
ns
10
-
Hz
%
ns
ns
ns
ns
-10
6
5
10
10
512fs
50
-
2013/06
- 12 -
[AK5730]
Parameter
Symbol
min
typ
Control Interface Timing (4-wire serial mode)
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
CCLK “↑” to CSN “↑”
tCSH
50
CDTO Delay
tDCD
CSN “↑” to CDTO Hi-Z
tCCZ
Control Interface Timing (I2C Bus):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
1.3
tBUF
Start Condition Hold Time (prior to first clock pulse)
0.6
tHD:STA
Clock Low Time
1.3
tLOW
Clock High Time
0.6
tHIGH
Setup Time for Repeated Start Condition
0.6
tSU :STA
SDA Hold Time from SCL Falling
(Note 19)
0
tHD :DAT
SDA Setup Time from SCL Rising
0.1
tSU :DAT
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
0.6
tSU:STO
Pulse Width of Spike Noise Suppressed by Input Filter
0
tSP :I2C
Cb
Capacitive load on bus
Power-down & Reset Timing
PDN Pulse Width
(Note 20)
tPD
150
PDN “↑” to SDTO valid (FS1/0bit=“00”) (Note 21)
tPDV
3153
PDN “↑” to SDTO valid (FS1/0bit=“01”) (Note 21)
2098
PDN “↑” to SDTO valid (FS1/0bit=“10”) (Note 21)
1729
Pulse Width of Spike Noise Suppressed by Input Filter
tSP :PD
0
Note 19. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 20. The AK5730 can be reset by setting the PDN pin to “L” upon power-up.
Note 21. These cycles are the numbers of LRCK rising from the PDN pin rising.
Note 22. I2C-bus is a trademark of NXP B.V.
Rev 0.8
max
Unit
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
400
1.0
0.3
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
20
ns
1/fs
1/fs
1/fs
ns
2013/06
- 13 -
[AK5730]
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tdLRKH
tdLRKL
Duty
= tdLRKH (or tdLRKL) x fs x 100
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 2. Clock Timing (TDM1/0 bits = “00” & Slave mode)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 3. Clock Timing (Except TDM1/0 bits = “00” & Slave mode)
Rev 0.8
2013/06
- 14 -
[AK5730]
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
LRCK
50%DVDD
tdLRKH
tdLRKL
dLRK
= tdLRKH (or tdLRKL) x fs x 100
1/fBCK
50%DVDD
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 4. Clock Timing (TDM1/0 bits = “00” & Master mode)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
50%DVDD
LRCK
tLRH
1/fBCK
50%DVDD
BICK
tdBCKH
tdBCKL
dBCK
= tdBCKH (or tdBCKL) x fs x 100
Figure 5. Clock Timing (Except TDM1/0 bits = “00” & Master mode)
Rev 0.8
2013/06
- 15 -
[AK5730]
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tLRS
tBSD
50%DVDD
SDTO
Figure 6. Audio Interface Timing (TDM1/0 bits = “00” & Slave mode)
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tBSS
tBSH
SDTO
50%DVDD
tSDS
tSDH
VIH
TDMI
VIL
Figure 7. Audio Interface Timing (Except TDM1/0 bits = “00” & Slave mode)
Rev 0.8
2013/06
- 16 -
[AK5730]
LRCK
50%DVDD
tMBLR
50%DVDD
BICK
tBSD
50%DVDD
SDTO
Figure 8. Audio Interface Timing (TDM1/0 bits = “00” & Master mode)
LRCK
50%DVDD
tMBLR
50%DVDD
BICK
tBSS
tBSH
50%DVDD
SDTO
tSDS
tSDH
VIH
TDMI
VIL
Figure 9. Audio Interface Timing (Except TDM1/0 bits = “00” & Master mode)
Rev 0.8
2013/06
- 17 -
[AK5730]
VIH
CSN
VIL
tCSS
tCCK
tCCKL tCCKH
VIH
CCLK
VIL
tCDH
tCDS
CDTI
C1
C0
VIH
A4
R/W
VIL
Hi-Z
CDTO
Figure 10. WRITE/READ command input timing (4-wire serial mode)
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
CDTI
VIL
D3
D2
D1
VIH
D0
VIL
Hi-Z
CDTO
Figure 11. WRITE data input timing (4-wire serial mode)
VIH
CSN
VIL
VIH
CCLK
VIL
CDTI
A1
VIH
A0
VIL
tDCD
CDTO
Hi-Z
D7
D6
D5
50%DVDD
Figure 12. READ data output timing 1 (4-wire serial mode)
Rev 0.8
2013/06
- 18 -
[AK5730]
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
VIL
tCCZ
CDTO
D3
D2
D1
50%DVDD
D0
Figure 13. READ data output timing 2 (4-wire serial mode)
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
Figure 14. I2C Bus Timing
tPD
VIH
PDN
VIL
tPDV
SDTO
50%DVDD
Figure 15. Power-down & Reset Timing
Rev 0.8
2013/06
- 19 -
[AK5730]
OPERATION OVERVIEW
■ System Clock
The MSN pin selects either master or slave mode. MSN pin = “H” selects master mode and “L” selects slave mode.
In slave mode, MCLK, LRCK(fs) and BICK are required to operate the AK5730. MCLK should be synchronized with
LRCK but the phase is not critical. Table 1 shows the relationship between the sampling rate and the frequencies of
MCLK and BICK. The sampling speed is set by FS0 and FS1 bits (Table 3).
After exiting reset at power-up in slave mode, the AK5730 is in power-down mode until MCLK and LRCK and BICK are
input.
In master mode, only MCLK is required. Master Clock Input Frequency should be set with the CKS1-0 bits (Table 2), and
the sampling speed should be set by the FS1-0 bits. After exiting reset at power-up in slave mode, the AK5730 is in
power-down mode until MCLK are input.
LRCK
fs
8kHz
32kHz
44.1kHz
48kHz
256fs
2.048
8.192
11.2896
12.288
MCLK (MHz)
384fs
3.072
12.288
16.9344
18.432
512fs
4.096
16.384
22.5792
24.576
BICK (MHz)
64fs
0.512
2.048
2.8224
3.072
Table 1. System Clock Example
CKS1 bit
CKS0 bit
Clock Speed
0
0
256fs
0
1
384fs
1
0
512fs
(default)
1
1
(reserved)
Table 2. Master Clock Control (Master Mode)
FS1 bit
0
0
1
1
FS0 bit
Sampling Rate
0
24kHz – 48kHz
1
12kHz – 24kHz
0
8kHz – 12kHz
1
8kHz – 12kHz (reserved)
Table 3. Sampling Rate (fs)
Rev 0.8
(default)
2013/06
- 20 -
[AK5730]
■ Master Mode and Slave Mode
Master Mode and Slave Mode are selected by setting the M/S pin. (“H”=Master Mode, “L”=Slave Mode)
In master mode (M/S pin= “H”), LRCK pin and BICK pin are output pins.
In slave mode (M/S pin= “L”), LRCK pin and BICK pins are input pins
PLL1/0 bits control the PLL modes which generates the internal MCLK from BICK.
Master clock should be input the 512fs in Master mode and BICK 512fs Output PLL mode. (PLL1/0 bits = “11”)
PDN
L
L
H
H
H
H
H
M/S pin
L
H
L
L
L
L
H
PLL1 bit
*
*
0
0
1
1
*
PLL0 bit
*
*
0
1
0
1
*
LRCK pin
Input
“L” Output
Input
Input
Input
Input
Output
BICK pin
Input
“L” Output
Input (PLL off)
64fs Input (PLL mode)
256fs Input (PLL mode)
512fs Input (PLL mode)
Output
(*: Don’t Care)
Table 4. LRCK and BICK pins
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz
and scales with the sampling rate (fs).
HPF are controlled by the HPE4-1 bits.
HPE1 bit
L
H
HPF
ADC1 HPF off
ADC1 HPF on
(default)
HPE2 bit
L
H
HPF
ADC2 HPF off
ADC2 HPF on
(default)
HPE3 bit
L
H
HPF
ADC3 HPF off
ADC3 HPF on
(default)
HPE4 bit
L
H
HPF
ADC4 HPF off
ADC4 HPF on
(default)
Table 5. HPF Operation Setting
Rev 0.8
2013/06
- 21 -
[AK5730]
■ Audio Serial Interface Format
Eight types of the date formats are available and selected by setting the DIF bit and the TDM1-0 bits. In all modes, the
serial data is MSB first, 2`s complement format. LRCK and BICK are output in master mode, input in slave mode.
Mode
0
1
2
3
4
5
-
DIF bit
0
0
0
0
1
1
1
1
TDM1 bit
0
0
1
1
0
0
1
1
TDM0 bit
0
1
0
1
0
1
0
1
BICK
64fs
256fs
512fs
64fs
256fs
512fs
-
Data Format
Stereo Mode (IIS)
TDM256 Mode(IIS)
TDM512 Mode(IIS)
(Reserved)
Stereo Mode (Left Justified)
TDM256 Mode (Left Justified)
TDM512 Mode (Left Justified)
(Reserved)
(default)
Table 6. TDM Mode Setting
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO1(o)
23 22
2
1
0
23:MSB, 0:LSB
SDTO2(o)
23 22
2
23 22
2
1
Data 1
1
Data 2
0
23:MSB, 0:LSB
0
23 22
2
Data 3
1
0
Data 4
Don’t Care
TDMI(i)
Figure 16. Mode 0 Timing (Stereo Mode (IIS))
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (O)
*
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
SDTO2 (O)
TDMI (I)
*
23
0
23
0
23
0
23
0
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
23
(*: Optional)
Figure 17. Mode1 Timing (TDM256 Mode (IIS))
Rev 0.8
2013/06
- 22 -
[AK5730]
512BICK
LRCK(Master)
LRCK(Slave)
BICK(512fs)
*
SDTO1(o)
23
0
23
0
23
0
23
23
0
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
SDTO2(o)
TDM1(i)
*
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
(*: Optional)
Figure 18. Mode2 Timing (TDM512 Mode (IIS))
LRCK
0
1
2
3
22
23
24
25
29
30
31
0
1
2
3
22
23
24
25
29
30
31
0
1
BICK(64fs)
SDTO(o)
23 22
2
1
23:MSB, 0:LSB
SDTO2(o)
23 22
2
0
23 22
2
1
Data 1
1
23:MSB, 0:LSB
0
Data 2
0
23 22
2
Data 3
1
0
Data 4
Don’t Care
TDMI(i)
Figure 19. Mode3 Timing (Stereo Mode (Left Justified))
256 BICK
LRCK (Master)
LRCK (Slave)
BICK (256fs)
SDTO1 (o)
*
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
SDTO2 (o)
TDMI (i) *
23
0
23
0
23
0
23
0
Data 5
Data 6
Data 7
Data 8
32 BICK
32 BICK
32 BICK
32 BICK
23
Figure 20. Mode4 Timing (TDM256 Mode (Left Justified))
Rev 0.8
2013/06
- 23 -
[AK5730]
512BICK
LRCK(Master)
LRCK(Slave)
BICK(512fs)
*
SDTO1(o)
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
SDTO2(o)
TDM1(i) *
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
0
23
Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK 32 BICK
(*: Optional)
Figure 21. Mode5 Timing (TDM512 Mode (Left Justified))
Rev 0.8
2013/06
- 24 -
[AK5730]
■ TDM Cascade Mode
(1)TDM256mode
Two devices can be connected in cascades at the TDM256 mode. In Figure 22, the SDTO1 pin of device #1 is connected
with the TDMI pin of device #2. It is possible to output 8channel TDM data from the SDTO1 pin of device # 2 as shown
in Figure 17 and Figure 20.
AK5730 #1
256fs or 512fs
MCLK
48kHz
LRCK
256fs
BICK
TDMI
GND
SDTO1
AK5730 #2
MCLK
TDMI
LRCK
BICK
8ch TDM
SDTO1
Figure 22. Cascade TDM Connection Diagram (TDM256 mode)
(2)TDM512mode
Four or less devices can be connected in cascades at the TDM512 mode. In Figure 23, the SDTO1 pin of device #1-3 is
connected with the TDMI pin of device #2-4. It is possible to output 16 channel TDM data from the SDTO1 pin of device
#4 as shown in Figure 18 and Figure 21.
AK5730 #1
256fs or 512fs
MCLK
48kHz
LRCK
512fs
BICK
TDMI
GND
SDTO1
AK5730 #2
MCLK
TDMI
LRCK
BICK
SDTO1
AK5730 #3
MCLK
TDMI
LRCK
BICK
SDTO1
AK5730 #4
MCLK
TDMI
LRCK
BICK
SDTO1
16ch TDM
Figure 23. Cascade TDM Connection Diagram (TDM512 mode)
Rev 0.8
2013/06
- 25 -
[AK5730]
■ System Reset
The AK5730 should be reset once by bringing the PDN pin = “L” upon power-up. The AK5730 is powered up and the
internal timing starts clocking by LRCK “↑” after exiting the power down state of reference voltage (such as VCOM) by
MCLK. In slave mode, the AK5730 is in power-down mode until MCLK and LRCK are input. In master mode, the
AK5730 is in power-down mode until MCLK is input. Following all clock inputs, set RSTN bit to “1” after setting
microphone bias voltage (MBS3-0 bits).
■ Digital Attenuator
The AK5730 has a channel-independent digital attenuator (256 levels, 0.5dB step). Attenuation level of each channel can
be set by each the ATT7-0 bits (Table 7).
ATT7-0
00H
01H
:
FEH
FFH
Attenuation Level
+12dB
+11.5dB
:
0dB(default)
-0.5dB
-1.0dB
:
-115.0dB
MUTE (-∞)
Table 7. Attenuation level of digital attenuator
Transition time between set values of ATT7-0 bits can be selected by ATS1-0 bits (Table 8). Transition between set
values is the soft transition in Mode1/2/3 eliminating a switching noise in the transition.
Mode
0
1
2
3
ATS1
0
0
1
1
ATS0
0
1
0
1
ATT speed
3712/fs
928/fs
1856/fs
7424/fs
(default)
Table 8. Transition Time between Set Values of ATT7-0 bits
The transition between set values is a soft transition of 3712 levels in mode 0. It takes 3712/fs (77.3ms@fs=48kHz) from
00H(0dB) to FFH(MUTE). If the PDN pin goes to “L”, the ATTs are initialized to 00H. The ATTs also become 00H
when RSTN bit = “0”, and fade to their current value when RSTN bit returns to “1”.
Rev 0.8
2013/06
- 26 -
[AK5730]
■ Analog Input Mode
The AK5730 has 4 Analog Input modes. Analog Input mode is controlled by LIN*1-0 bits. The input mode is fixed by
each set. The AC signal is input from IN*P/N, and the DC signal is input from INM*P/N. Except for Microphone Input
mode, the input voltage of IN*P/N(=1.65Vrms (Typ.), Differential) should be adjusted with external resistors. As for the
accuracy of external resistance, 0.1% is required for CMRR.
The input voltage of INM*P/N(=AVDD) should be adjusted with external resistors. Fault conditions are calculated
digitally, so the value of external resistance is fixed to 7:3. The input voltage of INM*P/N becomes 30% of VDC+/-. As
for the accuracy of external resistance, 0.1% is required for the accuracy of SAR.
The full scale of SAR is normalized to 11V (@AVDD=3.3V) for calculations of Fault Condition detection.
(A) Microphone Input Mode (LIN*1-0 bits = “00”)
The microphones are connected in a fully balanced manner. A separate cable shield for each microphone may be
connected to chassis ground. In this use case, a gain correction of 9.5dB by GAIN* bit = “1” is available.
Parameter
Mic Impedance
Mic Audio Output
Interchannel Isolation(max) of
Microphone inputs
Mic Phantom Voltage(Vbias)
Mic Supply Current
Resistors (symmetrical)
Specification
1 - 2kohm, 10kohm(max)
10...100mVrms, 1.75Vrms(max)
70dB
Remarks
5V - 9V
0.1 - 10mA
depending on type of microphone
per microphone
depending on type of microphone
200 - 10k
Table 9 Specification(Microphone Input mode)
Maximum Interchannel Isolation of Microphone inputs is 70dB.The isolation depends on MPWR common impedance.
In Figure 24, the microphone impedance and the microphone bias resistance is 2k ohm and MPWR voltage is 8.0V. At
this time, MPWR common impedance should be 0.2 ohms or less.
MPWR
+8.0V
max: 0.2ohm
2kohm
1kHz Sin Wave
100mVpp
2kohm
Isolation measured
AK5730
2kohm(Mic)
2kohm
2kohm(Mic)
2kohm
Figure 24. Interchannel Isolation of Microphone Inputs
Rev 0.8
2013/06
- 27 -
[AK5730]
Different types of microphones can be connected at the same time, with the same phantom voltage.
Mic
Bias,
CP
Mic
IN*+
IN*-
Figure 25. Microphone Input Mode(IN*+/- pins)
For Fault Conditions, refer to Table 10 and Figure 26.
Fault Conditions
Conditions
Positive/Negative input shorted to VBAT
VDC+/- ≥Vbias + Vth
Positive/Negative input shorted to GND
VDC+/- ≤ Vth
Pos. and neg. inputs shorted
|VDC+ - VDC-| ≤ Vth
Positive input open
Vbias - Vth ≤ VDC+ ≤ Vbias + Vth
Negative input open
VDC+/- ≤ Vth
Note. It is not possible to distinguish “Positive/Negative input shorted to GND” and “Negative input open”.
Vth: Error Monitor Threshold Voltage. Vth is set by Table 18.
Table 10 Fault Conditions (Microphone Input Mode)
Vbias
Mic
Bias,
CP
R1
VDC+
Mic
INM*P
INM*N
R2
VDC-
Figure 26. Microphone Input Mode (IN*MP/N pins)
Rev 0.8
2013/06
- 28 -
[AK5730]
(B)LINE and Phone Input mode (LIN*1-0 bits = “01”)
The stereo line input is a quasi-differential input, R and L share a common return. Line return, phone return and head unit
ground may be isolated from each other. Combinations of two stereo line inputs, one stereo line and one stereo phone
inputs are possible. Any combination of inputs shown left may be connected in the applications.
Parameter
Stereo Line Input Voltage
Phone Input Voltage
Specification
Remarks
1 - 3V RMS
(depending on customer)
0.1 - 3V RMS
(depending on customer)
Table 11 Specification (LINE and Phone Input mode)
LINE or Phone
R2
Mic
Bias,
CP
R1
IN*P
AC
IN*N
R2
Figure 27. LINE and Phone Input Mode(IN*P/N pins)
For Fault Conditions, refer to Table 12 and Figure 28. The “Pos. and neg. inputs shorted State (R2/(2R1+R2)) * Vbias” is
detected based on SAR Threshold A(THA12-01 bits).
The threshold A is a 12bit straight binary code which the full scale is 11V.
Fault Conditions
Positive/Negative input shorted to VBAT
Positive/Negative input shorted to GND
Pos. and neg. inputs shorted
Conditions
VDC+/- ≥ Vbias + Vth
VDC+/- ≤ Vth
R2/(2R1+R2) * Vbias –Vth ≤ VDC+ ≈
VDC- ≤ R2/(2R1+R2) * Vbias + Vth
Positive input open
Vbias - Vth ≤ VDC+ ≤ Vbias + Vth
Negative input open
VDC+/- ≤ Vth
Note. It is not possible to distinguish “Positive/Negative input shorted to GND” and “Negative input open”.
Note. The “Pos. and neg. inputs shorted” is a condition that occurs when there is no input signal, and DC voltage is not
supplied by the input signal.
Table 12 Fault Conditions (LINE and Phone Input Mode)
LINE or Phone
R2
Vbias
Mic
Bias,
CP
R1
VDC+
INM*P
AC
INM*N
VDC-
Figure 28. LINE and Phone Input Mode (IN*MP/N pins)
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[AK5730]
(C) Booster Input mode (LIN*1-0 bits = “10”)
The booster inputs are directly driven by a standard automotive power amp, either by a class AB, a class SB (I) or even by
a class D amplifier. The connection is made in a fully balanced manner. In case of using a class SB (I) amplifier, the input
voltage may contain common mode signal inside the audio bandwidth due to switching from bridge to single ended mode
and vice versa. Booster inputs may share a Quad-ADC with any other input type (line, phone and microphone).
Parameter
Input voltage typ.
Input voltage max.
Specification
Remarks
10.0V RMS
@ battery voltage <14.4V
11.7V RMS
@ battery voltage =16.5V
Table 13 Specification (Booster Input mode)
Power Amp
Mic
Bias,
CP
VBAT
R1
IN*P
R3
AMP
IN*N
R2
Figure 29. Booster Input mode (IN*P/N pins)
Diagnostic functions are performed by the external amplifier. A simple check can be made, whether the input is connected
or not. Input is connected to amp output: VDC+ = VDC- = VBAT / 2. Refer to Note 14 and Figure 30 about Fault
Conditions. The “Input open State ((R2+R3)/(R1+R2+R3) * Vbias) and (R2/(R1+R2+R3) * Vbias)” are detected based
on SAR threshold B and C (THB12-01 bits, THC12-01 bits). The threshold B and C are 12bit straight binary codes, which
the full scale is 11V (Typ.).
Fault Conditions
Conditions
Positive input open
(R2+R3)/(R1+R2+R3) * Vbias –Vth ≤ VDC+ ≤ (R2+R3)/(R1+R2+R3) * Vbias +Vth
Negative input open
R2/(R1+R2+R3) * Vbias – Vth ≤ VDC- ≤ R2/(R1+R2+R3) * Vbias + Vth
Note. Positive/Negative input open conditions are statuses when there is no input signal and DC voltage is not supplied by
the input signal.
Table 14 Fault Conditions (Booster Input mode)
Power Amp
Vbias
Mic
Bias,
CP
VBAT
R1
INM*P
AMP
R3
INM*N
R2
Figure 30. Booster Input Mode (INM*P/N pins)
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[AK5730]
(D) Internal unbalanced sources mode (LIN*1-0 bits = “11”)
Max. unbalanced input voltage < 2V RMS
A digital gain correction of 9.5dB can be applied to unbalanced inputs. Unbalanced input should be possible on either
positive and negative inputs. In this mode, No diagnosis is performed for internal connections.
(E) VBATM pin
The input voltage of the VBATM pin should be adjusted with external resistors as below.
The input voltage range is 0 to AVDD. When the input is AVDD voltage (=3.3V typ.), the SAR outputs Full-scale
data(typ.)
ex.) AVDD=3.3V
R1=2 MΩ, R2=360kΩ
When Battery voltage is 21.6V, the voltage at VBATM pin becomes 3.3V and the SAR outputs Full-scale data.
Battery = 21.6V → Full-scale
Battery
R1
VBATM
R2
Figure 31. VBATM pin
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[AK5730]
■ Error Detection
The following seven events cause the INT pin to show the status of the interrupt condition. When the PDN pin is “L”, the
INT pin goes to “Hi-z”.
1.
2.
3.
4.
5.
6.
7.
OPEN: Open circuit
SHTD: Short between the positive and negative mic input
SHTG: Short to ground
SHTV: Short to VBAT
OVCR1: Mic Bias Over-current(90mA(typ)) of booster
OVCR2: Charge Pump Over-current(600mA(typ)) of booster
OVTP: Over-temp(165 degrees(typ)) of booster
The INT pin outputs an ORed signal based on the above seven interrupt events. When error information is masked, the
interrupt event does not affect the operation of the INT pin. This pin should be connected to DVDD (typ. 3.3V) or lower
voltage via a 10kohm resistor.
Once the INT pin goes to “L”, it remains “L” until writing INTR bit = “1”. After writing “1” to INTR bit, it automatically
returns to “0”.
OPEN, SHTD, SHTG, SHTV, OVCR and OVTP bits in Address 07-0BH indicate the interrupt status events above in real
time. Once they go to “1”, it stays “1” until writing INTR bit = “1”.
When MSHTV*, MSHTG*, MSHTD*, MOPEN* (*: 1-4) bits (Address=0C-0FH) go to "1", error information at
SHTV*, SHTG*, SHTD*, OPEN* bits can not be masked but does not affect the operation of the INT pin. (Table 16)
When over-temperature (OVTP) or over-current (OVCR1, OVCR2) is detected, the AK5730 disable the block listed on
Table 15. Unless the error is due to over-temperature or over-current, error detection is restarted by writing INTR bit =
“1”. When the error is due to over-temperature or over-current, restart the AK5730 by the PDN pin or RSTN bit.
INT detection
CPUIF
REFBLK
PLL
VCMIREF
CP
MIC
ADC
SARIBUF
SAR
MICDIAGS
SAR ERR
A
A
A
A
A
A
A
A
A
A
TSD
Overtemp.
A
A
A
A
L
A
×
A
A
A
A
A
A
A
L
A
×
A
A
A
A
A
A
A
×
×
×
×
×
×
A
A
A
A
L
A
×
×
×
×
MIC
overcurrent +
MIC
overcurrent -
CP
overcurrent
A: Active Block, L: Active in Low Power Mode, ×: Power Down
Table 15. Block Conditions on Error Detection
Unmasked Event
Not detected
DETECTED
Masked Event
Not detected
DETECTED
INT pin
Hi-Z
L
(goes “Hi-Z” after writing INTR bit =
“1”)
Table 16. Error Handling in Serial Control Mode
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[AK5730]
RSTN
(4)
Cycle
Error Event
Normal
Fault
Normal
(1)
Monitor Bit
(2)
INT
READ(uP)
Err or Handling
write “1”
INTR
(3)
Figure 32 Error Detection timing
Notes:
(1) Execute error detection from 1ch to 8ch (IN1P~IN4P, IN1N~IN4N pins) in this order.
(2) After the error detection from 1ch to 8ch, the error detection results are ORed and reflected to INT pins. Indication
of INT pins can be masked by MSHTV*, MSHTG*, MSHTD*, MOPEN* (*: 1-4) bits (Address= 0C-0FH).
(3) Error monitor registers are reset by setting INTR bit to “1” after all error conditions are removed.
(4) When the detected error is due to over-temperature or over-current, restart the AK5730 by the PDN pin or RSTN
bit.
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[AK5730]
PDN pin ="L" to "H"
Initialize
Register Setting
Write RSTN bit = “1”
No
INT pin ="L"
Yes
Read “07H” to “0BH”
“ OVT P” ”OVCR2”
No
”O VCR 1” bit =”1”
Yes
(Error Handling)
(Error Handling)
INTR
Figure 33 Error Handling Sequence Example
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[AK5730]
■ Power Up/Down Sequence
The each block of the AK5730 is placed in power-down mode by bringing the PDN pin to “L” and both digital filters are
reset at the same time. The PDN pin =“L” also resets the control registers to their default values. In power-down mode, the
SDTO pin goes to “L”. This reset must always be executed after power-up.
In slave mode, after exiting reset at power-up and etc., the ADC starts operation from the rising edge of LRCK after
MLCK inputs. The AK5730 is in power-down mode until MCLK and LRCK and BICK are input.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 1041/fs cycles of LRCK clock. Figure 34 shows the sequences of the power-down and the
power-up.
When RSTN bit = “0”, all circuits are powered-down but the internal register are not initialized.
Power
(1) (2)
PDN pin
(3)
PLL
Normal Operation
(6)
VDD
VP pin
VDD
1.67 x VDD
(9)
(1.67 x VDD) x2
2VP pin
VDD
VDD
(9)
VDD
MICREF pin
MICPWR pin
0V
(4)
0V
Normal Operation
(7) 1041/fs
ADC Internal
State
Init Cycle
Power-down
Normal Operation
(8)
GD
ADC In
(Analog)
ADC Out
(Digital)
Clock In
“0”data
(5)
GD
“0”data
Don’t care
Don’t care
MCLK,LRCK,BICK
Figure 34 Power-up/down Sequence Example
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[AK5730]
Notes:
(1) The PDN pin should be set to “H” after all powers (DVDD, AVDD) are supplied. The AK5730 requires 150ns or
longer “L” period for a certain reset. Supply the power during the PDN pin = “L”.
(2) Set RSTN bit to “1” after setting microphone bias voltage (MBS3-0 bits).
(3) Power-on the PLL circuit:(PLL mode)
PLL1-0 bits = “01” or “10” or “11” & BICK is input.
PLL is locked within 1 - 2ms
(4) Power-on the MICREF circuit:
The CVP1 pin is charged up.
The MICREF pin becomes (1.67 x VDD) x 2 within about 20 - 40ms.
(5) ADC outputs “0” data in power-down state.
(6) Power-on the charge pump circuit1/2:
(Normal mode) PDN pin = “L” → “H”(or PLL is locked) & MCLK, BICK, LRCK is input.(normal mode)
(PLL mode)
PLL is locked.
The CVP1 pin becomes 1.67 x VDD within about 4 - 8ms.
The CVP2 pin becomes (1.67 x VDD) x 2 within about 4 - 8ms.
(7) The analog block of ADC is initialized after exiting the power-down state.
(8) Digital outputs corresponding to analog inputs and analog outputs corresponding to digital inputs have group
delay (GD).
(9) Charge pump circuit power down:
PDN pin = “H” Æ “L”
The CVP1/2 pin becomes VDD according to a flying capacitor and internal resistor. The internal resistor is 50kΩ
(typ). Therefore, when the CVP1/2 pin has a flying capacitor of 2.2µF, the time constant is 110ms (typ).
Rev 0.8
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[AK5730]
■ Serial Control Interface
(1) 4-wire Serial Control Mode (SPI pin = “H”)
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO.
The data on this interface consists of Chip address (1bit, C1 is fixed to “1”), Read/Write (1bit), Register address
(MSB first, 6bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK
and data is clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK,
after a high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a
low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. The PDN pin= “L” resets the registers to
their default values.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
WRITE
C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
CDTI
READ
C1 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
C1:
Chip Address (Fixed to “1”)
R/W:
READ/WRITE (0:READ, 1:WRITE)
A5-A0: Register Address
D7-D0: Control Data
Figure 35. 4-wire Serial Control I/F Timing
(2). I2C bus control mode (SPI pin = “L”)
The AK5730 supports the fast-mode I2C-bus (max: 400kHz).
(2)-1. WRITE Operations
Figure 36 shows the data transfer sequence of the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 42). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant five bits of the slave address are fixed as “00100”. The next bits are CAD1 and CAD0
(device address bit). This bit identifies the specific device on the bus. The hard-wired input pins (CAD1/0 pins) set these
device address bits (Figure 37). If the slave address matches that of the AK5730, the AK5730 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and release the SDA line
(HIGH) during the acknowledge clock pulse (Figure 43). R/W bit = “1” indicates that the read operation is to be executed.
“0” indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK5730. The format is MSB first, and those most
significant 2-bits are fixed to zeros (Figure 38). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 39). The AK5730 generates an acknowledge after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 42).
The AK5730 can perform more than one byte write operation per sequence. After receipt of the third byte the AK5730
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
Rev 0.8
2013/06
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[AK5730]
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 2DH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only be changed when the clock signal on the SCL line is LOW (Figure 44) except for the START and STOP
conditions.
S
T
A
R
T
SDA
S
T
O
P
R/W="0"
Slave
S Address
Sub
Address(n)
Data(n)
A
C
K
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 36. Data Transfer Sequence at The I2C-Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 37. The First Byte
0
0
A5
A4
A3
A2
A1
A0
D2
D1
D0
Figure 38. The Second Byte
D7
D6
D5
D4
D3
Figure 39. Byte Structure after The Second Byte
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[AK5730]
(2)-2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK5730. After transmission of data, the master can read the next
address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word.
After receiving each data packet the internal 6-bit address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds 2DH prior to generating a stop condition, the address
counter will “roll over” to 00H and the data of 00H will be read out.
The AK5730 supports two basic read operations: CURRENT ADDRESS READ and RANDOM ADDRESS READ.
(2)-2-1. CURRENT ADDRESS READ
The AK5730 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation would
access data from the address “n+1”. After receipt of the slave address with R/W bit “1”, the AK5730 generates an
acknowledge, transmits 1-byte of data to the address set by the internal address counter and increments the internal
address counter by 1. If the master does not generate an acknowledge but generates a stop condition instead, the AK5730
ceases transmission.
S
T
A
R
T
SDA
S
T
O
P
R/W="1"
Slave
S Address
Data(n)
Data(n+1)
Data(n+2)
MA
AC
SK
T
E
R
A
C
K
MA
AC
SK
T
E
R
Data(n+x)
MA
AC
SK
T
E
R
MA
AC
SK
T
E
R
P
MN
AA
SC
T
EK
R
Figure 40. CURRENT ADDRESS READ
(2)-2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing a slave address
with the R/W bit =“1”, the master must execute a “dummy” write operation first. The master issues a start request, a slave
address (R/W bit = “0”) and then the register address to read. After the register address is acknowledged, the master
immediately reissues the start request and the slave address with the R/W bit =“1”. The AK5730 then generates an
acknowledge, 1 byte of data and increments the internal address counter by 1. If the master does not generate an
acknowledge but generates a stop condition instead, the AK5730 ceases transmission.
S
T
A
R
T
SDA
S
T
A
R
T
R/W="0"
Sub
Address(n)
Slave
S Address
A
C
K
Slave
S Address
A
C
K
S
T
O
P
R/W="1"
Data(n)
A
C
K
Data(n+1)
MA
AC
S K
T
E
R
Data(n+x)
MA
AC
S
T K
E
R
MA
AC
S
T K
E
R
P
MN
A A
S
TC
E K
R
Figure 41. RANDOM ADDRESS READ
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2013/06
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[AK5730]
SDA
SCL
S
P
start condition
stop condition
Figure 42. START and STOP Conditions
DATA
OUTPUT BY
TRANSMITTER
not acknowledge
DATA
OUTPUT BY
RECEIVER
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 43. Acknowledge on the I2C-Bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 44. Bit Transfer on the I2C-Bus
Rev 0.8
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[AK5730]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
Register Name
General Setting 1
General Setting 2
Input mode
ADC1 Volume Control
ADC2 Volume Control
ADC3 Volume Control
ADC4 Volume Control
Monitor Summary
Monitor ADC1
Monitor ADC2
Monitor ADC3
Monitor ADC4
Mask ADC1
Mask ADC2
Mask ADC3
Mask ADC4
Threshold setting OPEN
Threshold setting SHTD
Threshold setting SHTG
Threshold setting SHTV
INT setting
ADC HPF
SAR Thresh A High byte
SAR Thresh A Low byte
SAR Thresh B High byte
SAR Thresh B Low byte
SAR Thresh C High byte
SAR Thresh C Low byte
SAR IN1+ High byte
SAR IN1+ Low byte
SAR IN1- High byte
SAR IN1- Low byte
SAR IN2+ High byte
SAR IN2+ Low byte
SAR IN2- High byte
SAR IN2- Low byte
SAR IN3+ High byte
SAR IN3+ Low byte
SAR IN3- High byte
SAR IN3- Low byte
SAR IN4+ High byte
SAR IN4+ Low byte
SAR IN4- High byte
SAR IN4- Low byte
SAR VBAT High byte
SAR VBAT Low byte
D7
CKS1
MBS3
LIN41
ATT17
ATT27
ATT37
ATT47
0
0
0
0
0
0
0
0
0
0
0
0
0
STD4
GAIN4
THA12
THA04
THB12
THB04
THC12
THC04
1P12
1P04
1N12
1N04
2P12
2P04
2N12
2N04
3P12
3P04
3N12
3N04
4P12
4P04
4N12
4N04
VB12
VB04
D6
CKS0
MBS2
LIN40
ATT16
ATT26
ATT36
ATT46
0
OVTP
0
0
0
0
0
0
0
0
0
0
0
STD3
GAIN3
THA11
THA03
THB11
THB03
THC11
THC03
1P11
1P03
1N11
1N03
2P11
2P03
2N11
2N03
3P11
3P03
1N11
3N03
4P11
4P03
4N11
4N03
VB11
VB03
D5
ATS1
MBS1
LIN31
ATT15
ATT25
ATT35
ATT45
0
OVCR2
0
0
0
0
0
0
0
0
0
0
0
STD2
GAIN2
THA10
THA02
THB10
THB02
THC10
THC02
1P10
1P02
1N10
1N02
2P10
2P02
2N10
2N02
3P10
3P02
3N10
3N02
4P10
4P02
2N10
4N02
VB10
VB02
D4
ATS0
MBS0
LIN30
ATT14
ATT24
ATT34
ATT44
0
OVCR1
0
0
0
0
0
0
0
0
0
0
0
STD1
GAIN1
THA09
THA01
THB09
THB01
THC09
THC01
1P09
1P01
1P09
1N01
2P09
2P01
2N09
2N01
3P09
3P01
3P09
3N01
4P09
4P01
4N09
4N01
VB09
VB01
D3
DIF
FS1
LIN21
ATT13
ATT23
ATT33
ATT43
ADC4
SHTV1
SHTV2
SHTV3
SHTV4
D2
TDM1
FS0
LIN20
ATT12
ATT22
ATT32
ATT42
ADC3
SHTG1
SHTG2
SHTG3
SHTG4
D1
TDM0
PLL1
LIN11
ATT11
ATT21
ATT31
ATT41
ADC2
SHTD1
SHTD2
SHTD3
SHTD4
D0
RSTN
PLL0
LIN10
ATT10
ATT20
ATT30
ATT40
ADC1
OPEN1
OPEN2
OPEN3
OPEN4
MSHTV1
MSHTV2
MSHTV3
MSHTV4
MSHTG1
MSHTG2
MSHTG3
MSHTG4
MSHTD1
MSHTD2
MSHTD3
MSHTD4
MOPEN1
MOPEN2
MOPEN3
MOPEN4
TOP4
TSD4
TSG4
TSV4
0
HPF4
THA08
0
THB08
0
THC08
0
1P08
0
1N08
0
2P08
0
2N08
0
3P08
0
3N08
0
4P08
0
4N08
0
VB08
0
TOP3
TSD3
TSG3
TSV3
0
HPF3
THA07
0
THB07
0
THC07
0
1P07
0
1N07
0
2P07
0
2N07
0
3P07
0
3N07
0
4P07
0
4N07
0
VB07
0
TOP2
TSD2
TSG2
TSV2
0
HPF2
THA06
0
THB06
0
THC06
0
1P06
0
1N06
0
2P06
0
2N06
0
3P06
0
3N06
0
4P06
0
4N06
0
VB06
0
TOP1
TSD1
TSG1
TSV1
INTR
HPF1
THA05
0
THB05
0
THC05
0
1P05
0
1N05
0
2P05
0
2N05
0
3P05
0
3N05
0
4P05
0
4N05
0
VB05
0
Note: For addresses from 2EH to 3FH, data is not written.
When the PDN pin goes to “L”, all registers are initialized to their default values.
When RSTN bit is set to “0”, the internal timing is reset, but registers are not initialized to their default values.
Rev 0.8
2013/06
- 41 -
[AK5730]
■ Register Definitions
Addr
00H
Register Name
General Setting
R/W
Default
D7
CKS1
R/W
1
D6
CKS0
R/W
0
D5
ATS1
R/W
0
D4
ATS0
R/W
0
D3
DIF
R/W
0
D2
TDM1
R/W
0
D1
TDM0
R/W
0
D0
RSTN
R/W
0
D4
MBS0
R/W
0
D3
FS1
R/W
0
D2
FS0
R/W
0
D1
PLL1
R/W
0
D0
PLL0
R/W
0
RSTN: Internal timing reset
0: Reset. Registers are not initialized. (default)
1: Normal operation
TDM1-0: TDM Mode Select (Table 6)
00: Normal mode. (default)
01: TDM256 mode
10: TDM512 mode
11: reserved
DIF: Data format setting (Table 6)
0: IIS. (default)
1: Left Justified
ATS1-0: Digital attenuator transition time setting (Table 8)
Default: “00”, mode 0
CKS1-0: Master Clock setting in Master mode.
Refer to Table 2
Addr
01H
Register Name
General Setting 2
R/W
Default
D7
MBS3
R/W
0
D6
MBS2
R/W
0
D5
MBS1
R/W
0
PLL1-0: PLL mode setting (Note 4)
00: Normal mode. PLL off. (default)
01: PLL mode (BICK=64fs)
10: PLL mode (BICK=256fs)
11: PLL mode (BICK=512fs)
FS1-0: Sampling Frequency setting (Table 3)
00: 24k-48kHz (default)
01: 12k-24kHz
10: 8k-12kHz
11: (Reserved)
Rev 0.8
2013/06
- 42 -
[AK5730]
MBS3-0: Mic bias voltage setting
MBS3-0
Bias Voltage
00H
5V
(default)
01H
5.5V
02H
6V
03H
6.5V
04H
7V
05H
7.5V
06H
8V
07H
8.5V
08H
9V
09H
Hi-Z
0AH-0FH
(reserved)
Table 17. MIC Bias Voltage Setting
Addr
02H
Register Name
Input mode
R/W
Default
D7
LIN41
R/W
0
D6
LIN40
R/W
0
D5
LIN31
R/W
0
D4
LIN30
R/W
0
D3
LIN21
R/W
0
D2
LIN20
R/W
0
D1
LIN11
R/W
0
D0
LIN10
R/W
0
LIN*1-*0: Mic/Line select for each ADC*
00: Mic mode (Default)
01: LINE and Phone mode
10: Booster input mode
11: Internal unbalanced sources mode. No diagnosis is performed for internal connections.
Addr
03H
04H
05H
06H
Register Name
ADC1 Volume Control
ADC2 Volume Control
ADC3 Volume Control
ADC4 Volume Control
R/W
Default
D7
ATT17
ATT27
ATT37
ATT47
R/W
0
D6
ATT16
ATT26
ATT36
ATT46
R/W
0
D5
ATT15
ATT25
ATT35
ATT45
R/W
0
D4
ATT14
ATT24
ATT34
ATT44
R/W
1
D3
ATT13
ATT23
ATT33
ATT43
R/W
1
D2
ATT12
ATT22
ATT32
ATT42
R/W
0
D1
ATT11
ATT21
ATT31
ATT41
R/W
0
D0
ATT10
ATT20
ATT30
ATT40
R/W
0
ATT*7-*0: ADC* Volume Control
refer to Table 7
Addr
07H
Register Name
Monitor Summary
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
ADC4
ADC3
ADC2
ADC1
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
ADC4-1: Error Monitor for each ADC
0: No error detected.
1: Error detected. set INT pin “Hi-z”. Returns to “L” when INTR bit = “1”.
Rev 0.8
2013/06
- 43 -
[AK5730]
Addr
08H
09H
0AH
0BH
Register Name
Monitor ADC1
Monitor ADC2
Monitor ADC3
Monitor ADC4
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
OVTP1
0
0
0
OVCR1
0
0
0
SHTV1
SHTV2
SHTV3
SHTV4
SHTG1
SHTG2
SHTG3
SHTG4
SHTD1
SHTD2
SHTD3
SHTD4
OPEN1
OPEN2
OPEN3
OPEN4
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
Error Monitor.
0: No error detected.
1: Error detected. Set ADCx bit “1” if unmasked.
Addr
0CH
0DH
0EH
0FH
Register Name
Mask ADC1
Mask ADC2
Mask ADC3
Mask ADC4
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSHTV1
MSHTG1
MSHTD1
MOPEN1
MSHTV2
MSHTG2
MSHTD2
MOPEN2
MSHTV3
MSHTG3
MSHTD3
MOPEN3
MSHTV4
MSHTG4
MSHTD4
MOPEN4
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
D7
0
0
0
0
RD
0
D6
0
0
0
0
RD
0
D5
0
0
0
0
RD
0
D4
0
0
0
0
RD
0
D3
TOP3
TSD3
TSG3
TSV3
R/W
0
D2
TOP2
TSD2
TSG2
TSV2
R/W
0
D1
TOP1
TSD1
TSG1
TSV1
R/W
1
D0
TOP0
TSD0
TSG0
TSV0
R/W
0
Error Monitor Mask.
0: No mask.
1: Mask error.
Addr
10H
11H
12H
13H
Register Name
Threshold setting OPEN
Threshold setting SHTD
Threshold setting SHTG
Threshold setting SHTV
R/W
Default
Error Monitor Threshold Setting
Threshold Voltage is proportional to AVDD voltage. This value is set in digital code.
The threshold voltage is a 12bit straight binary code which the full scale is AVDD/3 (11V@AVDD=3.3V). The
monitored voltage is multiplied by 0.3 by an external resistor and input to the voltage monitoring pin. Therefore, the
threshold voltage range is from +100mV/3(=+30mV) to +900mV/3(=+300mV) at the input pin.
bit3-0
Threshold Voltage
00H
+100mV
01H
+200mV
02H
+300mV
(default)
03H
+400mV
04H
+500mV
05H
+600mV
06H
+700mV
07H
+800mV
08H
+900mV
09H-0FH
(Reserved)
Table 18. Error Monitor Threshold Setting.
Rev 0.8
2013/06
- 44 -
[AK5730]
Addr
14H
Register Name
INT setting
R/W
Default
D7
STD4
R/W
0
D6
STD3
R/W
0
D5
STD2
R/W
0
D4
STD1
R/W
0
D3
0
RD
0
D2
0
RD
0
D1
1
RD
1
D0
INTR
R/W
0
INTR: INT pin reset
0: Normal operation (default)
1: Reset. Error Monitor Registers(07-0BH) are initialized.
STD1-4: ADC1-4 Mode setting
0: Differential mode(Default)
1: Single-ended mode.
When STD* bit =”1”, Single-ended IN*P pin, IN*N pin must be connected to signal common.
Addr
15H
Register Name
ADC HPF
R/W
Default
D7
GAIN4
R/W
0
D6
GAIN3
R/W
0
D5
GAIN2
R/W
0
D4
GAIN1
R/W
0
D3
HPF4
R/W
1
D2
HPF3
R/W
1
D1
HPF2
R/W
1
D0
HPF1
R/W
1
HPF4-1: ADC1-4 HPF on/off (Table 5)
0:ADC* HPF off
1:ADC* HPF on (default)
GAIN4-1: ADC1-4 Differential input Voltage setting
0: 1.68Vrms (default)
1: 0.56Vrms.
When GAIN*bit = “1”, input voltage is amplified threefold (+9.5dB)
In order to adjust full scale range to that of the default condition,
attenuation level of each channel should be set at -9.5dB by the ATT7-0 bits (Table 7).
Rev 0.8
2013/06
- 45 -
[AK5730]
Addr
16H
17H
18H
19H
1AH
1BH
Register Name
SAR Thresh A High byte
SAR Thresh A Low byte
SAR Thresh B High byte
SAR Thresh B Low byte
SAR Thresh C High byte
SAR Thresh C Low byte
R/W
Default
D7
THA12
THA04
THB12
THB04
THC12
THC04
R/W
0
D6
THA11
THA03
THB11
THB03
THC11
THC03
R/W
0
D5
THA10
THA02
THB10
THB02
THC10
THC02
R/W
0
D4
THA09
THA01
THB09
THB01
THC09
THC01
R/W
0
D3
THA08
0
THB08
0
THC08
0
R/W
0
D2
THA07
0
THB07
0
THC07
0
R/W
0
D1
THA06
0
THB06
0
THC06
0
R/W
0
D0
THA05
0
THB05
0
THC05
0
R/W
0
D2
1P07
0
1N07
0
2P07
0
2N07
0
3P07
0
3N07
0
4P07
0
4N07
0
VB07
0
RD
0
D1
1P06
0
1N06
0
2P06
0
2N06
0
3P06
0
3N06
0
4P06
0
4N06
0
VB06
0
RD
0
D0
1P05
0
1N05
0
2P05
0
2N05
0
3P05
0
3N05
0
4P05
0
4N05
0
VB05
0
RD
0
SAR Raw Data Threshold A/B/C.
A: R2/(2R1+R2)*Vbias:Pos. and neg. inputs shorted in LINE and Phone mode.
B: (R2+R3)/(R1+R2+R3)*Vbias: Input open in Booster input mode.
C: R2/(R1+R2+R3)*Vbias: Input open in Booster input mode.
Addr
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
Register Name
SAR IN1+ High byte
SAR IN1+ Low byte
SAR IN1- High byte
SAR IN1- Low byte
SAR IN2+ High byte
SAR IN2+ Low byte
SAR IN2- High byte
SAR IN2- Low byte
SAR IN3+ High byte
SAR IN3+ Low byte
SAR IN3- High byte
SAR IN3- Low byte
SAR IN4+ High byte
SAR IN4+ Low byte
SAR IN4- High byte
SAR IN4- Low byte
SAR VBAT High byte
SAR VBAT Low byte
R/W
Default
D7
1P12
1P04
1N12
1N04
2P12
2P04
2N12
2N04
3P12
3P04
3N12
3N04
4P12
4P04
4N12
4N04
VB12
VB04
RD
0
D6
1P11
1P03
1N11
1N03
2P11
2P03
2N11
2N03
3P11
3P03
1N11
3N03
4P11
4P03
4N11
4N03
VB11
VB03
RD
0
D5
1P10
1P02
1N10
1N02
2P10
2P02
2N10
2N02
3P10
3P02
3N10
3N02
4P10
4P02
2N10
4N02
VB10
VB02
RD
0
D4
1P09
1P01
1P09
1N01
2P09
2P01
2N09
2N01
3P09
3P01
3P09
3N01
4P09
4P01
4N09
4N01
VB09
VB01
RD
0
D3
1P08
0
1N08
0
2P08
0
2N08
0
3P08
0
3N08
0
4P08
0
4N08
0
VB08
0
RD
0
SAR Raw Data Readout.
When reading these registers, always read the high byte first. The low byte is only updated when the high byte is read.
This ensures that the values read from the two registers come from the same 12-bit word.
Rev 0.8
2013/06
- 46 -
[AK5730]
SYSTEM DESIGN
Figure 45 shows the system connection diagram example.
+
2.2u
+
+
Mic
0.1u
MCLK
Amp
DVDD
Mic
Bias,
CP
VSS2
0.1u
VSS1
2.2u
CP1
CN1
CP2
CN2
CVP1
CVP2
10u
AVDD
2.2u
+
10u
SPI
VREF
1u
MCLK
MUX
PLL
2.2u
IN1P
+
IN1N
-
ADC1
HPF,
LPF,
Gain
1u
Line
1u
1u
Battery
IN4P
IN4N
Amp
IIS
TDM Out
+
ADC4
-
INM1P
INM1N
1
2
INM4P
INM4N
VBATM
7
8
9
MUX
SAR
ADC
Mic.
Diags
IIC or SPI
I/F
BICK
LRLK
SDTO1
SDTO2
TDMI
MSN
PDN
Micro
Controller
1u
CAD0/CSN
CAD1/CDTO
SDA/CDTI
SCL/CCLK
INT
10k
DVDD
Figure 45. Typical Connection Diagram
■ Grounding and Power Supply Decoupling
AVDD should be supplied from an analog supply unit with low impedance and be separated from system digital supply.
An electrolytic capacitor of 10μF parallel with a 0.1μF ceramic capacitor should be attached to AVDD, DVDD, VSS1
and VSS2 pin to eliminate the effects of high frequency noise. The 0.1μF ceramic capacitor should be placed as near to
DVDD as possible.
Rev 0.8
2013/06
- 47 -
[AK5730]
PACKAGE(TBD)
48pin LQFP(Unit: mm)
1.70Max
9.0
0.13 ± 0.13
7.0
36
1.40 ± 0.05
24
48
13
7.0
37
1
9.0
25
12
0.09 ∼ 0.20
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
S
0.10 S
0.30 ~ 0.75
■ Package & Lead Frame Material
Package molding compound:
Epoxy
Lead frame material:
Cu
Lead frame surface treatment: Solder (Pb free) plate
Rev 0.8
2013/06
- 48 -
[AK5730]
MARKING
AK5730VQ
XXXXXXX
1
1) Pin #1 indication
2) Marking Code: AK5730VQ
3) Date Code: XXXXXXX (7 digits)
Rev 0.8
2013/06
- 49 -
[AK5730]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application of
AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM
or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants any
license to any intellectual property rights or any other rights of AKM or any third party with respect
to the information in this document. You are fully responsible for use of such information contained
in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR
ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF
SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including
but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices, elevators
and escalators, devices related to electric power, and equipment used in finance-related fields. Do not
use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible
for complying with safety standards and for providing adequate designs and safeguards for your
hardware, software and systems which minimize risk and avoid situations in which a malfunction or
failure of the Product could cause loss of human life, bodily injury or damage to property, including
data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and regulations.
The Products and related technology may not be used for or incorporated into any products or
systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth
in this document shall immediately void any warranty granted by AKM for the Product and shall not
create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
Rev 0.8
2013/06
- 50 -