TI1 CDCVF2509APWG4 3.3-v phase-lock loop clock driver with power down mode Datasheet

CDCVF2509A
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SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH POWER DOWN MODE
Check for Samples: CDCVF2509A
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
Designed to Meet and Exceed PC133
SDRAM Registered DIMM Specification
Rev. 1.1
Spread Spectrum Clock Compatible
Operating Frequency 20 MHz to 175 MHz
Static Phase Error Distribution at 66 MHz to
166 MHz Is ±125 ps
Jitter (cyc - cyc) at 60 MHz to 175 MHz Is
Typ = 65 ps
Advanced Deep Submicron Process
Results in More Than 40% Lower Power
Consumption Versus Current Generation
PC133 Devices
Auto Frequency Detection to Disable
Device (Power-Down Mode)
Available in Plastic 24-Pin TSSOP
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
Separate Output Enable for Each Output
Bank
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
•
•
•
25-Ω On-Chip Series Damping Resistors
No External RC Network Required
Operates at 3.3 V
APPLICATIONS
•
•
•
DRAM Applications
PLL Based Clock Distributors
Non-PLL Clock Buffer
PW PACKAGE
(TOP VIEW)
AGND
VCC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VCC
1G
FBOUT
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
AVCC
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
2G
FBIN
DESCRIPTION
The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is
specifically designed for use with synchronous DRAMs. The CDCVF2509A operates at a 3.3-V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or
disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase
and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. The device
automatically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into
a low state.
Unlike many products containing PLLs, the CDCVF2509A does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
CDCVF2509A
SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
For application information, see application reports High Speed Distribution Design Techniques for
CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking
(SSC) (SCAA039).
The CDCVF2509A is characterized for operation from 0°C to 85°C.
Because it is based on PLL circuitry, the CDCVF2509A requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application of a
fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals.
The PLL can be bypassed by strapping AVCC to ground to use as a simple clock buffer.
FUNCTION TABLE
Inputs
2
Outputs
PLL
AVCC
1G/2G
CLK
1Y/2Y
FBOUT
GND
L
Signal
L
Signal (delayed)
Bypassed / Off
GND
H
Signal
Signal (delayed)
Signal (delayed)
Bypassed / Off
3.3 V (nom)
L
CLK > 1 MHz
L
CLK (in phase)
On
3.3 V (nom)
H
CLK > 1 MHz
CLK (in phase)
CLK (in phase)
On
3.3 V (nom)
X
CLK < 1 MHz
L
L
Off
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SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010
FUNCTIONAL BLOCK DIAGRAM
1G
11
3
4
5
8
9
2G
CLK
AVCC
1Y1
1Y2
1Y3
1Y4
14
24
21
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÁÁÁÁÁÁ
ÎÎÎÎÎÎ
ÁÁÁÁÁÁ
ÎÎÎÎÎÎ
ÁÁÁÁÁÁ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
20
17
PLL
FBIN
1Y0
13
16
12
2Y0
2Y1
2Y2
2Y3
FBOUT
23
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE (PW)
0°C to 85°C
CDCVF2509APWR
CDCVF2509APW
PACKAGE THERMAL RESISTANCE (1)
CDCVF2509APW 24-PIN TSSOP
RqJA
High K
RqJC
High K
(1)
THERMAL AIRFLOW (CFM)
0
150
250
500
88
83
81
77
26.5
UNIT
°C/W
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
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CDCVF2509A
SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010
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Pin Functions
PIN
NAME
NO.
TYPE
DESCRIPTION
CLK
24
I
Clock input. CLK provides the clock signal to be distributed by the CDCVF2509A clock driver. CLK
is used to provide the reference signal to the integrated PLL that generates the clock output signals.
CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit
is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase
lock the feedback signal to its reference signal.
FBIN
13
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
1G
11
I
Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4)
are disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the
same frequency as CLK.
2G
14
I
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3)
are disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the
same frequency as CLK.
FBOUT
12
O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-Ω series-damping resistor.
1Y (0:4)
3, 4, 5, 8, 9
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via
the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control
input. Each output has an integrated 25-Ω series-damping resistor.
2Y (0:3)
16, 17, 21, 20
O
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via
the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control
input. Each output has an integrated 25-Ω series-damping resistor.
23
Power
Analog power supply. AVCC provides the power reference for the analog circuitry. In addition, AVCC
can be used to bypass the PLL. When AVCC is strapped to ground, PLL is bypassed and CLK is
buffered directly to the device outputs.
1
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
AVCC
AGND
VCC
2, 10, 15, 22
Power
Power supply
GND
6, 7, 18, 19
Ground Ground
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
AVCC
Supply voltage range
VCC
Supply voltage range
VI
Input voltage range
(2)
AVCC < VCC +0.7 V
–0.5 V to 4.3 V
(3)
–0.5 V to 4.6 V
(3) (4)
VO
Voltage range applied to any output in the high or low state
IIK
Input clamp current (VI< 0)
–50 mA
IOK
Output clamp current (VO< 0 or VO > VCC)
±50 mA
IO
Continuous output current (VO = 0 to VCC)
±50 mA
Continuous current through each VCC or GND
±100 mA
Maximum power dissipation at TA = 55°C (in still air) (5)
Tstg
(1)
(2)
(3)
(4)
(5)
4
Storage temperature range
–0.5 V to VCC + 0.5 V
0.7 W
–65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
AVCC must not exceed VCC+ 0.7 V
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For
more information, see the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book
(SCBD002).
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SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010
RECOMMENDED OPERATING CONDITIONS (1)
MIN
MAX
VCC, AVCC
Supply voltage
3
3.6
VIH
High-level input voltage
2
VIL
Low-level input voltage
VI
Input voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
0
V
V
0.8
0
UNIT
V
VCC
V
–12
mA
12
mA
85
°C
Unused inputs must be held high or low to prevent them from floating.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
fclk
Clock frequency
Input clock duty cycle
MIN
MAX
UNIT
20
175
MHz
40%
60%
Stabilization time (1)
(1)
1
ms
The time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for
propagation delay, skew and jitter parameters given in the switching characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input clamp voltage
VOH
II = -18 mA
High-level output voltage
VOL
VCC, AVCC
Low-level output voltage
3V
High-level output current
MAX
UNIT
–1.2
V
IOH = -100 µA
MIN to MAX
IOH = -12 mA
3V
2.1
IOH = -6 mA
3V
2.4
IOL = 100 µA
MIN to MAX
IOL = 12 mA
3V
0.8
IOL = 6 mA
3V
0.55
VO= 1 V
IOH
MIN TYP (1)
3V
VO = 1.65 V
3.3 V
VO = 3.135 V
3.6 V
VCC–0.2
V
0.2
V
–28
–36
mA
-8
VO= 1.95 V
3V
VO = 1.65 V
3.3 V
VO = 0.4 V
3.6 V
10
Input current
VI = VCC or GND
3.6 V
±5
µA
Supply current (static, output not switching)
VI = VCC or GND, IO = 0,
Outputs: low or high
3.6 V, 0 V
40
µA
ΔICC
Change in supply current
One input at VCC - 0.6 V,
Other inputs at VCC or GND
3.3 V to 3.6 V
500
µA
Ci
Input capacitance
VI = VCC or GND
3.3 V
2.5
pF
Co
Output capacitance
VO = VCC or GND
3.3 V
2.8
pF
IOL
Low-level output current
II
ICC
(1)
(2)
(2)
30
40
mA
For conditions shown as MIN or MAX, use the appropriate value specified under the recommended operating conditions section.
For dynamic ICC vs Frequency, see Figure 9 and Figure 10.
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SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF (see Figure 1 and Figure 2) (1)
FROM
(INPUT)
PARAMETER
t(f)
Phase error time- static (normalized) (see
Figure 4 through Figure 7)
CLK↑ = 25 MHz to 65 MHz
tsk(o)
Output skew time (3)
Any Y
Phase error time-jitter
FBIN↑
CLK↑ = 66 MHz to 166 MHz
(4)
VCC, AVCC = 3.3 V
± 0.3 V
TO
(OUTPUT)
MIN
TYP MAX
–150
150
–125
125
Any Y
CLK = 66 MHz to 100 MHz
Any Y or FBOUT
–50
CLK = 25 MHz to 40 MHz
Jitter(cycle-cycle) (see Figure 8)
Any Y or FBOUT
ps
100
ps
50
ps
200
65
CLK↑ = 25 MHz to 65 MHz
Dynamic phase offset (5)
UNIT
500
CLK = 41 MHz to 59 MHz
CLK = 60 MHz to 175 MHz
td(o)
(2)
1.5
FBIN↑
CLK↑ = 66 MHz to 166 MHz
ps
125
0.4
ns
Duty cycle
f(CLK) > 60 MHz
Any Y or FBOUT
45%
55%
tr
Rise time
VO = 0.4 V to 2 V
Any Y or FBOUT
0.3
1.1
ns/V
tf
Fall time
VO = 2 V to 0.4 V
Any Y or FBOUT
0.3
1.1
ns/V
tPLH
Low-to-high propagation delay time, bypass
mode
CLK
Any Y or FBOUT
1.8
3.9
ns
tPHL
High-to-low propagation delay time, bypass
mode
CLK
Any Y or FBOUT
1.8
3.9
ns
(1)
(2)
(3)
(4)
(5)
The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
These parameters are not production tested.
The tsk(o) specification is only valid for equal loading of all outputs.
Calculated per PC DRAM SPEC (tphase error, static-jitter(cycle-to-cycle)).
The parameter is assured by design but cannot be 100% production tested.
PARAMETER MEASUREMENT INFORMATION
3V
Input
50% VCC
0V
tpd
From Output
Under Test
500 W
2V
0.4 V
Output
25 pF
50% VCC
tr
LOAD CIRCUIT FOR OUTPUTS
VOH
2V
0.4 V
VOL
tf
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 133 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf ≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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PARAMETER MEASUREMENT INFORMATION (continued)
FBOUT
Any Y
tsk(o)
Any Y
Any Y
tsk(o)
Figure 2. Skew Calculations
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PARAMETER MEASUREMENT INFORMATION (continued)
CLK
FBIN
t(F)n
t(F)n+1
∑1
n=N
t(F) =
t(F)n
N
(N is a large number of samples)
a) Static Phase Offset
CLK
FBIN
t(F)
td(F)
t(F)
td(F)
b) Dynamic Phase Offset
Figure 3. Static and Dynmaic Phase Offset
8
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TYPICAL CHARACTERISTICS
STATIC PHASE ERROR
vs
LOAD CAPACITANCE
600
600
VCC = 3.3 V
fc = 100 MHz
C(LY1−n) = 25 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
200
VCC = 3.3 V
fc = 133 MHz
C(LY1−n) = 25 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
400
Static Phase Error − ps
400
Static Phase Error − ps
STATIC PHASE ERROR
vs
LOAD CAPACITANCE
CLK to Y1−n
0
−200
200
CLK to Y1−n
0
−200
CLK to FBOUT
CLK to FBOUT
−400
−400
−600
−600
3
8
13
18
23
28
33
38
3
8
13
C(LF) − Load Capacitance − pF
23
28
33
38
175
200
C(LF) − Load Capacitance − pF
Figure 4.
Figure 5.
STATIC PHASE ERROR
vs
SUPPLY VOLTAGE AT FBOUT
STATIC PHASE ERROR
vs
CLOCK FREQUENCY
0
0
fc = 133 MHz
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
−100
−150
CLK to FBOUT
−200
−250
−100
−150
−250
−300
−350
−350
−400
−400
3.1
3.2
3.3
3.4
3.5
3.6
CLK to FBOUT
−200
−300
3
VCC = 3.3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A, B, and C
−50
Static Phase Error − ps
−50
Static Phase Error − ps
18
50
VCC − Supply Voltage at FBOUT − V
Figure 6.
75
100
125
150
fc − Clock Frequency − MHz
Figure 7.
a. Trace length FBOUT to FBIN = 5 mm, ZO = 50Ω
b. C(LY) = Lumped capacitive load Y1-n
c. C(LFx) = Lumped feedback capacitance at FBOUT = FBIN
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TYPICAL CHARACTERISTICS (continued)
JITTER
vs
CLOCK FREQUENCY AT FBOUT
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
140
AI CC − Analog Supply Current − mA
120
25
VCC = 3.3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes C and D
Jitter − ps
100
80
60
Cycle to Cycle
40
20
0
50
75
100
125
150
175
AVCC = VCC = 3.6 V
Bias = 0/3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A and B
20
15
10
5
0
200
0
25
fc − Clock Frequency at FBOUT − MHz
50
75
100
125
150
175
200
fc − Clock Frequency − MHz
Figure 8.
Figure 9.
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
AVCC = VCC = 3.6 V
Bias = 0/3 V
C(LY) = 25 pF || 500 Ω
C(LF) = 12 pF || 500 Ω
TA = 25°C
See Notes A and B
I CC − Supply Current − mA
200
150
100
50
0
0
25
50
75
100
125
150
175
200
fc − Clock Frequency − MHz
Figure 10.
a.
b.
c.
d.
10
Trace length FBOUT to FBIN = 5 mm, ZO = 50 Ω
C(LY) = Lumped capacitive load Y1-n
C(LFx) = Lumped feedback capacitance at FBOUT = FBIN
C(LFx) = Lumped feedback capacitance at FBOUT = FBIN.
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SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010
REVISION HISTORY
Changes from Original (April 2004) to Revision A
•
Page
Changed the AVAILABLE OPTIONS table layout ................................................................................................................ 3
Changes from Revision A (July 2004) to Revision B
Page
•
Changed Features bullet - From: Jitter (cyc - cyc) at 66 MHz to 166 MHz Is Typ = 70 ps To: Jitter (cyc - cyc) at 60
MHz to 175 MHz Is Typ = 65 ps ........................................................................................................................................... 1
•
Added Phase error time- static - CLK↑ = 25 MHz to 65 MHz - to the SWITCHING CHARACTERISTICS table ................. 6
•
Changed Jitter values in the SWITCHING CHARACTERISTICS table ................................................................................ 6
•
Added Dynamic phase offset to the SWITCHING CHARACTERISTICS table .................................................................... 6
•
Changed Figure 2, Skew Calculations .................................................................................................................................. 7
•
Added Figure 3, Static and Dynmaic Phase Offset .............................................................................................................. 8
Changes from Revision B (June 2005) to Revision C
•
Page
Changed the FUNCTION TABLE - replaced with new table entries for clarity .................................................................... 2
Changes from Revision C (January 2009) to Revision D
Page
•
Changed the FUNCTION TABLE column 1 label From: AVDD To: AVCC .......................................................................... 2
•
Added the PACKAGE THERMAL RESISTANCE table ........................................................................................................ 3
Changes from Revision D (February 2010) to Revision E
•
Page
Changed the FUNCTION TABLE CLK column for 3.3V (nom) L and H entries From: CLK < 1 MHz To: CLK > 1
MHz ....................................................................................................................................................................................... 2
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
CDCVF2509APW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
CKV2509A
CDCVF2509APWG4
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
CKV2509A
CDCVF2509APWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
CKV2509A
CDCVF2509APWRG4
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 85
CKV2509A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CDCVF2509APWR
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCVF2509APWR
TSSOP
PW
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
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