ON MC74HCT132A Quad 2-input nand gate with schmitt-trigger inputs with lsttl compatible input Datasheet

MC74HCT132A
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
with LSTTL Compatible
Inputs
High−Performance Silicon−Gate CMOS
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MARKING
DIAGRAMS
The MC74HCT132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
The MC74HCT132A can be used to enhance noise immunity or to
square up slowly changing waveforms.
14
SOIC−14
D SUFFIX
CASE 751A
1
Features
•
•
•
•
•
•
•
•
•
HCT132AG
AWLYWW
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements as Defined by JEDEC
Standard No. 7A
Chip Complexity: 72 FETs or 18 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
14
HCT
132A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
1
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
A1
1
14
VCC
A
B1
2
13
B4
Y1
3
12
A4
A2
4
11
Y4
L
L
H
H
B2
5
10
B3
Y2
6
9
A3
GND
7
8
Y3
Output
B
Y
L
H
L
H
H
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Figure 1. Pin Assignment
© Semiconductor Components Industries, LLC, 2009
September, 2016 − Rev. 2
1
Publication Order Number:
MC74HCT132A/D
MC74HCT132A
A1
1
3
B1
A2
2
4
6
B2
Y1
Y2
5
Y = AB
A3
9
8
B3
Y3
10
A4 12
11
B4
Y4
13
PIN 14 = VCC
PIN 7 = GND
Figure 2. Logic Diagram
ORDERING INFORMATION
Device
Package
MC74HCT132ADG
MC74HCT132ADR2G
55 Units / Rail
SOIC−14
(Pb−Free)
NLV74HCT132ADR2G*
MC74HCT132ADTR2G
NLVHCT132ADTR2G*
Shipping†
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC74HCT132A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
Positive DC Supply Voltage
0.5 to 7.0
V
VIN
Digital Input Voltage
0.5 to 7.0
V
VOUT
DC Output Voltage
0.5 to 7.0
0.5 to VCC 0.5
V
IIK
Input Diode Current
20
mA
IOK
Output Diode Current
20
mA
IOUT
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
75
mA
IGND
DC Ground Current per Ground Pin
75
mA
TSTG
Storage Temperature Range
65 to 150
_C
260
_C
150
_C
14−SOIC
14−TSSOP
125
170
_C/W
SOIC
TSSOP
500
450
mW
Output in 3−State
High or Low State
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature Under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Flammability Rating
Level 1
Oxygen Index: 30% − 35%
UL 94 V0 @ 0.125 in
VESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
2000
100
500
V
ILatch−Up
Latch−Up Performance
Above VCC and Below GND at 85_C (Note 4)
300
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 3)
Min
Max
Unit
2.0
6.0
V
0
VCC
V
55
125
_C
−
No Limit
(Note 5)
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. When VIN 0.5 VCC, ICC >> quiescent current.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
MC74HCT132A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Guaranteed Limit
V
*55_C to 25_C
85_C
125_C
Unit
VOUT = 0.1 V
|IOUT| 20 mA
4.5
5.5
1.9
2.1
1.9
2.1
1.9
2.1
V
Minimum Positive−Going
Input Threshold Voltage
VOUT = 0.1 V
|IOUT| 20 mA
4.5
5.5
1.2
1.4
1.2
1.4
1.2
1.4
V
VT–max
Maximum Negative−Going
Input Threshold Voltage
VOUT = VCC – 0.1 V
|IOUT| 20 mA
4.5
5.5
1.2
1.4
1.2
1.4
1.2
1.4
V
VT–min
Minimum Negative−Going
Input Threshold Voltage
VOUT = VCC – 0.1 V
|IOUT| 20 mA
4.5
5.5
0.5
0.6
0.5
0.6
0.5
0.6
V
VHmin
(Note 7)
Minimum Hysteresis
Voltage
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| 20 mA
4.5
5.5
0.4
0.4
0.4
0.4
0.4
0.4
V
VOH
Minimum High−Level
Output Voltage
VIN VT−min or VT+max
|IOUT| 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
VIN −VT−min or VT+max
|IOUT| 4.0 mA
4.5
3.98
3.84
3.7
VIN ≥ VT+max
|IOUT| 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
Symbol
Parameter
VT+max
Maximum Positive−Going
Input Threshold Voltage
VT+min
VOL
Test Conditions
Maximum Low−Level
Output Voltage
VIN ≥ VT+max
|IOUT| 4.0 mA
V
IIN
Maximum Input Leakage
Current
VIN = VCC or GND
5.5
0.1
1.0
1.0
mA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN = VCC or GND
IOUT = 0 mA
5.5
1.0
10
40
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
7. VHmin (VT+min) (VT−max); VHmax = (VT+max) (VT−min).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns, VCC = 5.0 V ± 10%)
VCC
Symbol
Parameter
Guaranteed Limit
V
*55_C to 25_C
85_C
125_C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
5.0
25
31
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
5.0
15
19
22
ns
Maximum Input Capacitance
—
10
10
10
pF
Cin
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (per Gate) (Note 8)
24
8. Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .
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4
pF
MC74HCT132A
TEST POINT
tr
INPUT
A OR B
(VI)
tf
VCC
90%
VM
10%
OUTPUT
DEVICE
UNDER
TEST
GND
tPLH
tPHL
CL *
90%
VM
10%
Y
tTHL
tTLH
*Includes all probe and jig capacitance
VI = GND to 3.0 V
VM = 1.3 V
Figure 3. Switching Waveforms
Figure 4. Test Circuit
VCC
VCC
VH
VH
VIN
VT+
VT-
VT+
VT-
VIN
GND
GND
VOH
VOH
VOUT
VOUT
VOL
VOL
VCC
VOUT
VIN
(a)A SCHMITT TRIGGER SQUARES UP INPUTS
(a)WITH SLOW RISE AND FALL TIMES
(b)A SCHMITT TRIGGER OFFERS MAXIMUM
NOISE IMMUNITY
Figure 5. Typical Schmitt−Trigger Applications
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5
MC74HCT132A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE L
D
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
DIM
A
A1
A3
b
D
E
e
H
h
L
M
b
0.25
C A
M
S
B
S
0.10
X 45 _
M
A1
e
DETAIL A
h
A
C
SEATING
PLANE
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
MC74HCT132A
PACKAGE DIMENSIONS
TSSOP−14 WB
CASE 948G
ISSUE C
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
K
A
−V−
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
INCHES
MIN
MAX
MIN MAX
4.90
5.10 0.193 0.200
4.30
4.50 0.169 0.177
−−−
1.20
−−− 0.047
0.05
0.15 0.002 0.006
0.50
0.75 0.020 0.030
0.65 BSC
0.026 BSC
0.50
0.60 0.020 0.024
0.09
0.20 0.004 0.008
0.09
0.16 0.004 0.006
0.19
0.30 0.007 0.012
0.19
0.25 0.007 0.010
6.40 BSC
0.252 BSC
0_
8_
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
7
MC74HCT132A
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