Austin AS29F040DCG-60/Q 512k x 8 flash uniform sector 5.0v flash memory Datasheet

FLASH
AS29F040
Austin Semiconductor, Inc.
512K x 8 FLASH
PIN ASSIGNMENT
(Top View)
UNIFORM SECTOR 5.0V FLASH MEMORY
32-PIN Ceramic DIP (CW)
32-pin Flatpack (F)
32-pin Lead Formed Flatpack (DCG)
AVAILABLE AS MILITARY
SPECIFICATIONS
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
• MIL-STD-883
• SMD 5962-96692
FEATURES
• Single 5.0V ±10% power supply operation
• Fastest access times: 55, 60, 70, 90, 120, & 150ns
• Low power consumption:
3 20 mA typical active read current
3 30 mA typical program/erase current
3 1 µA typical standby current (standard access time to
active mode)
• Flexible sector architecture
3 Eight uniform 64 Kbyte each
3 Any combination of sectors can be erased
3 Supports full chip erase
• Sector protection
• Embedded Algorithms Erase & Program Algorithms
• Erase Suspend/Resume
• Minimum 1,000,000 Program/Erase Cycles per sector
guaranteed
• Compatible with JEDEC standards
3 Pinout and software compatible with single-powersupply FLASH
• Data\ Polling and Toggle Bits
• 20-year data retention at 125°C
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
WE\
A17
A14
A13
A8
A9
A11
OE\
A10
CE\
DQ7
DQ6
DQ5
DQ4
DQ3
A12
A15
A16
A18
VCC
WE\
A17
32-PAD Ceramic LCC (ECA)
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4 3 2
32 31 30
5
29
1
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
A14
A13
A8
A9
A11
OE\
A10
CE\
I/O 7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
OPTIONS
OPTIONS
• Timing
55ns
60ns
70ns
90ns
120ns
150ns
• Package Type
Ceramic DIP (600 mil)
Flatpack
Lead Formed Flatpack
Leadless Chip Carrier
MARKING
-55
-60
-70
-90
-120
-150
CW
F
DCG
ECA
• Temperature Ranges
Industrial Temperature (-40°C to +85°C) IT
Military Temperature (-55°C to +125°C) XT**
883C Processing (-55°C to +125°C)
883C
QML Processing (-55°C to +125°C)
Q
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS29F040
Rev. 2.2 09/07
MARKING
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
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Austin Semiconductor, Inc.
AS29F040
GENERAL DESCRIPTION
The AS29F040 is a 4Mbit, 5.0 Volt-only FLASH memory
organized as 524,288 Kbytes of 8 bits each. The 512 Kbytes of
data are divided into eight sectors of 64 Kbytes each for flexible
erase capability. The 8 bits of data appear on DQ0-DQ7. The
device is designed to be programmed in-system with the
standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not
required for write or erase operations. The device can also be
programmed in standard EPROM programmers.
This device is manufactured using 0.32 µm process
technology. In addition, it has a second toggle bit, DQ2, and
offers the ability to program in the Erase Suspend mode.
It is available with access times of 55, 60, ^+^+6=70, 90, 120,
and 150ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has
separate chip enable (CE\), write enable (WE\), and output enable (OE\) controls.
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The device is entirely command set compatible with the
JEDEC single-power-supply FLASH standard. Commands are
written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal
state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the
device is similar to reading from other FLASH or EPROM
devices.
Device programming occurs by executing the program
command sequence. This invokes the Embedded Program
algorithm -- an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin.
Device erasure occurs by executing the erase command
sequence. This invokes the Embedded Erase algorithm -- an
internal algorithm that automatically preprograms the array (if it
is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase
operation is complete by reading the DQ7 (Data\Polling) and
DQ6 (toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data or accept
another command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The device is fully erased when shipped from
the factory.
The hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
via programming equipment.
The erase suspect feature enables the user to put erase on
hold for any period of time to read data from, or program data to,
any sector that is not selected for erasure. True background
erase can thus be achieved.
The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode. The
device electrically erases all bits within a sector simultaneously
via Fowler-Nordheim tunneling. The data is programmed using
hot electron injection.
PIN CONFIGURATION
LOGIC SYMBOL
PIN
A0 - A18
DQ0 - DQ7
CE\
OE\
WE\
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
VCC
+5V Single Power Supply
VSS
Device Ground
AS29F040
Rev. 2.2 09/07
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2
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Austin Semiconductor, Inc.
AS29F040
FUNCTIONAL BLOCK DIAGRAM
AS29F040
Rev. 2.2 09/07
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AS29F040
Austin Semiconductor, Inc.
DEVICE BUS OPERATIONS
Writing Commands/Command Sequences
This section describes the requirements and use of the
device bus operations, which are initiated through the internal
command register. The command register itself does not
occupy any addressable memory location. The register is
composed of latches that store the commands, along with the
address and data information needed to execute the command.
The contents of the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the
device. The appropriate device bus operations table lists the
inputs and control levels required, and the resulting output.
The following subsections describe each of these operations
in further detail.
To write a command or command sequence (which includes
programming data to the device and erasing sectors of memory),
the system must drive WE\ and CE\ to VIL, and OE\ to VIH.
An erase operation can erase one sector, multiple sectors,
or the entire device. The Sector Address Tables indicate the
address space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select a
sector. See the “Command Definitions” section for details on
erasing a sector or the entire chip, or suspending/resuming the
erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on DQ7 - DQ0. Standard read
cycle timings apply in this mode. Refer to the “Autoselect
Mode” and “Autoselect Command Sequence” sections for more
information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The “AC
Characteristics” section contains timing specification tables
and timing diagrams for write operations.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE\ and OE\ pins to VIL. CE\ is the power control and
selects the device. OE\ is the output control and gates array
data to the output pins. WE\ should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This ensures
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in this
mode to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command register
contents are altered.
See “Reading Array Data” for more information. Refer to
the AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing waveforms.
ICC1 in the DC Characteristics table represents the active
current specification for reading array data.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits on
DQ7 - DQ0. Standard read cycle timings and ICC read
specifications apply. Refer to “Write Operation Status” for
more information, and to each AC Characteristics section for
timing diagrams.
TABLE 1: DEVICE BUS OPERATIONS
OPERATION
CE\
OE\
WE\
A0 - A20
DQ0 - DQ7
Read
L
L
H
AIN
DOUT
Write
L
H
L
AIN
DIN
CMOS Standby
VCC ± 0.5V
X
X
X
High-Z
TTL Standby
Output Disable
H
L
X
H
X
H
X
X
High-Z
High-Z
NOTES:
AS29F040
Rev. 2.2 09/07
See the “Sector Protection/Unprotection” section for more information.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Austin Semiconductor, Inc.
AS29F040
Definitions table shows the remaining address bits that are
don’t care. When all necessary bits have been set as required,
the programming equipment may then read the corresponding
identifier code on DQ7 - DQ0
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command register, as
shown in the Command Definitions table. This method does
not require VID. See “Command Definitions” for details on
using the autoselect mode.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE\ input.
The device enters the CMOS standby mode when the CE\
pin is held at VCC ± 0.5V. (Note that this is a more restricted
voltage range than VIH.) The device enters the TTL standby
mode when CE\ is held at VIH. The device requires the standard
access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is completed.
ICC3 in the DC Characteristics table represents the standby
current specification.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and erase
operations in previously protected sectors.
Sector protection/unprotection must be implemented
using programming equipment. The procedure requires a high
voltage (VID) on address pin A9 and the control pins. The
device is shipped with all sectors unprotected. It is possible to
determine whether a sector is protected or unprotected. See
“Autoselect Mode” for details.
Output Disable Mode
When the OE\ input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on DQ7 - DQ0. This mode is primarily
intended for programming equipment to automatically match a
device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed
in-system through the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pin A9. Address pins
A6, A1, and A0 must be as shown in the Autoselect Codes
(High Voltage Method) table. In addition, when verifying
sector protection, the sector address must appear on the
appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table). In
addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept
any write cycles. This protects data during VCC power-up and
TABLE 2: SECTOR ADDRESSES TABLE
SECTOR
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
NOTE:
A18
0
0
0
0
1
1
1
1
A17
0
0
1
1
0
0
1
1
A16
0
1
0
1
0
1
0
1
ADDRESS RANGE
00000h - 0FFFFh
10000h - 1FFFFh
20000h - 2FFFFh
30000h - 3FFFFh
40000h - 4FFFFh
50000h - 5FFFFh
60000h - 6FFFFh
70000h - 7FFFFh
All sectors are 64 Kbytes in size.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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AS29F040
Austin Semiconductor, Inc.
power-down. The command register and all internal program/
erase circuits are disabled, and the device resets. Subsequent
writes are ignored until VCC is greater than VLKO. The system
must provide the proper signals to the control pins to prevent
unintentional writes when VCC is greater than VLKO.
The device is also ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the
device enters the Erase Suspend mode. The system can read
array data using the standard read timings, except that if it
reads at an address within erase-suspended sectors, the device
outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See “Erase
Suspend/Erase Resume” for more information.
The system must issue the reset command to re-enable the
device for reading array data if DQ5 goes high, or while in the
autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information. The
Read Operations table provides the read parameters, and the
Read Operation Timings diagram shows the timing diagram.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE\, CE\, or WE\
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE\ = VIL,
CE\ = VIH or WE\ = VIH. To initiate a write cycle, CE\ and WE\
must be a logical zero while OE\ is a logical one.
Power-Up Write Inhibit
If WE\ = CE\ = VIL and OE\ = VIH during power up, the
device does not accept commands on the rising edge of WE\.
The internal state machine is automatically reset to reading
array data on power-up.
Reset Command
Writing the reset command to the device resets the device
to reading array data. Address bits are don’t care for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing begins.
This resets the device to reading array data. Once erasure
begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data (also applies
to programming in Erase Suspend Mode). Once programming
begins, however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to return
to reading array data (also applies to autoselect during Erase
Suspend).
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device to
reading array data.
All addresses are latched on the falling edge of WE\ or
CE\, whichever happens later. All data is latched on the rising
edge of WE\ or CE\, whichever happens first. Refer to the
appropriate timing diagrams in the “AC Characteristics”
section.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
TABLE 3: Autoselect Codes (High Voltage Method)
Description
A18 - A16 A15 - A10
A9
A8 - A7
A6
A5 - A2
A1
A0
Identifier Code
On DQ7 to DQ0
Manufacturer ID
X
X
VID
X
VIL
X
VIL
VIL
01h
Device ID
X
X
VID
X
VIL
X
VIL
VIH
A4h
Sector
Address
X
VID
X
VIL
X
VIH
VIL
Sector Protection
Verification
AS29F040
Rev. 2.2 09/07
01h (protected)
00h
(unprotected)
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6
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Austin Semiconductor, Inc.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to reading array
data (also applies during Erase Suspend).
AS29F040
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which in
turn invokes the Embedded Erase algorithm. The device does
not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored.
The system can determine the status of the erase
operation by using DQ7, DQ6, or DQ2. See “Write Operation
Status” for information on these status bits. When the
Embedded Erase algorithm is complete, the device returns to
reading array data and addresses are no longer latched.
Figure 2 illustrates the algorithm for the erase operation.
See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and the Chip /Sector Erase
Operation Timings for timing waveforms.
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes, and
determine whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires VID on address bit A9.
The auto select command sequence is initiated by writing
two unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h retrieves the manufacturer
code. A read cycle at address XX01h returns the device code.
A read cycle containing a sector address (SA) and the address
02h in returns 01h if that sector is protected, or 00h if it is
unprotected. Refer to the Sector Address tables for valid sector
addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
FIGURE 1: PROGRAM OPERATION
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
cycles, followed by the program set-up command. The
program address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not required
to provide further controls or timings. The device
automatically provides internally generated program pulses and
verify the programmed cell margin. The Command Definitions
take shows the address and data requirements for the byte
program command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses are no
longer latched. The system can determine the status of the
program operation by using DQ7 or DQ6. See “Write Operation
Status” for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from a “0”
back to a “1”. Attempting to do so may halt the operation and
set DQ5 to “1”, or cause the Data\ Polling algorithm to indicate
the operation was successful. However, a succeeding read will
show that the data is still “0”. Only erase operations can
convert a “0” to a “1”.
AS29F040
Rev. 2.2 09/07
NOTE:
See the appropriate Command Definitions table for program
command sequence.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
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Austin Semiconductor, Inc.
AS29F040
including the 50µs time-out period during the sector erase
command sequence. The Erase Suspend command is ignored if
written during the chip erase operation or Embedded Program
algorithm. Writing the Erase Suspect command during the
Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are “don’t
cares” when writing the Erase Suspect command.
When the Erase Suspect command is written during a
sector erase operation, the device requires a maximum of 20µs
to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-out,
the device immediately terminates the time-out period and
suspends the erase operation.
After the erase operation has been suspected, the system
can read array data from any sector not selected for erasure.
(The device “erase suspends” all sectors selected for erasure.)
Normal read and write timings and command definitions apply.
Reading at any address within erase-suspended sectors
produces status data on DQ7-DQ0. The system can use DQ7,
or DQ6 and DQ2 together, to determine if a sector is actively
erasing or is erase-suspended. See “Write Operation Status”
for information on these status bits.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the addresss of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements for
the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations.
After the command sequence is written, a sector erase
time-out of 50µs begins. During the time-out period, additional
sector addresses and sector erase commands may be written.
Loading the sector erase buffer may be done in any sequence,
and the number of sectors may be from one sector to all sectors.
The time between these additional cycles must be less than
50µs, otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended that
processor interrupts be disabled during this time to ensure all
commands are accepted. The interrupts can be re-enabled after
the last Sector Erase command is written. If the time between
additional sector erase commands can be assumed to be less
than 50µs, the system need not monitor DQ3. Any command
other than Sector Erase or Erase Suspend during the time-out
period resets the device to reading array data. The system
must rewrite the command sequence and any additional sector
addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See the “DQ3: Sector Erase Timer”
section.) The time-out begins from the rising edge of the final
WE\ pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using DQ7, DQ6, or DQ2. Refer to “Write
Operation Status” for information on these status bits.
Figure 2 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the “AC
Characteristics” section for parameters, and to the Sector Erase
Operations Timing diagram for timing waveforms.
FIGURE 2: ERASE OPERATION
Erase Suspend/Erase Resume Commands
The Erase Suspect command allows the system to
interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
AS29F040
Rev. 2.2 09/07
NOTE:
1) See the appropriate Command Definitions table for program
command sequence.
2) See “DQ3: Sector Erase Timer” for more information.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
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AS29F040
Austin Semiconductor, Inc.
After an erase-suspended program operation is complete,
the system can once again read array data within
non-suspended sectors. The system can determine the status
of the program operation using the DQ7 or DQ6 status bits, just
as in the standard program operation. See “Write Operation
Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode. The
device allows reading autoselect codes even at addresses within
erasing sectors, since the codes are not stored in the memory
array. When the device exits the autoselect mode, the device
reverts to the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence” for more
information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend mode
and continue the sector erase operation. Further writes of the
Resume command are ignored. Another Erase Suspend
command can be written after the device has resumed erasing.
Command Sequence
Cycles
TABLE 4: Command Definitions
1
5
Read
Reset
6
Manufacturer ID
Device ID
7
Autoselect
8
Sector Protect Verify
Program
Chip Erase
Sector Erase
9
Erase Suspend
Erase Resume
10
2,3,4
Bus Cycles
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
1
RA
RD
1
4
4
XXX
555
555
F0
AA
AA
2AA
2AA
55
55
555
555
90
90
4
555
AA
2AA
55
555
90
4
6
6
1
555
555
555
XXX
AA
AA
AA
B0
2AA
2AA
2AA
55
55
55
555
555
555
A0
80
80
1
XXX
30
X00
X01
SA
X02
PA
555
555
01
A4
00
01
PD
AA
AA
2AA
2AA
55
55
555
SA
10
30
LEGEND:
X = Don’t Care.
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE\ or CE\ pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE\ or CE\ pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18-A16 uniquely select any sector.
NOTES:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all command bus cycles are write operations.
4. Address bits A18 - A11 are don’t care for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is
providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See “Autoselect Command Sequence” for more information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
10. The Erase Resume command is valid only during the Erase Suspend mode.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
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Austin Semiconductor, Inc.
AS29F040
WRITE OPERATION STATUS
DQ6: Toggle Bit I
The device provides several bits to determine the status of
a write operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 5 and
the following subsections describe the functions of these bits.
DQ7 and DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress. These
three bits are discussed first.
Toggle bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or whether
the device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the rising edge of
the final WE\ pulse in the command sequence (prior to the
program or erase operation), and during the sector erase timeout.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address cause DQ6 to
DQ7: Data\ Polling
The Data\ Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or completed,
or whether the device is in Erase Suspend. Data\ Polling is
valid after the rising edge of the final WE\ pulse in the program
or erase command sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to DQ7.
The system must provide the program address to read valid
status information on DQ7. If a program address falls within a
protected sector, Data\ Polling on DQ7 is active for
approximately 2µs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data\ Polling
produces a “0” on DQ7. When the Embedded Erase algorithm
is complete, or if the device enters the Erase Suspend mode,
Data\ Polling produces a “1” on DQ7. This is analogous to the
complement/true datum output described for the Embedded
Program algorithm: the erase function changes all the bits in a
sector to “1”; prior to this, the device outputs the
“complement,” or “0”. The system must provide an address
within any of the sectors selected for erasure to read valid
status information on DQ7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data\ Polling on DQ7 is
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at DQ7-DQ0 on
the following read cycles. This is because DQ7 may change
asynchronously with DQ0-DQ6 while Output Enable (OE\) is
asserted low. The Data\ Polling Timings (During Embedded
Algorithms) figure in the “AC Characteristics” section
illustrates this.
Table 5 shows the outputs for Data\ Polling on DQ7.
Figure 3 shows the Data\ Polling algorithm.
AS29F040
Rev. 2.2 09/07
FIGURE 3: DATA\ POLLING ALGORITHM
NOTE:
1) VA = Valid address for programming. During a sector erase operation,
a valid address is an address within any sector selected for erasure. During
chip erase, a valid address is any non-protected sector address.
2) DQ7 should be rechecked even if DQ5 = “1” because DQ7 may change
simultaneously with DQ5.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
10
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Austin Semiconductor, Inc.
toggle. (The system may use either OE\ or CE\ to control the
read cycles.) When the operation is complete, DQ6 stops
toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, DQ6 toggles for
approximately 100µs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progress), DQ6 toggles. When the device
enters the Erase Suspend mode, DQ6 stops toggling. However
the system must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on “DQ7: Data\ Polling”).
If a program address falls within a protected sector, DQ6
toggles for approximately 2µs after the program command
sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit
algorithm, and to the Toggle Bit Timings figure in the “AC
Characteristics” section for the timing diagram. The DQ2 vs.
DQ6 figure shows the differences between DQ2 and DQ6 in
graphical form. See also the subsection on “DQ2: Toggle
Bit II”.
AS29F040
Reading Toggle Bit DQ6/DQ2
Refer to Figure 4 for the following discussion. Whenever
the system initially begins reading toggle bit status, it must
read DQ7-DQ0 at least twice in a row to determine whether a
toggle bit is toggling. Typically, a system would note and store
the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device has
FIGURE 4: TOGGLE BIT ALGORITHM
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising
edge of the final WE\ pulse in the command sequence.
DQ2 toggles when the system reads at addresses within
those sectors taht have been selected for erasure. (The system
may use either OE\ or CE\ to control the read cycles.) But DQ2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but cannot
distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer
to Table 5 to compare outputs for DQ2 and DQ6.
Figure 4 shows the toggle bit algorithm in flowchart form,
and the section “DQ2: Toggle Bit II” explains the algorithm.
See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle
Bit Timings figure for the toggle bit timing diagram. The DQ2
vs. DQ6 figure shows the differences between DQ2 and DQ6 in
graphical form.
AS29F040
Rev. 2.2 09/07
NOTE:
1) Read toggle bit twice to determine whether or not it is toggling. See
text.
2) Recheck toggle bit because it may stop toggling as DQ5 changes to
“1”. See text.
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AS29F040
Austin Semiconductor, Inc.
completed the program or erase operation. The system can
read array data on DQ7-DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of DQ5 is high (see the section
on DQ5). If it is, the system should then determine again whether
the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the program
or erase operation. If it is still toggling, the device did not
complete the operation successfully, and the system must write
the reset command to return to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit it toggling and DQ5 has not gone
high. The system may continue to monitor the toggle bit and
DQ5 through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 4).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1.” This is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The DQ5 failure condition may appear if the system tries to
program a “1” to a location that is previously programmed to
“0.” Only an erase operation can change a “0” back to a “1.”
Under this condition, the device halts the operation, and when
the operation has exceeded the timing limits, DQ5 produces a
“1.”
Under both these conditions, the system must issue the
reset command to return the device to reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an erase
operation has begun. (The sector erase timer does not apply to
the chip erase command.) If additional sectors are selected for
erasure, the entire time-out also applies after each additional
sector erase command. When the time-out is complete, DQ3
switches from “0” to “1.” The system may ignore DQ3 if the
system can guarantee that the time between additional sector
erase commands will always be less than 50µs. See also the
“Sector Erase Command Sequence” section.
After the sector erase command sequence is written, the
system should read the status on DQ7 (Data\ Polling) or DQ6
(Toggle Bit I) to ensure the device has accepted the command
sequence, and then read DQ3. If DQ3 is “1”, the internally
controlled erase cycle has begun; all further commands (other
than Erase Suspend) are ignored until the erase operation is
complete. If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been accepted,
the system software should check the status of DQ3 prior to
and following each subsequent sector erase command. If DQ3
is high on the second status check, the last command might not
have been accepted. Table 5 shows the outputs for DQ3.
TABLE 5: WRITE OPERATION STATUS
OPERATION
Standard
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Reading within Erase Suspended Sector
Erase
Suspend Reading within Non-Erase Suspended Sector
Mode
Erase-Suspend-Program
1
DQ6
DQ5
DQ7\
Toggle
0
2
1
DQ3
DQ2
0
0
No Toggle
Toggle
0
1
Toggle
1
No toggle
0
N/A
Toggle
Data
Data
Data
Data
Data
DQ7\
Toggle
0
N/A
N/A
DQ7
NOTES:
1. DQ7 and DQ2 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. See “DQ5:
Exceeding Timing Limits” for more information.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
12
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AS29F040
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature with Power Applied............-55°C to +125°C
Voltage with Respect to Ground
VCC1.................................................................-2.0V to +7.0V
A9, OE\2........................................................-2.0V to +12.5V
All other pins1...............................................-2.0V to +7.0V
VCC Supply Voltage (±10%)..........................................-4.5V to +5.5V
Output Short Circuit Current3..................................................200mA
Storage Temperature..................................................-65°C to +125°C
NOTES:
FIGURE 5: Maximum Negative
Overshoot Waveform
1. Minimum DC voltage on input or I/O pin is -0.5V. During voltage transitions, input
may overshoot VSS to -2.0V for periods of up to 20ns. See Figure 5. Maximum DC voltage
on input and I/O pins is VCC + 0.5V. During voltage transitions, input and I/O pins may
overshoot VCC + 2.0V for periods up to 20ns. See Figure 6.
2. Minimum DC voltage on A9 pin is -0.5V. During voltage transitions, A9 and OE\ pins
may overshoot VSS to -2.0V for periods of up to 20ns. See Figure 5. Maximum DC input
voltage on A9 and OE\ is +12.5V which may overshoot to 13.5V for periods up to 20ns.
3. No more than one output shorted to ground at a time. Duration of the short circuit
should not be greater than one second.
*Stresses greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operation section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
AS29F040
Rev. 2.2 09/07
FIGURE 6: Maximum Positive
Overshoot Waveform
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AS29F040
Austin Semiconductor, Inc.
DC CHARACTERISTICS: TTL/NMOS Compatible
PARAMETER
DESCRIPTION
SYM
MIN
TYP
MAX
UNIT
Input Load Current
VIN = VSS to VCC, VCC = VCC Max
ILI
±1.0
µA
A9 Input Load Current
VCC = VCC Max, A9 = 12.5V
ILIT
50
µA
VOUT = VSS to VCC, VCC = VCC Max
ILO
±1.0
µA
CE\ = VIL, OE\ = VIH
ICC1
20
30
mA
CE\ = VIL, OE\ = VIH
ICC2
30
40
mA
CE\ = VIH
ICC3
0.4
1.0
mA
Output Leakage Current
1,2
VCC Active Read Current
VCC Active Write (Program/Erase)
Current
2,3,4
2
VCC Standby Current
Input Low Voltage
VIL
-0.5
0.8
V
Input High Voltage
VIH
2.0
VCC + 0.5
V
10.5
12.5
V
0.45
V
Voltage for Autoselect and Sector
Protect
VCC = 5.25V
VID
Output Low Voltage
IOL = 12 mA, VCC = VCC Min
VOL
Output High Voltage
IOH = -2.5 mA, VCC = VCC Min
VOH
2.4
VLKO
3.2
Low VCC Lock-out Voltage
V
4.2
V
MAX
UNIT
DC CHARACTERISTICS: CMOS Compatible
PARAMETER
DESCRIPTION
SYM
MIN
TYP
Input Load Current
VIN = VSS to VCC, VCC = VCC Max
ILI
±1.0
µA
A9 Input Load Current
VCC = VCC Max, A9 = 12.5V
ILIT
50
µA
VOUT = VSS to VCC, VCC = VCC Max
ILO
±1.0
µA
CE\ = VIL, OE\ = VIH
ICC1
20
30
mA
CE\ = VIL, OE\ = VIH
ICC2
30
40
mA
CE\ = VCC ± 0.5V
ICC3
1
5
µA
Output Leakage Current
1,2
VCC Active Read Current
VCC Active Program/Erase
Current
2,3,4
2, 5
VCC Standby Current
Input Low Voltage
VIL
-0.5
0.8
V
Input High Voltage
VIH
0.7 x VCC
VCC + 0.3
V
10.5
12.5
V
0.45
V
Voltage for Autoselect and
Sector Protect
VCC = 5.25V
VID
Output Low Voltage
IOL = 12 mA, VCC = VCC Min
VOL
Output High Voltage
IOH = -2.5 mA, VCC = VCC Min
VOH1
0.85 VCC
V
IOH = -100 µA, VCC = VCC Min
VOH2
VCC - 0.4
V
VLKO
3.2
Low VCC Lock-out Voltage
4.2
V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component
typically is less than 2mA/MHz, with OE\ at VIH.
2. Maximum ICC specifications are tested with VCC = VCC Max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Not 100% tested.
5. For CMOS mode only, ICC3 = 20µA max at extended temperatures (>+85°C).
AS29F040
Rev. 2.2 09/07
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AS29F040
Austin Semiconductor, Inc.
FIGURE 7: TEST CONDITIONS,
Test Setup
TABLE 6: TEST CONDITIONS,
Test Specifications
CONDITIONS
Output Load
Output Load Capacitance, CL
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
-55
ALL OTHERS
1 TTL Gate
UNIT
30
100
pF
5
20
ns
0.0 - 3.0
0.45 - 2.4
V
1.5
0.8, 2.0
V
1.5
0.8, 2.0
V
AC CHARACTERISTICS: Read-Only Operations
SYMBOL
JEDEC Std
PARAMETER
3
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
tACC
Chip Enable to Output Delay
tELQV
tCE
tGLQV
Output Enable to Output Delay
Chip Enable to Output High Z
2, 3
2, 3
Output Enable to Output High Z
Output Enable Hold Time
TEST SETUP
-55
-150 UNITS
MIN
55
70
90
120
150
ns
MAX
55
70
90
120
150
ns
MAX
55
70
90
120
150
ns
tOE
MAX
30
30
35
50
55
ns
tEHQZ
tDF
MAX
18
20
20
30
35
ns
tGHQZ
tDF
18
20
20
30
35
ns
3
Output Hold Time From Addresses
CE\ or OE\, Whichever Occurs First
1
SPEED OPTIONS
-70
90
-120
tAXQX
CE\ = VIL
OE\ = VIL
OE\ = VIL
Read
tOEH Toggle and
Data Polling
MIN
0
0
0
0
0
ns
MIN
10
10
10
10
10
ns
tOH
MIN
0
0
0
0
0
ns
NOTES:
1. See Figure 7 and Table 6 for test specifications.
2. Output driver disable time.
3. Not 100% tested.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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FIGURE 8: AC CHARACTERISTICS, Read Operations Timings
0V
AC CHARACTERISTICS: Erase and Program Operations
PARAMETER
1
SYMBOL
JEDEC
Std
-55
55
SPEED OPTIONS
-70
90
-120
-150 UNITS
MIN
tAVAV
tWC
Address Setup Time
MIN
tAVWL
tAS
Address Hold Time
MIN
tWLAX
tAH
40
45
45
50
50
ns
Data Setup Time
MIN
tDVWH
tDS
25
30
45
50
50
ns
Data Hold Time
MIN
tWHDX
tDH
0
ns
Output Enable Setup Time
MIN
tOES
0
ns
Read Recover Time Before Write
(OE\ High to WE\ Low)
MIN
tGHWL
tGHWL
0
ns
CE\ Setup Time
MIN
tELWL
tCS
0
ns
CE\ Hold Time
MIN
tWHEH
tCH
0
ns
Write Pulse Width
MIN
tWLWH
tWP
Write Pulse Width High
MIN
tWHWL
tWPH
Write Cycle Time
2
Byte Programming Operation
2
Sector Erase Operation
VCC Set Up Time
1
70
90
120
150
0
30
35
45
ns
ns
50
50
ns
20
ns
TYP tWHWH1 tWHWH1
7
µs
TYP tWHWH2 tWHWH2
1
sec
50
µs
MIN
tVCS
NOTES:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
AS29F040
Rev. 2.2 09/07
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AS29F040
FIGURE 9: AC CHARACTERISTICS, Program Operation Timings
NOTES:
PA = program address, PD = program data, DOUT is the true data at the program address.
FIGURE 10: AC CHARACTERISTICS, Chip/Sector Erase
Operation Timings
NOTES:
SA = sector address (for Sector Erase), VA = Valid Address for reading status data.
AS29F040
Rev. 2.2 09/07
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AS29F040
FIGURE 11: Data\ Polling Timings (During Embedded Algorithms)
NOTES:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
FIGURE 12: AC CHARACTERISTICS, Toggle Bit Timings (During
Embedded Algorithms)
NOTES:
VA = Valid address, not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
AS29F040
Rev. 2.2 09/07
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FIGURE 13: AC CHARACTERISTICS, DQ2 vs. DQ6
NOTES:
Both DQ6 and DQ2 toggle with OE\ or CE\. See the text on DQ6 and DQ2 in section “Write Operation Status” for more information.
AC CHARACTERISTICS: Erase and Program Operations (Alternate
CE\ Controlled Writes)
PARAMETER
1
SYMBOL
JEDEC
Std
-55
55
SPEED OPTIONS
-70
90
-120
-150
UNITS
150
ns
MIN
tAVAV
tWC
Address Setup Time
MIN
tAVWL
tAS
Address Hold Time
MIN
tWLAX
tAH
40
45
45
50
50
ns
Data Setup Time
MIN
tDVWH
tDS
25
30
45
50
50
ns
Data Hold Time
MIN
tWHDX
tDH
0
ns
Output Enable Setup Time
MIN
tOES
0
ns
Read Recover Time Before Write
(OE\ High to WE\ Low)
MIN
tGHWL
tGHWL
0
ns
CE\ Setup Time
MIN
tELWL
tCS
0
ns
CE\ Hold Time
MIN
tWHEH
tCH
0
ns
Write Pulse Width
MIN
tWLWH
tWP
Write Pulse Width High
MIN
tWHWL
tWPH
Write Cycle Time
2
Byte Programming Operation
2
Sector Erase Operation
VCC Set Up Time
1
70
90
120
0
30
35
45
ns
50
50
ns
20
ns
TYP
tWHWH1 tWHWH1
7
µs
TYP
tWHWH2 tWHWH2
1
sec
50
µs
tVCS
MIN
NOTES:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AS29F040
FIGURE 14: AC CHARACTERISTICS, Alternate CE\ Controlled Write
Operation Timings
NOTES:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7\ = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AS29F040
Austin Semiconductor, Inc.
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
TYP
PARAMETER
Sector Erase Time
UNIT
8
sec
8
64
sec
7
300
µs
3.6
10.8
sec
Byte Programming Time
3
2
MAX
1
Chip Erase Time
Chip Programming Time
1
COMMENTS
Excludes 00h programming prior to erasure
Excludes system-level overhead
4
5
NOTES:
1. Typical program and erase times assume the following conditions: 25°C, 5.0V VCC, 1 million cycles. Additionally, programming typicals
assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5V; 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster
than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then does the device set DQ5 = 1.
See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4 for further
information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1 million cycles.
LATCHUP CHARACTERISTIC
PARAMETER
Input voltage with respect to VSS on all I/O pins
VCC Current
NOTES:
MIN
MAX
-1.0V
VCC + 1.0V
-100mA
+100mA
Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
PIN CAPACITANCE
PARAMETER
CONDITIONS
SYMBOL
TYP
MAX
UNIT
VIN = 0
CIN
4
6
pF
VOUT = 0
COUT
8
12
pF
VPP = 0
CIN2
8
12
pF
MIN
10
20
UNIT
Years
Years
Input Capacitance
Output Capacitance
Control Pin Capacitance
NOTES:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz
DATA RETENTION
PARAMETER
Minimum Pattern Data Retention Time
AS29F040
Rev. 2.2 09/07
CONDITIONS
150°C
125°C
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
21
FLASH
Austin Semiconductor, Inc.
AS29F040
MECHANICAL DEFINITIONS*
ASI Case (Package Designator CW)
SMD 5962-96692, Case Outline X
SYMBOL
A
A1
A2
B
B1
D
D1
D2
e
e1
SMD SPECIFICATIONS
MIN
MAX
0.140
0.200
0.019
0.047
0.125
0.193
0.009
0.012
0.588
0.617
1.654
1.686
0.580
0.605
1.492
1.508
0.100 BSC
0.016
0.020
*All measurements are in inches.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
22
FLASH
Austin Semiconductor, Inc.
AS29F040
MECHANICAL DEFINITIONS*
ASI Case (Package Designator F)
SMD 5962-96692, Case Outline U
SYMBOL
A
b
C
D
D1
E
E1
E2
e
L
Q
SMD SPECIFICATIONS
MIN
MAX
--0.125
0.015
0.019
0.004
0.007
0.810
0.830
0.750 TYP
0.405
0.415
0.305
0.315
0.050 TYP
0.050 TYP
0.380
0.420
0.022
0.028
*All measurements are in inches.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
23
FLASH
Austin Semiconductor, Inc.
AS29F040
MECHANICAL DEFINITIONS*
ASI Case (Package Designator DCG)
SMD 5962-96692, Case Outline T
SYMBOL
A
A1
A2
b
C
C2
D
D1
E
E1
E2
E3
e
eA
L
Q
R
SMD SPECIFICATIONS
MIN
MAX
--0.132
0.095
0.125
0.003
0.007
0.015
0.019
0.004
0.007
0.030 TYP
0.810
0.830
0.750 TYP
0.405
0.415
0.525
0.535
0.305
0.315
0.050 TYP
0.050 TYP
0.436 TYP
0.060 TYP
0.022
0.028
0.007 TYP
*All measurements are in inches.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
24
FLASH
AS29F040
Austin Semiconductor, Inc.
MECHANICAL DEFINITION*
ASI Case #208 (Package Designator ECA)
E1
L1
e
D1
D
R
E
A
A1
SYMBOL
A
A1
B1
D
D1
E
E1
e
L
L1
R
L
B1
SMD SPECIFICATIONS
MIN
MAX
0.060
0.080
0.040
0.050
0.022
0.028
0.540
0.560
0.390
0.410
0.442
0.458
0.290
0.310
0.045
0.055
0.045
0.055
0.075
0.095
0.004
0.014
*All measurements are in inches.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
25
FLASH
Austin Semiconductor, Inc.
AS29F040
ORDERING INFORMATION
EXAMPLE:
Device Number
AS29F040
AS29F040
AS29F040
AS29F040
AS29F040
AS29F040
EXAMPLE:
Device Number
AS29F040
AS29F040
AS29F040
AS29F040
AS29F040
AS29F040
EXAMPLE:
Device Number
AS29F040
AS29F040
AS29F040
AS29F040
AS29F040
AS29F040
EXAMPLE:
Device Number
AS29F040
AS29F040
AS29F040
AS29F040
AS29F040
AS29F040
AS29F040CW-55/883C
Package Type
CW
CW
CW
CW
CW
CW
AS29F040F-60/XT
Package Type
F
F
F
F
F
F
Speed ns Process
-55
/*
-60
/*
-70
/*
-90
/*
-120
/*
-150
/*
AS29F040DCG-70/Q
Package Type
DCG
DCG
DCG
DCG
DCG
DCG
Speed ns Process
-55
/*
-60
/*
-70
/*
-90
/*
-120
/*
-150
/*
AS29F040ECA-90/Q
Package Type
ECA
ECA
ECA
ECA
ECA
ECA
*AVAILABLE PROCESSES
XT = Military Temperature Range
IT = Industrial Temperature Range
883C = 883C Processing
Q = QML Processing
AS29F040
Rev. 2.2 09/07
Speed ns Process
-55
/*
-60
/*
-70
/*
-90
/*
-120
/*
-150
/*
Speed ns Process
-55
/*
-60
/*
-70
/*
-90
/*
-120
/*
-150
/*
Temperature
-55oC to +125oC
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
26
FLASH
Austin Semiconductor, Inc.
AS29F040
ASI TO DSCC PART NUMBER
CROSS REFERENCE*
ASI Package Designator CW
ASI Part #
AS29F040CW-55/Q
AS29F040CW-60/Q
AS29F040CW-70/Q
AS29F040CW-90/Q
AS29F040CW-120/Q
AS29F040CW-150/Q
SMD Part #
5962-9669206HXA
5962-9669205HXA
5962-9669204HXA
5962-9669203HXA
5962-9669202HXA
5962-9669201HXA
ASI Package Designator F
ASI Part #
AS29F040F-55/Q
AS29F040F-60/Q
AS29F040F-70/Q
AS29F040F-90/Q
AS29F040F-120/Q
AS29F040F-150/Q
SMD Part #
5962-9669206HUA
5962-9669205HUA
5962-9669204HUA
5962-9669203HUA
5962-9669202HUA
5962-9669201HUA
ASI Package Designator DCG
ASI Part #
AS29F040DCG-55/Q
AS29F040DCG-60/Q
AS29F040DCG-70/Q
AS29F040DCG-90/Q
AS29F040DCG-120/Q
AS29F040DCG-150/Q
SMD Part #
5962-9669206HTA
5962-9669205HTA
5962-9669204HTA
5962-9669203HTA
5962-9669202HTA
5962-9669201HTA
ASI Package Designator ECA
ASI Part #
AS29F040ECA-55/Q
AS29F040ECA-60/Q
AS29F040ECA-70/Q
AS29F040ECA-90/Q
AS29F040ECA-120/Q
AS29F040ECA-150/Q
SMD Part #
5962-9669206H_A
5962-9669205H_A
5962-9669204H_A
5962-9669203H_A
5962-9669202H_A
5962-9669201H_A
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
AS29F040
Rev. 2.2 09/07
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
27