DS08MB200 www.ti.com SNLS197D – MAY 2006 – REVISED MARCH 2013 DS08MB200 Dual 800 Mbps 2:1/1:2 LVDS Mux/Buffer Check for Samples: DS08MB200 FEATURES DESCRIPTION • • The DS08MB200 is a dual-port 1 to 2 repeater/buffer and 2 to 1 multiplexer. High-speed data paths and flow-through pinout minimize internal device jitter and simplify board layout. The differential inputs and outputs interface to LVDS or Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, or to CML or LVPECL signals. 1 2 • • • • • • • Up to 800 Mbps Data Rate per Channel LVDS/BLVDS/CML/LVPECL Compatible Inputs, LVDS Compatible Outputs Low Output Skew and Jitter On-Chip 100Ω Input Termination 15 kV ESD Protection on LVDS Inputs/Outputs Hot Plug Protection Single 3.3V Supply Industrial -40 to +85°C Temperature Range 48-pin WQFN Package The 3.3V supply, CMOS process, and robust I/O ensure high performance at low power over the entire industrial -40 to +85°C temperature range. Switch Fabric B LVDS Backplane or Cable Switch Fabric A LVDS Typical Application Mux Buffer FPGA or ASIC Block Diagram ENA_0 ENB_0 SOA_0 LI_0 SOB_0 ENL_0 SIA_0 LO_0 SIB_0 MUX_S0 Channel 0 Channel 1 Figure 1. DS08MB200 Block Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006–2013, Texas Instruments Incorporated DS08MB200 SNLS197D – MAY 2006 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS Pin Name WQFN Pin Number I/O, Type Description SWITCH SIDE DIFFERENTIAL INPUTS SIA_0+ SIA_0− 30 29 I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SIA_1+ SIA_1− 19 20 I, LVDS Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SIB_0+ SIB_0− 28 27 I, LVDS Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SIB_1+ SIB_1− 21 22 I, LVDS Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. LINE SIDE DIFFERENTIAL INPUTS LI_0+ LI_0− 40 39 I, LVDS Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. LI_1+ LI_1− 9 10 I, LVDS Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or LVPECL compatible. SWITCH SIDE DIFFERENTIAL OUTPUTS SOA_0+ SOA_0− 34 33 O, LVDS Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (1) (2). SOA_1+ SOA_1− 15 16 O, LVDS Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (1) (2). SOB_0+ SOB_0− 32 31 O, LVDS Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (1) (2). SOB_1+ SOB_1− 17 18 O, LVDS Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (1) (2). LINE SIDE DIFFERENTIAL OUTPUTS LO_0+ LO_0− 42 41 O, LVDS Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (1) (2). LO_1+ LO_1− 7 8 O, LVDS Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (1) (2). DIGITAL CONTROL INTERFACE MUX_S0 MUX_S1 38 11 I, LVTTL Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed through to the Line-side. ENA_0 ENA_1 ENB_0 ENB_1 36 13 35 14 I, LVTTL Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side and Bside has a separate enable pin. ENL_0 ENL_1 45 4 I, LVTTL Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a separate enable pin. VDD 6, 12, 37, 43, 48 I, Power VDD = 3.3V ±0.3V. GND 2, 3, 46, 47 (3) I, Power Ground reference for LVDS and CMOS circuitry. For the WQFN package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the WQFN-48 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. N/C 1, 5, 23, 24, 25, 26, 44 POWER (1) (2) (3) 2 No Connect For interfacing LVDS outputs to CML or LVPECL compatible inputs, refer to the APPLICATIONS section of this datasheet. The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS08MB200 device have been optimized for point-to-point backplane and cable applications. Note that the DAP on the backside of the WQFN package is the primary GND connection for the device when using the WQFN package. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS08MB200 DS08MB200 www.ti.com SNLS197D – MAY 2006 – REVISED MARCH 2013 Connection Diagrams N/C GND GND 1 48 ENL_1 2 N/C 3 VDD 4 LO-1+ N/C 5 LO_1- GND 6 LI_1+ GND 7 LI_1- ENL_1 8 MUX_S1 N/C 9 VDD VDD ENB_1 LO-1+ 12 11 10 13 LO_1- ENA_1 Top View LI_1+ LI_1- MUX_S1 VDD Top View 47 GND ENB_1 SOA_1+ 15 46 GND SOA_1+ GND SOA_1- 16 45 ENL_0 SOA_1- ENL_0 SOB_1+ 17 44 N/C SOB_1+ SOB_1- 18 43 VDD SOB_1- VDD SIA_1+ 19 42 LO_0+ SIA_1+ LO_0+ SIA_1- 20 41 LO_0- SIA_1- LO_0- SIB_1+ 21 40 LI_0+ SIB_1+ LI_0+ SIB_1- 22 39 LI_0- SIB_1- LI_0- N/C 23 38 MUX_S0 N/C MUX_S0 N/C 37 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD N/C VDD Figure 2. WQFN Package See Package Number RHS0048A DAP = GND VDD Channel 1 GND N/C ENA_0 ENB_0 SOA_0+ SOA_0- SOB_0+ SOB_0- SIA_0+ SIA_0- SIB_0+ SIB_0- N/C Channel 0 N/C ENB_0 SOA_0+ SOA_0- SOB_0+ SOB_0- SIA_0+ SIA_0- SIB_0+ SIB_0- N/C DAP (GND) ENA_0 ENA_1 14 N/C VDD Figure 3. Directional Signal Paths (Refer to pin names for signal polarity) TRI-STATE and Powerdown Modes The DS08MB200 has output enable control on each of the six onboard LVDS output drivers. This control allows each output individually to be placed in a low power TRI-STATE mode while the device remains active, and is useful to reduce power consumption on unused channels. In TRI-STATE mode, some outputs may remain active while some are in TRI-STATE. When all six of the output enables (all drivers on both channels) are deasserted (LOW), then the device enters a Powerdown mode that consumes only 0.5mA (typical) of supply current. In this mode, the entire device is essentially powered off, including all receiver inputs, output drivers and internal bandgap reference generators. When returning to active mode from Powerdown mode, there is a delay until valid data is presented at the outputs because of the ramp to power up the internal bandgap reference generators. Any single output enable that remains active will hold the device in active mode even if the other five outputs are in TRI-STATE. When in Powerdown mode, any output enable that becomes active will wake up the device back into active mode, even if the other five outputs are in TRI-STATE. Input Failsafe Biasing External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. Please refer to application note SNLA051B AN-1194, “Failsafe Biasing of LVDS Interfaces” for more information. Output Characteristics The output characteristics of the DS08MB200 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS08MB200 3 DS08MB200 SNLS197D – MAY 2006 – REVISED MARCH 2013 www.ti.com MULTIPLEXER TRUTH TABLE (1) (2) Data Inputs (3) Output SIB_0 MUX_S0 ENL_0 LO_0 X valid 0 1 SIB_0 valid X 1 1 SIA_0 X (1) (2) Control Inputs SIA_0 X X 0 (3) Z Same functionality for channel 1 X = Don't Care Z = High Impedance (TRI-STATE) When all enable inputs from both channels are Low, the device enters a powerdown mode. Refer to the TRI-STATE and Powerdown Modes section. REPEATER/BUFFER TRUTH TABLE (1) (2) Data Input LI_0 (1) (2) (3) Control Inputs ENA_0 Outputs ENB_0 SOA_0 Z (3) SOB_0 Z (3) X 0 0 valid 0 1 Z valid 1 0 LI_0 Z valid 1 1 LI_0 LI_0 LI_0 Same functionality for channel 1 X = Don't Care Z = High Impedance (TRI-STATE) When all enable inputs from both channels are Low, the device enters a powerdown mode. Refer to the TRI-STATE and Powerdown Modes section. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage (VDD) −0.3V to +4.0V CMOS Input Voltage -0.3V to (VDD+0.3V) LVDS Receiver Input Voltage (2) -0.3V to (VDD+0.3V) LVDS Driver Output Voltage -0.3V to (VDD+0.3V) LVDS Output Short Circuit Current +40 mA Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Solder, 4sec) 260°C Max Pkg Power Capacity @ 25°C 5.2W Thermal Resistance (θJA) 24°C/W Package Derating above +25°C ESD Last Passing Voltage 41.7mW/°C HBM, 1.5kΩ, 100pF 15kV EIAJ, 0Ω, 200pF 250V CDM (1) (2) 8kV LVDS pins to GND only 1000V Absolute maximum ratings are those values beyond which damage to the device may occur. Texas Instruments does not recommend operation of products outside of recommended operation conditions. VID max < 2.4V RECOMMENDED OPERATING CONDITIONS Supply Voltage (VCC) Input Voltage (VI) 3.0V to 3.6V (1) 0V to VCC Output Voltage (VO) Operating Temperature (TA) (1) 4 0V to VCC Industrial −40°C to +85°C VID max < 2.4V Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS08MB200 DS08MB200 www.ti.com SNLS197D – MAY 2006 – REVISED MARCH 2013 ELECTRICAL CHARACTERISTICS Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (1) Max Units V LVTTL DC SPECIFICATIONS (MUX_Sn, ENA_n, ENB_n, ENL_n) VIH High Level Input Voltage 2.0 VDD VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA CIN1 Input Capacitance Any Digital Input Pin to VSS 3.5 pF COUT1 Output Capacitance Any Digital Output Pin to VSS 5.5 pF VCL Input Clamp Voltage ICL = −18 mA −0.8 V −1.5 LVDS INPUT DC SPECIFICATIONS (SIA±, SIB±, LI±) VTH Differential Input High Threshold (2) VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V VTL Differential Input Low Threshold (2) VCM = 0.8V or 1.2V or 3.55V, VDD = 3.6V −100 VID Differential Input Voltage VCM = 0.8V to 3.55V, VDD = 3.6V 100 VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.6V 0.05 CIN2 Input Capacitance IN+ or IN− to VSS IIN Input Current VIN = 3.6V, VDD = VDDMAX −15 +15 µA VIN = 0V, VDD = VDDMAX −15 +15 µA 500 mV 35 mV 1.475 V 35 mV -40 mA 0 100 0 mV mV 2400 3.55 3.5 mV V pF LVDS OUTPUT DC SPECIFICATIONS (SOA_n±, SOB_n±, LO_n±) VOD Differential Output Voltage (2) ΔVOD Change in VOD between Complementary States RL is the internal 100Ω between OUT+ and OUT− 250 360 -35 (3) VOS Offset Voltage ΔVOS Change in VOS between Complementary States 1.05 1.22 IOS Output Short Circuit Current OUT+ or OUT− Short to GND −21 COUT2 Output Capacitance OUT+ or OUT− to GND when TRISTATE 5.5 All inputs and outputs enabled and active, terminated with differential load of 100Ω between OUT+ and OUT-. 225 275 mA ENA_0 = ENB_0 = ENL_0= ENA_1 = ENB_1 = ENL_1 = L 0.6 4.0 mA 170 250 ps 170 250 ps 1.0 2.5 ns 1.0 2.5 ns -35 pF SUPPLY CURRENT (Static) ICC Supply Current ICCZ Supply Current - Powerdown Mode SWITCHING CHARACTERISTICS—LVDS OUTPUTS tLHT Differential Low to High Transition Time tHLT Differential High to Low Transition Time tPLHD Differential Low to High Propagation Delay tPHLD Differential High to Low Propagation Delay tSKD1 Pulse Skew |tPLHD–tPHLD| (4) 25 75 ps tSKCC Output Channel to Channel Skew Difference in propagation delay (tPLHD or tPHLD) among all output channels. (4) 50 115 ps (1) (2) (3) (4) Use an alternating 1 and 0 pattern at 200 Mb/s, measure between 20% and 80% of VOD. (4) Use an alternating 1 and 0 pattern at 200 Mb/s, measure at 50% VOD between input to output. Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested. Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Not production tested. Ensured by statistical analysis on a sample basis at the time of characterization. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS08MB200 5 DS08MB200 SNLS197D – MAY 2006 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Over recommended operating supply and temperature ranges unless other specified. Symbol tJIT Parameter Jitter (5) Conditions RJ - Alternating 1 and 0 at 400 MHz Min (6) Typ (1) Max Units 1.3 1.5 psrms DJ - K28.5 Pattern, 800 Mbps (7) 15 34 psp-p TJ - PRBS 27-1 Pattern, 800 Mbps (8) 16 34 psp-p tON LVDS Output Enable Time Time from ENA_n, ENB_n, or ENL_n to OUT± change from TRI-STATE to active. 0.5 1.5 µs tON2 LVDS Output Enable time from powerdown mode Time from ENA_n, ENB_n, or ENL_n to OUT± change from Powerdown to active 10 20 µs tOFF LVDS Output Disable Time Time from ENA_n, ENB_n, or ENL_n to OUT± change from active to TRI-STATE or powerdown. 12 ns (5) (6) (7) (8) 6 Jitter is not production tested, but ensured through characterization on a sample basis. Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 400 MHz, tr = tf = 50ps (20% to 80%). Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500mV, K28.5 pattern at 800 Mbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage = VID = 500mV, 27-1 PRBS pattern at 800 Mbps, tr = tf = 50ps (20% to 80%). Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS08MB200 DS08MB200 www.ti.com SNLS197D – MAY 2006 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Current vs. Bit Data Rate Total Jitter vs. Temperature POWER SUPPLY CURRENT (mA) 350 300 250 200 150 100 50 0 0 200 400 600 800 BIT DATA RATE (Mbps) 7-1 Dynamic power supply current was measured with all channels active Total Jitter measured at 0V differential while running a PRBS 2 pattern with one channel active, all other channels are disabled. VDD = and toggling at the bit data rate. Data pattern has no effect on the power consumption. VDD = 3.3V, TA = +25°C, VID = 0.5V, VCM = 1.2V. 3.3V, VID = 0.5V, VCM = 1.2V, 800 Mbps data rate. Stimulus and fixture jitter has been subtracted. Figure 4. Figure 5. Total Jitter vs. Bit Data Rate Total Jitter measured at 0V differential while running a PRBS 27-1 pattern with one channel active, all other channels are disabled. VDD = 3.3V, TA = +25°C, VID = 0.5V. Stimulus and fixture jitter has been subtracted. Figure 6. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS08MB200 7 DS08MB200 SNLS197D – MAY 2006 – REVISED MARCH 2013 www.ti.com APPLICATIONS Interfacing LVPECL to LVDS An LVPECL driver consists of a differential pair with coupled emitters connected to GND via a current source. This drives a pair of emitter-followers that require a 50 ohm to VCC-2.0 load. A modern LVPECL driver will typically include the termination scheme within the device for the emitter follower. If the driver does not include the load, then an external scheme must be used. The 1.3 V supply is usually not readily available on a PCB, therefore, a load scheme without a unique power supply requirement may be used. 50: 15MB200 LVPECL 50: R1 150: R2 150: Figure 7. DC Coupled LVPECL to LVDS Interface Figure 7 is a separated π termination scheme for a 3.3 V LVPECL driver. R1 and R2 provides proper DC load for the driver emitter followers, and may be included as part of the driver device. The DS08MB200 includes a 100 ohm input termination for the transmission line. The common mode voltage will be at the normal LVPECL levels – around 2 V. This scheme works well with LVDS receivers that have rail-to-rail common mode voltage, VCM, range. Most Texas Instruments LVDS receivers have wide VCM range. The exceptions are noted in devices’ respective datasheets. Those LVDS devices that do have a wide VCM range do not vary in performance significantly when receiving a signal with a common mode other than standard LVDS VCM of 1.2 V. 0.1 PF 50: 15MB200 LVPECL 50: R1 150: R2 150: 0.1 PF Figure 8. AC Coupled LVPECL to LVDS Interface An AC coupled interface is preferred when transmitter and receiver ground references differ more than 1 V. This is a likely scenario when transmitter and receiver devices are on separate PCBs. Figure 8 illustrates an AC coupled interface between a LVPECL driver and LVDS receiver. R1 and R2, if not present in the driver device, provide DC load for the emitter followers and may range between 140-220 ohms for most LVPECL devices for this particular configuration. The DS08MB200 includes an internal 100 ohm resistor to terminate the transmission line for minimal reflections. The signal after ac coupling capacitors will swing around a level set by internal biasing resistors (i.e. fail-safe) which is either VDD/2 or 0 V depending on the actual failsafe implementation. If internal biasing is not implemented, the signal common mode voltage will slowly wander to GND level. 8 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS08MB200 DS08MB200 www.ti.com SNLS197D – MAY 2006 – REVISED MARCH 2013 Interfacing LVDS to LVPECL An LVDS driver consists of a current source (nominal 3.5mA) which drives a CMOS differential pair. It needs a differential resistive load in the range of 70 to 130 ohms to generate LVDS levels. In a system, the load should be selected to match transmission line characteristic differential impedance so that the line is properly terminated. The termination resistor should be placed as close to the receiver inputs as possible. When interfacing an LVDS driver with a non-LVDS receiver, one only needs to bias the LVDS signal so that it is within the common mode range of the receiver. This may be done by using separate biasing voltage which demands another power supply. Some receivers have required biasing voltage available on-chip (VT, VTT or VBB). 50: LVPECL 15MB200 50: R1 50: R2 50: VT Figure 9. DC Coupled LVDS to LVPECL Interface Figure 9 illustrates interface between an LVDS driver and a LVPECL with a VT pin available. R1 and R2, if not present in the receiver, provide proper resistive load for the driver and termination for the transmission line, and VT sets desired bias for the receiver. VDD 0.1PF R1 83: R2 83: 50: LVPECL 15MB200 50: 0.1PF R3 130: R4 130: Figure 10. AC Coupled LVDS to LVPECL Interface Figure 10 illustrates AC coupled interface between an LVDS driver and LVPECL receiver without a VT pin available. The resistors R1, R2, R3, and R4, if not present in the receiver, provide a load for the driver, terminate the transmission line, and bias the signal for the receiver. The bias networks shown above for LVPECL drivers and receivers may or may not be present within the driver device. The LVPECL driver and receiver specification must be reviewed closely to ensure compatibility between the driver and receiver terminations and common mode operating ranges. Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: DS08MB200 9 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS08MB200TSQ/NOPB ACTIVE WQFN RHS 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 08MB200 DS08MB200TSQX/NOPB ACTIVE WQFN RHS 48 2500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 08MB200 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS08MB200TSQ/NOPB WQFN RHS 48 250 178.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 DS08MB200TSQX/NOPB WQFN RHS 48 2500 330.0 16.4 7.3 7.3 1.3 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS08MB200TSQ/NOPB WQFN RHS DS08MB200TSQX/NOPB WQFN RHS 48 250 213.0 191.0 55.0 48 2500 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA RHS0048A SQA48A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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