AD ADV7300A Multiformat sd, progressive scan/hdtv video encoder with six nsvâ ¢ 12-bit dac Datasheet

a
Multiformat SD, Progressive Scan/HDTV
Video Encoder with Six NSV™ 12-Bit DACs
ADV7300A/ADV7301A
FEATURES
High Definition Input Formats
YCrCb Compliant to SMPTE293M (525 p),
ITU-R.BT1358 (625 p), SMPTE274M (1080 i),
SMPTE296M (720 p), and Any Other High Definition
Standard Using Async Timing Mode
RGB in 3 10-Bit 4:4:4 Format
BTA T-1004 EDTV2 525 p Parallel
High Definition Output Formats (525 p/625 p/720 p/1080 i)
YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB + H/V (HDTV 5-Wire Format)
CGMS-A (720 p/1080 i)
Macrovision Rev 1.0 (525 p/625 p)*
CGMS-A (525 p)
Standard Definition Input Formats
CCIR-656 4:2:2 8-/10-Bit Parallel Input
CCIR-601 4:2:2 16-/20-Bit Parallel Input
Standard Definition Output Formats
Composite NTSC M, N;
PAL M, N, B, D, G, H, I, PAL-60
SMPTE170M NTSC Compatible Composite Video
ITU-R.BT470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YUV (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1*
CGMS/WSS
Closed Captioning
GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling (108 MHz/148.5 MHz)
On-Board Voltage Reference
6 NSV Precision Video 12-Bit DACs
2-Wire Serial MPU Interface
Dual I/O Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-LQFP Package
Lead-Free Product
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
STANDARD DEFINITION
CONTROL BLOCK
S9–S0
COLOR CONTROL
BRIGHTNESS
DNR
GAMMA
PROGRAMMABLE FILTERS
SD TEST PATTERN
D
E
M
U
X
PROGRAMMABLE
RGB MATRIX
Y9–Y0
C9–C0
S_HSYNC
S_VSYNC
S_BLANK
P_HSYNC
P_VSYNC
P_BLANK
CLKIN_A
CLKIN_B
D
E
M
U
X
HIGH DEFINITION
CONTROL BLOCK
HD TEST PATTERN
TIMING
GENERATOR
COLOR CONTROL
ADAPTIVE FILTER CTRL
SHARPNESS FILTER
PLL
ADV7300A/
ADV7301A
12-BIT
DAC
O
V
E
R
S
A
M
P
L
I
N
G
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
12-BIT
DAC
I2C
INTERFACE
GENERAL DESCRIPTION
The ADV7300A/ADV7301A is a high speed, digital-to-analog
encoder on a single monolithic chip. It includes six high speed
video D/A converters with TTL compatible inputs.
The ADV7300A/ADV7301A has three separate 10-bit wide input
ports that accept data in high definition and/or standard definition video format. For all standards, external horizontal, vertical,
and blanking signals, or EAV/SAV timing codes, control the
insertion of appropriate synchronization signals into the digital
data stream and therefore the output signals.
APPLICATIONS
High End DVD Players
SD/Program Scan/HDTV Display Devices
SD/Program Scan/HDTV Set-Top Boxes
SD/HDTV Studio Equipment
NSV (Noise Shaped Video) is a trademark of Analog Devices, Inc.
*ADV7300A Only
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
ADV7300A/ADV7301A
DETAILED FEATURES
High Definition Programmable Features (720 p/1080 i)
2 Oversampling (148.5 MHz)
Internal Test Pattern Generator (Color Hatch, Black
Bar, Flat Field/Frame)
Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720 p/1080 i)
High Definition Programmable Features (525 p/625 p)
4 Oversampling (108 MHz Output)
Internal Test Pattern Generator (Color Hatch, Black
Bar, Flat Frame)
Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
HD PIXEL
INPUT
CLKIN_B
Y
DEINTER- CR
LEAVE
CB
TEST
PATTERN
P_HSYNC
P_VSYNC
P_BLANK
TIMING
GENERATOR
S_HSYNC
S_VSYNC
S_BLANK
TIMING
GENERATOR
CLKIN_A
SD PIXEL
INPUT
SHARPNESS
AND
ADAPTIVE
FILTER
CONTROL
Macrovision Rev 1.0 (525 p/625 p)*
CGMS-A (525 p)
Standard Definition Programmable Features
8 Oversampling (108 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and UV Output Delay
Gamma Correction
Digital Noise Reduction
Multiple Chroma and Luma Filters
Luma-SSAF™ Filter with Programmable Gain/
Attenuation
UV SSAF
Separate Pedestal Control on Component and
Composite/S-Video Outputs
VCR FF/RW Sync Mode
Macrovision Rev 7.1*
CGMS/WSS
Closed Captioning
DAC
Y COLOR
CR COLOR
CB COLOR
PS 4
HDTV 2
4:2:2
TO
4:4:4
DAC
DAC
CLOCK
CONTROL
AND PLL
UV SSAF
CB
DEINTER- CR
LEAVE
Y
TEST
PATTERN
DAC
RGB
MATRIX
SD 8
DAC
DNR
GAMMA
COLOR
CONTROL
DAC
SYNC
INSER- U
TION
V
CGMS
WSS
LUMA
AND
CHROMA
FILTERS
2 OVERSAMPLING
FSC
MODULATION
Figure 1. Functional Block Diagram
HDTV
SD
Standard Definition Video, conforming to
ITU-R.BT601/ITU-R.BT656.
High Definition Television Video, conforming to
SMPTE274M or SMPTE296M.
YCrCb
SD or HD Component Digital Video.
HD
High Definition Video, i.e., Progressive Scan or HDTV.
YPrPb
HD Component Analog Video.
PS
Progressive Scan Video, conforming to SMPTE293M
or ITU-R.BT1358.
YUV
SD Component Analog Video.
TERMS USED IN THIS DATA SHEET
SSAF is a trademark of Analog Devices, Inc.
*ADV7300A Only
–2–
REV. A
ADV7300A/ADV7301A–SPECIFICATIONS
(VAA = VDD = 2.375 V–2.625 V, VDD_IO = 2.375 V–3.600 V, VREF = 1.235 V, RSET = 760 , RLOAD = 150 , TMIN to TMAX (0C to 70C), unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions
Bits
LSB
LSB
LSB
VAA = 2.5 V
VAA = 2.5 V
1
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
Differential Nonlinearity, +ve2
Differential Nonlinearity, –ve2
DIGITAL OUTPUTS
Output Low Voltage, VOL
Output High Voltage, VOH
Three-State Leakage Current
Three-State Output Capacitance
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current
Input Capacitance, CIN
ANALOG OUTPUTS
Full-Scale Output Current
Output Current Range
Full-Scale Output Current
Output Current Range
DAC to DAC Matching
Output Compliance Range, VOC
Output Capacitance, COUT
VOLTAGE REFERENCE
Reference Range, VREF
POWER REQUIREMENTS
Normal Power Mode
IDD4
IDD_IO
IAA5,6
Sleep Mode
IDD
IAA
IDD_IO
Power Supply Rejection Ratio
12
± 2.0
0.25
2.0
0.4 [0.4]3
3
2.4 [2.0]
± 1.0
2
2
0.8
1
2
8.2
8.2
4.1
4.1
0
1.15
8.7
8.7
4.35
4.35
2.0
1.0
7
1.235
93
52
84
90
99
108
0.2
70
130
10
110
0.01
9.2
9.2
4.6
4.6
1.4
1.3
110
75
V
V
µA
pF
V
V
µA
pF
mA
mA
mA
mA
%
V
pF
ISINK = 3.2 mA
ISOURCE = 400 µA
VIN = 0.4 V, 2.4 V
VIN = 2.4 V
RSET1, 2 = 1520 Ω
RSET1, 2 = 1520 Ω
V
mA
mA
mA
mA
mA
mA
mA
mA
SD Only [8⫻]
PS Only [4⫻]
HDTV Only [2⫻]
SD and PS
SD [8⫻] and HDTV
SD and HDTV [2⫻]
µA
µA
µA
%/%
NOTES
1
Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.
2
DNL measures the deviation of the actual DAC o/p voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for –ve DNL, the
actual step values lie below the ideal step value.
3
Value in brackets for V DD_IO = 2.375 V to 2.750 V.
4
IDD or the circuit current is the continuous current required to drive the digital core without the I PLL.
5
IAA is the total current required to supply all DACs including the V REF and PLL circuitry.
6
All DACs on.
Specifications subject to change without notice.
REV. A
–3–
ADV7300A/ADV7301A
DYNAMIC SPECIFICATIONS
Parameter
(VAA = VDD = 2.375 V–2.625 V, VDD_IO = 2.375 V–3.600 V, VREF = 1.235 V, RSET = 760 ,
RLOAD = 150 , TMIN to TMAX (0C to 70C), unless otherwise noted.)
Min
Typ
Max
Unit
Test Conditions
PROGRESSIVE SCAN MODE
Luma Bandwidth
Chroma Bandwidth
SNR
SNR
SNR
12.5
5.8
62
78
72
MHz
MHz
dB
dB
dB
Luma Ramp Unweighted
Flat Field up to 5 MHz
Flat Field Full Bandwidth
HDTV MODE
Luma Bandwidth
Chroma Bandwidth
SNR
SNR
SNR
30
13.75
62
78
72
MHz
MHz
dB
dB
dB
Luma Ramp Unweighted
Flat Field up to 5 MHz
Flat Field Full Bandwidth
STANDARD DEFINITION MODE
Hue Accuracy
Color Saturation Accuracy
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma/Luma Intermodulation
Chroma/Luma Gain Inequality
Chroma/Luma Delay Inequality
Luminance Nonlinearity
Chroma AM Noise
Chroma PM Noise
Differential Gain
Differential Phase
SNR
SNR
SNR
0.2
0.5
± 0.4
± 0.3
± 0.05
± 98
0.9
± 0.4
84
74
0.6
1.4
62
78
72
Degrees
%
%
Degrees
%
%
ns
%
dB
dB
%
Degrees
dB
dB
dB
Referenced to 40 IRE
NTSC
NTSC
Luma Ramp
Flat Field up to 5 MHz
Flat Field Full Bandwidth
Specifications subject to change without notice.
–4–
REV. A
ADV7300A/ADV7301A
(VAA = VDD = 2.375 V–2.625 V, VDD_IO = 2.375 V–3.600 V, VREF = 1.235 V, RSET = 760 , RLOAD = 150 ,
MIN to TMAX (0C to 70C), unless otherwise noted.)
TIMING SPECIFICATIONS T
Parameter
Min
Typ
Max
Unit
400
kHz
µs
µs
µs
Test Conditions
1
MPU PORT
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
0
0.6
1.3
0.6
Setup Time (Start Condition), t4
0.6
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
100
300
300
0.6
100
ANALOG OUTPUTS
Analog Output Delay2
Output Skew
CLOCK CONTROL AND PIXEL PORT3
fCLK
fCLK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Output Access Time, t13
Output Hold Time, t14
Pipeline Delay
µs
8
1
First Clock Generated after
This Period
Relevant for Repeated Start
Condition
ns
ns
ns
µs
ns
ns
ns
27
61
62.5
66.5
33
MHz
MHz
% 1 clkcycle
% 1 clkcycle
ns
ns
ns
ns
clkcycles
clkcycles
clkcycles
clkcycles
43.5
36
clkcycles
clkcycles
81
40
40
2.0
2.0
14
4.0
Progressive Scan Mode
HDTV Mode/Async Mode
SD [2⫻]
SD [8⫻]
SD Component Filter [8⫻]
PS [1⫻], HD [1⫻], Async
Timing Mode
PS [4⫻]
HD [2⫻]
NOTES
1
Guaranteed by characterization.
2
Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3
Data: C[9:0]; S[9:0]; Y[9:0]
Control: P_HSYNC; P_ VSYNC; P_BLANK; S_HSYNC; S_VSYNC; S_BLANK
Specifications subject to change without notice.
REV. A
–5–
ADV7300A/ADV7301A
CLKIN_A
t9
CONTROL
I/PS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
t11
CONTROL
O/PS
t13
S_HSYNC,
S_VSYNC
t14
t9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME
Figure 2. HD 4:2:2 Input Data Format Timing Diagram, Input Mode: PS Input Only, HDTV
Input Only (Input Mode at Subaddress 01h = 001 or 010)
CLKIN_A
t9
CONTROL
I/PS
Y9–Y0
Y0
Y1
Y2
C9–C0
Cb0
Cb1
Cb2
S9–S0
Cr0
Cr1
Cr2
t11
CONTROL
O/PS
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Yxxx
Yxxx
Cb3
Cbxxx
Cbxxx
Cr3
Crxxx
Crxxx
t12
t13
S_HSYNC,
S_VSYNC
t14
t9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME
Figure 3. HD 4:4:4 YCrCb Input Data Format Timing Diagram, Input Mode: PS Input Only,
HDTV Input Only (Input Mode at Subaddress 01h = 001 or 010)
–6–
REV. A
ADV7300A/ADV7301A
CLKIN_A
t9
CONTROL
I/PS
Y9–Y0
G0
G1
G2
G3
Gxxx
Gxxx
C9–C0
B0
B1
B2
B3
Bxxx
Bxxx
S9–S0
R0
R1
R2
Rxxx
Rxxx
t11
CONTROL
O/PS
t10
P_HSYNC,
P_VSYNC,
P_BLANK
t12
t13
S_HSYNC,
S_VSYNC
t14
t9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME
Figure 4. HD 4:4:4 RGB Input Data Format Timing Diagram, HD RGB Input Enabled (Input
Mode at Subaddress 01h = 001 or 010)
CLKIN_B
t9
CONTROL
I/PS
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Cb0
Y0
Cr0
Y1
t12
t11
CONTROL
O/PS
Crxxx
Yxxx
t12
t11
t13
S_HSYNC,
S_VSYNC
t14
t9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME
Figure 5. PS 4:2:2 1 ⫻ 10-Bit Interleaved @ 27 MHz, Input Mode: PS Input Only (Input
Mode at Subaddress 01h = 100)
REV. A
–7–
ADV7300A/ADV7301A
CLKIN_A
t10
t9
CONTROL
I/PS
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Cb0
t11
Y0
Cr0
t12
Y1
Crxxx
Yxxx
t13
t14
CONTROL
O/PS
S_HSYNC,
S_VSYNC
t9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME
Figure 6. PS 4:2:2 1 ⫻ 10-Bit Interleaved @ 54 MHz, Input Mode: PS 54 MHz Input (Input
Mode at Subaddress 01h = 111)
CLKIN_A
t9
CONTROL
I/PS
t10
t12
S_HSYNC,
S_VSYNC,
S_BLANK
S9–S2
IN SLAVE
MODE
Cb
Y
Cr
Y
t11
CONTROL
O/PS
Cb
Y
t13
IN MASTER/SLAVE
MODE WITH
EAV/SAV
S_HSYNC,
S_VSYNC
t14
Figure 7. 8-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000)
–8–
REV. A
ADV7300A/ADV7301A
CLKIN_A
@ 27MHz
t9
CONTROL
I/PS
t12
t10
S_HSYNC,
S_VSYNC,
S_BLANK
IN SLAVE
MODE
S9–S2
Y0
Y1
Y2
Y9–Y2
Cb0
Cr0
Cb2
t11
CONTROL
O/PS
Y3
Cr2
t13
IN MASTER/SLAVE
MODE WITH
EAV/SAV
S_HSYNC,
S_VSYNC
t14
Figure 8. 16-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000)
CLKIN_B
t9
CONTROL
I/PS
t12
t10
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
Y0
Y1
Y2
Y3
Y4
Y5
C9–C0
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
HD INPUT
t11
CLKIN_A
CONTROL
I/PS
S_HSYNC,
S_VSYNC,
S_BLANK
S9–S0
t9
t12
t10
SD INPUT
Cb0
Y0
Y1
Cr0
Cb1
Y2
t11
Figure 9. SD and HD Simultaneous Input, Input Mode: SD and PS 20-Bit or SD and HDTV (Input Mode at
Subaddress 01h = 011, 101, or 110)
REV. A
–9–
ADV7300A/ADV7301A
CLKIN_B
t10
t9
CONTROL
I/PS
P_HSYNC,
P_VSYNC,
P_BLANK
Y9–Y0
PS INPUT
Cb0
t11
Y0
Cr0
Crxxx
Y1
t12
Yxxx
t12
t11
CLKIN_A
CONTROL
I/PS
S_HSYNC,
S_VSYNC,
S_BLANK
S9–S0
t9
t12
t10
SD INPUT
Cb0
Y0
Cr0
Cb1
Y1
Y2
t11
Figure 10. SD and HD Simultaneous Input, Input Mode: SD and PS 10-Bit (Input Mode at Subaddress 01h = 100)
P_HSYNC
P_VSYNC
a
P_BLANK
Y9–Y0
Cb
Y
Cr
Y
b
a = 32 CLKCYCLES FOR 525p
a = 24 CLKCYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLKCYCLES FOR 525p
b(MIN) = 264 CLKCYCLES FOR 625p
Figure 11. PS 4:2:2 1 ⫻ 10-Bit Interleaved @ 54 MHz Input Timing Diagram
–10–
REV. A
ADV7300A/ADV7301A
P_HSYNC
P_VSYNC
a
P_BLANK
Y9–Y0
Y0
Y1
Y2
Y3
S9–S0
Cr0
Cr1
Cr2
Cr3
C9–C0
Cb0
Cb1
Cb2
Cb3
Cb
Y
Cr
Y
b
a = 16 CLKCYCLES FOR 525p
a = 12 CLKCYCLES FOR 626p
a = 44 CLKCYCLES FOR 1080i
a = 70 CLKCYCLES FOR 720p
AS RECOMMENDED BY STANDARD
b(MIN) = 122 CLKCYCLES FOR 525p
b(MIN) = 132 CLKCYCLES FOR 625p
b(MIN) = 236 CLKCYCLES FOR 1080i
b(MIN) = 300 CLKCYCLES FOR 720p
Figure 12. HD Input Timing Diagram
HSYNC
FIELD
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
BLANK
PIXEL
DATA
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 13. SD Timing Input for Timing Mode 1
t3
t5
t3
SDA
t1
t6
SCLK
t2
t4
t7
Figure 14. MPU Port Timing Diagram
REV. A
–11–
t8
ADV7300A/ADV7301A
The ADV7300A/ADV7301A is a lead-free environmentally
friendly product. It is manufactured using the most up to date
materials and processes. The coating on the leads of each device
is 100% pure tin electroplate. The device is suitable for lead-free
applications and is able to withstand surface-mount soldering up
to 255°C (± 5°C). In addition, it is backward compatible with
conventional tin-lead soldering processes. This means that the
electroplated tin coating can be soldered with tin-lead solder
pastes at conventional reflow temperatures of 220°C to 235°C.
ABSOLUTE MAXIMUM RATINGS*
VAA to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to –0.3 V
VDD_IO to IO_GND . . . . . . . . . . . . . –0.3 V to VDD_IO + 0.3 V
Ambient Operating Temperature (TA) . . . . . . . 0°C to +70°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Infrared Reflow Soldering (20 sec) . . . . . . . . . . . . . . . . 260°C
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
THERMAL CHARACTERISTICS
θJC = 11ºC/W
θJA = 47ºC/W
Model
Package Description
Package Option
ADV7300AKST
ADV7301AKST
Plastic Quad Flatpack
Plastic Quad Flatpack
ST-64B
ST-64B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7300A/ADV7301A features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
S_VSYNC
S_HSYNC
S0
S1
S2
S3
VDD
S4
DGND
S5
S6
S7
S8
S9
CLKN_B
GND_IO
PIN CONFIGURATION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 S_BLANK
VDD_IO 1
Y0 2
PIN 1
IDENTIFIER
Y1 3
47 RSET1
46 VREF
Y2 4
45 COMP1
Y3 5
44 DAC A
43 DAC B
Y4 6
Y5 7
ADV7300A/ADV7301A
42 DAC C
Y6 8
TOP VIEW
(Not to Scale)
41 VAA
40 AGND
Y7 9
VDD 10
DGND 11
39 DAC D
Y8 12
37 DAC F
Y9 13
36 COMP2
C0 14
35 RSET2
34 EXT_LF
38 DAC E
C1 15
33 RESET
C2 16
CLKIN_A
RTC_SCR_TR
C9
C8
C7
C6
C5
P_VSYNC
P_BLANK
P_HSYNC
SCLK
SDA
I2C
ALSB
C4
C3
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Input/Output
Function
1
VDD_IO
P
Power Supply for Digital Inputs and Outputs
2–9, 12, 13
Y0–Y9
I
10-Bit Progressive Scan/HDTV Input Port for Y Data. The LSBs are set up on
Pins Y0 and Y1. In Default Mode, the input on this port is output on DAC D.
10, 56
VDD
P
Digital Power Supply
11, 57
DGND
G
Digital Ground
–12–
REV. A
ADV7300A/ADV7301A
Pin No.
Mnemonic
Input/Output
Function
14–18, 26–30
C0–C9
I
10-Bit Progressive Scan/HDTV Input Port for CrCb color data in 4:2:2 Input
Mode. In 4:4:4 Input Mode, this input port is used for the Cb (Blue/U) data.
The LSBs are set up on Pins C0 and C1. In Default Mode, the input on this
port is output on DAC E.
19
I2 C
I
This input pin must be tied high (VDD_IO) for the ADV7300A/ADV7301A to
interface over the I2C port.
20
ALSB
I/O
TTL Address Input. This signal sets up the LSB of the MPU address. When
this pin is tied low, the I2C filter is activated, which reduces noise on the I2C interface.
21
SDA
I/O
MPU Port Serial Data Input/Output
22
SCLK
I
MPU Port Serial Interface Clock Input
23
P_HSYNC
I
Video Horizontal Sync Control Signal for HD Sync in Simultaneous SD/HD
Mode and HD Only Mode
24
P_VSYNC
I
Video Vertical Sync Control Signal for HD Sync in Simultaneous SD/HD
Mode and HD Only Mode
25
P_BLANK
I
Video Blanking Control Signal for HD Sync in Simultaneous SD/HD Mode
and HD Only Mode
31
RTC_SCR_TR
I
Multifunctional Input: Realtime Control (RTC) Input, Timing Reset Input,
and Subcarrier Reset Input
32
CLKIN_A
I
Pixel Clock Input for HD Only or SD Only Modes
33
RESET
I
This input resets the on-chip timing generator and sets the ADV7300A/
ADV7301A into default register setting. Reset is an active low signal.
34
EXT_LF
I
External Loop Filter for the internal PLL
35, 47
RSET2, 1
I
A 760 Ω resistor must be connected from this pin to AGND and is used to
control the amplitudes of the DAC outputs.
36, 45
COMP2, 1
O
Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to VAA.
37
DAC F
O
In SD Only Mode: Chroma/Red/V Analog Output, in HD Only Mode and
Simultaneous HD/SD: Pb/Blue (HD) Analog Output
38
DAC E
O
In SD Only Mode: Luma/Blue/U Analog Output, in HD Only Mode and
Simultaneous HD/SD: Pr/Red (HD) Analog Output
39
DAC D
O
In SD Only Mode: CVBS/Green/Y Analog Output, in HD Only Mode and
Simultaneous HD/SD: Y/Green (HD) Analog Output
40
AGND
G
Analog Ground
41
VAA
P
Analog Power Supply
42
DAC C
O
Chroma/Red/V SD Analog Output
43
DAC B
O
Luma/Blue/U SD Analog Output
44
DAC A
O
CVBS/Green/Y SD Analog Output
46
VREF
I/O
Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V)
48
S_BLANK
I/O
Video Blanking Control Signal for SD
49
S_VSYNC
I/O
Video Vertical Control Signal for SD. Option to output SD VSYNC or SD
HSYNC in SD Slave Mode 0 and/or any HD Mode.
50
S_HSYNC
I/O
Video Horizontal Control Signal for SD. Option to output SD HSYNC or
HD HSYNC in SD Slave Mode 0 and/or any HD Mode.
51–55, 58–62
S0–S9
I
10-Bit Standard Definition Input Port or Progressive Scan/HDTV Input Port
for Cr (Red/V) color data in 4:4:4 Input Mode. The LSBs are set up on Pins
S0 and S1. In Default Mode, the input on this port is output on DAC F.
63
CLKIN_B
I
Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan
Mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV Mode. This
clock input pin is only used in Simultaneous SD/HD Mode.
64
GND_IO
REV. A
Digital Ground
–13–
ADV7300A/ADV7301A
MPU PORT DESCRIPTION
The ADV7300A/ADV7301A supports a 2-wire serial (I2C compatible) microprocessor bus driving multiple peripherals. Two
inputs, serial data (SDA) and serial clock (SCLK), carry information between any device connected to the bus. Each slave device
is recognized by a unique address. The ADV7300A/ADV7301A
has four possible slave addresses for both read and write operations. These are unique addresses for each device and are
illustrated in Figures 15 and 16. The LSB sets either a read or
write operation. Logic Level “1” corresponds to a read operation,
while Logic Level “0” corresponds to a write operation. A1 is set
by setting the ALSB pin of the ADV7300A/ADV7301A to Logic
Level “0” or Logic Level “1.” When ALSB is set to “1,” there is
greater input bandwidth on the I2C lines, which allows high
speed data transfers on this bus. When ALSB is set to “0,” there
is reduced input bandwidth on the I2C lines, which means that
pulses of less than 50 ns will not pass into the I2C internal controller. This mode is recommended for noisy systems.
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
WRITE
READ
Figure 15. ADV7300A Slave Address = D4h
0
1
0
1
0
1
A1
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, it will cause an immediate jump to the idle condition. During a given SCLK high
period, the user should issue only one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7300A/ADV7301A will not issue an acknowledge and will
return to the idle condition. If in Autoincrement Mode the user
exceeds the highest subaddress, the following action will be taken:
2. In Write Mode, the data for the invalid byte will not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7300A/ADV7301A, and the part will
return to the idle condition.
X
ADDRESS
CONTROL
Before writing to the subcarrier frequency registers, it is a requirement that the ADV7300A/ADV7301A has been reset at least
once since power-up.
SET UP BY
ALSB
READ/WRITE
CONTROL
0
1
The ADV7300A/ADV7301A acts as a standard slave device on
the bus. The data on the SDA pin is eight bits long, supporting
the 7-bit addresses plus the R/W Bit. It interprets the first byte
as the device address and the second byte as the starting
subaddress. The subaddress’s autoincrement allows data to be
written to or read from the starting subaddress. A data transfer
is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without having to update all the registers.
1. In Read Mode, the highest subaddress register contents will
continue to be output until the master device issues a noacknowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDA line is not pulled low on the
ninth pulse.
READ/WRITE
CONTROL
0
1
A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The four subcarrier frequency registers must be updated starting with subcarrier frequency register 0. The subcarrier
frequency will not update until the last subcarrier frequency
register byte has been received by the ADV7300A/ADV7301A.
WRITE
READ
Figure 16. ADV7301A Slave Address = 54h
To control the various devices on the bus, the following protocol
must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on
SDA, while SCLK remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start condition
and shift the next 8 bits (7-bit address + R/W Bit). The bits are
transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line
low during the ninth clock pulse. This is known as an Acknowledge Bit. All other devices withdraw from the bus at this
point and maintain an idle condition. The idle condition is where
the device monitors the SDA and SCLK lines waiting for the
start condition and the correct transmitted address. The R/W
Bit determines the direction of the data.
Figure 17 illustrates an example of data transfer for a read
sequence and the start and stop conditions.
Figure 18 shows bus write and read sequences.
SDATA
SCLOCK
–14–
S
1–7
8
9
START ADRR R/W ACK
1–7
8
9
SUBADDRESS ACK
1–7
DATA
8
9
P
ACK
STOP
Figure 17. Bus Data Transfer
REV. A
ADV7300A/ADV7301A
WRITE
SEQUENCE
S
SLAVE ADDR
A(S)
SUB ADDR
A(S)
DATA
LSB = 0
READ
SEQUENCE
S
SLAVE ADDR A(S)
S = START BIT
P = STOP BIT
A(S)
DATA
A(S) P
LSB = 1
SUB ADDR
A(S) S SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M)
P
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
Figure 18. Read and Write Sequence
REGISTER ACCESSES
REGISTER PROGRAMMING
The MPU can write to or read from all of the registers of the
ADV7300A/ADV7301A except the subaddress registers that are
write-only registers. The subaddress register determines which
register the next read or write operation accesses. All communications with the part through the bus start with an access to the
subaddress register. Then a read/write operation is performed
from/to the target address which then increments to the next
address until a stop command on the bus is performed.
The following section describes the functionality of each register. All registers can be read from as well as written to, unless
otherwise stated.
Subaddress Register (SR7–SR0)
The Communications Register is an 8-bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The Subaddress
Register determines to/from which register the operation
takes place.
Register Select (SR7–SR0)
These bits are set up to point to the required starting address.
REV. A
–15–
ADV7300A/ADV7301A
Table I. Power Mode Register
Subaddress
Register
Bit Description
00h
Power Mode Register
Sleep Mode1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
PLL and Oversampling
Control2
DAC F: Power On/Off
DAC E: Power On/Off
DAC D: Power On/Off
DAC C: Power On/Off
DAC B: Power On/Off
DAC A: Power On/Off
0
Sleep Mode Off
1
Sleep Mode On
0
PLL On
1
PLL Off
0
DAC F Off
1
DAC F On
0
DAC E Off
1
DAC E On
0
DAC D Off
1
DAC D On
0
DAC C Off
1
DAC C On
0
DAC B Off
1
DAC B On
0
DAC A Off
1
DAC A On
Reset
Fch
NOTES
1
When enabled, the current consumption is reduced to µA level. All DACs and the internal PLL circuit are disabled. I2C registers can be read from and written to.
2
This control allows the internal PLL circuit to be powered down and the oversampling to be switched off.
Table II. Input Mode Register
Subaddress Register
Bit Description
01h
BTA T-1004 Compatibility
Input Mode Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reserved
0
0
Pixel Align
1
Clock Align
Disabled
1
Enabled
38h
Zero must be written
to this bit.
Video input data starts
with a Y0 bit. Only for
PS Interleaved Mode.
Video input data starts
with a Cb0 bit.
0
1
Input Mode
Reserved
0
Reset
0
0
0
Must be set if the
phase delay between
the two input clocks is
<9.25 ns or >27.75 ns.
Only if two input
clocks are used.
SD Input Only
0
0
1
PS Input Only
0
1
0
HDTV Input Only
0
1
1
SD and PS (20-Bit)
1
0
0
SD and PS (10-Bit)
1
0
1
1
1
0
SD and HDTV (SD
Oversampled)
SD and HDTV
(HDTV Oversampled)
1
1
1
0
PS 54 MHz Input
Zero must be written
to this bit.
–16–
REV. A
ADV7300A/ADV7301A
Table III. Mode Register
Subaddress Register
Bit Description
02h
Reserved
Mode Register 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
0
0
Test Pattern Black Bar
1
1
0
SYNC on RGB
1
1
0
SD SYNC
1
HD SYNC
Output SD SYNCs on
S_HSYNC and
S_VSYNC
No SYNC Output
0
1
03h
RGB Matrix 0
X
X
Output HD SYNCs
on S_HSYNC and
S_VSYNC
LSB for GY
04h
RGB Matrix 1
X
X
LSB for RV
X
05h
REV. A
RGB Matrix 2
X
X
X
X
20h
SYNC on all RGB
Outputs
RGB Component
Outputs
YUV Component
Outputs
No SYNC Output
0
RGB/YUV Output
Reset
Enabled. 0x11h, Bit 2
must also be enabled.
Disable Programmable
RGB Matrix
Enable Programmable
RGB Matrix
No SYNC
0
RGB Matrix
Zero must be written
to these bits.
Disabled
X
X
X
X
X
03h
F0h
LSB for BU
LSB for GV
LSB for GU
X
X
X
X
Bits 9–2 for GY
4Eh
06h
RGB Matrix 3
X
X
X
X
X
X
X
X
Bits 9–2 for GU
0Eh
07h
RGB Matrix 4
X
X
X
X
X
X
X
X
Bits 9–2 for GV
24h
08h
RGB Matrix 5
X
X
X
X
X
X
X
X
Bits 9–2 for BU
92h
09h
RGB Matrix 6
X
X
X
X
X
X
X
X
Bits 9–2 for RV
7Ch
0Ah
Reserved
00h
0Bh
Reserved
00h
0Ch
Reserved
00h
0Dh
Reserved
00h
0Eh
Reserved
00h
0Fh
Reserved
00h
–17–
ADV7300A/ADV7301A
Table IV. HD Mode Register
Subaddress
Register
Bit Description
10h
HD Mode Register 1
HD Output Standard
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
HD Input Control Signals
HD 625 p
HD 720 p
HD BLANK Polarity
HD Macrovision for
525 p/625 p
0
0
EIA770.2 Output
0
1
EIA770.1 Output
1
0
1
1
Output Levels for Full
Input Range
Reserved
0
0
0
1
HSYNC ,VSYNC ,
BLANK
EAV/SAV Codes 1
1
0
Async Timing Mode
1
1
Reserved
0
525 p
1
625 p
0
1080 i
1
720 p
0
BLANK Active High
1
BLANK Active Low
0
Macrovision Off
1
11h
HD Mode Register 2
Macrovision On
HD Pixel Data Valid
0
Pixel Data Valid Off
1
Pixel Data Valid On
0
HD Test Pattern Enable
HD Test Pattern
Hatch/Field
HD VBI Open
HD Undershoot Limiter
HD Sharpness Filter
HD Mode Register 3
HD Test Pattern Off
1
HD Test Pattern On
0
Hatch
1
Field/Frame
0
Disabled
1
Enabled
0
0
Disabled
0
1
–11 IRE
1
0
–6 IRE
1
1
–1.5 IRE
0
Disabled
Enabled
HDY Delay wrt Falling
Edge of HSYNC
HD Color Delay wrt
Falling Edge of HSYNC
HD CGMS
HD CGMS CRC
00h
Reserved
0
1
12h
Reset
00h
0
0
0
0 Clock Cycle
0
0
1
1 Clock Cycle
0
1
0
2 Clock Cycle
0
1
1
3 Clock Cycle
1
0
0
4 Clock Cycle
0
0
0
0 Clock Cycle
0
0
1
1 Clock Cycle
0
1
0
2 Clock Cycle
0
1
1
3 Clock Cycle
1
0
0
4 Clock Cycle
0
Disabled
1
Enabled
0
Disabled
1
Enabled
–18–
REV. A
ADV7300A/ADV7301A
Table IV. HD Mode Register (continued)
Subaddress Register
Bit Description
13h
HD Cr/Cb Sequence 2
HD Mode Register 4
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
1
0
0
HD Input Format
8-Bit Input
1
Sync Filter on DAC D, E, F
10-Bit Input
0
Disabled
1
Enabled
0
HD Chroma SSAF2
HD Chroma Input
Reserved
0
Disabled
1
Enabled
0
4:4:4
1
HD Double Buffering
14h
HD Mode Register 5
15h
HD Mode Register 6
4:2:2
0
Disabled
1
Enabled
0
0
0
0
0
0
HD Color DAC Swap3
0
0
A low-high-low
00h
transition resets the
internal HD timing
counters.
Zero must be written 00h
to this bit.
Disabled
1
Enabled
HD Adaptive Filter Mode
0
Disabled
1
Enabled
0
DAC E = Pr,
DAC F = Pb
DAC F = Pr,
DAC E = Pb
Gamma Curve A
1
Gamma Curve B
1
HD Gamma Curve A/B
HD Adaptive Filter Enable
X
0
HD Sync on PrPb
0
Disabled
1
Enabled
0
Mode A
1
Mode B
0
Disabled
1
Enabled
NOTES
1
EAV/SAV codes are not supported for PS 1 ⫻ 10-Bit Interleaved Mode at 54 MHz.
2
4:2:2 Input Format Only
3
4:4:4 Input Format Only
REV. A
0
Reserved
HD RGB Input
HD Gamma Curve Enable
–19–
Reset
Cb after Falling
4Ch
Edge of HSYNC
Cr after Falling Edge
of HSYNC
Reserved
ADV7300A/ADV7301A
Table V. Register Settings
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reset
16h
HD Y Color
X
X
X
X
X
X
X
X
Y Color Value
A0h
17h
HD Cr Color
X
X
X
X
X
X
X
X
Cr Color Value
80h
18h
HD Cb Color
X
X
X
X
X
X
X
X
Cb Color Value
80h
19h
Reserved
00h
1Ah
Reserved
00h
1Bh
Reserved
00h
1Ch
Reserved
00h
1Dh
Reserved
00h
1Eh
Reserved
00h
1Fh
Reserved
20h
HD Sharpness Filter
Gain
Subaddress Register
Bit Description
00h
HD Sharpness Filter Gain
Value A
HD Sharpness Filter Gain
Value B
0
0
0
0
Gain A = 0
0
0
0
1
Gain A = +1
…
…
…
…
…
0
1
1
1
Gain A = +7
1
0
0
0
Gain A = –8
…
…
…
…
…
1
1
1
1
Gain A = –1
0
0
0
0
Gain B = 0
0
0
0
1
Gain B = +1
…
…
…
…
…
0
1
1
1
Gain B = +7
1
0
0
0
Gain B = –8
…
…
…
…
…
1
1
1
1
Gain B = –1
00h
21h
HD CGMS Data 0
HD CGMS Data Bits
0
0
0
0
C19
C18
C17
C16
CGMS 19–16
00h
22h
HD CGMS Data 1
HD CGMS Data Bits
C15
C14
C13
C12
C11
C10
C9
C8
CGMS 15–8
00h
23h
HD CGMS Data 2
HD CGMS Data Bits
C7
24h
HD Gamma A
25h
HD Gamma A
26h
HD Gamma A
27h
HD Gamma A
28h
HD Gamma A
29h
HD Gamma A
2Ah
HD Gamma A
2Bh
HD Gamma A
2Ch
HD Gamma A
2Dh
HD Gamma A
2Eh
HD Gamma B
2Fh
HD Gamma B
30h
HD Gamma B
31h
HD Gamma B
32h
HD Gamma B
33h
HD Gamma B
34h
HD Gamma B
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
HD Gamma
Points
C6
C5
C4
C3
C2
C1
C0
CGMS 7–0
00h
Curve A Data X
X
X
X
X
X
X
X
A0
00h
Curve A Data X
X
X
X
X
X
X
X
A1
00h
Curve A Data X
X
X
X
X
X
X
X
A2
00h
Curve A Data X
X
X
X
X
X
X
X
A3
00h
Curve A Data X
X
X
X
X
X
X
X
A4
00h
Curve A Data X
X
X
X
X
X
X
X
A5
00h
Curve A Data X
X
X
X
X
X
X
X
A6
00h
Curve A Data X
X
X
X
X
X
X
X
A7
00h
Curve A Data X
X
X
X
X
X
X
X
A8
00h
Curve A Data X
X
X
X
X
X
X
X
A9
00h
Curve B Data X
X
X
X
X
X
X
X
B0
00h
Curve B Data X
X
X
X
X
X
X
X
B1
00h
Curve B Data X
X
X
X
X
X
X
X
B2
00h
Curve B Data X
X
X
X
X
X
X
X
B3
00h
Curve B Data X
X
X
X
X
X
X
X
B4
00h
Curve B Data X
X
X
X
X
X
X
X
B5
00h
Curve B Data X
X
X
X
X
X
X
X
B6
00h
–20–
REV. A
ADV7300A/ADV7301A
Table VI. HD Adaptive Filters
Subaddress Register
HD Adaptive Filter
38h
Gain 1
39h
3Ah
3Bh
3Ch
3Dh
REV. A
HD Adaptive Filter
Gain 2
HD Adaptive Filter
Gain 3
HD Adaptive Filter
Threshold A
HD Adaptive Filter
Threshold B
HD Adaptive Filter
Threshold C
Bit Description
HD Adaptive Filter Gain 1
Value A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
0
0
0
Gain A = 0
0
0
0
1
Gain A = +1
0
1
1
1
Gain A = +7
1
0
0
0
Gain A = –8
1
1
1
1
Gain A = –1
HD Adaptive Filter Gain 1 0
Value B
0
0
0
0
Gain B = 0
0
0
1
Gain B = +1
0
1
1
1
Gain B = +7
1
0
0
0
Gain B = –8
1
1
1
1
HD Adaptive Filter Gain 2
Value A
Gain B = –1
0
0
0
0
Gain A = 0
0
0
0
1
Gain A = +1
0
1
1
1
Gain A = +7
1
0
0
0
Gain A = –8
1
1
1
1
Gain A = –1
HD Adaptive Filter Gain 2 0
Value B
0
0
0
0
Gain B = 0
0
0
1
Gain B = +1
0
1
1
1
Gain B = +7
1
0
0
0
Gain B = –8
1
1
1
1
Gain B = –1
HD Adaptive Filter Gain 3
Value A
0
0
0
0
Gain A = 0
0
0
0
1
Gain A = +1
0
1
1
1
Gain A = +7
1
0
0
0
Gain A = –8
1
1
1
1
Gain A = –1
HD Adaptive Filter Gain 3 0
Value B
0
0
0
0
Gain B = 0
0
0
1
Gain B = +1
0
1
1
1
Gain B = +7
1
0
0
0
Gain B = –8
1
1
1
1
X
X
X
X
HD Adaptive Filter
Threshold A Value
HD Adaptive Filter
Threshold B Value
HD Adaptive Filter
Threshold C Value
Reset
00hex
00hex
00hex
Gain B = –1
X
X
X
X
Threshold A
00hex
X
X
X
X
X
X
X
X
Threshold B
00hex
X
X
X
X
X
X
X
X
Threshold C
00hex
–21–
ADV7300A/ADV7301A
Table VII. SD Mode Registers
Subaddress Register
3Eh
Reserved
3Fh
Reserved
40h
SD Mode Register 0
Bit Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
00h
00h
SD Standard
SD Luma Filter
SD Chroma Filter
41h
Reserved
42h
SD Mode Register 1
Reset
0
0
NTSC
0
1
PAL B, D, G, H, I
1
0
PAL M
1
1
PAL N
0
0
0
LPF NTSC
0
0
1
LPF PAL
0
1
0
Notch NTSC
0
1
1
Notch PAL
1
0
0
SSAF Luma
1
0
1
Luma CIF
1
1
0
Luma QCIF
1
1
1
Reserved
0
0
0
1.3 MHz
0
0
1
0.65 MHz
0
1
0
1.0 MHz
0
1
1
2.0 MHz
1
0
0
Reserved
1
0
1
Chroma CIF
1
1
0
Chroma QCIF
1
1
1
3.0 MHz
00h
00h
SD UV SSAF
SD DAC Output 1*
0
1
SD DAC Output 2
0
0
Disabled
1
Enabled
08h
DAC A, B, C: CVBS,
L, C; DAC D, E, F:
GBR or YUV
DAC A, B, C: GBR or
YUV; DAC D, E, F:
CVBS, L, C
Swap DAC A and
DAC D Outputs
1
SD Pedestal
SD Square Pixel
SD VCR FF/RW Sync
SD Pixel Data Valid
SD Active Video Edge
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
Disabled
1
Enabled
–22–
REV. A
ADV7300A/ADV7301A
Table VII. SD Mode Registers (continued)
Subaddress Register
43h
SD Mode Register 2
Bit Description
SD Pedestal YUV Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
No Pedestal on YUV
1
SD Output Levels Y
SD Output Levels UV
SD VBI Open
SD CC Field Control
0
7.5 IRE Pedestal on
YUV
Y = 700 mV/300 mV
1
Y = 714 mV/286 mV
0
0
0
1
700 mV p-p [PAL];
1000 mV p-p [NTSC]
700 mV p-p
1
0
1000 mV p-p
1
1
648 mV p-p
0
Disabled
1
Enabled
0
0
CC Disabled
0
1
CC on Odd Field Only
1
0
1
1
CC on Even Field
Only
CC on Both Fields
1
44h
SD Mode Register 3
Reserved
SD VSYNC-3H
SD RTC/TR/SCR
SD Chroma
SD Burst
Reserved
Disabled
1
0
0
VSYNC = 2.5 lines
[PAL]; VSYNC = 3
lines [NTSC]
Genlock Disabled
0
1
Subcarrier Reset
1
0
Timing Reset
1
1
RTC Enabled
720 Pixels
1
0
710 (NTSC);
702(PAL)
Chroma Enabled
1
Chroma Disabled
0
Enabled
1
Disabled
0
Disabled
1
Enabled
0
00h
Zero must be written
to this bit.
45h
Reserved
00h
46h
Reserved
00h
47h
SD Mode Register 4
SD UV Scale
SD Y Scale
SD Hue Adjust
SD Brightness
SD Luma SSAF Gain
Reserved
0
Reserved
Reserved
REV. A
0
0
SD Active Video Length
SD Color Bars
Reset
00h
0
0
–23–
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
Disabled
1
Enabled
Zero must be written
to this bit.
Zero must be written
to this bit.
Zero must be written
to this bit.
00h
ADV7300A/ADV7301A
Table VII. SD Mode Registers (continued)
Subaddress Register
Bit Description
48h
Reserved
SD Mode Register 5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
0
Zero must be written
to this bit.
Zero must be written
to this bit.
Disabled
1
Enabled
Reserved
0
SD Double Buffering
SD Input Format
SD Digital Noise
Reduction
SD Gamma Control
SD Gamma Curve
0
0
8-Bit Input
0
1
16-Bit Input
1
0
10-Bit Input
1
1
20-Bit Input
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
SD Mode Register 6
Gamma Curve B
SD Undershoot Limiter
SD Black Burst Output on
DAC Y
SD Black Burst Output on
DAC Luma
SD Chroma Delay
Reserved
Reserved
00h
Gamma Curve A
1
49h
Reset
0
0
0
0
Disabled
0
1
–11 IRE
1
0
–6 IRE
1
1
–1.5 IRE
0
Disabled
1
Enabled
0
Disabled
1
Enabled
0
0
Disabled
0
1
4 Clock Cycles
1
0
8 Clock Cycles
1
1
Reserved
00h
Zero must be written
to this bit.
Zero must be written
to this bit.
*For more detail, see Input and Output Configuration section.
–24–
REV. A
ADV7300A/ADV7301A
Table VIII. SD Registers
Subaddress
Register
Bit Description
4Ah
SD Timing Register 0
SD Slave/Master Mode
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
SD Timing Mode
SD BLANK Input
0
Slave Mode
1
Master Mode
0
0
Mode 0
0
1
Mode 1
1
0
Mode 2
1
1
Mode 3
1
SD Min. Luma Value
SD Timing Reset
4Bh
SD Timing Register 1
X
0
No Delay
0
1
2 Clock Cycles
1
0
4 Clock Cycles
1
1
6 Clock Cycles
–40 IRE
1
–7.5 IRE
0
0
0
0
SD HSYNC Width
SD HSYNC to VSYNC
Delay
SD HSYNC to VSYNC
Rising Edge Delay (Mode 1
Only); VSYNC Width
(Mode 2 Only)
HSYNC to Pixel Data
Adjust
0
0
A low-high-low
transistion will reset the
internal SD timing
counters.
0
0
Ta = 1 Clock Cycle
0
1
Ta = 4 Clock Cycles
1
0
Ta = 16 Clock Cycles
1
1
Ta = 128 Clock Cycles
0
0
Tb = 0 Clock Cycle
0
1
Tb = 4 Clock Cycles
1
0
Tb = 8 Clock Cycles
1
1
Tb = 18 Clock Cycles
X
0
Tc = Tb
X
1
Tc = Tb + 32 µs
0
0
1 Clock Cycle
0
1
4 Clock Cycles
1
0
16 Clock Cycles
1
1
128 Clock Cycles
0
0
0 Clock Cycle
0
1
1 Clock Cycle
1
0
2 Clock Cycles
1
1
SD FSC Register 0
X
X
X
X
X
X
X
X
4Dh
SD FSC Register 1
X
X
X
X
X
X
X
X
4Eh
SD FSC Register 2
X
X
X
X
X
X
X
X
4Fh
SD FSC Register 3
X
X
X
X
X
X
X
X
50h
SD FSC Phase
X
X
X
X
X
X
X
X
51h
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
53h
SD Closed Captioning Extended Data on Even
Fields
SD Closed Captioning Extended Data on Even
Fields
SD Closed Captioning Data on Odd Fields
X
X
X
X
X
X
X
54h
SD Closed Captioning Data on Odd Fields
X
X
X
X
X
X
X
55h
SD Pedestal Register 0 Pedestal on Odd Fields
17
16
15
14
13
12
56h
SD Pedestal Register 1 Pedestal on Odd Fields
25
24
23
22
21
20
57h
SD Pedestal Register 2 Pedestal on Even Fields
17
16
15
14
13
58h
SD Pedestal Register 3 Pedestal on Even Fields
25
24
23
22
21
–25–
00h
3 Clock Cycles
4Ch
52h
REV. A
Disabled
0
0
0
08h
Enabled
0
SD Luma Delay
Reset
Subcarrier Frequency
Bits 7–0
Subcarrier Frequency
Bits 15–8
Subcarrier Frequency
Bits 23–16
Subcarrier Frequency
Bits 31–24
Subcarrier Phase Bits
9–2
Extended Data Bits 7–0
16h
7Ch
F0h
21h
00h
00h
00h
X
Extended Data Bits
15–8
Data Bits 7–0
X
Data Bits 15–8
00h
11
10
19
18
12
11
10
Setting any of these bits 00h
to 1 will disable
pedestal on the line
00h
number indicated by
the bit settings.
00h
20
19
18
00h
00h
ADV7300A/ADV7301A
Table VIII. SD Registers (continued)
Subaddress
Register
Bit Description
59h
SD CGMS/WSS 0
SD CGMS Data
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
19
SD CGMS CRC
SD CGMS on Odd Fields
SD CGMS on Even Fields
SD WSS
5Ah
SD CGMS/WSS 1
SD CGMS/WSS 2
SD CGMS/WSS Data
5Ch
SD LSB Register
SD LSB for Y Scale Value
0
CGMS Data Bits
C19–C16
Disabled
1
Enabled
0
Disabled
Enabled
0
Disabled
Enabled
0
Disabled
1
Enabled
15
14
7
6
13
12
11
10
9
8
5
4
3
2
1
0
X
X
X
SD LSB for V Scale Value
SD Y Scale Register
16
1
SD LSB for U Scale Value
5Dh
17
1
SD CGMS/WSS Data
5Bh
18
X
Reset
00h
CGMS Data Bits
00h
C13–C8 or WSS Data
Bits C13–C8
CGMS Data Bits
C15–C14
CGMS/WSS Data Bits 00h
C7–C0
SD Y Scale Bits 1–0
X
SD U Scale Bits 1–0
X
SD V Scale Bits 1–0
00h
SD LSB for FSC Phase
X
X
SD Y Scale Value
X
X
X
X
X
X
X
X
Subcarrier Phase Bits
1–0
SD Y Scale Bits 7–2
5Eh
SD V Scale Register
SD V Scale Value
X
X
X
X
X
X
X
X
SD V Scale Bits 7–2
00h
5Fh
SD U Scale Register
SD U Scale Value
X
X
X
X
X
X
X
X
SD U Scale Bits 7–2
00h
60h
SD Hue Register
SD Hue Adjust Value
X
X
X
X
X
X
X
X
61h
SD Brightness/WSS
X
X
X
X
X
X
X
SD Hue Adjust Bits
00h
7–0
SD Brightness Bits 6–0 00h
SD Brightness Value
SD Blank WSS Data*
62h
63h
SD Luma SSAF
SD DNR 0
SD Luma SSAF
Gain/Attenuation
0
Disabled
1
Enabled
0
0
0
0
0
0
0
0
–4 dB
0
0
0
0
0
1
1
0
0 dB
0
0
0
0
1
1
0
0
+4 dB
Coring Gain Border
Coring Gain Data
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
–26–
0
0
0
0
No Gain
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
+1/16 (–1/8 in DNR
Mode)
+2/16 (–2/8 in DNR
Mode)
+3/16 (–3/8 in DNR
Mode)
+4/16 (–4/8 in DNR
Mode)
+5/16 (–5/8 in DNR
Mode)
+6/16 (–6/8 in DNR
Mode)
+7/16 (–7/8 in DNR
Mode)
+8/16 (–1 in DNR
Mode)
No Gain
00h
00h
+1/16 (–1/8 in DNR
Mode)
+2/16 (–2/8 in DNR
Mode)
+3/16 (–3/8 in DNR
Mode)
+4/16 (–4/8 in DNR
Mode)
+5/16 (–5/8 in DNR
Mode)
+6/16 (–6/8 in DNR
Mode)
+7/16 (–7/8 in DNR
Mode)
+8/16 (–1 in DNR
Mode)
REV. A
ADV7300A/ADV7301A
Table VIII. SD Registers (continued)
Subaddress Register
64h
SD DNR 1
Bit Description
DNR Threshold
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
0
0
0
0
0
0
0
Border Area
0
0
0
0
0
1
1
1
1
1
1
1
0
62
1
1
1
1
1
1
63
0
2 Pixels
1
Block Size Control
65h
SD DNR 2
4 Pixels
0
8 Pixels
1
16 Pixels
DNR Input Select
DNR Mode
DNR Block Offset
66h
SD Gamma A
67h
SD Gamma A
68h
SD Gamma A
69h
SD Gamma A
6Ah
SD Gamma A
6Bh
SD Gamma A
6Ch
SD Gamma A
6Dh
SD Gamma A
6Eh
SD Gamma A
6Fh
SD Gamma A
70h
SD Gamma B
71h
SD Gamma B
72h
SD Gamma B
73h
SD Gamma B
74h
SD Gamma B
75h
SD Gamma B
76h
SD Gamma B
77h
SD Gamma B
78h
SD Gamma B
SD Gamma Curve A
Points
SD Gamma Curve A
Points
SD Gamma Curve A
Points
SD Gamma Curve A
Points
SD Gamma Curve A
Points
SD Gamma Curve A
Points
SD Gamma Curve A
Points
SD Gamma Curve A
Points
SD Gamma Curve A
Points
SD Gamma Curve A
Points
SD Gamma Curve B
Points
SD Gamma Curve B
Points
SD Gamma Curve B
Points
SD Gamma Curve B
Points
SD Gamma Curve B
Points
SD Gamma Curve B
Points
SD Gamma Curve B
Points
SD Gamma Curve B
Points
SD Gamma Curve B
Points
SD Gamma Curve B
Points
Detect SD Brightness Value
79h
SD Gamma B
7Ah
SD Brightness
7Bh
Field Count Register
0
1
Filter A
0
1
0
Filter B
0
1
1
Filter C
1
0
0
Filter D
DNR Mode
1
DNR Sharpness Mode
00h
0
0
0
0
0 Pixel Offset
0
0
0
1
1 Pixel Offset
1
1
1
0
14 Pixel Offset
1
1
1
1
Data X
X
X
X
X
X
X
X
A0
00h
Data X
X
X
X
X
X
X
X
A1
00h
Data X
X
X
X
X
X
X
X
A2
00h
Data X
X
X
X
X
X
X
X
A3
00h
Data X
X
X
X
X
X
X
X
A4
00h
Data X
X
X
X
X
X
X
X
A5
00h
Data X
X
X
X
X
X
X
X
A6
00h
Data X
X
X
X
X
X
X
X
A7
00h
Data X
X
X
X
X
X
X
X
A8
00h
15 Pixel Offset
Data X
X
X
X
X
X
X
X
A9
00h
Data X
X
X
X
X
X
X
X
B0
00h
Data X
X
X
X
X
X
X
X
B1
00h
Data X
X
X
X
X
X
X
X
B2
00h
Data X
X
X
X
X
X
X
X
B3
00h
Data X
X
X
X
X
X
X
X
B4
00h
Data X
X
X
X
X
X
X
X
B5
00h
Data X
X
X
X
X
X
X
X
B6
00h
Data X
X
X
X
X
X
X
X
B7
00h
Data X
X
X
X
X
X
X
X
B8
00h
Data X
X
X
X
X
X
X
X
B9
00h
X
X
X
X
X
X
X
X
Read-Only
X
X
X
Read-Only
Reserved
0
Reserved
0
Reserved
REV. A
0
0
Field Count
Reserved Code
Reset
00h
0
X
X
–27–
Zero must be written
to this bit.
Zero must be written
to this bit.
Zero must be written
to this bit.
Read-Only
ADV7300A/ADV7301A
Table VIII. SD Registers (continued)
Subaddress
Register
Bit Description
7Ch
Reset Register
Timing Reset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reserved
00h
No reset of Timing
Generator in Subcarrier
Reset Mode. 44h, Bits
1 and 2 must be set to
Subcarrier Reset.
1
Reset Timing
Generator in Subcarrier
Reset Mode
0
Reserved
Zero must be written to
this bit.
Zero must be written to
this bit.
Zero must be written to
this bit.
Zero must be written to
this bit.
Zero must be written to
this bit.
Zero must be written to
this bit.
Zero must be written to
this bit.
0
Reserved
0
Reserved
0
Reserved
0
Reserved
0
Reserved
Reset
0
0
*Line 23
LINE 1
HSYNC
LINE 313
LINE 314
tA
tC
tB
VSYNC
Figure 19. Timing Register 1 in PAL Mode
Table IX. Macrovision Registers*
Subaddress Register
Bit Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting
Reset
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 3a [7:0]
00h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 3b [15:8]
00h
82h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 3c [23:16]
00h
83h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 3d [31:24]
00h
84h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 3e [39:32]
00h
85h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 3f [47:40]
00h
86h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 40 [55:48]
00h
87h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 41 [63:56]
00h
88h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 42 [71:64]
00h
89h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 43 [79:72]
00h
8Ah
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 44 [87:80]
00h
8Bh
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 45 [95:88]
00h
8Ch
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 46 [103:96]
00h
8Dh
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 47 [111:104]
00h
8Eh
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 48 [119:112]
00h
8Fh
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 49 [127:120]
00h
90h
Macrovision
MV Control Bits
X
X
X
X
X
X
X
X
MV 4A [135:128]
00h
91h
Macrovision
MV Control Bit
X
MV 4B [136]
00h
7Dh
Reserved
7Eh
Reserved
7Fh
Reserved
80h
81h
0
0
0
0
0
0
0
Zero must be written
to these bits.
*Macrovision Registers are only available on the ADV7300A.
–28–
REV. A
ADV7300A/ADV7301A
Register at Address 01h accordingly. If the YCrCb data does not
conform to SMPTE293M (525 p), ITU-R.BT1358M (625 p),
SMPTE274M (1080 i), SMPTE296M (720 p), or BTA-T1004,
the Async Timing Mode must be used.
INPUT AND OUTPUT CONFIGURATION
STANDARD DEFINITION ONLY
The 8- or 10-bit multiplexed input data is input on Pins S9–S0,
with S0 being the LSB in 10-bit Input Mode. For 8-bit Input
Mode, the data is input on Pins S9–S2. ITU-R.BT601/ITUR.BT656 input standards are supported. In 16-bit Input Mode,
the Y pixel data is input on Pins S9–S2 and CrCb data on
Pins Y9–Y2. In 20-bit Input Mode, the Y pixel data is input on
S9–S0 and CrCb pixel data on Pins Y9–Y0. The 27 MHz clock
input must be input on Pin CLKIN_A. Input sync signals
are optional and are input on the S_VSYNC, S_HSYNC,
and S_BLANK pins.
The 8- or 10-bit standard definition data must be compliant to
ITU-R.BT601/ITU-R.BT656 in 4:2:2 format. Standard definition
data is input on Pins S9–S0, with S0 being the LSB. Using 8-bit input
format, the data is input on Pins S9–S2. The clock input for SD must
be input on CLKIN_A, and the clock input for HD must be input
on CLKIN_B. Synchronization signals are optional. SD syncs are
input on Pins S_VSYNC, S_HSYNC, and S_BLANK; the
HD syncs on Pins P_VSYNC, P_HSYNC, and P_BLANK.
ADV7300A/
ADV7301A
S_VSYNC
S_HSYNC
S_BLANK
3
MPEG2
DECODER
3
MPEG2
DECODER
27MHz
YCrCb
27MHz
YCrCb
ADV7300A/
ADV7301A
CrCb 10
10
S9–S0
Y
10
INTERLACED
TO
PROGRESSIVE
Figure 20. Standard Definition Only Input Mode
3
PROGRESSIVE SCAN ONLY OR HDTV ONLY
YCrCb Progressive Scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4 format. In 4:2:2 Input Mode, the
Y data is input on Pins Y9–Y0 and the CrCb data on Pins C9–
C0. In 4:4:4 Input Mode, Y data is input on Pins Y9–Y0, Cb
data on Pins C9–C0, and Cr data on Pins S9–S0. If the
YCrCb data does not conform to SMPTE293M (525 p), ITUR.BT1358M (625 p), SMPTE274M (1080 i), SMPTE296M
(720 p), or BTA-T1004, the Async Timing Mode must be used.
RGB data can only be input in 4:4:4 format in PS Input Mode
only, or HDTV Input Mode only, when HD RGB input is
enabled. G data is input on Pins Y9–Y0, R data on S9–S0, and
B data on Pins C9–C0. The clock signal must be input on Pin
CLKIN_A. Synchronization signals are optional and are input on
Pins P_VSYNC, P_HSYNC, and P_BLANK.
27MHz
Cb 10
Y
10
3
S9–S0
C9–C0
Y9–Y0
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
Figure 22. Simultaneous Progressive Scan and SD Input
ADV7300A/
ADV7301A
3
SDTV
DECODER
27MHz
YCrCb 8
HDTV
DECODER CrCb
1080 i
Y
720 p
ADV7300A/
ADV7301A
Cr 10
INTERLACED
TO
PROGRESSIVE
27MHz
8
8
3
MPEG2
DECODER
YCrCb
CLKIN_A
10
CLKIN_A
S_VSYNC
S_HSYNC
S_BLANK
74MHz
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S9–S2
C9–C2
Y9–Y2
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
CLKIN_A
Figure 23. Simultaneous HDTV and SD Input
S9–S0
If in Simultaneous Input Mode the two clock phases differ by less
than 9.25 ns or more than 27.75 ns, the Clock Align Bit must be
set accordingly. This also applies if the Pixel Align Bit is set. If
the application uses the same clock source for both SD and PS,
the Clock Align Bit must be set since the phase difference
between both inputs is less than 9.25 ns.
C9–C0
Y9–Y0
P_VSYNC
P_HSYNC
P_BLANK
Figure 21. Progressive Scan Only Input Mode
SIMULTANEOUS STANDARD DEFINITION AND
PROGRESSIVE SCAN OR HDTV
YCrCb PS, HDTV, or any other HD data must be input in 4:2:2
format. In 4:2:2 Input Mode, the Y data is input on Pins Y9–Y0
and the CrCb data on C9–C0. If PS 4:2:2 data is interleaved onto
a single 10-bit bus, Pins Y9–Y0 are used for the Input Port. The
interleaved data is to be input at 27 MHz in setting the Input Mode
REV. A
–29–
tDELAY
tDELAY
9.25ns OR
27.75ns
Figure 24. Clock Phase with Two Input Clocks
ADV7300A/ADV7301A
PROGRESSIVE SCAN AT 27 MHz OR 54 MHz
CLKIN_A
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 10-bit bus and is input
on Pins Y9–Y0. For PS Input Only Mode, the input clock
must be input on CLKIN_A. In Simultaneous SD/HD Mode,
the input clock is input on CLKIN_B.
MPEG2
DECODER
YCrCb
INTERLACED
TO
PROGRESSIVE
27MHz OR
54MHz
YCrCb 10
3
ADV7300A/
ADV7301A
CLKIN_A
Y9–Y0
PIXEL INPUT
DATA
00
00
XY
Y0
Cb0
Y1
Cr0
Figure 26. Input Sequence in PS 10-Bit
Interleaved Mode, EAV/SAV Followed by Y0 Data
If the input sequence starts with Cb0 data as shown in Figure 27,
initially PIXEL ALIGN [Subaddress 01h] must be set to “0.”
This ensures that the ADV7300A/ADV7301A locks to the
input sequence in decoding the embedded timing information
correctly. For correct color decoding, the Pixel Align Bit
[Subaddress 01h] must then be set to “l” after a delay of one
field. The ADV7300A/ADV7301A is now in free run mode;
any changes in the timing information are ignored.
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_A
Figure 25. 1 ⫻ 10-Bit PS @ 27 MHz or 54 MHz
When the input sequence of the PS data, i.e., 10-bit interleaved
at 27 MHz, starts with Y0 data, as shown in Figure 26, PIXEL
ALIGN [Subaddress 01h] must be set to “0.” In this case, the
timing information embedded in the data stream is recognized
and the video data is transferred to the according Y channel
and CrCb channel processing blocks.
3FF
PIXEL INPUT
DATA
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
Figure 27. Input Sequence in PS 10-Bit
Interleaved Mode, EAV/SAV Followed by Cb0 Data
PS 10-bit interleaved at 54 MHz must be input with separate
timing signals. EAV/SAV codes cannot be used in this mode.
–30–
REV. A
ADV7300A/ADV7301A
Table X. Overview of All Possible Input Configurations
Input Format
Total Bits
ITU-R.BT656
8
4:2:2 YCrCb
Input Video Input Pins
S9–S2 [MSB = S9]
01h, 48h
00h, 00h
10
4:2:2 YCrCb
S9–S0 [MSB = S9]
01h, 48h
00h, 10h
16
4:2:2 Y
S9–S2 [MSB = S9]
01h, 48h
00h, 08h
20
4:2:2 Y
01h, 48h
00h, 18h
8 (27 MHz Clock)
4:2:2 YCrCb
Y9–Y2 [MSB = Y9]
01h, 13h
10h, 40h
10 (27 MHz Clock) 4:2:2 YCrCb
Y9–Y0 [MSB = Y9]
01h, 13h
10h, 44h
CrCb
Y9–Y2 [MSB = Y9]
S9–S0 [MSB = S9]
CrCb
PS Only
8 (54 MHz Clock)
Y9–Y0 [MSB = Y9]
4:2:2 YCrCb
Y9–Y2 [MSB = Y9]
01h, 13h
70h, 40h
10 (54 MHz Clock) 4:2:2 YCrCb
Y9–Y0 [MSB = Y9]
01h, 13h
10h, 44h
16
4:2:2 Y
Y9–Y2 [MSB = Y9]
01h, 13h
10h, 40h
20
4:2:2 Y
01h, 13h
10h, 44h
24
4:4:4 Y
01h, 13h
10h, 00h
01h, 13h
10h, 04h
01h, 13h
20h, 40h
CrCb
C9–C2 [MSB = C9]
Y9–Y0 [MSB = Y9]
CrCb
C9–C0 [MSB = C9]
Y9–Y2 [MSB = Y9]
Cb
C9–C2 [MSB = C9]
Cr
30
S9–S2 [MSB = S9]
4:4:4 Y
Y9–Y0 [MSB = Y9]
Cb
C9–C0 [MSB= C9]
Cr
HDTV Only
8
S9–S0 [MSB = S9]
4:2:2 YCrCb
Y9–Y2 [MSB = Y9]
10
4:2:2 YCrCb
Y9–Y0 [MSB = Y9]
01h, 13h
20h, 44h
16
4:2:2 Y
Y9–Y2 [MSB = Y9]
01h, 13h
20h, 40h
01h, 13h
20h, 44h
01h, 13h
20h, 00h
01h, 13h
20h, 04h
01h, 13h,
15h
10h or 20h,
00h, 02h
01h, 13h,
15h
10h or 20h,
04h, 02h
CrCb
20
C9–Y2 [MSB = C9]
4:2:2 Y
Y9–Y0 [MSB = Y9]
CrCb
24
30
HD RGB
24
30
C9–C0 [MSB = C9]
4:4:4 Y
Y9–Y2 [MSB = Y9]
Cb
C9–Y2 [MSB = C9]
Cr
S9–S2 [MSB = S9]
4:4:4 Y
Y9–Y0 [MSB = Y9]
Cb
C9–C0 [MSB = C9]
Cr
S9–S0 [MSB = S9]
4:4:4 G
Y9–Y2 [MSB = Y9]
B
C9–C2 [MSB = C9]
R
S9–S2 [MSB = S9]
4:4:4 G
Y9–Y0 [MSB = Y9]
B
C9–C0 [MSB = C9]
R
ITU-R.BT656
and PS
8
10
ITU-R.BT656
8
and PS or HDTV
10
S9–S0 [MSB = S9]
4:2:2 YCrCb
S9–S2 [MSB = S9]
01h
40h
4:2:2 YCrCb
Y9–Y2 [MSB = Y9]
13h, 48h
40h, 00h
4:2:2 YCrCb
S9–S0 [MSB = S9]
01h
40h
4:2:2 YCrCb
Y9–Y0 [MSB = Y9]
13h, 48h
44h, 10h
4:2:2 YCrCb
S9–S2 [MSB = S9]
01h
4:2:2 YCrCb
S9–S0 [MSB = S9]
01h
16
4:2:2 Y
Y9–Y2 [MSB = Y9]
13h, 48h
30h, 50h, or
60h
30h, 50h, or
60h
40h, 00h
20
4:2:2 Y
13h, 48h
44h, 10h
CrCb
C9–C2 [MSB = C9]
Y9–Y0 [MSB = Y9]
CrCb
REV. A
Subaddress Register Setting
C9–C0 [MSB = C9]
–31–
ADV7300A/ADV7301A
OUTPUT CONFIGURATION
Tables XI–XIII demonstrate what output signals are assigned to the DACs when corresponding control bits are set.
Table XI. Output Configuration in SD Only Mode
RGB/YUV O/P
Addr 02h, Bit 5
SD DAC O/P 1
Addr 42h, Bit 2
SD DAC O/P 2
Addr 42h, Bit 1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CVBS
G
G
CVBS
CVBS
Y
Y
CVBS
Luma
B
Luma
B
Luma
U
Luma
U
Chroma
R
Chroma
R
Chroma
V
Chroma
V
G
CVBS
CVBS
G
Y
CVBS
CVBS
Y
B
Luma
B
Luma
U
Luma
U
Luma
R
Chroma
R
Chroma
V
Chroma
V
Chroma
Table XII. Output Configuration in HD Only Mode
HD I/P
Format
HD RGB I/P
Addr 15h, Bit 1
RGB/YUV O/P
Addr 02h, Bit 5
HD Color Swap
Addr 15h, Bit 3
DAC A DAC B DAC C DAC D DAC E DAC F
YCrCb 4:2:2
YCrCb 4:2:2
YCrCb 4:2:2
YCrCb 4:2:2
YCrCb 4:4:4
YCrCb 4:4:4
YCrCb 4:4:4
YCrCb 4:4:4
RGB 4:4:4
RGB 4:4:4
RGB 4:4:4
RGB 4:4:4
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
G
G
Y
Y
G
G
Y
Y
G
G
G
G
B
R
Pb
Pr
B
R
Pb
Pr
B
R
B
R
R
B
Pr
Pb
R
B
Pr
Pb
R
B
R
B
Table XIII. Output Configuration in Simultaneous SD/HD Mode
Input Formats
RGB/YUV O/P
Addr 02h, Bit 5
HD Color Swap
Addr 15h, Bit 3
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
SD YCrCb in 4:2:2 and
HD YCrCb in 4:2:2
0
0
CVBS
Luma
Chroma
G
B
R
SD YCrCb in 4:2:2 and
HD YCrCb in 4:2:2
0
1
CVBS
Luma
Chroma
G
R
B
SD YCrCb in 4:2:2 and
HD YCrCb in 4:2:2
1
0
CVBS
Luma
Chroma
Y
Pb
Pr
SD YCrCb in 4:2:2 and
HD YCrCb in 4:2:2
1
1
CVBS
Luma
Chroma
Y
Pr
Pb
–32–
REV. A
ADV7300A/ADV7301A
The minimum time the pin has to be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the SD timing counters only.
TIMING MODES
HD Async Timing Mode
[Subaddress 10h, Bits 3–2]
For any input data that does not conform to SMPTE293M,
SMPTE274M, SMPTE296M, or ITU-R.BT1358 standards,
an Asynchronous Timing Mode can be used to interface to the
ADV7300A/ADV7301A. Timing control signals for HSYNC,
VSYNC, and BLANK have to be programmed by the user.
Macrovision is not available in Async Timing Mode.
b. Subcarrier phase reset, a low-to-high transition on the
RTC_SCR_TR pin (Pin 31), will reset the subcarrier phase
to zero when the SD RTC/TR/SCR control bits at Address 44h
are set to “01.” This reset signal will have to be held high for
a minimum of one clock cycle. Since the Field Counter is
not reset, it is recommended to apply the reset in Field 7
(PAL). The reset of the phase will then occur on the next field
by being correctly lined up with the internal counters. The
Field Count Register at Address 7Bh can be used to identify
the number of the active field.
Figure 28 shows an example of how to program the ADV7300A/
ADV7301A to accept a different high definition standard, other
than SMPTE293M, SMPTE274M, SMPTE296M, or
ITU-R.BT1358 standards.
c. In RTC Mode, the ADV7300A/ADV7301A can be used to
lock to an external video source. The Real-time Control Mode
allows the ADV7300A/ADV7301A to automatically alter the
subcarrier frequency to compensate for line length variations.
When the part is connected to a device that outputs a digital
data stream in the RTC format (such as a ADV7185 video
decoder; see Figure 29), the part will automatically change to
the compensated subcarrier frequency on a line-by-line basis.
This digital data stream is 67 bits wide and the subcarrier is
contained in Bits 0 to 21. Each bit is two clock cycles long.
00h should be written into all four Subcarrier Frequency
Registers when using this mode.
Table XIV must be followed when programming the control signals in Async Timing Mode.
HD Timing Reset
A timing reset is achieved in setting the HD Timing Reset Control Bit at Address 14h from “0” to “1.” In this state, the
horizontal and vertical counters will remain reset. On setting
this bit back to “0,” the internal counters will again commence
counting. The minimum time the pin has to be held high is one
clock cycle; otherwise, this reset signal might not be recognized.
This timing reset applies to the HD timing counters only.
SD Timing
Real-time Control, Subcarrier Reset, Timing Reset
[Subaddress 44h, Bits 2–1]
Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 44h, Bits 1–2], the ADV7300A/ADV7301A can be
used in Timing Reset Mode, Subcarrier Phase Reset Mode,
or RTC Mode.
a. A timing reset is achieved in a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set
to low), the internal counters will again commence counting.
CLK
P_HSYNC
PROGRAMMABLE
INPUT TIMING
P_VSYNC
P_BLANK*
HORIZONTAL SYNC
ACTIVE VIDEO
ANALOG
OUTPUT
81
66
a
66
b
243
1920
c
d
e
*SET ADDRESS 10h, BIT 6 TO “1”
Figure 28. Async Timing Mode, Programming Input Control Signals for SMPTE295M Compatibility
REV. A
–33–
ADV7300A/ADV7301A
Table XIV. Truth Table
P_HSYNC
P_VSYNC1
P_BLANK1
1→0
0
0→1
1
1
0
0→1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0
0→1
1→0
Reference2
50% point of falling edge of tri-level horizontal sync signal
25% point of rising edge of tri-level horizontal sync signal
50% point of falling edge of tri-level horizontal sync signal
50% start of active video
50% end of active video
a
b
c
d
e
NOTES
For standards that do not require a tri-sync level, P_BLANK must be tied low at all times.
1
When Async Timing Mode is enabled, P_BLANK, Pin 25 becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.
2
See Figure 28.
ADV7300A/
ADV7301A
CLKIN_A
DAC A
DAC B
LCC1
COMPOSITE
VIDEO1
RTC_SCR_TR
GLL
ADV7185
DAC C
DAC D
P19–P10
VIDEO
DECODER
S9–S0
DAC E
DAC F
4 BITS
RESERVED
H/L TRANSITION
14 BITS
COUNT START
LOW RESERVED
128
13
0
SEQUENCE
BIT3
RESERVED
FSC PLL INCREMENT2
21
RESET
BIT4
0
RTC
TIME SLOT 01
14
6768
19
VALID INVALID
SAMPLE SAMPLE
NOT USED
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
NOTES
1i.e., VCR OR CABLE
2F
SC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7300A/ADV7301A FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7300A/ADV7301A.
3PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE
4RESET ADV7300A/ADV7301A DDS
Figure 29. RTC Timing and Connections
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW Sync Control Bit can be used for
nonstandard input video, i.e., in Fast Forward or Rewind Modes.
In Fast Forward Mode, the sync information for the start of a
new field in the incoming video usually occurs before the total
number of lines/fields are reached; in Rewind Mode, this sync
signal occurs usually after the total number of lines/fields are
reached. Conventionally, this means that the output video will
have an erroneous start of new field signals, one generated by the
incoming video and one when the internal lines/field counters
reach the end of a field. When VCR FF/RW sync control is en-
abled [Subaddress 42h, Bit 5], the lines/field counters are
updated according to the incoming VSYNC signal, and the analog output matches the incoming VSYNC signal.
This control is available in all slave timing modes except Slave
Mode 0.
RESET SEQUENCE
A reset is activated with a high-to-low transition on the RESET
pin (Pin 33) according to the timing specifications. The
ADV7300A/ADV7301A will revert to the default output configuration. Figure 30 illustrates the RESET sequence timing.
RESET
DACs
DIGITAL TIMING
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
VALID VIDEO
TIMING ACTIVE
PIXEL DATA
VALID
Figure 30. RESET Timing Sequence
–34–
REV. A
ADV7300A/ADV7301A
VERTICAL BLANKING INTERVAL
FILTERS
The ADV7300A/ADV7301A accepts input data that contains
VBI data [CGMS, WSS, VITS, etc.] in SD and HD Modes.
Table XV shows an overview of the programmable filters available on the ADV7300A/ADV7301A.
For SMPTE293M (525 p) standards, VBI data can be inserted on
Lines 13 to 42 of each frame, or Lines 6 to 43 for ITU-R.BT1358
(625 p) standard.
For SD NTSC, this data can be present on Lines 10 to 20, in
PAL on Lines 7 to 22.
If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.
In Slave Mode 0, if VBI is enabled, the Blanking Bit in the
EAV/SAV code is overwritten and it is possible to use VBI in
this timing mode as well.
In Slave Mode 1 or 2, the BLANK Control Bit must be set to
enabled [Address 4Ah, Bit 3] to allow VBI data to pass through
the ADV7300A/ADV7301A. Otherwise, the ADV7300A/
ADV7301A automatically blanks the VBI to standard.
If CGMS is enabled and VBI disabled, the CGMS data will
nevertheless be available at the output.
SD SUBCARRIER FREQUENCY REGISTERS
[Subaddress 4Ch–4Fh]
Four 8-bit wide registers are used to set up the subcarrier frequency. The value of these registers is calculated in using the
equation:
Table XV. Selectable Filters
Filter
Subaddress
SD Luma LPF NTSC
SD Luma LPF PAL
SD Luma Notch NTSC
SD Luma Notch PAL
SD Luma SSAF
SD Luma CIF
SD Luma QCIF
SD Chroma 0.65 MHz
SD Chroma 1.0 MHz
SD Chroma 1.3 MHz
SD Chroma 2.0 MHz
SD Chroma 3.0 MHz
SD Chroma CIF
SD Chroma QCIF
SD UV SSAF
HD Chroma Input
HD Sync Filter
HD Chroma SSAF
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
40h
42h
13h
13h
13h
HD Sync Filter
0.5
0.4
Subcarrier Frequency Register =
0.3
# of Subcarrier Frequency Cycles in One Video Line
× 2 32
# of 27 MHz Clock Cycles in One Video Line
GAIN – dB
0.2
Example:
NTSC Mode
Subcarrier Frequency =
227.5
× 2 32 = 569408542 *
1716
0
–0.1
–0.2
–0.3
–0.4
Subcarrier Register Value = 21F07C1Eh
SD FSC Register 0:
SD FSC Register 1:
SD FSC Register 2:
SD FSC Register 3:
0.1
–0.5
1Eh
7Ch
F0h
21h
0
5
10
15
20
FREQUENCY – MHz
25
30
Figure 31. HD Sync Filter Enabled
Refer to the MPU Port Description section for more detail on
how to access the subcarrier frequency registers.
0.5
0.4
0.3
SUBCARRIER PHASE REGISTER
[Subaddress 50h, 5Ch, Bits 7, 6]
0.2
GAIN – dB
Ten bits are used to set up the subcarrier phase. Each bit represents 0.352°. For normal operation, this register is set to 00h.
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
5
10
15
20
FREQUENCY – MHz
25
Figure 32. HD Sync Filter Disabled
*Rounded to the nearest integer
REV. A
0
–35–
30
ADV7300A/ADV7301A
HD 4:2:2 to 4:4:4 Interpolation Filters and Chroma SSAF
The chroma SSAF is controlled with Address 13h, Bit 5.
When the HD input format is 4:2:2, the HD Chroma Input Bit
[Address 13h, Bit 6] must be set to “1.”
2ⴛ/4ⴛ/8ⴛ Oversampling Filters
The oversampling filters are enabled in setting the PLL ON
control [Subaddress 00h, Bit 1] to “1.” If enabled, PS and
ITU-R.BT656 data is output at a rate of 108 MHz, HDTV at a
rate of 148 MHz.
0
0
–10
–10
–20
–20
–30
–30
GAIN – dB
GAIN – dB
It is recommended to input data in 4:2:2 Input Mode to make
use of the HD chroma SSAFs on the ADV7300A/ADV7301A.
This filter has a 0 dB pass-band response and prevents signal
components from being folded back into the frequency band. In
4:4:4 Input Mode, the video data is already interpolated by the
external input device and the chroma SSAFs of the ADV7300A/
ADV7301A are bypassed.
–40
–50
–50
–60
–60
–70
–70
–80
–80
0
10
20
30
40
50
60
70
FREQUENCY – MHz
80
90
100
0
110
Figure 33. Y – PS 4⫻ Oversampling Filter
40
20
60
80
100
FREQUENCY – MHz
120
140
160
Figure 35. Y – HDTV 2⫻ Oversampling Filter
1.0
1.0
0.5
0.5
0
0
–0.5
–0.5
GAIN – dB
GAIN – dB
–40
–1.0
–1.0
–1.5
–1.5
–2.0
–2.0
–2.5
–2.5
–3.0
–3.0
0
2
4
6
8
FREQUENCY – MHz
10
12
0
14
Figure 34. Y – PS 4⫻ Oversampling Filter in the
Pass Band
5
10
15
20
FREQUENCY – MHz
25
30
35
Figure 36. Y – HDTV 2⫻ Oversampling Filter in
the Pass Band
–36–
REV. A
0
1.0
–10
0.5
–20
0
–30
–0.5
GAIN – dB
GAIN – dB
ADV7300A/ADV7301A
–40
–50
–1.5
–60
–2.0
–70
–2.5
–3.0
–80
0
10
20
30
40
50
60
70
FREQUENCY – MHz
80
90
100
0
110
Figure 37. UV – HDTV 2⫻ Oversampling Filter
0
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
–60
–70
–70
–80
10
20
30
40
50
60
70
FREQUENCY – MHz
80
90
100
6
8
10
12
FREQUENCY – MHz
14
16
18
–80
110
0
Figure 38. UV – PS 4⫻ Oversampling Filter, Linear
REV. A
4
–40
–50
0
2
Figure 39. UV – HDTV 2⫻ Oversampling Filter, Pass Band
GAIN – dB
GAIN – dB
–1.0
10
20
30
40
50
60
70
FREQUENCY – MHz
80
90
100
110
Figure 40. UV – PS 4⫻ Oversampling Filter, SSAF
–37–
ADV7300A/ADV7301A
SD Internal Filter Response
[Subaddress 42h, Bit 0]
0
–10
GAIN – dB
The Y filter supports several different frequency responses
including two low-pass responses, two notch responses, an
extended (SSAF) response with or without gain boost/attenuation, a CIF response, and a QCIF response. The UV filter
supports several different frequency responses, including six
low-pass responses, a CIF response, and a QCIF response, as
can be seen in Figures 41–59.
–20
–30
–40
If SD SSAF gain is enabled, there is the option of 12 responses
in the range from –4 dB to +4 dB. The desired response can be
chosen by the user by programming the correct value via the
I2C. The variation of frequency responses can be seen in
Figures 41–59.
–50
–60
0
1
2
3
4
5
6
FREQUENCY – MHz
In addition to the chroma filters listed above, the ADV7300A/
ADV7301A contains an SSAF filter specifically designed for
and applicable to the color difference component outputs U and
V. This filter has a cutoff frequency of approximately 2.7 MHz
and –40 dB at 3.8 MHz, as shown in Figure 41. This filter can
be controlled via Address 42h, Bit 0. If this filter is disabled, the
selectable chroma filters shown in Table XVI can be used for
the CVBS or chroma signal.
Filter
Pass-Band
Ripple1 (dB)
3 dB
Bandwidth2 (MHz)
Luma LPF NTSC
Luma LPF PAL
Luma Notch NTSC
Luma Notch PAL
Luma SSAF
Luma CIF
Luma QCIF
Chroma 0.65 MHz
Chroma 1.0 MHz
Chroma 1.3 MHz
Chroma 2.0 MHz
Chroma 3.0 MHz
Chroma CIF
Chroma QCIF
0.16
0.1
0.09
0.1
0.04
0.127
Monotonic
Monotonic
Monotonic
0.09
0.048
Monotonic
Monotonic
Monotonic
4.24
4.81
2.3/4.9/6.6
3.1/5.6/6.4
6.45
3.02
1.5
0.65
1
1.395
2.2
3.2
0.65
0.5
0
–10
MAGNITUDE – dB
Table XVI. Internal Filter Specifications
Figure 41. UV SSAF Filter
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
FREQUENCY – MHz
Figure 42. Luma NTSC Low-Pass Filter
0
MAGNITUDE – dB
–10
NOTES
1
Pass-band ripple is the maximum fluctuation from the 0 dB response in the
pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz)
frequency limits for a low-pass filter, 0 Hz to f1 (Hz) and f2 (Hz) to infinity for
a notch filter, where fc, f1, f2 are the –3 dB points.
2
+3 dB bandwidth refers to the –3 dB cutoff frequency.
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
FREQUENCY – MHz
Figure 43. Luma PAL Low-Pass Filter
–38–
REV. A
0
0
–10
–10
–20
–20
MAGNITUDE – dB
MAGNITUDE – dB
ADV7300A/ADV7301A
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
10
8
12
0
2
4
FREQUENCY – MHz
Figure 44. Luma NTSC Notch Filter
10
8
12
Figure 47. Luma SSAF Filter up to 12 MHz
0
4
–10
2
0
MAGNITUDE – dB
–20
MAGNITUDE – dB
6
FREQUENCY – MHz
–30
–40
–2
–4
–6
–50
–8
–60
–10
–70
–12
0
2
4
6
10
8
12
0
1
2
3
4
5
6
7
FREQUENCY – MHz
FREQUENCY – MHz
Figure 45. Luma PAL Notch Filter
Figure 48. Luma SSAF Filter, Programmable Responses
5
0
–10
4
MAGNITUDE – dB
GAIN – dB
–20
–30
–40
–50
3
2
1
–60
0
–70
–80
–1
0
10
20
30
40
50
60
70
FREQUENCY – MHz
80
90
100
110
0
2
3
4
5
6
7
FREQUENCY – MHz
Figure 46. Luma SSAF Filter up to 108 MHz
REV. A
1
Figure 49. Luma SSAF Filter, Programmable Gain
–39–
ADV7300A/ADV7301A
1
0
–10
MAGNITUDE – dB
MAGNITUDE – dB
0
–1
–2
–3
–20
–30
–40
–50
–4
–60
–70
–5
0
1
2
3
5
4
6
0
7
2
6
0
–10
–10
–20
–20
MAGNITUDE – dB
0
–30
–40
10
12
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
0
12
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 54. Chroma 2.0 MHz LP Filter
Figure 51. Luma CIF LP Filter
0
0
–10
–10
–20
–20
MAGNITUDE – dB
MAGNITUDE – dB
8
Figure 53. Chroma 3.0 MHz LP Filter
Figure 50. Luma SSAF Filter, Programmable Attenuation
MAGNITUDE – dB
4
FREQUENCY – MHz
FREQUENCY – MHz
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
0
12
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 55. Chroma 1.3 MHz LP Filter
Figure 52. Luma QCIF LP Filter
–40–
REV. A
0
0
–10
–10
–20
–20
MAGNITUDE – dB
MAGNITUDE – dB
ADV7300A/ADV7301A
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
0
12
2
4
8
10
12
Figure 58. Chroma CIF LP Filter
0
0
–10
–10
–20
–20
MAGNITUDE – dB
MAGNITUDE – dB
Figure 56. Chroma 1.0 MHz LP Filter
–30
–40
–30
–40
–50
–50
–60
–60
–70
–70
0
2
4
6
8
10
0
12
2
4
6
8
10
FREQUENCY – MHz
FREQUENCY – MHz
Figure 57. Chroma 0.65 MHz LP Filter
REV. A
6
FREQUENCY – MHz
FREQUENCY – MHz
Figure 59. Chroma QCIF LP Filter
–41–
12
ADV7300A/ADV7301A
COLOR CONTROLS AND RGB MATRIX
HD Y Color, HD Cr Color, HD Cb Color
[Subaddresses 16h–18h]
Three 8-bit wide registers at Addresses 16h, 17h, and 18h are used
to program the output color of the internal HD test pattern generator, be it the lines of the crosshatch pattern or the uniform field
test pattern. They are not functional as color controls on external
pixel data input. For this purpose, the RGB matrix is used.
The standard used for the values for Y and the color difference
signals to obtain white, black, and the saturated primary and
complementary colors conforms to the ITU-R.BT601–
ITU-R.BT604 standards. Table XVII shows sample color
values to be programmed into the color registers when Output
Standard Selection is set to EIA 770.2.
Color Y
Value
Color Cr
Value
Color Cb
Value
White
Black
Red
Green
Blue
Yellow
Cyan
Magenta
235 (EB)
16 (10)
81 (51)
145 (91)
41 (29)
210 (D2)
170 (AA)
106 (6A)
128 (80)
128 (80)
240 (F0)
34 (22)
110 (6E)
146 (92)
16 (10)
222 (DE)
128 (80)
128 (80)
90 (5A)
54 (36)
240 (F0)
16 (10)
166 (A6)
202 (CA)
To make use of the programmable RGB matrix, the YCrCb
data should contain the HSYNC signal on the Y channel only.
The RGB matrix should be enabled [Address 02h, Bit 3], the
output should be set to RGB [Address 02h, Bit 3], Sync on
PrPb should be disabled [Address 15h, Bit 2], and Sync on
RGB is optional [Address 02h, Bit 4].
GY at Addresses 03h and 05h control the output levels on the
green signal, BU at 04h and 08h the blue signal output levels,
and RV at 04h and 09h the red output levels. To control YPrPb
output levels, YUV output should be enabled [Address 02h,
Bit 5]. In this case, GY [Address 05h; Address 03, Bits 0–1] is
used for the Y output, RV [Address 09; Address 04, Bits 0–1] is
used for the Pr output, and BU [Address 08h; Address 04h,
Bits 2–3] is used for the Pb output.
Table XVII. Sample Color Values for EIA 770.2 Output
Standard Selection
Sample
Color
standards due to altering the DAC output stages, such as termination resistors, for example. The programmable RGB matrix is
used for external HD data and is not functional when the HD
test pattern is enabled.
If RGB output is selected, the RGB matrix scaler uses the following equations:
R = GY × Y + RV × Cr
G = GY × Y − GU × Cb − GV × Cr
B = GY × Y + BU × Cb
If YUV output is selected, the following equations are used:
R = RV × Cr
G = GY × Y
B = BU × Cb
HD RGB Matrix
[Subaddresses 03h–09h]
When the programmable RGB matrix is disabled [Address 02h,
Bit 3], the internal RGB matrix takes care of all YCrCb to YUV
or RGB scaling according to the input standard programmed
into the device.
On power-up, the RGB matrix is programmed with default values:
Address 03h: 03h
Address 04h: F0h
Address 05h: 4Eh
Address 06h: 0Eh
Address 07h: 24h
Address 08h: 92h
Address 09h: 7Ch
When the programmable RGB matrix is enabled, the color
components are converted according to the SMPTE274M
standard (1080 i):
Y ' = (0.2126 × R') + (0.7152 × G ') + (0.0722 × B')
When the programmable RGB matrix is not functional, the
ADV7300A/ADV7301A automatically scales YCrCb inputs to
all standards supported. For SMPTE293M, the register values
are as follows:
0.5
× (B' −Y ')
1 − 0.0722
0.5
× (R' −Y ')
Cr ' =
1 − 0.2126
Cb' =
Address 03h: 03h
Address 04h: 1Eh
Address 05h: 4Eh
Address 06h: 1Bh
Address 07h: 38h
Address 08h: 8Bh
Address 09h: 6Eh
This is reflected in the preprogrammed values for GY = 13Bh,
RV = 1F0h, BU = 248h, GV = 93h, and GU = 3Bh.
If another input standard is used, the scale values for GY, GU,
GV, BU, and RV have to be adjusted according to this input
standard. It must be considered by the user that the color component conversion might use different scale values. For
example, SMPTE293M uses the following conversion:
Address 15h, Bit 3 must be set to “1” in this mode.
SD Color Control
[Subaddresses 5Ch, 5Dh, 5Eh, and 5Fh]
Y ' = (0.299 × R') + (0.587 × G ') + (0.114 × B')
SD Y SCALE, SD Cr SCALE, and SD Cb SCALE are three
10-bit wide control registers to scale the Y, U, and V output
levels.
0.5
× (B' −Y ')
1 − 0.114
0.5
× (R' −Y ')
Cr ' =
1 − 0.299
Cb' =
The programmable RGB matrix can be used to control the HD
output levels in cases where the video output does not conform to
Each of these registers represents the value required to scale the U
or V level from 0 to 2.0 and the Y level from 0 to 1.5 of its initial
level. The value of these 10 bits is calculated using the equation:
–42–
REV. A
ADV7300A/ADV7301A
Y, U, or V Scalar Value = Scale Factor ⫻ 512
SD Brightness Control
[Subaddress 61h]
Example:
Scale Factor = 1.18
The brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the scaled Y data. For NTSC with pedestal, the setup can
vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and
for PAL, the setup can vary from –7.5 IRE to +15 IRE.
Y, U, or V Scale Value = 1.18 ⫻ 512 = 665.6
Y, U, or V Scale Value = 665 (rounded to nearest integer)
Y, U, or V Scale Value = 1010011001b
The Brightness Control Register is an 8-bit wide register. Seven
bits are used to control the brightness level. This brightness
level can be a positive or negative value.
Address 5Ch, SD LSB Register = 15h
Address 5Dh, SD Y Scale Register = A6h
Address 5Eh, SD V Scale Register = A6h
Address 5Fh, SD U Scale Register = A6h
Example:
Standard: NTSC with pedestal. To add +20 IRE brightness
level, write 28h to Address 61h, SD Brightness:
SD Hue Adjust Value
[Subaddress 60h]
The hue adjust value is used to adjust the hue on the composite
and chroma outputs.
SD Brightness Value (hex) = (IRE Value ⫻ 2.015631)
These 8 bits represent the value required to vary the hue of the
video data, i.e., the variance in phase of the subcarrier during
active video with respect to the phase of the subcarrier during the
color burst. The ADV7300A/ADV7301A provide a range of
± 22.5° in increments of 0.17578125°. For normal operation (zero
adjustment), this register is set to 80h. FFh and 00h represent the
attainable upper and lower limit (respectively) of adjustment.
For a positive hue adjust value:
Example:
To adjust the hue by +4°, write 97h to the Hue Adjust Value
Register:
SD Brightness Value (hex) = (IRE Value ⫻ 2.015631)
0001110b = (7 ⫻ 2.015631) = 14.109417
0001110 in twos complement equals 1110010, or 72h.
The ADV7300A/ADV7301A allows monitoring of the brightness level of the incoming video data. The Brightness Detect
Register is a read-only register.
Double Buffering
[Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]
+4
+ 128 = 151 = 97 h
0.17578125
where 151 is rounded to the nearest integer. To adjust the hue
by –4°, write 69h to the Hue Adjust Value Register:
where 105 is rounded to the nearest integer.
Standard: PAL. To add –7 IRE brightness level, write 72h to
Address 61h, SD Brightness:
SD Brightness Detect
[Subaddress 7Ah]
0.17578125° ⫻ (HCR – 128)
–4
+ 128 = 105 = 69h
0.17578125
28h = (20 ⫻ 2.015631) = 40.31262
Double buffered registers are updated once per field on the
falling edge of the VSYNC signal. Double buffering improves
the overall performance since modifications to register settings
will not be made during active video but take effect on the start
of the active video.
Double buffering can be activated on the following HD registers: HD Gamma A and Gamma B curves and HD CGMS
Registers. Double buffering can be activated on the following
SD Registers: SD Gamma A and Gamma B Curves,
SD Y Scale, SD U Scale, SD V Scale, SD Brightness,
SD Closed Captioning, and SD Macrovision Bits 5–0.
Table XVIII. Brightness Control Values
Setup Level—
NTSC w/Pedestal (IRE)
Setup Level—
NTSC w/o Pedestal (IRE)
Setup Level—
PAL (IRE)
SD Brightness
Value
22.5
15
7.5
0
+15
+7.5
0
–7.5
+15
+7.5
0
–7.5
1Eh
0Fh
00h
71h
Values in the range from 3Fh to 44h might result in an invalid output signal.
NTSC WITHOUT PEDESTAL
+7.5 IRE
100 IRE
0 IRE
–7.5 IRE
NO SETUP
VALUE ADDED
POSITIVE SETUP
VALUE ADDED
NEGATIVE SETUP
VALUE ADDED
Figure 60. Examples for Brightness Control Values
REV. A
–43–
ADV7300A/ADV7301A
Example:
Gamma Correction
[Subaddresses 21h–37h for HD;
Subaddresses 66h–79h for SD]
  8  0.5

y24 =  
× 224 + 16 = 58 *

  224 



Gamma correction is available for SD and HD video. For each
standard there are twenty 8-bit wide registers. They are used to
program the Gamma Correction Curves A and B. HD Gamma
Curve A is programmed at Addresses 24h–2Dh and HD
Gamma Curve B at 2Eh–37h. SD Gamma Curve A is programmed at Addresses 66h–6Fh, and SD Gamma Curve B at
Addresses 70h–79h.
y32
  32  0.5

y 48 =  
× 224 + 16 = 101 *

  224 



Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used.
  48 
y64 =  
  224 

Gamma correction uses the function:
SignalOUT = (SignalIN )
where ␥ equals the gamma power factor.
y96
Gamma correction is performed on the luma data only. The
user has the choice to use two different curves, Curve A or
Curve B. At any one time only one of these curves can be used.
The response of the curve is programmed at 10 predefined
locations. In changing the values at these locations, the gamma
curve can be modified. Between these points, linear interpolation is used to generate intermediate values. Considering the
curve to have a total length of 256 points, the 10 locations are
at: 24, 32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0,
16, 240, and 255 are fixed and cannot be changed.

× 224 + 16 = 120 *


  80  0.5

= 
× 224 + 16 = 150 *

  224 



  112  0.5

y128 =  
× 224 + 16 = 174 *

  224 



  144  0.5

y160 =  
× 224 + 16 = 195 *

  224 



  176  0.5

y192 =  
× 224 + 16 = 214 *

  224 



For the length of 16 to 240, the gamma correction curve must
be calculated as:
  208  0.5

y224 =  
× 224 + 16 = 232 *

  224 



y = xγ
To program the gamma correction registers, the values for y
must be calculated using the formula:
0.5
  64  0.5

y80 =  
× 224 + 16 = 136 *

  224 



γ
where y = gamma corrected output, x = linear input signal, and
␥ = the gamma power factor.
  16  0.5

= 
× 224 + 16 = 76 *

  224 



The gamma curves shown in Figures 61 and 62 are examples.
Any user-defined curve is acceptable in the range of 16–240.
300
γ
GAMMA CORRECTED AMPLITUDE
 x(n−16) 
yn = 
 × (240 − 16) + 16
 240 − 16 
where x(n–16) = the value for x along the x-axis at points n = 24,
32, 48, 64, 80, 96, 128, 160, 192, or 224; yn = the value for y
along the y-axis, which has to be written into the Gamma Correction Register.
250
0.5
200
SIGNAL OUTPUT
150
100
SIGNAL INPUT
50
0
0
50
100
150
LOCATION
200
250
Figure 61. Signal Input (Ramp) and Signal Output
for Gamma 0.5
*Rounded to the nearest integer
–44–
REV. A
ADV7300A/ADV7301A
To select one of the 256 individual responses, the corresponding gain values for each filter, which range from –8 to +7, must
be programmed into the HD Sharpness Filter Gain Register at
Address 20h.
GAMMA CORRECTED AMPLITUDE
300
250
SIGNAL INPUT
0.3
HD Adaptive Filter Mode
200
The HD Adaptive Filter Threshold A, B, C Registers, the HD
Adaptive Filter Gain 1, 2, and 3 Registers, and the HD Sharpness Filter Gain Register are used in Adaptive Filter Mode. To
activate the adaptive filter control, the HD Sharpness Filter and
HD Adaptive Filter Enable must be enabled.
0.5
150
1.5
100
1.8
The derivative of the incoming signal is compared to the three
programmable threshold values: HD Adaptive Filter Threshold
A, B, C. The recommended threshold range is from 16–235,
although any value in the range of 0–255 can be used.
50
0
0
50
100
150
LOCATION
200
250
The edges can then be attenuated with the settings in HD
Adaptive Filter Gain 1, 2, 3 Registers and HD Sharpness Filter
Gain Register.
Figure 62. Signal Input (Ramp) and Selectable
Gamma Output
According to the settings of the HD Adaptive Filter Mode control, there are two adaptive filter modes available:
HD SHARPNESS FILTER CONTROL AND ADAPTIVE
FILTER CONTROL
[Subaddresses 20h and 38h-3Dh]
There are three filter modes available on the ADV7300A/
ADV7301A: Sharpness Filter Mode and two adaptive filter
modes.
HD Sharpness Filter Mode
1.5
1.4
1.4
1.3
1.3
1.2
1.2
1.1
1.0
0.9
1.6
1.1
1.0
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
2. Mode B is used when Adaptive Filter Mode is set to “1.” In
this mode, a cascade of Filter A and Filter B is used. Both
settings for Gain A and Gain B in the HD Sharpness Filter
Gain, HD Adaptive Filter Gain 1, 2, 3 become active when
needed.
MAGNITUDE – Linear Scale
1.5
MAGNITUDE
INPUT SIGNAL:
STEP
MAGNITUDE
To enhance or attenuate the Y signal in the frequency ranges
shown in Figure 63, the following register settings must be used:
HD Sharpness Filter must be enabled and HD Adaptive Filter
Enable must be set to disabled.
1. Mode A is used when Adaptive Filter Mode is set to “0.” In
this case, Filter B (LPF) will be used in the adaptive filter
block. Also, only the programmed values for Gain B in the
HD Sharpness Filter Gain, HD Adaptive Filter Gain 1, 2, 3
are applied when needed. The Gain A values are fixed and
cannot be changed.
1.5
1.4
1.3
1.2
1.1
0.5
1.0
FREQUENCY – MHz
FREQUENCY – MHz
FILTER A RESPONSE – Gain Ka
FILTER B RESPONSE – Gain Kb
0
2
4
6
8
10
FREQUENCY – MHz
12
FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7
Figure 63. Sharpness and Adaptive Filter Control Block
REV. A
–45–
ADV7300A/ADV7301A
a
d
b
e
c
f
Figure 64. HD Sharpness Filter Control with Different Gain Settings for HD Sharpness Filter Gain Value
HD Sharpness Filter and Adaptive Filter Application Examples
HD Sharpness Filter Application
The HD sharpness filter can be used to enhance or attenuate
the Y video output signal.
Adaptive Filter Control Application
Figure 65 shows a typical signal to be processed by the adaptive
filter control block.
: 692mV
@: 446mV
: 332ns
@: 12.8ms
The register settings in Tables XIX and XX are used to achieve
the results shown in Figure 64. Input data was generated by an
external signal source.
Table XIX. Sharpness Filter on Frequency Sweep
Address
Register Setting
Reference*
00h
01h
02h
10h
11h
20h
20h
20h
20h
20h
20h
FCh
10h
20h
00h
81h
00h
08h
04h
40h
80h
22h
a
b
c
d
e
f
Figure 65. Input Signal to Adaptive Filter Control
: 690mV
@: 446mV
: 332ns
@: 12.8ms
*See Figure 64.
The effect of the sharpness filter can also be seen when using the
internally generated crosshatch pattern.
Table XX. Sharpness Filter on Internal Test Pattern
Address
Register Setting
00h
01h
02h
10h
11h
20h
FCh
10h
20h
00h
85h
99h
In toggling the Sharpness Filter Enable Bit [Address 11h,
Bit 8], it can be seen that the line contours of the crosshatch
pattern change their sharpness.
Figure 66. Output Signal After Adaptive Filter Control
The register settings in Table XXI are used to obtain the results
shown in Figure 66, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.
–46–
REV. A
ADV7300A/ADV7301A
Table XXI. Adaptive Filter Control on Step Input Signal
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
38h
20h
00h
81h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
SD DIGITAL NOISE REDUCTION
[Subaddresses 63h, 64h, and 65h]
DNR is applied to the Y data only. A filter block selects the high
frequency, low amplitude components of the incoming signal
(DNR input select). The absolute value of the filter output is
compared to a programmable threshold value (DNR threshold
control). There are two DNR modes available: DNR Mode and
DNR Sharpness Mode.
In DNR Mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount (coring gain border, coring gain data) of this noise signal
will be subtracted from the original signal.
All other register settings are 00h.
When changing the Adaptive Filter Mode to Mode B
[Address 15h, Bit 6], the output in Figure 67 can be obtained.
: 674mV
@: 446mV
: 332ns
@: 12.8ms
In DNR Sharpness Mode, if the absolute value of the filter
output is less than the programmed threshold, it is assumed to
be noise, as before. Otherwise, if the level exceeds the threshold,
now being identified as a valid signal, a fraction of the signal
(coring gain border, coring gain data) will be added to the original signal in order to boost high frequency components and to
sharpen the video image.
In MPEG systems, it is common to process the video information
in blocks of 8 ⫻ 8 pixels for MPEG2 systems or 16 ⫻ 16 pixels for
MPEG1 systems (block size control). DNR can be applied to the
resulting block transition areas that are known to contain noise.
Generally, the block transition area contains two pixels. It is possible to define this area to contain four pixels (border area.)
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the (DNR
block offset.)
DNR MODE
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
GAIN
Figure 67. Output Signal from Adaptive Filter Control
NOISE
SIGNAL PATH
The adaptive filter control can also be demonstrated using the
internally generated crosshatch test pattern and toggling the Adaptive Filter Control Bit [Address 15h, Bit 7], shown in Table XXII.
INPUT FILTER
BLOCK
Table XXII. Adaptive Filter Control on Internal Test Pattern
Address
Register Setting
00h
01h
02h
10h
11h
15h
20h
38h
39h
3Ah
3Bh
3Ch
3Dh
FCh
38h
20h
00h
85h
80h
00h
ACh
9Ah
88h
28h
3Fh
64h
CORING GAIN DATA
CORING GAIN BORDER
FILTER
OUTPUT
< THRESHOLD ?
Y DATA
INPUT
SUBTRACT SIGNAL
IN THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
FILTER OUTPUT
> THRESHOLD
DNR OUT
MAIN SIGNAL PATH
DNR
SHARPNESS
MODE
DNR CONTROL
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
GAIN
NOISE
SIGNAL PATH
CORING GAIN DATA
CORING GAIN BORDER
INPUT FILTER
BLOCK
Y DATA
INPUT
FILTER
OUTPUT
> THRESHOLD ?
ADD SIGNAL
ABOVE THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
FILTER OUTPUT
< THRESHOLD
DNR OUT
MAIN SIGNAL PATH
Figure 68. DNR Block Diagram
REV. A
–47–
ADV7300A/ADV7301A
The Digital Noise Reduction Registers are three 8-bit wide
registers. They are used to control the DNR processing.
Block Size Control
[Address 64h, Bit 7]
Coring Gain Border
[Address 63h, Bits 3–0]
This bit is used to select the size of the data blocks to be processed. Setting the block size control function to a Logic “1”
defines a 16 ⫻ 16 pixel data block; a Logic “0” defines an 8 ⫻ 8
pixel data block, where one pixel refers to two clock cycles at
27 MHz.
These four bits are assigned to the gain factor applied to the
border areas. In DNR Mode the range of gain values is 0–1, in
increments of 0.125. This factor is applied to the DNR filter
output that lies below the set threshold range. The result is then
subtracted from the original signal.
In DNR Sharpness Mode, the range of gain values is 0 to 0.5, in
increments of 0.0625. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added
to the original signal.
DNR Input Select Control
[Address 65h, Bits 2–0]
Three bits are assigned to select the filter that is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that will be DNR processed. The figure
below shows the filter responses selectable with this control.
Coring Gain Data
[Address 63h, Bits 7–4]
1.0
FILTER D
These four bits are assigned to the gain factor applied to the
luma data inside the MPEG pixel block.
0.8
In DNR Mode, the range of gain values is 0–1, in increments of
0.125. This factor is applied to the DNR filter output that lies
below the set threshold range. The result is then subtracted
from the original signal.
FILTER C
0.6
0.4
In DNR Sharpness Mode, the range of gain values is 0–0.5, in
increments of 0.0625. This factor is applied to the DNR filter
output that lies above the threshold range. The result is added
to the original signal.
0.2
FILTER A
0
APPLY DATA
CORING GAIN
APPLY BORDER
CORING GAIN
DNR27 – DNR24 = 01HEX
2
3
4
FREQUENCY – Hz
5
6
This bit controls the DNR Mode selected. A Logic “0” selects
DNR Mode, and a Logic “1” selects DNR Sharpness Mode.
DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.
OXXXX XXO OXXXX XXO
DNR Threshold
[Address 64h, Bits 5–0]
These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.
Border Area
[Address 64h, Bit 6]
In setting this bit to a Logic “1,” the block transition area can
be defined to consist of four pixels. If this bit is set to a Logic
“0,” the border transition area consists of two pixels, where one
pixel refers to two clock cycles at 27 MHz.
2 PIXEL
BORDER DATA
8ⴛ8 PIXEL BLOCK
1
DNR Mode Control
[Address 65h, Bit 3]
OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING
Figure 69. DNR Block Offset Control
720ⴛ485 PIXELS
(NTSC)
0
Figure 71. DNR Input Select
OXXXX XXO OXXXX XXO
OXXXX XXO OXXXX XXO
FILTER B
In DNR Mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.
When DNR Sharpness Mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the original signal, since this data is assumed to be valid data and not
noise. The overall effect is that the signal will be boosted (similar
to using extended SSAF filter).
Block Offset Control
[Address 65h, Bits 7–4]
Four bits are assigned to this control which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel
such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.
8ⴛ8 PIXEL BLOCK
Figure 70. DNR Border Area
–48–
REV. A
ADV7300A/ADV7301A
SD ACTIVE VIDEO EDGE
[Subaddress 42h, Bit 7]
When the active video edge is enabled, the first three pixels and
the last three pixels of the active video on the Luma Channel are
scaled in such a way that maximum transitions on these pixels
are not possible. The scaling factors are 1/8⫻, 1/2⫻, and 7/8⫻.
All other active video passes through unprocessed.
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED
LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED
100 IRE
100 IRE
87.5 IRE
50 IRE
12.5 IRE
0 IRE
0 IRE
Figure 72. Active Video Edge Functionality Example
BOARD DESIGN AND LAYOUT CONSIDERATIONS
DAC Termination and Layout Considerations
6.8H
The ADV7300A/ADV7301A contain an on-board voltage reference. The VREF pin is normally terminated to VAA through a
0.1 µF capacitor when the internal VREF is used. Alternatively,
the ADV7300A/ADV7301A can be used with an external VREF (e.g.,
AD1580). The RSET resistors are connected between the RSET
pins and AGND and are used to control the full-scale output
current and, therefore, the DAC voltage output levels. For
full-scale output, RSET must have a value of 760 Ω. The RSET
values should not be changed. RLOAD has a value of 150 Ω for
full-scale output.
Output buffering on all six DACs is necessary in order to drive
output devices, such as SD or HD monitors. Analog Devices
produces a range of suitable op amps for this application, for
example the AD8061. More information on line driver buffering
circuits is given in the relevant op amp data sheets.
An optional analog reconstruction LPF might be required as an
antialias filter if the ADV7300A/ADV7301A is connected to a
device that requires this filtering. The filter specifications vary
with the application, see Table XXIII.
Table XXIII. External Filter Requirements
300R
SD
SD
PS
PS
HDTV
HDTV
2⫻
8⫻
1⫻
4⫻
1⫻
2⫻
REV. A
>6.5 MHz
>6.5 MHz
>12.5 MHz
>12.5 MHz
>30 MHz
>30 MHz
75R
300R
BNC O/P
600R
Figure 73. Example for Output Filter for SD, 8⫻
Oversampling
36n480
0
–10
MAGNITUDE (dB)
GROUP DELAY (sec)
–20
30n360
24n240
–30
18n120
–40
12n0
6n–120
–50
PHASE (Deg)
–60
1
External Filter Cutoff
Oversampling Frequency Attenuation
47pF
600R
THIRD ORDER LOW-PASS BUTTERWORTH
Video Output Buffer and Optional Output Filter
Input
Mode
6.8H
DAC O/P
10
CIRCUIT FREQUENCY RESPONSE – MHz
0n–240
100
Figure 74. Filter Plot for Output Filter for SD, 8⫻
Oversampling
–50 dB @ 20.5 MHz
–50 dB @ 101.5 MHz
–50 dB @ 14.5 MHz
–50 dB @ 95.5 MHz
–50 dB @ 44.25 MHz
–50 dB @ 118.5 MHz
–49–
ADV7300A/ADV7301A
6.8H
2.2H
6.8pF
18pF
Table XXIV. Possible Output Rates
DAC O/P
300R
75R
300R
600R
BNC O/P
Output Rate
SD
Off
On
27 MHz (2⫻)
108 MHz (8⫻)
PS
Off
On
27 MHz (1⫻)
108 MHz (4⫻)
HDTV
Off
On
74.25 MHz (1⫻)
148.5 MHz (2⫻)
SD and
Off
On
Off
On
27 MHz (2⫻)
108 MHz (8⫻)
27 MHz (1⫻)
108 MHz (4⫻)
Off
On
Off
On
27 MHz (2⫻)
108 MHz (8⫻)
74.25 MHz (1⫻)
74.25 MHz (1⫻)
Off
On
Off
On
27 MHz (2⫻)
27 MHz (2⫻)
74.25 MHz (1⫻)
148.5 MHz (2⫻)
30n480
0
FOURTH ORDER LOW-PASS BUTTERWORTH
PLL
Addr 00h, Bit 1
600R
Figure 75. Example of Output for Output Filter for
PS, 4⫻ Oversampling
MAGNITUDE (dB)
25n360
–10
PS
GROUP DELAY (sec)
–20
20n240
–30
15n120
–40
10n0
SD* and
HDTV
SD and
PHASE (Deg)
–50
5n–120
–60
0n–240
HDTV*
10M
100M
CIRCUIT FREQUENCY RESPONSE – Hz
*Oversampled
Figure 76. Filter Plot for Output Filter for PS, 4⫻
Oversampling
470nH
220nH
33pF
82pF
BNC O/P
75R
75R
500R
DAC O/P
500R
300R
Figure 77. Example for Output Filter HDTV, 2⫻
Oversampling
14n498
0
FOURTH ORDER LOW-PASS BUTTERWORTH
Input Mode
Addr 01h, Bits 6–4
MAGNITUDE (dB)
12n398
–8.6
GROUP DELAY (sec)
PCB Board Layout Considerations
The ADV7300A/ADV7301A is optimally designed for lowest
noise performance, both radiated and conducted noise. To
complement the excellent noise performance of the ADV7300A/
ADV7301A, it is imperative that great care be given to the PC
board layout. The layout should be optimized for the lowest
noise on the ADV7300A/ADV7301A power and ground lines.
This can be achieved by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA
and AGND, VDD and DGND, and VDD_IO and GND_IO pins
should be kept as short as possible to minimize
inductive ringing.
It is recommended that a four-layer printed circuit board be
used with power and ground planes separating the layer of the
signal carrying traces of the components and solder side layer.
Placement of components should take into account noisy circuits, such as crystal clocks, high speed logic circuitry, and
analog circuitry.
–17.1
10n298
There should be a separate analog ground plane and a separate
digital ground plane.
–25.7
8n198
–34.3
6n97.6
–42.9
4n0
Power planes should encompass a digital and an analog power
plane. The analog power plane should contain the DACs and all
associated circuitry, VREF circuitry. The digital power plane
should contain all logic circuitry. The analog and digital power
planes should be individually connected to the common power
plane at one single point through a suitable filtering device, such
as a ferrite bead.
PHASE (Deg)
–51.4
2n–102
0n–203
–60.0
1
10
100
CIRCUIT FREQUENCY RESPONSE – MHz
Figure 78. Filter Plot for Output Filter for HDTV,
2⫻ Oversampling
DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than three inches). The DAC
termination resistors should be placed as close as possible to the
DAC outputs and should overlay the PCB’s ground plane. As
–50–
REV. A
ADV7300A/ADV7301A
Digital Signal Interconnect
well as minimizing reflections, short analog output traces will
reduce noise pickup due to neighboring digital circuitry.
The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane. Due to
the high clock rates used, long clock lines to the ADV7300A/
ADV7301A should be avoided to minimize noise pickup. Any
active pull-up termination resistors for the digital inputs should
be connected to the digital power plane and not the analog
power plane.
To avoid crosstalk between the DAC outputs, it is recommended
to leave as much space as possible between the tracks of the
individual DAC output pins.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of decoupling capacitors. Optimum performance is achieved
by the use of 0.1 µF ceramic capacitors. Each of the group of
VAA, VDD, or VDD_IO pins should be individually decoupled to
ground. This should be done by placing the capacitors as close
as possible to the device with the capacitor leads as short as
possible, thus minimizing lead inductance.
Analog Signal Interconnect
The ADV7300A/ADV7301A should be located as close as possible to the output connectors, thus minimizing noise pickup
and reflections due to impedance mismatch. For optimum performance, the analog outputs should each be source and load
terminated, as shown in Figure 79. The termination resistors
should be as close as possible to the ADV7300A/ADV7301A to
minimize reflections.
Any unused inputs should be tied to ground.
POWER SUPPLY DECOUPLING FOR
EACH POWER SUPPLY GROUP
VAA
0.1F
10nF
VAA
0.1F
VDD
VAA
0.1F
10nF
10, 56
0.1F
10nF
VDD_IO
0.1F
COMP1 COMP2 VAA VDD VDD_IO
VREF
S0–S9
SD CVBS/GREEN/Y
DAC A
150
S_HSYNC
DAC B
S_VSYNC
SD LUMA/BLUE/U
150
S BLANK
SD CHROMA/RED/V
DAC C
150
C0–C9
HD Y/GREEN
DAC D
Y0–Y9
ADV7300A/
ADV7301A
150
DAC E
P_HSYNC
HD Pb/BLUE
150
VDD_IO
P_VSYNC
DAC F
VAA
HD Pr/RED
150
P_BLANK
5k
47k
SCLK
RESET
4.7F
6.3V
SDA
CLKIN_B
VDD_IO
I2C
VAA
CLKIN_A
VDD_IO
ALSB
820pF
GND_IO AGND DGND
3.9nF
5k
RSET1
EXT_LF
680R
760
RSET2
760
11, 57
UNUSED INPUTS SHOULD BE GROUNDED
Figure 79. Circuit Layout
REV. A
VDD_IO
–51–
5k
5k
I2C
BUS
ADV7300A/ADV7301A
Appendix A
COPY GENERATION MANAGEMENT SYSTEM
HD CGMS DATA Registers 2–0
[Subaddress 12h]
March 1998” and IEC61880, 1998, video systems (525/60)—
video and accompanied data using the vertical blanking
interval—analog interface.
HD CGMS is available in 525 p Mode only, conforming to
“CGMS-A EIA-J CPR1204-1, Transfer Method of Video ID
information using vertical blanking interval (525 p System),
When HD CGMS is enabled, CGMS data is inserted on
Line 41. The HD CGMS Data Registers are to be found at
Addresses 21h, 22h, and 23h.
CRC SEQUENCE
+700mV
BIT 1
REF
BIT 20
70% 10%
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0mV
–300mV
21.2s 0.22s
22T
5.8s 0.15s
6T
T = 1/(fH 33) = 963ns
fH = HORIZONTAL SCAN FREQUENCY
T 30ns
Figure 80. CGMS Waveform
output directly from the CGMS registers (no CRC calculated;
must be calculated by the user).
SD CGMS Data Registers 2–0
[Subaddresses 59h, 5Ah, and 5Bh]
The ADV7300A/ADV7301A supports Copy Generation Management System (CGMS) conforming to the standard. CGMS
data is transmitted on Line 20 of the odd fields and Line 283 of
the even fields. Bits C/W05 and C/W06 control whether or not
CGMS data is output on odd and even fields. CGMS data can
only be transmitted when the ADV7300A/ADV7301A is configured in NTSC Mode. The CGMS data is 20 bits long; the
function of each of these bits is as shown below. The CGMS
data is preceded by a reference pulse of the same amplitude and
duration as a CGMS bit, see Figure 81.
If SD CGMS CRC [Address 59h, Bit 4] is set to a Logic “1,”
the last six bits, C19–C14, that comprise the 6-bit CRC check
sequence are calculated automatically on the ADV7300A/
ADV7301A based on the lower 14 bits (C0–C13) of the data in
the data registers and output with the remaining 14 bits to form
the complete 20 bits of the CGMS data. The calculation of the
CRC sequence is based on the polynomial:
Table XXV. Function of CGMS Bits
Word
Bit
Function
0
B1
Aspect Ratio
B2
Display Format
B3
B4–B6
Undefined
Identification Information about Video
and Other Signals (i.e., Audio)
1
B7–B10
Identification Signal. Incidental to Word 0.
2
B11–B14
Identification Signal and Information.
Incidental to Word 0.
0 = 4:3
1 = 16:9
0 = Normal
1 = Letterbox
x6 + x + 1
with a preset value of 111111. If SD CGMS CRC [Address
59h, Bit 4] is set to a Logic “0,” then all 20 bits (C0–C19) are
+100 IRE
CRC SEQUENCE
REF
+70 IRE
C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
0 IRE
–40 IRE
49.1s 0.5s
11.2s
2.235s 20ns
Figure 81. CGMS Waveform
–52–
REV. A
ADV7300A/ADV7301A
Appendix B
SD WIDE SCREEN SIGNALING
[Subaddresses 59h, 5Ah, and 5Bh]
Table XXVII. Function of WSS Bits 0–3
The ADV7300A/ADV7301A supports Wide Screen Signaling
(WSS) conforming to the standard. WSS data is transmitted on
Line 23. WSS data can only be transmitted when the ADV7300A/
ADV7301A is configured in PAL Mode. The WSS data is 14 bits
long. The function of each of these bits is shown in Table XXVI.
The WSS data is preceded by a run-in sequence and a start code
(see Figure 82). If SD WSS [Address 59h, Bit 7] is set to a Logic
“1,” it enables the WSS data to be transmitted on Line 23. The
latter portion of Line 23 (42.5 µs from the falling edge of HSYNC)
is available for the insertion of video.
B0 B1 B2 B3
Aspect Ratio
Format
Position
0
1
0
1
0
1
0
1
4:3
14:9
14:9
16:9
16:9
>16:9
14:9
16:9
Full Format
Letterbox
Letterbox
Letterbox
Letterbox
Letterbox
Full Format
N/A
N/A
Center
Top
Center
Top
Center
Center
N/A
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
0
0
1
0
1
1
0
It is possible to blank the WSS portion of Line 23 with
Subaddress 61h, Bit 7.
Table XXVI. Function of WSS Bits
Bit
Function
0
Aspect Ratio
1
Format
2
Position
3
Odd Parity Check of Bits 0–2
4
0 = Camera Mode
1 = Film Mode
5
0 = Standard Coding
1 = Motion Adaptive Color Plus
6
0 = No Helper
1 = Modulated Helper
7
Reserved
8
Reserved
9–10
00 = No Open Subtitles
10 = Subtitles Inside Active Image Area
01 = Subtitles Outside Active Image Area
11 = Reserved
11
0 = No Surround Sound Information
1 = Surround Sound Mode
12–13
Reserved
500mV
RUN-IN
SEQUENCE
START
CODE
W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13
11.0␮s
38.4␮s
42.5␮s
Figure 82. WSS Waveform
REV. A
–53–
ACTIVE
VIDEO
ADV7300A/ADV7301A
Appendix C
SD CLOSED CAPTIONING
[Subaddresses 51h–54h]
ADV7301A. All pixels inputs are ignored during Lines 21 and 284 if
closed captioning is enabled.
The ADV7300A/ADV7301A supports closed captioning conforming to the standard television synchronizing waveform for
color transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of the even fields.
FCC Code of Federal Regulations (CFR) 47, Section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.
The ADV7300A/ADV7301A uses a single buffering method.
This means that the closed captioning buffer is only 1 byte
deep; therefore, there will be no frame delay in outputting the
closed captioning data unlike other 2-byte deep buffering
systems. The data must be loaded one line before (Line 20 or
Line 283) it is output on Line 21 and Line 284. A typical
implementation of this method is to use VSYNC to interrupt a
microprocessor that in turn will load the new data (2 bytes)
every field. If no new data is required for transmission, “0”
must be inserted in both data registers; this is called nulling. It
is also important to load “control codes,” all of which are
double bytes on Line 21, or a TV will not recognize them. If
there is a message like “Hello World” that has an odd number
of characters, it is important to pad it out to even to get the
“end of caption” 2-byte control code to land in the same field.
Closed captioning consists of a seven cycle sinusoidal burst that
is frequency and phase-locked to the caption data. After the
clock run-in signal, the blanking level is held for 2 data bits and
is followed by a Logic Level “1” start bit. Sixteen bits of data
follow the start bit. These consist of two 8-bit bytes, 7 data bits,
and 1 odd parity bit. The data for these bytes is stored in the
SD Closed Captioning Registers [Addresses 53h–54h].
The ADV7300A/ADV7301A also supports the extended closed
captioning operation that is active during even fields and is
encoded on Line 284. The data for this operation is stored in
the SD Closed Captioning Registers [Addresses 51h–52h].
All clock run-in signals and timing to support closed captioning on
Lines 21 and 284 are generated automatically by the ADV7300A/
10.5 0.25s
12.91s
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
50 IRE
P
A
R
I
T
Y
D0–D6
D0–D6
BYTE 0
P
A
R
I
T
Y
BYTE 1
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
10.003s
27.382s
33.764s
Figure 83. Closed Captioning Waveform, NTSC
–54–
REV. A
ADV7300A/ADV7301A
Appendix D
TEST PATTERNS
The ADV7300A/ADV7301A can generate SD and HD test
patterns.
Figure 84. NTSC Color Bars
Figure 87. PAL Color Bars
Figure 85. NTSC Black Bar (–21 mV, 0 mV, +3.5 mV,
+7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV)
Figure 88. PAL Black Bar (–21 mV, 0 mV, +3.5 mV,
+7 mV, +10.5 mV, +14 mV, +18 mV, +23 mV)
Figure 86. 525 p Hatch Pattern
REV. A
Figure 89. 625 p Hatch Pattern
–55–
ADV7300A/ADV7301A
Figure 90. 525 p Field Pattern
Figure 92. 625 p Field Pattern
Figure 93. 625 p Black Bar (–35 mV, 0 mV, +7 mV,
+14 mV, +21 mV, +28 mV, +35 mV)
Figure 91. 525 p Black Bar (–35 mV, 0 mV, +7 mV,
+14 mV, +21 mV, +28 mV, +35 mV)
–56–
REV. A
ADV7300A/ADV7301A
Table XXVIII. NTSC CVBS Output on DAC A
Table XXXII. 525 p Hatch Pattern on DAC D
Subaddress
Register Setting
Subaddress
Register Setting
00h
11h
40h
42h
44h
4Ah
4Ch
4Dh
4Eh
4Fh
82h
01h
10h
40h
40h
08h
16h
7Ch
F0h
21h
00h
01h
02h
10h
11h
16h
17h
18h
12h
10h
20h
40h
05h
A0h
80h
80h
All other registers are set to 00h.
For a 625 p Hatch Pattern on DAC D, the same settings in
Table XXXII are used except for Subaddress 10h, which has a
register setting of 50h.
All other registers are set to 00h.
For PAL CVBS output on DAC A, the same settings in
Table XXVIII are used except those listed in Table XXIX.
Table XXXIII. 525 p Field Pattern*
Table XXIX. PAL CVBS Output on DAC A
Subaddress
Register Setting
40h
4Ch
4Dh
4Eh
4Fh
11h
CBh
8Ah
09h
2Ah
Table XXX. NTSC Black Bar Pattern Output on DAC A
Subaddress
Register Setting
00h
02h
11h
40h
42h
44h
4Ah
4Ch
4Dh
4Eh
4Fh
82h
04h
01h
10h
40h
40h
08h
16h
7Ch
F0h
21h
Subaddress
Register Setting
00h
01h
02h
10h
11h
16h
17h
18h
12h
10h
20h
40h
0Dh
A0h
80h
80h
All other registers are set to 00h.
*See Figure 90.
For a 625 p Field Pattern on DAC D, the same settings in
Table XXXIII are used except for Subaddress 10h, which has a
register setting of 50h.
For a 525 p Black Bar Pattern Output on DAC D, the same
settings in Table XXXIII are used except for Subaddresses 02h,
which has a register setting of 24h.
For a 625 p Black Bar Pattern Output on DAC D, the same
settings in Table XXXIII are used except for Subaddresses 02h
and 10h, which have register settings of 24h and 50h, respectively.
All other registers are set to 00h. The Subcarrier Frequency Registers 4Ch–4Fh
will be needed to generate the correct color burst signal.
For PAL Black Bar Pattern Output on DAC A, the same settings in Table XXX are used except those listed in Table XXXI.
Table XXXI. PAL Black Bar Pattern Output on DAC A
Subaddress
Register Setting
40h
4Ch
4Dh
4Eh
4Fh
11h
CBh
8Ah
09h
2Ah
REV. A
–57–
ADV7300A/ADV7301A
Appendix E
timing information is transmitted using a 4-byte synchronization
pattern. A synchronization pattern is sent immediately before and
after each line during active picture and retrace. S_VSYNC,
S_HSYNC, and S_BLANK (if not used) pins should be tied high
during this mode. Blank output is available.
SD TIMING MODES
[Subaddress 4Ah]
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7300A/ADV7301A is controlled by the start active video
(SAV) and end active video (EAV) time codes in the pixel data. All
ANALOG
VIDEO
EAV CODE
SAV CODE
C
F 0 0 X 8 1 8 1
Y
Y
r
F 0 0 Y 0 0 0 0
INPUT PIXELS
C
C
8 1 8 1 F 0 0 X C Y C Y C
Y r Y b
b
0 0 0 0 F 0 0 Y b
r
0 F F A A A
0 F F B B B
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
268 CLOCK
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
1440 CLOCK
4 CLOCK
4 CLOCK
280 CLOCK
PAL SYSTEM
(625 LINES/50Hz)
1440 CLOCK
START OF ACTIVE
VIDEO LINE
END OF ACTIVE
VIDEO LINE
Figure 94. SD Slave Mode 0
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7300A/ADV7301A generates H, V, and F signals
required for the SAV and EAV time codes in the CCIR-656
standard. The H bit is output on the S_HSYNC pin, the V bit is
output on the S_BLANK pin, and the F bit is output on the
S_VSYNC pin.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
H
V
F
ODD FIELD
EVEN FIELD
Figure 95. SD Master Mode 0, NTSC
–58–
REV. A
ADV7300A/ADV7301A
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
H
V
EVEN FIELD
F
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
H
V
F
ODD FIELD
EVEN FIELD
Figure 96. SD Master Mode 0, PAL
ANALOG
VIDEO
H
F
V
Figure 97. SD Master Mode 0 Data Transitions
REV. A
–59–
334
335
336
ADV7300A/ADV7301A
retrace. The BLANK signal is optional. When the BLANK input
is disabled, the ADV7300A/ADV7301A automatically blanks all
normally blank lines as per CCIR-624. HSYNC is input on the
S_HSYNC pin, BLANK on the S_BLANK pin, and FIELD on
the S_VSYNC pin.
Mode 1: Slave Option
HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0)
In this mode, the ADV7300A/ADV7301A accepts horizontal
SYNC and odd/even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical
DISPLAY
DISPLAY
522
523
VERTICAL BLANK
524
525
1
2
3
4
6
5
7
8
9
10
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
260
261
VERTICAL BLANK
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 98. SD Slave Mode 1, NTSC
DISPLAY
DISPLAY
622
623
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 99. SD Slave Mode 1, PAL
–60–
REV. A
ADV7300A/ADV7301A
Mode 1: Master Option
HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7300A/ADV7301A can generate horizontal SYNC and odd/even FIELD signals. A transition of the
FIELD input when HSYNC is low indicates a new frame, i.e.,
vertical retrace. The blank signal is optional. When the BLANK
input is disabled, the ADV7300A/ADV7301A automatically
blanks all normally blank lines as per CCIR-624. Pixel data is
latched on the rising clock edge following the timing signal
transitions. HSYNC is output on the S_HSYNC pin, BLANK
on the S_BLANK pin, and FIELD on the S_VSYNC pin.
HSYNC
FIELD
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 100. SD Timing Mode 1 Odd/Even Field Transitions, Master/Slave
REV. A
–61–
Cr
Y
ADV7300A/ADV7301A
A VSYNC low transition when HSYNC is high indicates the
start of an even field. The BLANK signal is optional. When the
BLANK input is disabled, the ADV7300A/ADV7301A automatically blanks all normally blank lines as per CCIR-624.
HSYNC is input on the S_HSYNC pin, BLANK on the
S_BLANK pin, and FIELD on the S_VSYNC pin.
Mode 2: Slave Option
HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0)
In this mode, the ADV7300A/ADV7301A accepts horizontal
and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field.
DISPLAY
522
DISPLAY
VERTICAL BLANK
523
524
525
1
2
3
4
6
5
7
8
10
9
20
11
21
22
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
260
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
Figure 101. SD Slave Mode 2, NTSC
DISPLAY
622
623
DISPLAY
VERTICAL BLANK
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
309
310
VERTICAL BLANK
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 102. SD Slave Mode 2, PAL
–62–
REV. A
ADV7300A/ADV7301A
field. A VSYNC low transition when HSYNC is high indicates
the start of an even field. The BLANK signal is optional. When
the BLANK input is disabled, the ADV7300A/ADV7301A
automatically blanks all normally blank lines as per CCIR-624.
HSYNC is output on the S_HSYNC pin, BLANK on the
S_BLANK pin, and FIELD on the S_VSYNC pin.
Mode 2: Master Option
HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7300A/ADV7301A can generate horizontal and vertical SYNC signals. A coincident low transition of
both HSYNC and VSYNC inputs indicates the start of an odd
HSYNC
VSYNC
BLANK
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
PIXEL
DATA
Cb
Y
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 103. SD Timing Mode 2 Even to Odd Field Transition, Master/Slave
HSYNC
VSYNC
PAL = 12 CLOCK/2
NTSC = 16 CLOCK/2
PAL = 864 CLOCK/2
NTSC = 858 CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 CLOCK/2
NTSC = 122 CLOCK/2
Figure 104. SD Timing Mode 2 Odd to Even Field Transition, Master/Slave
REV. A
–63–
Cr
Y
ADV7300A/ADV7301A
i.e., vertical retrace. The BLANK signal is optional. When the
BLANK input is disabled, the ADV7300A/ADV7301A automatically blanks all normally blank lines as per CCIR-624. HSYNC
is interfaced on the S_HSYNC pin, BLANK on the S_BLANK
pin, and FIELD on the S_VSYNC pin.
Mode 3: Master/Slave Option
HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode, the ADV7300A/ADV7301A accepts or generates
horizontal SYNC and odd/even FIELD signals. A transition of
the FIELD input when HSYNC is high indicates a new frame,
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
5
7
8
9
10
20
11
21
22
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
260
DISPLAY
VERTICAL BLANK
261
262
263
264
265
266
267
268
269
270
271
272
273
283
274
284
285
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 105. SD Timing Mode 3, NTSC
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
5
6
7
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
317
318
319
320
334
335
336
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
Figure 106. SD Timing Mode 3, PAL
–64–
REV. A
ADV7300A/ADV7301A
Appendix F
VIDEO OUTPUT LEVELS
INPUT CODE
EIA-770.2, STANDARD FOR Y
OUTPUT VOLTAGE
INPUT CODE
EIA-770.3, STANDARD FOR Y
OUTPUT VOLTAGE
+700mV
940
+700mV
940
VIDEO ACTIVE
VIDEO ACTIVE
+300mV
64
0mV
0mV
64
–300mV
EIA-770.2, STANDARD FOR Pr/Pb
960
–300mV
EIA-770.3, STANDARD FOR Pr/Pb
OUTPUT VOLTAGE
+350mV
OUTPUT VOLTAGE
+350mV
960
+300mV
VIDEO ACTIVE
VIDEO ACTIVE
0mV
512
0mV
512
–300mV
–300mV
–350mV
64
Figure 107. EIA-770.2 Standard Output Signals (525 p)
INPUT CODE
EIA-770.1, STANDARD FOR Y
–350mV
64
Figure 109. EIA-770.3 Standard Output Signals
(1080 i, 720 p)
OUTPUT VOLTAGE
+782mV
INPUT CODE
Y–OUTPUT LEVELS FOR
FULL I/P SELECTION
OUTPUT VOLTAGE
+714mV
940
1023
VIDEO ACTIVE
VIDEO ACTIVE
64
+700mV
0mV
64
0mV
–286mV
EIA-770.1, STANDARD FOR Pr/Pb
–300mV
OUTPUT VOLTAGE
INPUT CODE
960
+350mV
1023
Pr/Pb–OUTPUT LEVELS FOR
FULL I/P SELECTION
OUTPUT VOLTAGE
+700mV
VIDEO ACTIVE
512
0mV
VIDEO ACTIVE
–300mV
64
64
–350mV
Figure 108. EIA-770.1 Standard Output Signals (525 p)
0mV
–300mV
Figure 110. Output Levels for Full Input Selection
REV. A
–65–
ADV7300A/ADV7301A
Appendix G
VIDEO STANDARDS
0HDATUM
SMPTE274M
ANALOG WAVEFORM
DIGITAL HORIZONTAL BLANKING
4T
272T
4T
1920T
EAV CODE
ANCILARY DATA
(OPTIONAL) OR BLANKING CODE
SAV CODE
DIGITAL
ACTIVE LINE
F
F
INPUT PIXELS
0
0
0 F
0 V
H*
F
F
4 CLOCK
SAMPLE NUMBER
2112
C
0 F C
0 V b Y r
H*
0
0
C
Y
r
4 CLOCK
2116 2156
0
2199
44
188
192
2111
FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1–562: F = 0
SAV/EAV: LINE 563–1125: F = 1
SAV/EAV: LINE1–20; 561–583; 1124–1125: V = 1
SAV/EAV: LINE 21–560; 584–1123: V = 0
Figure 111. EAV/SAV Input Data Timing Diagram, SMPTE274M
SMPTE293M
ANALOG WAVEFORM
ANCILLARY DATA
(OPTIONAL)
EAV CODE
F
F
INPUT PIXELS
0
0
F
0 V
0 H*
F
F
4 CLOCK
SAMPLE NUMBER
719
DIGITAL
ACTIVE LINE
SAV CODE
0
0
F
0
V
0
H*
C
C
b Y r
C
Y r
Y
4 CLOCK
723 736
0HDATUM
799
853
857
0
719
DIGITAL HORIZONTAL BLANKING
FVH* = FVH AND PARITY BITS
SAV: LINE 43–525 = 200H
SAV: LINE 1–42 = 2AC
EAV: LINE43–525 = 274H
EAV: LINE 1–42 = 2D8
Figure 112. EAV/SAV Input Data Timing Diagram, SMPTE293M
–66–
REV. A
ADV7300A/ADV7301A
ACTIVE
VIDEO
522
523
ACTIVE
VIDEO
VERTICAL BLANK
524
525
1
2
5
6
7
8
9
12
13
14
15
16
42
43
44
Figure 113. SMPTE293M
ACTIVE
VIDEO
622
623
624
ACTIVE
VIDEO
VERTICAL BLANK
625
1
2
4
5
6
7
8
9
10
11
12
13
43
44
45
Figure 114. ITU-R.BT1358 (625 p)
DISPLAY
VERTICAL BLANKING INTERVAL
747
748
749
750
1
2
3
4
5
6
7
8
26
25
27
744
745
Figure 115. SMPTE296M (720 p)
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 1
1124
1125
1
2
3
4
5
6
7
8
20
21
22
560
DISPLAY
VERTICAL BLANKING INTERVAL
FIELD 2
561
562
563
564
565
566
567
568
569
570
Figure 116. SMPTE274M (1080 i)
REV. A
–67–
583
584
585
1123
ADV7300A/ADV7301A
OUTLINE DIMENSIONS
64-Lead Thin Plastic Quad Flatpack [LQFP]
(ST-64B)
0.75
0.60
0.45
C02861–0–11/02(A)
Dimensions shown in millimeters
12.00 BSC
1.60
MAX
64
49
1
48
SEATING
PLANE
TOP VIEW
10.00 BSC
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
0.20
0.09
SEATING
PLANE
7ⴗ
3.5ⴗ
0ⴗ
0.08 MAX
COPLANARITY
VIEW A
16
33
32
17
0.50
BSC
VIEW A
ROTATED 90ⴗ CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026BCD
Revision History
Location
Page
11/02—Data Sheet changed from REV. 0 to REV. A.
Changes to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Added Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Changes to Table IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Changes to Table XII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Changes to Table XIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Changes to the Realtime Control, Subcarrier Reset, Timing Reset section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Changes to SD SUBCARRIER FREQUENCY REGISTERS [Subaddress 4Ch-4Fh] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Changes to Figure 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Changes to Figure 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Changes to Figure 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
–68–
REV. A
PRINTED IN U.S.A.
Changes to Figure 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50