Freescale MC68HC705JJ7CP Microcontroller Datasheet

MC68HC705JJ7
MC68HC705JP7
MC68HC705SJ7
MC68HC705SP7
MC68HRC705JJ7
MC68HRC705JP7
Advance Information Data Sheet
M68HC05
Microcontrollers
MC68HC705JJ7
Rev. 4.1
09/2005
freescale.com
This document contains certain information on a new product.Specifications and information herein are subject to change without notice.
MC68HC705JJ7
MC68HC705SJ7
MC68HRC705JJ7
MC68HRC705SJ7
MC68HC705JP7
MC68HC705SP7
Advance Information Data Sheet
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the most current. Your printed copy may be an earlier revision. To verify you have the latest information
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MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
3
Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
August,
2001
September,
2005
Revision
Level
4.0
4.1
Page
Number(s)
Description
General reformat to bring document up to current publication standards
All
References to MC68HRC705SJ7 and MC68HRC705SP7 removed
throughout
All
Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit — Change label of
register $1FF0 from mask option register to COP register
94
Table 7-2. Port B Pin Functions — PB0–PB4 — Change heading under
Comparator 1 from OPT in MOR to OPT in COPR
96
12.4 PEPROM Programming — Contact information updated
179
Figure 13-3. EPROM Security in COP and Security Register (COPR) —
Figure title change
188
13.4 EPROM Programming — Contact information updated and corrected
reference to COP register from COP to COPR
189
15.15 SIOP Timing (VDD = 5.0 Vdc) — Value change for clock (SCK) low
time
225
15.16 SIOP Timing (VDD = 3.0 Vdc) — Value change for clock (SCK) low
time
226
Section 15. Electrical Specifications — Added Figure 15-1 through Figure
15-10 and Figure 15-12
213, 214,
219, 223,
and 227
Updated to meet Freescale identity guidelines.
Throughout
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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List of Chapters
Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 3 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Chapter 5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 6 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 7 Parallel Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Chapter 8 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 9 Simple Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Chapter 10 Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Chapter 11 Programmable Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Chapter 12 Personality EPROM (PEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Chapter 13 EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Chapter 14 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Chapter 15 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Chapter 16 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Chapter 17 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
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List of Chapters
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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Freescale Semiconductor
Table of Contents
Chapter 1
General Description
1.1
1.2
1.3
1.4
1.5
1.6
1.6.1
1.6.2
1.6.3
1.6.4
1.6.5
1.7
1.8
1.9
1.10
1.11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VDD and VSS Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OSC1 and OSC2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PA0–PA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PB0–PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PC0–PC7 (MC68HC705JP7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
14
16
17
17
17
18
18
18
18
18
19
19
19
19
Chapter 2
Memory
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User and Interrupt Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Erasable Programmable Read-Only Memory (EPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
21
21
26
26
26
27
Chapter 3
Central Processor Unit (CPU)
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
29
30
30
30
31
31
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Table of Contents
Chapter 4
Interrupts
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
4.7.3
4.8
4.9
4.9.1
4.9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PA0–PA3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparator Input Match Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
33
34
36
36
36
37
38
39
39
39
40
40
40
40
40
41
41
41
Chapter 5
Resets
5.1
5.2
5.3
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
5.5.7
5.5.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Bit Programmable Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Oscillator and Internal Low-Power Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
44
44
44
44
45
45
46
46
46
46
46
47
47
47
47
47
Chapter 6
Operating Modes
6.1
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Oscillator Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Table of Contents
6.3
6.3.1
6.3.2
6.3.3
6.3.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
52
53
53
54
Chapter 7
Parallel Input/Output
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulldown Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulldown Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PB0, PBI, PB2, and PB3 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PB4/AN4/TCMP/CMP1 Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PB5/SDO Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PB6/SDI Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PB7/SCK Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C (28-Pin Versions Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C Pulldown Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port C Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
55
55
56
56
57
57
58
58
59
59
60
60
61
63
64
65
67
67
67
68
68
69
Chapter 8
Analog Subsystem
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2
Analog Multiplex Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.3
Analog Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4
Analog Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.5
A/D Conversion Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6
Voltage Measurement Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.1
Absolute Voltage Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.1.1
Internal Absolute Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.1.2
External Absolute Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.2
Ratiometric Voltage Readings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.2.1
Internal Ratiometric Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.6.2.2
External Ratiometric Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
73
76
79
81
89
90
90
90
91
91
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8.7
8.7.1
8.7.2
8.8
8.9
8.10
8.11
8.12
8.13
8.14
Voltage Comparator Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Comparator 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Comparator 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Source Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Temperature Sensing Diode Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Interaction with Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Pins as Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port B Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
92
93
93
93
93
94
94
94
94
Chapter 9
Simple Synchronous Serial Interface
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SIOP Signal Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Serial Data Input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Serial Data Output (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SIOP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SIOP Control Register (SCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SIOP Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SIOP Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Chapter 10
Core Timer
10.1
10.2
10.3
10.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Core Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
101
102
103
103
Chapter 11
Programmable Timer
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capture Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Operation during Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Operation during Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Operation during Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
105
107
108
109
110
112
113
114
114
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Chapter 12
Personality EPROM (PEPROM)
12.1
12.2
12.2.1
12.2.2
12.3
12.4
12.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEPROM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEPROM Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
115
116
116
116
117
118
118
Chapter 13
EPROM/OTPROM
13.1
13.2
13.2.1
13.2.2
13.2.3
13.3
13.3.1
13.3.2
13.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mask Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Security Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MOR Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPMSEC Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
119
119
119
120
122
122
123
123
123
Chapter 14
Instruction Set
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
14.2.7
14.2.8
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.4
14.5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
125
125
125
125
126
126
126
126
126
127
127
128
129
130
130
131
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Table of Contents
Chapter 15
Electrical Specifications
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
15.10
15.11
15.12
15.13
15.14
15.15
15.16
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics (5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics (3.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Subsystem Characteristics (5.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Subsystem Characteristics (3.0 Vdc). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Timing (5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Timing (3.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PEPROM and EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIOP Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIOP Timing (VDD = 3.0 Vdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
139
139
139
139
140
140
143
144
145
146
148
149
152
153
154
154
Chapter 16
Mechanical Specifications
16.1
16.2
16.3
16.4
16.5
16.6
16.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin Plastic Dual In-Line Package (Case 738) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin Small Outline Integrated Circuit (Case 751D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Plastic Dual In-Line Package (Case 710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Small Outline Integrated Circuit (Case 751F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin Windowed Ceramic Integrated Circuit (Case 732) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28-Pin Windowed Ceramic Integrated Circuit (Case 733A) . . . . . . . . . . . . . . . . . . . . . . . . . . .
157
157
158
158
159
159
160
Chapter 17
Ordering Information
17.1
17.2
17.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
MC68HC705JJ7 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
MC68HC705JP7 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
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Chapter 1
General Description
1.1 Introduction
The MC68HC705JJ7 and MC68HC705JP7 are erasable programmable read-only memory (EPROM)
versions of the MC68HC05JJ/JP Family of microcontrollers (MCU).
1.2 Features
Features of the two parts include:
• Low-cost, M68HC05 core MCU in 20-pin package (MC68HC705JJ7) or 28-pin package
(MC68HC705JP7)
• 6160 bytes of user EPROM, including 16 bytes of user vectors
• 224 bytes of low-power user random-access memory (RAM)
• 64 bits of personality EPROM (serial access)
• 16-bit programmable timer with input capture and output compare
• 15-stage core timer, including 8-bit free-running counter and 4-stage selectable real-time interrupt
generator
• Simple serial input/output port (SIOP) with interrupt capability
• Two voltage comparators, one of which can be combined with the 16-bit programmable timer to
create a 4-channel, single-slope analog-to-digital (A/D) converter
• Output of voltage comparator can drive port pin PB4 directly under software control
• 14 input/output (I/O) lines (MC68HC705JJ7) or 22 I/O lines (MC68HC705JP7), including
high-source/sink current capability on 6 I/O pins (MC68HC705JJ7) or 14 I/O pins
(MC68HC705JP7)
• Programmable 8-bit mask option register (MOR) to select mask options found in read-only memory
(ROM) based versions
• MOR selectable software programmable pulldowns on all I/O pins and keyboard scan interrupt on
four I/O pins
• Software mask and request bit for IRQ interrupt with MOR selectable sensitivity on IRQ interrupt
(edge- and level-sensitive or edge-only)
• On-chip oscillator with device option of crystal/ceramic resonator or resistor-capacitor (RC)
operation and MOR selectable shunt resistor, 2 MΩ by design
• Internal oscillator for lower-power operation, approximately 100 kHz (500 kHz selected as device
option)
• EPROM security bit(1) to aid in locking out access to programmable EPROM array
• MOR selectable computer operating properly (COP) watchdog system
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
13
General Description
•
•
•
•
•
Power-saving stop and wait mode instructions (MOR selectable STOP conversion to halt and
option for fast 16-cycle restart
and power-on reset)
On-chip temperature measurement diode
MOR selectable reset module to reset central processor unit (CPU) in low-voltage conditions
Illegal address reset
Internal steering diode and pullup device on RESET pin to VDD
1.3 Device Options
These device options are available:
• On-chip oscillator type: crystal/ceramic resonator connections or resistor-capacitor (RC)
connections
• Nominal frequency of internal low-power oscillator: 100 or 500 kHz
NOTE
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
Any reference to voltage, current, or frequency specified in the following
sections will refer to the nominal values. The exact values and their
tolerance or limits are specified in Chapter 15 Electrical Specifications.
Combinations of the various device options are specified by part number. Refer to Table 1-1 and to
Chapter 17 Ordering Information for specific ordering information.
Table 1-1. Device Options by Part Number
Part
Number
Pin
Count
Oscillator
Type
Internal LPO Nominal
Frequency (kHz)
MC68HC705JJ7
MC68HC705JP7
20
28
Crystal/resonator
Crystal/resonator
100
100
MC68HC705SJ7
MC68HC705SP7
20
28
Crystal/resonator
Crystal/resonator
500
500
MC68HRC705JJ7
MC68HRC705JP7
20
28
Resistor-capacitor
Resistor-capacitor
100
100
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
14
Freescale Semiconductor
Device Options
OSC1
+
COMP1
–
TRANSFER
CONTROL
EXTERNAL
OSCILLATOR
OSC2
INTERNAL
OSCILLATOR
VDD
+
COMP2
–
CURRENT
SOURCE
÷2
VDD
16-BIT TIMER
(1) INPUT CAPTURE
(1) OUTPUT COMPARE
INT
LVR
TCAP
TCMP
COMPARATOR
CONTROL &
MULTIPLEXER
ICF
15-STAGE
CORE TIMER
SYSTEM
OCF
TEMPERATURE
DIODE
TOF
VSS
WATCHDOG &
ILLEGAL ADDR
DETECT
PB0/AN0
VSS
RESET
CPU CONTROL
ALU
INT
68HC05 CPU
IRQ/VPP
ACCUM
CPU REGISTERS
PB1/AN1
PB2/AN2
PORT B
PORT B DATA DIR. REG.
VSS
PB3/AN3/TCAP
PB4/AN4/TCMP/CMP1*
PB5/SDO
PB6/SDI
INDEX REG
PB7/SCK
0 0 0 0 0 0 0 0 1 1 STK PTR
INT
SIMPLE SERIAL
INTERFACE
(SIOP)
1 1 1H I NZC
BOOT ROM — 240 BYTES
STATIC RAM (4T) — 224 BYTES
PORT A DATA DIR. REG.
COND CODE REG
PA5*
PA4*
PORT A
PROGRAM COUNTER
PA0*†
PC7*
PC6*
PC5*
PORT C
PORT C DATA DIR. REG.
* High sink current capability
* High source current capability
† IRQ interrupt capability
PA2*†
PA1*†
USER EPROM — 6160 BYTES
PERSONALITY EPROM — 64 BITS
PA3*†
PC4*
PC3*
PC2*
PORT C
ONLY ON
28-PIN
VERSIONS
PC1*
PC0*
Figure 1-1. User Mode Block Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
15
General Description
1.4 Functional Pin Description
Refer to Figure 1-2 for the pinouts of the MC68HC705JJ7 and MC68HC705JP7 in the user mode.
The following paragraphs give a description of the general function of each pin.
MC68HC705JJ7
PB1/AN1
1
20
PB0/AN0
PB2/AN2
2
19
VDD
PB3/AN3/TCAP
3
18
VSS
*PB4/AN4/TCMP/CMP1
4
17
OSC1
PB5/SDO
5
16
OSC2
PB6/SDI
6
15
RESET
PB7/SCK
7
14
IRQ/VPP
*PA5
8
13
PA0*†
* PA4
9
12
PA1*†
†* PA3
10
11
PA2*†
MC68HC705JP7
PB1/AN1
1
28
PB0/AN0
PB2/AN2
2
27
VDD
PB3/AN3/TCAP
3
26
VSS
*PB4/AN4/TCMP/CMP1
4
25
OSC1
PB5/SDO
5
24
OSC2
* PC4
6
23
PC3*
*PC5
7
22
PC2*
* PC6
8
21
PC1*
*PC7
9
20
PC0*
PB6/SDI
10
19
RESET
PB7/SCK
11
18
IRQ/VPP
*PA5
12
17
PA0*†
* PA4
13
16
PA1*†
†* PA3
14
15
PA2*†
* Denotes 10 mA sink /5 mA source capability
† Denotes IRQ interrupt capability
Figure 1-2. User Mode Pinouts
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
16
Freescale Semiconductor
VDD and VSS Pins
1.5 VDD and VSS Pins
Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground. The
MCU operates from a single power supply.
Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high
short-duration current demands on the power supply. To prevent noise problems, special care should be
taken to provide good power supply bypassing at the MCU by using bypass capacitors with good
high-frequency characteristics that are positioned as close to the MCU as possible.
1.6 OSC1 and OSC2 Pins
The OSC1 and OSC2 pins are the connections for the external pin oscillator (EPO). The OSC1 and OSC2
pins can accept these sets of components:
• A crystal as shown in Figure 1-3 (a)
• A ceramic resonator as shown in Figure 1-3 (a)
• An external resistor as shown in Figure 1-3 (b)
• An external clock signal as shown in Figure 1-3 (c)
The selection of the crystal/ceramic resonator or RC oscillator configuration is done by product part
number selection as described in Chapter 17 Ordering Information.
The frequency, fOSC, of the EPO or external clock source is divided by two to produce the internal
operating frequency, fOP.
MCU
MCU
MCU
2 MΩ
OSC1
OSC1
OSC2
OSC2
OSC1
OSC2
R
UNCONNECTED
EXTERNAL CLOCK
(a) Crystal or
Ceramic Resonator
Connections
(b) RC Oscillator
Connections
(c) External Clock
Source Connection
Figure 1-3. EPO Oscillator Connections
1.6.1 Crystal Oscillator
The circuit in Figure 1-3 (a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. The
crystal manufacturer’s recommendations should be followed, as the crystal parameters determine the
external component values required to provide maximum stability and reliable startup. The load
capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal
and components should be mounted as close as possible to the pins for startup stabilization and to
minimize output distortion. An internal startup resistor of approximately 2 MΩ can be provided between
OSC1 and OSC2 for the crystal type oscillator by use of the OSCRES bit in the MOR.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
17
General Description
1.6.2 Ceramic Resonator Oscillator
In cost-sensitive applications, a ceramic resonator can be used in place of the crystal. The circuit in
Figure 1-3 (a) can be used for a ceramic resonator. The resonator manufacturer’s recommendations
should be followed, as the resonator parameters determine the external component values required for
maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design
should include all stray capacitances. The ceramic resonator and components should be mounted as
close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup
resistor of approximately 2 MΩ can be provided between OSC1 and OSC2 for the ceramic resonator type
oscillator by use of the OSCRES bit in the MOR.
1.6.3 RC Oscillator
The lowest cost oscillator is the RC oscillator configuration where a resistor is connected between the two
oscillator pins as shown in Figure 1-3 (b).
The selection of the RC oscillator configuration is done by product part number selection as described in
Chapter 17 Ordering Information.
NOTE
Do not use the internal startup resistor between OSC1 and OSC2 for the
RC-type oscillator.
1.6.4 External Clock
An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the
OSC2 input not connected, as shown in Figure 1-3 (c). This oscillator can be selected via software. This
configuration is possible regardless of whether the crystal/ceramic resonator or RC oscillator
configuration is used.
NOTE
Do not use the internal startup resistor between OSC1 and OSC2 for the
external clock.
1.6.5 Internal Low-Power Oscillator
An internal low-power oscillator (LPO) is provided which is the default oscillator out of reset. When
operating from this internal LPO, the other oscillator can be powered down by software to further conserve
power.
The selection of the LPO configuration is done by product part number selection as described in
Chapter 17 Ordering Information.
1.7 RESET Pin
The RESET pin can be used as an input to reset the MCU to a known startup state by pulling it to the low
state. It also functions as an output to indicate that an internal COP watchdog, illegal address, or
low-voltage reset has occurred. The RESET pin contains a pullup device to allow the pin to be left
disconnected without an external pullup resistor. The RESET pin also contains a steering diode that,
when the power is removed, will discharge to VDD any charge left on an external capacitor connected
between the RESET pin and VSS. The RESET pin also contains an internal Schmitt trigger to improve its
noise immunity as an input.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
18
Freescale Semiconductor
IRQ/VPP Pin
1.8 IRQ/VPP Pin
The IRQ/VPP input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt
function uses the LEVEL bit in the MOR to provide either negative edge-sensitive triggering or both
negative edge-sensitive and low level-sensitive triggering. If the LEVEL bit is set to enable level-sensitive
triggering, the IRQ/VPP pin requires an external resistor to VDD for “wired-OR” operation. If the IRQ/VPP
pin is not used, it must be tied to the VDD supply. The IRQ/VPP pin contains an internal Schmitt trigger as
part of its input to improve noise immunity.
The voltage on this pin may affect operation if the voltage on the IRQ/VPP pin is above VDD when the
device is released from a reset condition. The IRQ/VPP pin should only be taken above VDD to program
an EPROM memory location or personality EPROM bit. For more information, refer to 15.13 PEPROM
and EPROM Programming Characteristics.
NOTE
Each of the PA0–PA3 I/O pins may be connected as an OR function with
the IRQ interrupt function by the PIRQ bit in the MOR. This capability allows
keyboard scan applications where the transitions or levels on the I/O pins
will behave the same as the IRQ/VPP pin, except that active transitions and
levels are inverted. The edge or level sensitivity selected by the LEVEL bit
in the MOR for the IRQ/VPP pin also applies to the I/O pins that are ORed
to create the IRQ signal. For more information, refer to 4.5 External
Interrupts.
1.9 PA0–PA5
These six I/O lines comprise port A, a general-purpose bidirectional I/O port. This port also has four pins
which have keyboard interrupt capability. All six of these pins have high current source and sink capability.
All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the
MOR.
1.10 PB0–PB7
These eight I/O lines comprise port B, a general-purpose bidirectional I/O port. This port is also shared
with the 16-bit programmable timer input capture and output compare functions, with the two voltage
comparators in the analog subsystem, and with the simple serial interface (SIOP).
The outputs of voltage comparator 1 can directly drive the PB4 pin; and the PB4 pin has high current
source and sink capability.
All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the
MOR.
1.11 PC0–PC7 (MC68HC705JP7)
These eight I/O lines comprise port C, a general-purpose bidirectional I/O port. This port is only available
on the 28-pin MC68HC705JP7. All eight of these pins have high current source and sink capability.
All of these pins have software programmable pulldowns which can be disabled by the SWPDI bit in the
MOR.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
19
General Description
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
20
Freescale Semiconductor
Chapter 2
Memory
2.1 Introduction
This section describes the organization of the memory on the MC68HC705JJ7/MC68HC705JP7.
2.2 Memory Map
The central processor unit (CPU) can address 8 kilobytes of memory space as shown in Figure 2-1. The
memory map includes:
• The erasable programmable read-only memory (EPROM) portion of memory holds the program
instructions, fixed data, user-defined vectors, and interrupt service routines.
• The random-access memory (RAM) portion of memory holds variable data.
• Input/output (I/O) registers are memory mapped so that the CPU can access their locations in the
same way that it accesses all other memory locations.
$1EFF
Figure 2-1. Memory Map
2.3 Input/Output Registers
Figure 2-2 and Figure 2-3 summarize:
• The first 32 addresses of the memory space, $0000–$001F, containing the I/O registers section
• One I/O register located outside the 32-byte I/O section, which is the computer operating properly
register (COPR) mapped at $1FF0
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
21
Memory
Address
Register Name
$0000
Port A Data Register
$0001
Port B Data Register
$0002
Port C Data Register *
$0003
Analog MUX Register
$0004
Port A Data Direction Register
$0005
Port B Data Direction Register
$0006
Port C Data Direction Register *
$0007
Unused
$0008
Core Timer Status & Control Register
$0009
Core Timer Counter
$000A
Serial Control Register
$000B
Serial Status Register
$000C
Serial Data Register
$000D
IRQ Status & Control Register
$000E
Personality EPROM Bit Select Register
$000F
Personality EPROM Status & Control Register
$0010
Port A and Port C Pulldown Register *
$0011
Port B Pulldown Register
$0012
Timer Control Register
$0013
Timer Status Register
$0014
Input Capture Register (MSB)
$0015
Input Capture Register (LSB)
$0016
Output Compare Register (MSB)
$0017
Output Compare Register (LSB)
$0018
Timer Counter Register (MSB)
$0019
Timer Counter Register (LSB)
$001A
Alternate Counter Register (MSB)
$001B
Alternate Counter Register (LSB)
$001C
EPROM Programming Register
$001D
Analog Control Register
$001E
Analog Status Register
$001F
Reserved
* Features related to port C are only available on the 28-pin
MC68HC705JP7 devices.
Figure 2-2. I/O Registers
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
22
Freescale Semiconductor
Input/Output Registers
Addr.
$0000
$0001
$0002
$0003
$0004
$0005
$0006
Register
Port A Data Register Read:
(PORTA) Write:
See page 55. Reset:
Port B Data Register Read:
(PORTB) Write:
See page 58. Reset:
Port C(1) Data Register Read:
(PORTC) Write:
See page 67. Reset:
Read:
0
4
3
2
1
Bit 0
PA5
PA4
PA3
PA2
PA1
PA0
PB2
PB1
PB0
PC2
PC1
PC0
Unaffected by reset
PB7
PB6
PB5
PB4
PB3
Unaffected by reset
PC7
PC6
PC5
PC4
PC3
Unaffected by reset
DHOLD
INV
VREF
MUX4
MUX3
MUX2
MUX1
1
0
0
0
0
0
0
0
Data Direction Register A Read:
(DDRA) Write:
See page 56. Reset:
0
0
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
CTOF
RTIF
CTOFE
RTIE
0
0
CTOFR
RTIFR
RT1
RT0
Data Direction Register B Read:
(DDRB) Write:
See page 59. Reset:
Data Direction Register C Read:
(DDRC) Write:
See page 67. Reset:
$0008
Core Timer Status and Control
Register (CTSCR)
See page 102.
Read:
Write:
Reset:
$000B
0
5
HOLD
Unimplemented
$000A
6
Analog Multiplex Register
(AMUX) Write:
See page 73. Reset:
$0007
$0009
Bit 7
Core Timer Counter Register Read:
(CTCR) Write:
See page 103. Reset:
SIOP Control Register Read:
(SCR) Write:
See page 97. Reset:
Read:
SIOP Status Register
(SSR) Write:
See page 99. Reset:
0
0
0
0
0
0
1
1
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
SPIE
SPE
LSBF
MSTR
CPHA
SPR1
SPR0
0
SPIR
0
0
0
0
0
0
0
0
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
Figure 2-3. Register Summary (Sheet 1 of 3)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
23
Memory
Addr.
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
Register
Read:
SIOP Data Register
(SDR) Write:
See page 100. Reset:
IRQ Status and Control Register Read:
(ISCR) Write:
See page 38. Reset:
PEPROM Bit Select Register Read:
(PEBSR) Write:
See page 116. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
IRQE
OM2
OM1
0
IRQF
0
0
0
1
1
0
0
0
0
U
0
PEB7
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
0
0
0
0
0
0
0
0
0
0
0
0
PEPRZF
R
R
R
PEPROM Status and Control Read: PEDATA
Register (PESCR) Write:
See page 116. Reset:
U
0
PEPGM
R
IRQR
0
0
0
0
0
0
1
Read:
Pulldown Register Port A
and Port C(1) (PDRA) Write:
See page 56. Reset:
PDICH
PDICL
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
0
0
0
0
0
0
0
0
Pulldown Register B Read:
(PDRB) Write:
See page 59. Reset:
PDIB7
PDIB6
PDIB5
PDIB4
PDIB3
PDIB2
PDIB1
PDIB0
0
0
0
0
0
0
0
0
ICIE
OCIE
TOIE
0
0
0
IEDG
OLVL
0
0
0
0
0
0
U
0
ICF
OCF
TOF
0
0
0
0
0
Timer Control Register Read:
(TCR) Write:
See page 112. Reset:
Timer Status Register Read:
(TSR) Write:
See page 113. Reset:
U
U
U
0
0
0
0
0
Input Capture Register High
(ICRH) Write:
See page 110. Reset:
Bit 15
14
13
12
11
10
9
Bit 8
Input Capture Register Low Read:
(ICRL) Write:
See page 110. Reset:
Bit 7
2
1
Bit 0
10
9
Bit 8
2
1
Bit 0
Read:
Output Compare Register High Read:
(OCRH) Write:
See page 111. Reset:
Output Compare Register Low Read:
(OCRL) Write:
See page 111. Reset:
Unaffected by reset
6
5
4
3
Unaffected by reset
Bit 15
14
13
12
11
Unaffected by reset
Bit 7
6
5
4
3
Unaffected by reset
= Unimplemented
R
= Reserved
U = Unaffected
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
Figure 2-3. Register Summary (Sheet 2 of 3)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
24
Freescale Semiconductor
Input/Output Registers
Addr.
$0018
$0019
$001A
$001B
$001C
$001D
$001E
Register
Bit 7
6
5
4
3
2
1
Bit 0
Programmable Timer Register High
(TMRH) Write:
See page 107. Reset:
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Programmable Timer Register Low Read:
(TMRL) Write:
See page 107. Reset:
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
1
1
1
0
0
Alternate Counter Register High Read:
(ACRH) Write:
See page 108. Reset:
Bit 15
14
13
12
11
10
9
Bit 8
1
1
1
1
1
1
1
1
Alternate Counter Register Low Read:
(ACRL) Write:
See page 108. Reset:
Bit 15
14
13
12
11
10
9
Bit 8
1
0
0
ELAT
MPGM
EPGM
Read:
1
1
1
1
1
0
0
0
0
0
R
R
R
R
0
0
0
0
0
0
0
0
CHG
ATD2
ATD1
ICEN
CPIE
CP2EN
CP1EN
ISEN
0
0
0
0
0
0
0
0
CPF2
CPF1
0
0
CMP1
CPFR1
VOFF
CMP2
CPFR2
COE1
0
0
0
0
0
0
0
0
Reserved
R
R
R
R
R
R
R
R
Reserved
R
R
R
R
R
R
R
R
Read:
EPROM Programming Register
(EPROG) Write:
See page 119. Reset:
Analog Counter Register Read:
(ACR) Write:
See page 77. Reset:
Analog Status Register Read:
(ASR) Write:
See page 77. Reset:
$001F
R
↓
$1FEF
$1FF0
COP and Security Register Read:
(COPR) Write: EPMSEC
See pages 27, 92, 104, and 122. Reset:
OPT
COPC
Unaffected by reset
= Unimplemented
R
= Reserved
U = Unaffected
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
Figure 2-3. Register Summary (Sheet 3 of 3)
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Memory
2.4 User and Interrupt Vector Mapping
The interrupt vectors are contained in the upper memory addresses above $1FF0 as shown in Figure 2-4.
Address
Register Name
$1FF0
COP Register and EPROM Security
$1FF1
Mask Option Register
$1FF2
Analog Interrupt Vector (MSB)
$1FF3
Analog Interrupt Vector (LSB)
$1FF4
Serial Interrupt Vector (MSB)
$1FF5
Serial Interrupt Vector ((LSB)
$1FF6
Timer Interrupt Vector (MSB)
$1FF7
Timer Interrupt Vector (LSB)
$1FF8
Core Timer Interrupt Vector (MSB)
$1FF9
Core Timer Interrupt Vector (LSB)
$1FFA
External IRQ Vector (MSB)
$1FFB
External IRQ Vector (LSB)
$1FFC
SWI Vector (MSB)
$1FFD
SWI Vector (LSB)
$1FFE
Reset Vector (MSB)
$1FFF
Reset Vector (LSB)
Figure 2-4. Vector Mapping
2.5 Random-Access Memory (RAM)
The 224 addresses from $0020 to $00FF serve as both the user RAM and the stack RAM. The central
processor unit (CPU) uses five RAM bytes to save all CPU register contents before processing an
interrupt. During a subroutine call, the CPU uses two bytes to store the return address. The stack pointer
decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines or multiple interrupt levels. The
CPU may overwrite data in the RAM during a subroutine or during the
interrupt stacking operation.
2.6 Erasable Programmable Read-Only Memory (EPROM)
The EPROM is located in three areas of the memory map:
• Addresses $0700–$1EFF contain 6144 bytes of user EPROM.
• Addresses $1FF0–$1FF1 contain 2 bytes of EPROM reserved for user vectors and COP and
security register (COPR), and the mask option register. Only bit 7 of $1FF0 is a programmable bit.
• Addresses $1FF2–$1FFF contain 14 bytes of interrupt vectors.
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Freescale Semiconductor
COP Register
2.7 COP Register
As shown in Figure 2-5, a register location is provided at $1FF0 to set the EPROM security(1), select the
optional features, and reset the COP watchdog timer. The OPT bit controls the function of the PB4 port
pin and the availability to add an offset to any measured analog voltages. See 8.4 Analog Status Register
for more information
Address: $1FF0
$1FF0
Bit 7
6
Read:
Write:
EPMSEC
5
4
3
2
OPT
Reset:
1
Bit 0
COPC
Unaffected by reset
= Unimplemented
Figure 2-5. COP and Security Register (COPR)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
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Memory
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Chapter 3
Central Processor Unit (CPU)
3.1 Introduction
This section describes the central processor unit (CPU) registers. Figure 3-1 shows the five CPU
registers. CPU registers are not part of the memory map.
7
0
A
ACCUMULATOR (A)
7
0
X
6
15
0
0
0
1
1
0
0
0
10
15
1
0
0
1
8
7
INDEX REGISTER (X)
0
5
1
SP
STACK POINTER (SP)
0
PCH
PCL
7
1
1
5
4
1
H
PROGRAM COUNTER (PC)
0
I
N
Z
C
CONDITION CODE REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 3-1. M68HC05 Programming Model
3.2 Accumulator
The accumulator is a general-purpose 8-bit register as shown in Figure 3-2. The CPU uses the
accumulator to hold operands and results of arithmetic and non-arithmetic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
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Central Processor Unit (CPU)
3.3 Index Register
The index register is a general-purpose 8-bit register as shown in Figure 3-3. In the indexed addressing
modes, the CPU uses the byte in the index register to determine the conditional address of the operand.
The 8-bit index register can also serve as a temporary data storage location.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-3. Index Register (X)
3.4 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next location on the stack as shown
in Figure 3-4. During a reset or after the reset stack pointer (RSP) instruction, the stack pointer initializes
to $00FF. The address in the stack pointer decrements as data is pushed onto the stack and increments
as data is pulled from the stack.
Read:
Write:
Reset:
Bit
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
5
4
3
2
1
Bit
0
1
1
1
1
1
1
Figure 3-4. Stack Pointer (SP)
The 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer
produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A
subroutine uses two stack locations; an interrupt uses five locations.
3.5 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched as shown in Figure 3-5. The three most significant bits of the program counter are ignored
internally and appear as 111 during stacking and subroutine calls.
Normally, the address in the program counter automatically increments to the next sequential memory
location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential location.
Read:
Write:
Reset:
Bit
15
14
13
1
1
1
0
0
0
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Loaded with vector from $1FFE and $1FFF
Figure 3-5. Program Counter (PC)
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Freescale Semiconductor
Condition Code Register
3.6 Condition Code Register
The condition code register is an 8-bit register whose three most significant bits are permanently fixed at
111 as shown in Figure 3-6. The condition code register contains the interrupt mask and four flags that
indicate the results of the instruction just executed. The following paragraphs describe the functions of the
condition code register.
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
1
1
1
H
I
N
C
Z
1
1
1
U
1
U
U
U
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
Half-Carry Flag (H)
The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during
an ADD or ADC operation. The half-carry flag is required for binary coded decimal (BCD) arithmetic
operations. Reset has no effect on the half-carry flag.
Interrupt Mask (I)
Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is
a logic 0, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask is set, the interrupt request is
latched. The CPU processes the latched interrupt as soon as the interrupt mask is cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt
mask to its cleared state. After a reset, the interrupt mask is set and can be cleared only by a CLI
instruction.
Negative Flag (N)
The CPU sets the negative flag when an arithmetic operation, logical operation, or data manipulation
produces a negative result. Reset has no affect on the negative flag.
Zero Flag (Z)
The CPU sets the zero flag when an arithmetic operation, logical operation, or data manipulation
produces a result of $00. Reset has no affect on the zero flag.
Carry/Borrow Flag (C)
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the
accumulator or when a subtraction operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag. Reset has no effect on the
carry/borrow flag.
3.7 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logical operations defined by the instruction set. The binary
arithmetic circuits decode instructions and set up the ALU for the selected operation. Most binary
arithmetic is based on the addition algorithm, carrying out subtraction as negative addition. Multiplication
is not performed as a discrete operation but as a chain of addition and shift operations within the ALU.
The multiply instruction (MUL) requires 11 internal clock cycles to complete this chain of operations.
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Central Processor Unit (CPU)
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Chapter 4
Interrupts
4.1 Introduction
An interrupt temporarily stops normal program execution to process a particular event. An interrupt does
not stop the execution of the instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the central processor unit (CPU)
registers on the stack and loads the program counter with a user-defined vector address.
4.2 Interrupt Vectors
Table 4-1 summarizes the reset and interrupt sources and vector assignments.
NOTE
If more than one interrupt request is pending, the CPU fetches the vector of
the higher priority interrupt first. A higher priority interrupt does not actually
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit.
Table 4-1. Reset/Interrupt Vector Addresses
Function
Reset
Source
Power-on logic
RESET pin
Low-voltage reset
Illegal address reset
COP watchdog
Software
interrupt (SWI)
MOR
Control
Bit
—
Global
Hardware
Mask
Local
Software
Mask
Priority
(1 = Highest)
Vector
Address
—
—
1
$1FFE–$1FFF
—
—
Same priority
as instruction
$1FFC–$1FFD
I bit
IRQE bit
2
$1FFA–$1FFB
3
$1FF8–$1FF9
COPEN(1)
User code
—
IRQ/VPP pin
—
PA3 pin
External
PA2 pin
interrupt (IRQ)
PIRQ(2)
PA1 pin
PA0 pin
Core timer
TOF bit
—
interrupts
RTIF bit
ICF bit
Programmable
OCF bit
—
timer interrupts
TOF bit
Serial interrupt
SPIF bit
—
CPF1 bit
Analog interrupt
—
CPF2 bit
1. COPEN enables the COP watchdog timer.
2. PIRQ enables port A external interrupts on PA0–PA3.
4
$1FF6–$1FF7
I bit
TOFE bit
RTIE bit
ICIE bit
OCIE bit
TOIE bit
SPIE bit
5
$1FF4–$1FF5
I bit
CPIE bit
6
$1FF2–$1FF3
I bit
I bit
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Interrupts
4.3 Interrupt Processing
To begin servicing an interrupt, the CPU does these actions:
• Stores the CPU registers on the stack in the order shown in Figure 4-1
• Sets the I bit in the condition code register to prevent further interrupts
• Loads the program counter with the contents of the appropriate interrupt vector locations as shown
in Table 4-1
The return-from-interrupt (RTI) instruction causes the CPU to recover its register contents from the stack
as shown in Figure 4-1. The sequence of events caused by an interrupt is shown in the flowchart in
Figure 4-2.
$0020
Bottom of RAM
$0021
$00BE
$00BF
$00C0
Bottom of Stack
$00C1
$00C2
Unstacking
Order
?
n
Condition Code Register
5
1
n+1
Accumulator
4
2
n+2
Index Register
3
3
n+3
Program Counter (High Byte)
2
4
n+4
Program Counter (Low Byte)
1
5
›
Stacking
Order
$00FD
$00FE
$00FF
Top of Stack (RAM)
Figure 4-1. Interrupt Stacking Order
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Interrupt Processing
FROM
RESET
YES
I BIT SET?
NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQ LATCH
NO
CORE TIMER
INTERRUPT?
YES
NO
TIMER
INTERRUPT?
YES
NO
SERIAL
INTERRUPT?
YES
NO
ANALOG
INTERRUPT?
YES
STACK PCL, PCH, X, A, CCR
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
NO
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CCR, A, X, PCH, PCL
NO
EXECUTE INSTRUCTION
Figure 4-2. Interrupt Flowchart
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Interrupts
4.4 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable interrupt.
4.5 External Interrupts
These sources can generate external interrupts:
• IRQ/VPP pin
• PA3–PA0 pins
Setting the I bit in the condition code register or clearing the IRQE bit in the interrupt status and control
register disables these external interrupts.
4.5.1 IRQ/VPP Pin
An interrupt signal on the IRQ/VPP pin latches an external interrupt request. To help clean up slow edges,
the input from the IRQ/VPP pin is processed by a Schmitt trigger gate. When the CPU completes its
current instruction, it tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition
code register and the IRQE bit in the IRQ status and control register (ISCR). If the I bit is clear and the
IRQE bit is set, then the CPU begins the interrupt sequence. The CPU clears the IRQ latch while it fetches
the interrupt vector, so that another external interrupt request can be latched during the interrupt service
routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new
interrupt request. Figure 4-3 shows the logic for external interrupts.
NOTE
If the IRQ/VPP pin is not in use, it should be connected to the VDD pin.
The IRQ/VPP pin can be negative edge-triggered only or negative edge- and low level-triggered. External
interrupt sensitivity is programmed with the LEVEL bit in the mask option register (MOR).
With the edge- and level-sensitive trigger MOR option, a falling edge or a low level on the IRQ/VPP pin
latches an external interrupt request. The edge- and level-sensitive trigger MOR option allows connection
to the IRQ/VPP pin of multiple wired-OR interrupt sources. As long as any source is holding the IRQ low,
an external interrupt request is present, and the CPU continues to execute the interrupt service routine.
With the edge-sensitive-only trigger option, a falling edge on the IRQ/VPP pin latches an external interrupt
request. A subsequent interrupt request can be latched only after the voltage level on the IRQ/VPP pin
returns to a logic 1 and then falls again to logic 0.
NOTE
The response of the IRQ/VPP pin can be affected if the external interrupt
capability of the PA0 through PA3 pins is enabled. If the port A pins are
enabled as external interrupts, then any high level on a PA0–PA3 pin will
cause the IRQ changes and state to be ignored until all of the PA0–PA3
pins have returned to a low level.
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External Interrupts
VPP TO
USER EPROM
AND PEPROM
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ/VPP
PA3
VDD
PA2
IRQ
LATCH
EXTERNAL
INTERRUPT
REQUEST
R
PA1
PA0
IRQR
IRQF
IRQE
LEVEL
PIRQ
RST
IRQ VECTOR FETCH
IRQ STATUS/CONTROL REGISTER ($000D)
MASK OPTION REGISTER ($1FF1)
INTERNAL DATA BUS
Figure 4-3. External Interrupt Logic
4.5.2 PA0–PA3 Pins
Programming the PIRQ bit in the MOR to a logic 1 enables the PA0–PA3 pins (PA0:3) to serve as
additional external interrupt sources. A rising edge on a PA0:3 pin latches an external interrupt request.
After completing the current instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU then
tests the I bit in the condition code register and the IRQE bit in the ISCR. If the I bit is clear and the IRQE
bit is set, the CPU then begins the interrupt sequence. The CPU clears the IRQ latch while it fetches the
interrupt vector, so that another external interrupt request can be latched during the interrupt service
routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new
interrupt request.
The PA0:3 pins can be edge-triggered or edge- and level-triggered. External interrupt triggering sensitivity
is selected by the LEVEL bit in the MOR.
With the edge- and level-sensitive trigger MOR option, a rising edge or a high level on a PA0:3 pin latches
an external interrupt request. The edge- and level-sensitive trigger MOR option allows connection to a
PA0:3 pin of multiple wired-OR interrupt sources. As long as any source is holding the pin high, an
external interrupt request is present, and the CPU continues to execute the interrupt service routine.
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Interrupts
With the edge-sensitive only trigger MOR option, a rising edge on a PA0:3 pin latches an external interrupt
request. A subsequent external interrupt request can be latched only after the voltage level of the previous
interrupt signal returns to a logic 0 and then rises again to a logic 1.
NOTE
If the port A pins are enabled as external interrupts, then a high level on any
PA0:3 pin will drive the state of the IRQ function such that the IRQ/VPP pin
and other PA0:3 pins are to be ignored until ALL of the PA0:3 pins have
returned to a low level. Similarly, if the IRQ/VPP pin is at a low level, the
PA0:3 pins will be ignored until the IRQ/VPP pin returns to a high state.
4.5.3 IRQ Status and Control Register (ISCR)
The IRQ status and control register (ISCR), shown in Figure 4-4, contains an external interrupt mask
(IRQE), an external interrupt flag (IRQF), and a flag reset bit (IRQR). Unused bits will read as logic 0s.
The ISCR also contains two control bits for the oscillators, external pin oscillator, and internal low-power
oscillator. Reset sets the IRQE and OM2 bits and clears all the other bits.
Address:
Read:
Write:
Reset:
$000D
Bit 7
6
5
IRQE
OM2
OM1
1
1
0
= Unimplemented
4
3
2
0
IRQF
0
R
Bit 0
0
0
IRQR
R
0
1
0
0
= Reserved
U
0
U = Unaffected
Figure 4-4. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
OM1 and OM2 — Oscillator Select Bits
These bits control the selection and enabling of the oscillator source for the MCU. One choice is the
internal low-power oscillator (LPO). The other choice is the external pin oscillator (EPO) which is
common to most M68HC05 MCU devices. The EPO uses external components like filter capacitors
and a crystal or ceramic resonator and consumes more power. The selection and enable conditions
for these two oscillators are shown in Table 4-2.
Table 4-2. Oscillator Selection
Internal
Low-Power
Oscillator
(LPO)
External Pin
Oscillator
(EPO)
Power
Consumption
Disabled
Lowest
OM2
OM1
Oscillator
Selected
by CPU
0
0
Internal
Enabled
0
1
External
Disabled
Enabled
Normal
1
0
Internal
Enabled
Disabled
Lowest
1
1
Internal
Enabled
Enabled
Normal
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Freescale Semiconductor
Core Timer Interrupts
Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2
set is provided so that the EPO can be started and allowed to stabilize while the LPO still clocks the
MCU. The reset state is for OM1 to be cleared and OM2 to be set, which selects the LPO and disables
the EPO.
IRQF — External Interrupt Request Flag
The IRQ flag is a clearable, read-only bit that is set when an external interrupt request is pending.
Writing to the IRQF bit has no effect. Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
The following conditions set the IRQ flag:
• An external interrupt signal on the IRQ/VPP pin
• An external interrupt signal on pin PA0, PA1, PA2, or PA3
when the PA0–PA3 pins are enabled by the PIRQ bit in the MOR to serve as external interrupt
sources.
The following conditions clear the IRQ flag:
• When the CPU fetches the interrupt vector
• When a logic 1 is written to the IRQR bit
IRQR — Interrupt Request Reset Bit
This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines.
Writing a logic 1 to IRQR clears the IRQF. Writing a logic 0 to IRQR has no effect. IRQR always reads
as a logic 0. Reset has no effect on IRQR.
1 = Clear IRQF flag bit
0 = No effect
4.6 Core Timer Interrupts
The core timer can generate the following interrupts:
• Timer overflow interrupt
• Real-time interrupt
Setting the I bit in the condition code register disables core timer interrupts. The controls and flags for
these interrupts are in the core timer status and control register (CTSCR) located at $0008.
4.6.1 Core Timer Overflow Interrupt
An overflow interrupt request occurs if the core timer overflow flag (TOF) becomes set while the core timer
overflow interrupt enable bit (TOFE) is also set. The TOF flag bit can be reset by writing a logic 1 to the
CTOFR bit in the CTSCR or by a reset of the device.
4.6.2 Real-Time Interrupt
A real-time interrupt request occurs if the real-time interrupt flag (RTIF) in the CTSCR becomes set while
the real-time interrupt enable bit (RTIE) is also set. The RTIF flag bit can be reset by writing a logical 1 to
the RTIFR bit in the CTSCR or by a reset of the device.
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Interrupts
4.7 Programmable Timer Interrupts
The 16-bit programmable timer can generate an interrupt whenever the following events occur:
• Input capture
• Output compare
• Timer counter overflow
Setting the I bit in the condition code register disables timer interrupts. The controls for these interrupts
are in the timer control register (TCR) located at $0012 and in the status bits in the timer status register
(TSR) located at $0013.
4.7.1 Input Capture Interrupt
An input capture interrupt occurs if the input capture flag (ICF) becomes set while the input capture
interrupt enable bit (ICIE) is also set. The ICF flag bit is in the TSR, and the ICIE enable bit is located in
the TCR. The ICF flag bit is cleared by a read of the TSR with the ICF flag bit set, and then followed by a
read of the LSB of the input capture register (ICRL) or by reset. The ICIE enable bit is unaffected by reset.
4.7.2 Output Compare Interrupt
An output compare interrupt occurs if the output compare flag (OCF) becomes set while the output
compare interrupt enable bit (OCIE) is also set. The OCF flag bit is in the TSR and the OCIE enable bit
is in the TCR. The OCF flag bit is cleared by a read of the TSR with the OCF flag bit set, and then followed
by an access to the LSB of the output compare register (OCRL) or by reset. The OCIE enable bit is
unaffected by reset.
4.7.3 Timer Overflow Interrupt
A timer overflow interrupt occurs if the timer overflow flag (TOF) becomes set while the timer overflow
interrupt enable bit (TOIE) is also set. The TOF flag bit is in the TSR and the TOIE enable bit is in the
TCR. The TOF flag bit is cleared by a read of the TSR with the TOF flag bit set, and then followed by an
access to the LSB of the timer registers (TMRL) or by reset. The TOIE enable bit is unaffected by reset.
4.8 Serial Interrupts
The simple serial interface can generate the following interrupts:
• Receive sequence complete
• Transmit sequence complete
Setting the I bit in the condition code register disables serial interrupts. The controls for these interrupts
are in the serial control register (SCR) located at $000A and in the status bits in the serial status register
(SSR) located at $000B.
A transfer complete interrupt occurs if the serial interrupt flag (SPIF) becomes set while the serial interrupt
enable bit (SPIE) is also set. The SPIF flag bit is in the serial status register (SSR) located at $000B, and
the SPIE enable bit is located in the serial control register (SCR) located at $000A. The SPIF flag bit is
cleared by a read of the SSR with the SPIF flag bit set, and then followed by a read or write to the serial
data register (SDR) located at $000C. The SPIF flag bit can also be reset by writing a one to the SPIR bit
in the SCR.
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Analog Interrupts
4.9 Analog Interrupts
The analog subsystem can generate the following interrupts:
• Voltage on positive input of comparator 1 is greater than the voltage on the negative input of
comparator 1.
• Voltage on positive input of comparator 2 is greater than the voltage on the negative input of
comparator 2.
• Trigger of the input capture interrupt from the programmable timer as described in 4.7.1 Input
Capture Interrupt
Setting the I bit in the condition code register disables analog subsystem interrupts. The controls for these
interrupts are in the analog subsystem control register (ACR) located at $001D, and the status bits are in
the analog subsystem status register (ASR) located at $001E.
4.9.1 Comparator Input Match Interrupt
A comparator input match interrupt occurs if either compare flag bit (CPF1 or CPF2) in the ASR becomes
set while the comparator interrupt enable bit (CPIE) in the ACR is also set. The CPF1 and CPF2 flag bits
can be reset by writing a one to the corresponding CPFR1 or CPFR2 bits in the ASR. Reset clears these
bits.
4.9.2 Input Capture Interrupt
The analog subsystem can also generate an input capture interrupt through the 16-bit programmable
timer. The input capture can be triggered when there is a match in the input conditions for the voltage
comparator 2. If comparator 2 sets the CP2F flag bit in the ASR and the input capture enable (ICEN) in
the ACR is set, then an input capture will be performed by the programmable timer. If the ICIE enable bit
in the TCR is also set, then an input compare interrupt will occur. Reset clears these bits.
NOTE
For the analog subsystem to generate an interrupt using the input capture
function of the programmable timer, the ICEN enable bit in the ACR, and
the ICIE and IEDG bits in the TCR must all be set.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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41
Interrupts
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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Freescale Semiconductor
Chapter 5
Resets
5.1 Introduction
This section describes the five reset sources and how they initialize the microcontroller unit (MCU). A
reset immediately stops the operation of the instruction being executed, initializes certain control bits, and
loads the program counter with a user-defined reset vector address. These conditions produce a reset:
• Initial power-up of device (power-on reset)
• A logic 0 applied to the RESET pin (external reset)
• Timeout of the computer operating properly (COP) watchdog (COP reset)
• Low voltage applied to the device (LVR reset)
• Fetch of an opcode from an address not in the memory map (illegal address reset)
Figure 5-1 shows a block diagram of the reset sources and their interaction.
INTERNAL DATA BUS
COPEN
LVREN
MASK OPTION REGISTER ($1FF1)
COP WATCHDOG
LOW-VOLTAGE RESET
VDD
POWER-ON RESET
ILLEGAL ADDRESS RESET
INTERNAL
ADDRESS BUS
S
D
RESET
LATCH
RESET
RST
TO CPU
AND
SUBSYSTEMS
R
3-CYCLE
CLOCKED
1-SHOT
INTERNAL
CLOCK
Figure 5-1. Reset Sources
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
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Resets
5.2 Power-On Reset
A positive transition on the VDD pin generates a power-on reset. The power-on reset is strictly for
conditions during powering up and cannot be used to detect drops in power supply voltage.
A delay of 16 or 4064 internal bus cycles (tcyc) after the oscillator becomes active allows the clock
generator to stabilize. If the RESET pin is at logic 0 at the end of this multiple tcyc time, the MCU remains
in the reset condition until the signal on the RESET pin goes to a logic 1.
5.3 External Reset
A logic 0 applied to the RESET pin for a minimum of one and one half tcyc generates an external reset.
This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage
separated by a minimum amount of hysteresis. The external reset occurs whenever the RESET pin is
pulled below the lower threshold and remains in reset until the RESET pin rises above the upper
threshold. This active low input will generate the internal RST signal that resets the CPU and peripherals.
The RESET pin can also be pulled to a low state by an internal pulldown device that is activated by three
internal reset sources. This reset pulldown device will only be asserted for three to four cycles of the
internal bus or as long as the internal reset source is asserted.
NOTE
Do not connect the RESET pin directly to VDD, as this may overload some
power supply designs if the internal pulldown on the RESET pin should
activate. If an external reset function is not required, the RESET pin should
be left unconnected.
5.4 Internal Resets
The four internally generated resets are:
• Initial power-on reset (POR) function
• COP watchdog timer reset
• Low-voltage reset (LVR)
• Illegal address detector
Only the COP watchdog timer reset, low-voltage reset, and illegal address detector will also assert the
pulldown device on the RESET pin for the duration of the reset function or for three to four internal bus
cycles, whichever is longer.
5.4.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly
for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out); that
function can be performed by the LVR. Depending on the DELAY bit in the mask option register (MOR),
there is an oscillator stabilization delay of 16 or 4064 internal bus cycles after the LPO becomes active.
The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the
end of the 16- or 4064-cycle delay, the RST signal will remain in the reset condition until the other reset
condition(s) end.
POR will not activate the pulldown device on the RESET pin. VDD must drop below VPOR for the internal
POR circuit to detect the next rise of VDD.
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Freescale Semiconductor
Internal Resets
5.4.2 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error
detection system and must be cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to the COPC bit of the COPR register at location
$1FF0. The COPC bit, shown in Figure 5-2, is a write-only bit.
Address:
Read:
Write:
Reset:
$1FF0
Bit 7
6
EPMSEC
OPT
U
U
5
4
3
2
1
Bit 0
COPC
U
= Unimplemented
U
U
U
U
U
U = Unaffected
Figure 5-2. COP and Security Register (COPR)
EPMSEC — EPROM Security(1) Bit
The EPMSEC bit is an EPROM, write-only security bit to protect the contents of the user EPROM code
stored in locations $0700–$1FFF.
OPT — Optional Features Bit
The OPT bit enables two additional features: direct drive by comparator 1 output to PB4 and voltage
offset capability to sample capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
NOTE
See 8.7.1 Voltage Comparator 1 and 8.10 Sample and Hold for further
descriptions of the OPT bit.
COPC — COP Clear Bit
COPC is a write-only bit. Periodically writing a logic 0 to COPC prevents the COP watchdog from
resetting the MCU. Reset clears the COPC bit.
1 = No effect on COP watchdog timer
0 = Reset COP watchdog timer
The COP watchdog reset will assert the pulldown device to pull the RESET pin low for three to four cycles
of the internal bus.
The COP watchdog reset function can be enabled or disabled by programming the COPEN bit in the
MOR.
5.4.3 Low-Voltage Reset (LVR)
The LVR activates the RST reset signal to reset the device when the voltage on the VDD pin falls below
the LVR trip voltage. The LVR will assert the pulldown device to pull the RESET pin low for three to four
cycles of the internal bus.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
45
Resets
The LVR reset function can be enabled or disabled by programming the LVREN bit in the MOR.
NOTE
The LVR is intended for applications where the VDD supply voltage
normally operates above 4.5 volts.
5.4.4 Illegal Address Reset
An opcode fetch (execution of an instruction) at an address that is not in the EPROM (locations
$0700–$1FFF) or the RAM (locations $0020–$00FF) generates an illegal address reset. The illegal
address reset will assert the pulldown device to pull the RESET pin low for three to four cycles of the
internal bus.
5.5 Reset States
This subsection describe how the various resets initialize the MCU.
5.5.1 CPU
A reset has these effects on the CPU:
• Loads the stack pointer with $FF
• Sets the I bit in the condition code register, inhibiting interrupts
• Loads the program counter with the user-defined reset vector from locations $1FFE and $1FFF
• Clears the stop latch, enabling the CPU clock
• Clears the wait latch, bringing the CPU out of the wait mode
5.5.2 I/O Registers
A reset has these effects on input/output (I/O) registers:
• Clears bits in data direction registers configuring pins as inputs:
– DDRA5–DDRA0 in DDRA for port A
– DDRB7–DDRB0 in DDRB for port B
– DDRC7–DDRC0 in DDRC for port C(1)
• Clears bits in pulldown inhibit registers to enable pulldown devices:
– PDIA5–PDIA0 in PDRA for port A
– PDIB7–PDIB0 in PDRB for port B
– PDICH and PDICL in PDRA for port C(1)
• Has no effect on port A, B, or C(1) data registers
• Sets the IRQE bit in the interrupt status and control register (ISCR)
5.5.3 Core Timer
A reset has these effects on the core timer:
• Clears the core timer counter register (CTCR)
• Clears the core timer interrupt flag and enable bits in the core timer status and control register
(CTSCR)
• Sets the real-time interrupt (RTI) rate selection bits (RT0 and RT1) such that the device will start
with the longest real-time interrupt and longest COP timeout delays
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices
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Freescale Semiconductor
Reset States
5.5.4 COP Watchdog
A reset clears the COP watchdog timeout counter.
5.5.5 16-Bit Programmable Timer
A reset has these effects on the 16-bit programmable timer:
• Initializes the timer counter registers (TMRH and TMRL) to a value of $FFFC
• Initializes the alternate timer counter registers (ACRH and ACRL) to a value of $FFFC
• Clears all the interrupt enables and the output level bit (OLVL) in the timer control register (TCR)
• Does not affect the input capture edge bit (IEDG) in the TCR
• Does not affect the interrupt flags in the timer status register (TSR)
• Does not affect the input capture registers (ICRH and ICRL)
• Does not affect the output compare registers (OCRH and OCRL)
5.5.6 Serial Interface
A reset has these effects on the serial interface:
• Clears all bits in the SIOP control register (SCR)
• Clears all bits in the SIOP status register (SSR)
• Does not affect the contents of the SIOP data register (SDR)
A reset, therefore, disables the SIOP and leaves the shared port B pins as general I/O. Any pending
interrupt flag is cleared and the SIOP interrupt is disabled. Also the baud rate defaults to the slowest rate.
5.5.7 Analog Subsystem
A reset has these effects on the analog subsystem:
• Clears all the bits in the multiplex register (AMUX) bits except the hold switch bit (HOLD) which is
set
• Clears all the bits in the analog control register (ACR)
• Clears all the bits in the analog status register (ASR)
A reset, therefore, connects the negative input of comparator 2 to the channel selection bus, which is
switched to VSS. Both comparators are set up as non-inverting (a higher positive voltage on the positive
input results in a positive output) and both are powered down. The current source and discharge device
on the PB0/AN0 pin is disabled and powered down. Any analog subsystem interrupt flags are cleared and
the analog interrupt is disabled. Direct drive by comparator 1 to the PB4 pin and the voltage offset to the
sample capacitor are disabled (if both are enabled by the OPT bit being set in the COPR).
5.5.8 External Oscillator and Internal Low-Power Oscillator
A reset presets the oscillator select bits (OM1 and OM2) in the interrupt status and control register (ISCR)
such that the device runs from the internal oscillator (OM1 = 0, OM2 = 1) which has these effects on the
oscillators:
• The internal low-power oscillator is enabled and selected.
• The external oscillator is disabled.
• The CPU bus clock is driven from the internal low-power oscillator.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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Resets
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Freescale Semiconductor
Chapter 6
Operating Modes
6.1 Introduction
This section describes the operation of the device with respect to the oscillator source and the low-power
modes:
• Stop mode
• Wait mode
• Halt mode
• Data-retention mode
6.2 Oscillator Source
The microcontroller unit (MCU) can be clocked by either an internal low-power oscillator (LPO) without
external components or by an external pin oscillator (EPO) which uses external components. The enable
and selection of the clock source is determined by the state of the oscillator select bits (OM1 and OM2)
in the interrupt status and control register (ISCR) as shown in Figure 6-1.
Address:
$000D
Bit 7
Read:
Write:
Reset:
6
5
IRQE
OM2
OM1
1
1
0
= Unimplemented
4
3
2
1
Bit 0
0
IRQF
0
0
0
IRQR
R
0
0
R
0
0
0
= Reserved
Figure 6-1. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Refer to Chapter 4 Interrupts for more details.
OM1 and OM2 — Oscillator Select Bits
These bits control the selection and enabling of the oscillator source for the MCU. One choice is the
internal LPO and the other oscillator is the EPO which is common to most M68HC05 MCU devices.
The EPO uses external components like filter capacitors and a crystal or ceramic resonator and
consumes more power than the LPO. The selection and enable conditions for these two oscillators are
shown in Table 6-1. Reset clears OM1 and sets OM2, which selects the LPO and disables the EPO.
Therefore, the lowest power is consumed when OM1 is cleared. The state with both OM1 and OM2
set is provided so that the EPO can be started up and allowed to stabilize while the LPO still clocks the
MCU.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
49
Operating Modes
.
Table 6-1. Oscillator Selection
Internal
Low-Power
Oscillator
(LPO)
External Pin
Oscillator
(EPO)
Power
Consumption
OM2
OM1
Oscillator
Selected
0
0
Internal
Enabled
Disabled
Lowest
0
1
External
Disabled
Enabled
Normal
1
0
Internal
Enabled
Disabled
Lowest
1
1
Internal
Enabled
Enabled
Normal
NOTE
When switching from LPO to EPO, the user must be careful to ensure that
the EPO has been enabled and powered up long enough to stabilize before
shifting clock sources.
IRQF — External Interrupt Request Flag
The IRQF flag is a clearable, read-only bit that is set when an external interrupt request is pending.
Refer to Chapter 4 Interrupts for more details.
IRQR — Interrupt Request Reset Bit
This write-only bit clears the IRQF flag bit and prevents redundant execution of interrupt routines. Refer
to Chapter 4 Interrupts for more details.
6.3 Low-Power Modes
Four modes of operation reduce power consumption:
• Stop mode
• Wait mode
• Halt mode
• Data-retention mode
Figure 6-2 shows the sequence of events in stop, wait, and halt modes.
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Freescale Semiconductor
Low-Power Modes
STOP
SWAIT BIT
IN MOR SET?
HALT
YES
NO
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
CLEAR CTOF, RTIF, CTOFE, AND RTIE BITS IN TSCR.
CLEAR ICF, OCF, AND TOF BITS IN TSR.
CLEAR ICIE, OCIE, AND TOIE BITS IN TCR.
DISABLE EXTERNAL PIN OSCILLATOR.
TURN OFF INTERNAL LOW-POWER OSCILLATOR.
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
KEEP OTHER MODULE
CLOCKS ACTIVE.
YES
EXTERNAL
RESET?
WAIT
CLEAR I BIT IN CCR.
SET IRQE BIT IN ISCR.
TURN OFF CPU CLOCK.
KEEP OTHER MODULE
CLOCKS ACTIVE.
YES
EXTERNAL
RESET?
NO
NO
EXTERNAL
RESET?
YES
YES
YES
YES
EXTERNAL
INTERRUPT?
CORE
TIMER
INTERRUPT?
NO
YES
CORE
TIMER
INTERRUPT?
NO
NO
YES
TURN ON SELECTED OSCILLATOR.
RESET STABILIZATION DELAY TIMER.
PROG.
TIMER
INTERRUPT?
NO
YES
PROG.
TIMER
INTERRUPT?
NO
YES
YES
YES
NO
NO
EXTERNAL
INTERRUPT?
EXTERNAL
INTERRUPT?
SIOP
INTERRUPT?
NO
YES
SIOP
INTERRUPT?
NO
END OF
STABILIZATION
DELAY?
YES
NO
ANALOG
INTERRUPT?
NO
YES
ANALOG
INTERRUPT?
NO
YES
TURN ON CPU CLOCK.
COP
RESET?
NO
YES
COP
RESET?
NO
NO
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT.
a. SAVE CPU REGISTERS ON STACK.
b. SET I BIT IN CCR.
c. LOAD PC WITH INTERRUPT VECTOR.
Figure 6-2. Stop/Wait/Halt Flowchart
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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51
Operating Modes
6.3.1 Stop Mode
The STOP instruction puts the MCU in a mode with the lowest power consumption and affects the MCU
as follows:
• Turns off the central processor unit (CPU) clock and all internal clocks by stopping both the external
pin oscillator and the internal low-power oscillator. The selection of the oscillator by the OM1 and
OM2 bits in the ISCR is not affected. The stopped clocks turn off the COP watchdog, the core timer,
the programmable timer, the analog subsystem, and the SIOP.
• Removes any pending core timer interrupts by clearing the core timer interrupt flags (CTOF and
RTIF) in the core timer status and control register (CTSCR)
• Disables any further core timer interrupts by clearing the core timer interrupt enable bits (CTOFE
and RTIE) in the CTSCR
• Removes any pending programmable timer interrupts by clearing the timer interrupt flags (ICF,
OCF, and TOF) in the timer status register (TSR)
• Disables any further programmable timer interrupts by clearing the timer interrupt enable bits (ICIE,
OCIE, and TOIE) in the timer control register (TCR)
• Enables external interrupts via the IRQ/VPP pin by setting the IRQE bit in the IRQ status and control
register (ISCR). External interrupts are also enabled via the PA0 through PA3 pins, if the port A
interrupts are enabled by the PIRQ bit in the mask option register (MOR).
• Enables interrupts in general by clearing the I bit in the condition code register
The STOP instruction does not affect any other bits, registers, or I/O lines.
The following conditions bring the MCU out of stop mode:
• An external interrupt signal on the IRQ/VPP pin — A high-to-low transition on the IRQ/VPP pin loads
the program counter with the contents of locations $1FFA and $1FFB.
• An external interrupt signal on a port A external interrupt pin — If selected by the PIRQ bit in the
MOR, a low-to-high transition on a PA3–PA0 pin loads the program counter with the contents of
locations $1FFA and $1FFB.
• External reset — A logic 0 on the RESET pin resets the MCU and loads the program counter with
the contents of locations $1FFE and $1FFF.
When the MCU exits stop mode, processing resumes after a stabilization delay of 16 or 4064 internal bus
cycles, depending on the state of the DELAY bit in the MOR.
NOTE
Execution of the STOP instruction without setting the SWAIT bit in the MOR
will cause the oscillators to stop, and, therefore, disable the COP watchdog
timer. If the COP watchdog timer is to be used, stop mode should be
changed to halt mode as described in 6.3.3 Halt Mode.
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Low-Power Modes
6.3.2 Wait Mode
The WAIT instruction puts the MCU in a low-power wait mode which consumes more power than the stop
mode and affects the MCU as follows:
• Enables interrupts by clearing the I bit in the condition code register
• Enables external interrupts by setting the IRQE bit in the IRQ status and control register
• Stops the CPU clock which drives the address and data buses, but allows the selected oscillator
to continue to clock the core timer, programmable timer, analog subsystem, and SIOP
The WAIT instruction does not affect any other bits, registers, or I/O lines.
These conditions restart the CPU bus clock and bring the MCU out of wait mode:
• An external interrupt signal on the IRQ/VPP pin — A high-to-low transition on the IRQ/VPP pin loads
the program counter with the contents of locations $1FFA and $1FFB.
• An external interrupt signal on a port A external interrupt pin — If selected by PIRQ bit in the MOR,
a low-to-high transition on a PA3–PA0 pin loads the program counter with the contents of locations
$1FFA and $1FFB.
• A core timer interrupt — A core timer overflow or a real-time interrupt loads the program counter
with the contents of locations $1FF8 and $1FF9.
• A programmable timer interrupt — A programmable timer interrupt driven by an input capture,
output compare, or timer overflow loads the program counter with the contents of locations $1FF6
and $1FF7.
• An SIOP interrupt — An SIOP interrupt driven by the completion of transmitted or received 8-bit
data loads the program counter with the contents of locations $1FF4 and $1FF5.
• An analog subsystem interrupt — An analog subsystem interrupt driven by a voltage comparison
loads the program counter with the contents of locations $1FF2 and $1FF3.
• A COP watchdog reset — A timeout of the COP watchdog resets the MCU and loads the program
counter with the contents of locations $1FFE and $1FFF. Software can enable real-time interrupts
so that the MCU can periodically exit the wait mode to reset the COP watchdog.
• An external reset — A logic 0 on the RESET pin resets the MCU and loads the program counter
with the contents of locations $1FFE and $1FFF.
When the MCU exits the wait mode, there is no delay before code executes like occurs when exiting the
stop or halt modes.
6.3.3 Halt Mode
The STOP instruction puts the MCU in halt mode if selected by the SWAIT bit in the MOR. Halt mode is
identical to wait mode, except that a variable recovery delay occurs when the MCU exits halt mode. A
recovery time of from 1 to 16 or from 1 to 4064 internal bus cycles can be selected by the DELAY bit in
the MOR.
If the SWAIT bit is set in the MOR to put the MCU in halt mode, the COP watchdog cannot be turned off
inadvertently by a STOP instruction.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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Operating Modes
6.3.4 Data-Retention Mode
In the data-retention mode, the MCU retains random-access memory (RAM) contents and CPU register
contents at VDD voltages as low as 2.0 Vdc. The data retention feature allows the MCU to remain in a
low-power consumption state during which it retains data, but the CPU cannot execute instructions.
Current consumption in this mode is not tested.
To put the MCU in the data retention mode:
1. Drive the RESET pin to a logic 0.
2. Lower the VDD voltage. The RESET pin must remain low continuously during data retention mode.
To take the MCU out of the data retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to a logic 1.
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Freescale Semiconductor
Chapter 7
Parallel Input/Output
7.1 Introduction
The MC68HC705JJ7 has 14 bidirectional input/output (I/O) pins which form two parallel I/O ports, A
and B. The MC68HC705JP7 has 22 bidirectional I/O pins which form three parallel I/O ports, A, B and C.
Each I/O pin is programmable as an input or an output. The contents of the data direction registers
determine the data direction of each of the I/O pins. All I/O pins have software programmable pulldown
devices which can be enabled or disabled globally by the SWPDI bit in the mask option register (MOR).
7.2 Port A
Port A is a 6-bit, general-purpose, bidirectional I/O port with these features:
• Individual programmable pulldown devices
• High current sinking capability on all port A pins, with a maximum total for port A
• High current sourcing capability on all port A pins, with a maximum total for port A
• External interrupt capability (pins PA3–PA0)
7.2.1 Port A Data Register
The port A data register (PORTA) contains a bit for each of the port A pins. When a port A pin is
programmed to be an output, the state of its data register bit determines the state of the output pin. When
a port A pin is programmed to be an input, reading the port A data register returns the logic state of the
pin. The upper two bits of the port A data register will always read as logic 0s.
Address:
Read:
Write:
$0000
Bit 7
6
0
0
5
4
3
2
1
Bit 0
PA5
PA4
PA3
PA2
PA1
PA0
KYBD2
KYBD1
KYBD0
Reset:
Unaffected by reset
Alternate:
KYBD3
= Unimplemented
Figure 7-1. Port A Data Register (PORTA)
PA5–PA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of each bit is under the control of the
corresponding bit in the port A data direction register (DDRA). Reset has no effect on port A data.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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Parallel Input/Output
7.2.2 Data Direction Register A
The contents of the port A data direction register (DDRA) determine whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the associated port A pin. A
DDRA bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRA bit
disables the output buffer for the associated port A pin. The upper two bits always read as logic 0s. A reset
initializes all DDRA bits to logic 0s, configuring all port A pins as inputs and disabling the voltage
comparators from driving PA4 or PA5.
Address:
$0004
Bit 7
6
0
0
0
0
Read:
Write:
Reset:
5
4
3
2
1
Bit 0
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
= Unimplemented
Figure 7-2. Data Direction Register A (DDRA)
DDRA5–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears the DDRA5–DDRA0 bits.
1 = Corresponding port A pin configured as output and pulldown device disabled
0 = Corresponding port A pin configured as input
7.2.3 Pulldown Register A
All port A pins can have software programmable pulldown devices enabled or disabled globally by SWPDI
bit in the MOR. These pulldown devices are controlled by the write-only pulldown register A (PDRA)
shown in Figure 7-3. Clearing the PDIA5–PDIA0 bits in the PDRA turns on the pulldown devices if the port
A pin is an input. Reading the PDRA returns undefined results since it is a write-only register; therefore,
do not change the value in PDRA with read/modify/write instructions. On the MC68HC705JP7 the PDRA
contains two pulldown control bits (PDICH and PDICL) for port C. Reset clears the PDIA5–PDIA0, PDICH,
and PDICL bits, which turns on all the port A and port C pulldown devices.
Address:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
Write:
PDICH
PDICL
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
0
0
0
0
0
0
0
0
Read:
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
PDICH — Upper Port C Pulldown Inhibit Bits (MC68HC705JP7)
Writing to this write-only bit controls the port C pulldown devices on the upper four bits (PC4–PC7).
Reading these pulldown register A bits returns undefined data. Reset clears bit PDICH.
1 = Upper four port C pins pulldown devices turned off
0 = Upper four port C pins pulldown devices turned on if pin has been programmed by the DDRC
to be an input
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Freescale Semiconductor
Port A
PDICL — Lower Port C Pulldown Inhibit Bits (MC68HC705JP7)
Writing to this write-only bit controls the port C pulldown devices on the lower four bits (PC0–PC3).
Reading these pulldown register A bits returns undefined data. Reset clears bit PDICL.
1 = Lower four port C pins pulldown devices turned off
0 = Lower four port C pins pulldown devices turned on if pin has been programmed by the DDRC
to be an input
PDIA5–PDIA0 — Port A Pulldown Inhibit Bits
Writing to these write-only bits controls the port A pulldown devices. Reading these pulldown register
A bits returns undefined data. Reset clears bits PDIA5–PDIA0.
1 = Corresponding port A pin pulldown device turned off
0 = Corresponding port A pin pulldown device turned on if pin has been programmed by the DDRA
to be an input
7.2.4 Port A External Interrupts
The PIRQ bit in the MOR enables the PA3–PA0 pins to serve as external interrupt pins in addition to the
IRQ/VPP pin. The active interrupt state for the PA3–PA0 pins is a logic 1 or a rising edge. A state of the
PIRQ bit in the MOR determines whether external interrupt inputs are edge-sensitive only or both edgeand level-sensitive. Port A interrupts are also interactive with each other and the IRQ/VPP pin as described
in 4.5 External Interrupts.
NOTE
When testing for external interrupts, the BIH and BIL instructions test the
voltage on the IRQ/VPP pin, not the state of the internal IRQ signal.
Therefore, BIH and BIL cannot test the port A external interrupt pins.
7.2.5 Port A Logic
When a PA0:PA5 pin is programmed as an output, reading the port bit actually reads the value of the data
latch and not the voltage on the pin itself. When a PA0:PA5 pin is programmed as an input, reading the
port bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of
its DDR bit. Figure 7-4 shows the I/O logic of PA0–PA5 pins of port A.
The data latch can always be written, regardless of the state of its DDR bits. Table 7-1 summarizes the
operations of the port A pins.
Table 7-1. Port A Pin Functions
Port A
Pin(s)
SWPDI
(in MOR)
PA0
PA1
PA2
PA3
PA4
PA5
PORTA Access
(Pin or Data Register)
Port A
Result on
Port A Pins
PDIAx
DDRAx(1)
Read
Write
Pulldown
Pin
0
0
0
Pin
Data
On
PAx in
0
1
0
Pin
Data
Off
PAx in
1
X
0
Pin
Data
Off
PAx in
X(2)
X(2)
1
Data
Data
Off
PAx out
1. DDRA can always be read or written.
2. Don’t care
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
57
Parallel Input/Output
EXTERNAL
INTERRUPT
REQUEST
(PA0:3)
READ $0004
WRITE $0004
DATA DIRECTION
REGISTER A
BIT DDRAx
PORT A DATA
REGISTER
BIT PAx
WRITE $0000
PAx
HIGH SINK/SOURCE
CURRENT
CAPABILITY
READ $0000
WRITE $0010
PULLDOWN
REGISTER A
BIT PDIAx
R
PULLDOWN
DEVICE
SWPDI
INTERNAL DATA BUS
R
RESET
MASK OPTION REG. ($1FF1)
Figure 7-4. Port A I/O Circuit
7.3 Port B
Port B is an 8-bit, general-purpose, bidirectional I/O port with these features:
• Programmable pulldown devices
• PB0–PB4 are shared with the analog subsystem.
• PB3 and PB4 are shared with the 16-bit programmable timer.
• PB4 can be driven directly by the output of comparator 1.
• PB5–PB7 are shared with the simple serial interface (SIOP).
• High current sinking capability on the PB4 pin
• High current sourcing capability on the PB4 pin
7.3.1 Port B Data Register
The port B data register (PORTB) contains a bit for each of the port B pins. When a port B pin is
programmed to be an output, the state of its data register bit determines the state of the output pin. When
a port B pin is programmed to be an input, reading the port B data register returns the logic state of the
pin. Reset has no effect on port B data.
Address:
Read:
Write:
$0001
Bit 7
6
5
4
3
2
1
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Reset:
Unaffected by reset
Alternate:
SCK
SDI
SDO
AN4
AN3
AN2
AN1
AN0
Alternate:
SCK
SDI
SDO
TCMP
TCAP
AN2
AN1
AN0
Alternate:
SCK
SDI
SDO
CMP1
TCAP
AN2
AN1
AN0
Figure 7-5. Port B Data Register (PORTB)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
58
Freescale Semiconductor
Port B
PB0-PB7 — Port B Data Bits
These read/write bits are software programmable. Data direction of each bit is under the control of the
corresponding bit in data direction register B. Reset has no effect on port B data.
7.3.2 Data Direction Register B
The contents of the port B data direction register (DDRB) determine whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the associated port B pin. A
DDRB bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRB bit
disables the output buffer for the associated port B pin. A reset initializes all DDRB bits to logic 0s,
configuring all port B pins as inputs.
Address:
Read:
Write:
Reset:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
0
0
0
0
0
0
0
0
Figure 7-6. Data Direction Register B (DDRB)
DDRB7–DDRB0 — Port B Data Direction Bits
These read/write bits control port B data direction. Reset clears the bits DDRB7–DDRB0.
1 = Corresponding port B pin configured as output and pulldown device disabled
0 = Corresponding port B pin configured as input
7.3.3 Pulldown Register B
All port B pins can have software programmable pulldown devices enabled or disabled globally by the
SWPDI bit in the MOR. These pulldown devices are individually controlled by the write-only pulldown
register B (PDRB) shown in Figure 7-7. Clearing the PDIB7–PDIB0 bits in the PDRB turns on the pulldown
devices if the port B pin is an input. Reading the PDRB returns undefined results since it is a write-only
register. Reset clears the PDIB7–PDIB0 bits, which turns on all the port B pulldown devices.
Address:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
Write:
PDIB7
PDIB6
PDIB5
PDIB4
PDIB3
PDIB2
PDIB1
DIB0
Reset:
0
0
0
0
0
0
0
0
Read:
= Unimplemented
Figure 7-7. Pulldown Register B (PDRB)
PDIB7–PDIB0 — Port B Pulldown Inhibit Bits
Writing to these write-only bits controls the port B pulldown devices. Reading these pulldown register
B bits returns undefined data. Reset clears bits PDIB7–PDIB0.
1 = Corresponding port B pin pulldown device turned off
0 = Corresponding port B pin pulldown device turned on if pin has been programmed by the DDRB
to be an input
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
59
Parallel Input/Output
7.3.4 Port B Logic
All port B pins have the general I/O port logic similar to port A; but they also share this function with inputs
or outputs from other modules, which are also attached to the pin itself or override the general I/O
function. PB0, PB1, PB2, and PB3 simply share their inputs with another module. PB4, PB5, PB6, and
PB7 will have their operation altered by outputs or controls from other modules.
7.3.5 PB0, PBI, PB2, and PB3 Logic
The typical I/O logic shown in Figure 7-8 is used for PB0, PB1, PB2, and PB3 pins of port B. When these
port B pins are programmed as an output, reading the port bit actually reads the value of the data latch
and not the voltage on the pin itself. When these port B pins are programmed as an input, reading the port
bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its
DDRB bit. The operations of the PB0–PB3 pins are summarized in Table 7-2.
READ $0005
WRITE $0005
R
DATA DIRECTION
REGISTER B
BIT DDRBx
PORT BDATA
REGISTER
BIT PBx
WRITE $0001
PBx
READ $0001
WRITE $0011
R
RESET
PULLDOWN
REGISTER B
BIT PDIBx
PULLDOWN
DEVICE
SWPDI
INTERNAL DATA BUS
ANALOG SUBSYSTEM,
AND PROGRAMMABLE
TIMER INPUT CAPTURE
(PINS PB0, PB1, PB2, PB3)
MASK OPTION REG. ($1FF1)
Figure 7-8. PB0–PB3 Pin I/O Circuit
The PB0–PB3 pins share their inputs with another module. When using the other attached module, these
conditions must be observed:
1. If the DDRB configures the pin as an output, then the port data register can provide an output which
may conflict with any external input source to the other module. The pulldown device will be
disabled in this case.
2. If the DDRB configures the pin as an input, then reading the port data register will return the state
of the input in terms of the digital threshold for that pin (analog inputs will default to logic states).
3. If DDRB configures the pin as an input and the pulldown device is activated for a pin, it will also
load the input to the other module.
4. If interaction between the port logic and the other module is not desired, the pin should be
configured as an input by clearing the appropriate DDRB bit. The input pulldown device is disabled
by clearing the appropriate PDRB bit (or by disabling programmable pulldowns with the SWPDI bit
in the MOR).
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
60
Freescale Semiconductor
Port B
7.3.6 PB4/AN4/TCMP/CMP1 Logic
The PB4/AN4/TCMP/CMP1 pin can be used as a simple I/O port pin, be controlled by the OLVL bit from
the output compare function of the 16-bit programmable timer, or be controlled directly by the output of
comparator 1 as shown in Figure 7-9. The PB4 data, the programmable timer OLVL bit, and the output of
comparator 1 are all logically ORed together to drive the pin. Also, the analog subsystem input channel 4
multiplexer is connected directly to this pin. The operations of PB4 pin are summarized in Table 7-2.
ANALOG SUBSYSTEM
INPUT AN4 AND
TIMER OUTPUT COMPARE
READ $0005
WRITE $0005
INTERNAL DATA BUS
R
DATA DIRECTION
REGISTER B
BIT DDRB4
PORT BDATA
REGISTER
BIT PB4
WRITE $0001
PB4
AN4
TCMP
OLVL
(TIMER OUTPUT COMPARE)
HIGH SINK/
SOURCE CURRENT
CAPABILITY
CMP1
(COMPARATOR 1 OUT)
READ $0001
R
PULLDOWN
REGISTER B
BIT PDIB4
PULLDOWN
DEVICE
SWPDI
WRITE $0011
RESET
OPT
MASK OPTION REG. ($1FF1)
COP REGISTER ($1FF0)
Figure 7-9. PB4/AN4/TCMP/CMP1 Pin I/O Circuit
When using the PB4/AN4/TCMP/CMP1 pin, these interactions must be noted:
1. If the OLVL timer output compare function is the required output function, then the DDRB4 bit must
be set, the PB4 data bit must be cleared, and the OPT bit in the COPR must be cleared. The
PB4/AN4/TCMP/CMP1 pin becomes an output which follows the state of the OLVL bit. The
pulldown device will be disabled in this case. The analog subsystem would not normally use this
pin as an analog input in this case.
2. If the PB4 data bit is the required output function, then the DDRB4 bit must be set, the OLVL bit in
the TCR must be cleared, and the OPT bit in the COPR must be cleared. The pulldown device will
be disabled in this case. The analog subsystem would not normally use this pin as an analog input
in this case.
3. If the comparator 1 output is the desired output function, then the PB4 data bit must be cleared, the
DDRB4 bit must be set, the OLVL bit in the TCR must be cleared, and the OPT bit in the COPR
must be set. The PB4/AN4/TCMP/CMP1 pin becomes an output which follows the state of the
OLVL bit. The pulldown device will be disabled in this case. The analog subsystem would not
normally use this pin as an analog input in this case.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
61
Parallel Input/Output
4. If the PB4 pin is to be an input to the analog subsystem or a digital input, then the DDRB4 bit must
be cleared. In this case, the PB4 pin can still be read, but the voltage present will be returned as a
binary value. Depending on the external application, the PB4 pulldown may also be disabled by
setting the PDIB4 pulldown inhibit bit. In this case, both the digital and analog functions connected
to this pin can be utilized.
.
Table 7-2. Port B Pin Functions — PB0–PB4
Control Bits
Port B
Pin
Comparator 1
CMP1 COE1
PB0
PB1
PB2
PB3
X(2)
X(2)
PB4
X(2)
X(2)
Timer
OPT in COPR
X(2)
X(2)
OLVL
X(2)
X(2)
SWPDI
in MOR
PORTB Access
(Pin or Data
Register)
Port B
Result on
Port B Pins
PDIBx
DDRBx(1)
Read
Write
Pulldown
Pin
0
0
0
Pin
Data
On
PBx in
0
1
0
Pin
Data
Off
PBx in
1
X(2)
0
Pin
Data
Off
PBx in
X(2)
X(2)
1
Data
Data
Off
PBx out
0
0
0
Pin
Data
On
PB4 in
0
1
0
Pin
Data
Off
PB4 in
1
X(2)
0
Pin
Data
Off
PB4 in
X(2)
X(2)
0
0
X(2)
X(2)
1
Data
Data
Off
PB4 out
X(2)
0
1
0
X(2)
X(2)
1
Data
Data
Off
PB4 out
0
1
1
0
X(2)
X(2)
1
Data
Data
Off
PB4 out
X(2)
X(2)
X(2)
1
X(2)
X(2)
1
1
Data
Off
1
1
1
1
X(2)
X(2)
X(2)
1
1
Data
Off
1
1. DDRB can always be read or written.
2. Don’t care
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
62
Freescale Semiconductor
Port B
7.3.7 PB5/SDO Logic
The PB5/SDO pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in Figure 7-10. The operations of the PB5 pin are summarized in Table 7-3.
When using the PB5/SDO pin, these interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB5/SDO
pin buffer to be enabled and to be driven by the serial data output (SDO) from the SIOP. The
pulldown device will be disabled in this case.
2. If the SIOP function is in control of the PB5/SDO pin, the DDRB5 and PB5 data register bits are
still accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB5 bit is cleared, reading the PB5 data register will return the current state of
the PB5/SDO pin.
SERIAL DATA OUT (SDO)
SERIAL ENABLE (SPE)
VDD
READ $0005
WRITE $0005
INTERNAL DATA BUS
R
DATA DIRECTION
REGISTER B
BIT DDRB5
PORT B DATA
REGISTER
BIT PB5
WRITE $0001
PB5
SDO
READ $0001
WRITE $0011
RESET
PULLDOWN
DEVICE
SWPDI
R
PULLDOWN
REGISTER B
BIT PDIB5
MASK OPTION REG. ($1FF1)
Figure 7-10. PB5/SDO Pin I/O Circuit
3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
in the DDRB5, PDIB5, and PB5 register bits will then control the PB5/SDO pin.
4. If the PB5/SDO pin is to be a digital input, then both the SPE bit in the SCR and the DDRB5 bit
must be cleared. Depending on the external application, the pulldown device may also be disabled
by setting the PDIB5 pulldown inhibit bit.
5. If the PB5/SDO pin is to be a digital output, then the SPE bit in the SCR must be cleared and the
PDIB5 bit must be set. The pulldown device will be disabled in this case.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
63
Parallel Input/Output
7.3.8 PB6/SDI Logic
The PB6/SDI pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in Figure 7-11. The operations of PB6/SDI pin are summarized in Table 7-3.
SERIAL DATA IN (SDI)
SERIAL ENABLE (SPE)
READ $0005
WRITE $0005
INTERNAL DATA BUS
R
DATA DIRECTION
REGISTER B
BIT DDRB6
PORT B DATA
REGISTER
BIT PB6
WRITE $0001
PB6
SDI
READ $0001
WRITE $0011
PULLDOWN
DEVICE
SWPDI
R
RESET
PULLDOWN
REGISTER B
BIT PDIB6
MASK OPTION REG. ($1FF1)
Figure 7-11. PB6/SDI Pin I/O Circuit
When using the PB6/SDI pin, these interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB6/SDI
pin buffer to be disabled to allow the PB6/SDI pin to act as an input that feeds the serial data input
(SDI) of the SIOP. The pulldown device is disabled in this case.
2. If the SIOP function is in control of the PB6/SDI pin, the DDRB6 and PB6 data register bits are still
accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB6 bit is cleared, reading the PB6 data register will return the current state of
the PB6/SDI pin.
3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
in the DDRB6, PDIB6, and PB6 register bits will then control the PB6/SDI pin.
4. If the PB6/SDI pin is to be a digital input, then both the SPE bit in the SCR and the DDRB6 bit must
be cleared. Depending on the external application, the pulldown device may also be disabled by
setting the PDIB6 pulldown inhibit bit.
5. If the PB6/SDI pin is to be a digital output, then the SPE bit in the SCR must be cleared and the
DDRB6 bit must be set. The pulldown device will be disabled in this case.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
64
Freescale Semiconductor
Port B
7.3.9 PB7/SCK Logic
The PB7/SCK pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in Figure 7-12. The operations of the PB7/SCK pin are summarized in Table 7-3.
SERIAL DATA CLOCK (SCK)
CLOCK SOURCE (MSTR)
SERIAL ENABLE (SPE)
READ $0005
INTERNAL DATA BUS
WRITE $0005
R
DATA DIRECTION
REGISTER B
BIT DDRB7
PORT B DATA
REGISTER
BIT PB7
WRITE $0001
PB7
SCK
READ $0001
WRITE $0011
PULLDOWN
DEVICE
SWPDI
R
RESET
PULLDOWN
REGISTER B
BIT PDIB7
MASK OPTION REG. ($1FF1)
Figure 7-12. PB7/SCK Pin I/O Circuit
When using the PB7/SCK pin, these interactions must be noted:
1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB7/SCK
pin buffer to be controlled by the MSTR control bit in the SCR. The pulldown device is disabled in
these cases.
a. If the MSTR bit is set, then the PB7/SCK pin buffer will be enabled and driven by the serial
data clock (SCK) from the SIOP.
b. If the MSTR bit is clear, then the PB7/SCK pin buffer will be disabled, allowing the PB7/SCK
pin to drive the serial data clock (SCK) into the SIOP.
2. If the SIOP function is in control of the PB7/SCK pin, the DDRB7 and PB7 data register bits are still
accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB7 bit is cleared, reading the PB7 data register will return the current state of
the PB7/SCK pin.
3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
in the DDRB7, PDIB7, and PB7 register bits will then control the PB7/SCK pin.
4. If the PB7/SCK pin is to be a digital input, then both the SPE bit in the SCR and the DDRB7 bit
must be cleared. Depending on the external application, the pulldown device may also be disabled
by setting the PDIB7 pulldown inhibit bit.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
65
Parallel Input/Output
5. If the PB7/SCK pin is to be a digital output, then the SPE bit in the SCR must be cleared and the
DDRB7 bit must be set. The pulldown device will be disabled when the pin is set as an output.
Table 7-3. Port B Pin Functions — PB5–PB7
Control Bits
Port B
Pin
SIOP
SPE
0
MSTR
X(2)
PB5
1
0
X(2)
X(2)
SWPDI
in MOR
PORTB Access
(Pin or Data
Register)
Port B
Result on
Port B Pins
PDIBx
DDRBx(1)
Read
Write
Pulldown
Pin
0
0
0
Pin
Data
On
PB5 in
0
1
0
Pin
Data
Off
PB5 in
1
X
0
Pin
Data
Off
PB5 in
X(2)
X(2)
1
Data
Data
Off
PB5 out
X(2)
X(2)
0
SDO
Data
Off
SDO out
1
Data
Data
Off
SDO out
0
0
0
Pin
Data
On
PB6 in
0
1
0
Pin
Data
Off
PB6 in
1
X(2)
0
Pin
Data
Off
PB6 in
X(2)
X(2)
1
Data
Data
Off
PB6 out
X(2))
X(2)
0
SDI
Data
Off
SDI in
1
Data
Data
Off
SDI in
0
0
0
Pin
Data
On
PB7 in
0
1
0
Pin
Data
Off
PB7 in
1
X(2)
0
Pin
Data
Off
PB7 in
X(2)
X(2)
1
Data
Data
Off
PB7 out
X(2)
X(2)
0
SCK
Data
Off
SCK in
1
Data
Data
Off
SCK in
X(2)
X(2)
0
SCK
Data
Off
SCK out
1
Data
Data
Off
SCK out
PB6
1
0
X(2)
X(2)
PB7
0
1
1
1. DDRB can always be read or written.
2. Don’t care
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
66
Freescale Semiconductor
Port C (28-Pin Versions Only)
7.4 Port C (28-Pin Versions Only)
Port C is an 8-bit, general-purpose, bidirectional I/O port with these features:
• Individual programmable pulldown devices
• High current sinking capability on all port C pins, with a maximum total for port C
• High current sourcing capability on all port C pins, with a maximum total for port C
7.4.1 Port C Data Register
The port C data register (PORTC) contains a bit for each of the port C pins. When a port C pin is
programmed to be an output, the state of its data register bit determines the state of the output pin. When
a port C pin is programmed to be an input, reading the port C data register returns the logic state of the pin.
Address:
Read:
Write:
$0002
Bit 7
6
5
4
3
2
1
Bit 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Reset:
Unaffected by reset
Figure 7-13. Port C Data Register (PORTC)
PC7–PC0 — Port C Data Bits
These read/write bits are software programmable. Data direction of each bit is under the control of the
corresponding bit in the port C data direction register (DDRC). Reset has no effect on port C data.
7.4.2 Data Direction Register C
The contents of the port C data direction register (DDRC) determine whether each port C pin is an input
or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the associated port C pin. A
DDRC bit set to a logic 1 also disables the pulldown device for that pin. Writing a logic 0 to a DDRC bit
disables the output buffer for the associated port C pin. A reset initializes all DDRC bits to logic 0s,
configuring all port C pins as inputs.
Address:
Read:
Write:
Reset:
$0006
Bit 7
6
5
4
3
2
1
Bit 0
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
0
0
0
0
0
0
0
0
Figure 7-14. Data Direction Register C (DDRC)
DDRC7–DDRC0 — Port C Data Direction Bits
These read/write bits control port C data direction. Reset clears the DDRC7–DDRC0 bits.
1 = Corresponding port C pin configured as output and pulldown device disabled
0 = Corresponding port C pin configured as input
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
67
Parallel Input/Output
7.4.3 Port C Pulldown Devices
All port C pins can have software programmable pulldown devices enabled or disabled globally by the
SWPDI bit in the MOR. These pulldown devices are individually controlled by the write-only pulldown
register A (PDRA) shown in Figure 7-3. PDICH controls the upper four pins (PC7–PC4) and PDICL
controls the lower four pins (PC3–PC0). Clearing the PDICH or PDICL bits in the PDRA turns on the
pulldown devices if the port C pin is an input. Reading the PDRA returns undefined results since it is a
write-only register. Reset clears the PDICH and PDICL bits, which turns on all the port C pulldown
devices.
7.4.4 Port C Logic
Figure 7-15 shows the I/O logic of port C.
When a port C pin is programmed as an output, reading the port bit actually reads the value of the data
latch and not the voltage on the pin itself. When a port C pin is programmed as an input, reading the port
bit reads the voltage level on the pin. The data latch can always be written, regardless of the state of its
DDR bit. Table 7-4 summarizes the operations of the port C pins.
READ $0006
WRITE $0006
INTERNAL DATA BUS
R
DATA DIRECTION
REGISTER C
BIT DDRCx
PORT C DATA
REGISTER
BIT PCx
WRITE $0002
PCx
HIGH SINK/SOURCE
CURRENT CAPABILITY
READ $0002
WRITE $0010
PULLDOWN
DEVICE
SWPDI
R
RESET
PULLDOWN
REGISTER A
BIT PDICx
MASK OPTION REGISTER ($1FF1)
Figure 7-15. Port C I/O Circuit
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
68
Freescale Semiconductor
Port Transitions
Table 7-4. Port C Pin Functions (28-Pin Versions Only)
Control Bits
Port C
Pin(s)
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PORTC Access
(Pin or Data Register)
Port C
Result on
Port C Pins
SWPDI
in MOR
PDICH
PDICL
DDRCx(1)
Read
Write
Pulldown
Pin
0
X(2)
0
0
Pin
Data
On
PCx in
0
X(2)
1
0
Pin
Data
Off
PCx in
1
X
X(2)
0
Pin
Data
Off
PCx in
X(2)
X(2)
X(2)
1
Data
Data
Off
PCx out
0
0
X(2)
0
Pin
Data
On
PCx in
0
1
X(2)
0
Pin
Data
Off
PCx in
1
X
X(2)
0
Pin
Data
Off
PCx in
X(2)
X(2)
X(2)
1
Data
Data
Off
PCx out
1. DDRC can always be read or written.
2. Don’t care
7.5 Port Transitions
Glitches and temporary floating inputs can occur if the control bits regarding each port I/O pin are not
performed in the correct sequence.
• Do not use read-modify-write instructions on pulldown register A or B.
• Avoid glitches on port pins by writing to the port data register before changing data direction
register bits from a logic 0 to a logic 1.
• Avoid a floating port input by clearing its pulldown register bit before changing its data direction
register bit from a logic 1 to a logic 0.
• The SWPDI bit in the MOR turns off all port pulldown devices and disables software control of the
pulldown devices. Reset has no effect on the pulldown devices when the SWPDI bit is set.
• Two or more output pins of the same port can be connected electrically to provide output currents
up to the sum of the maximum specified drive currents as defined in 15.7 DC Electrical
Characteristics (5.0 Vdc) and 15.8 DC Electrical Characteristics (3.0 Vdc). Care must be taken to
ensure that all ganged pins always maintain the same output logic value.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
69
Parallel Input/Output
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
70
Freescale Semiconductor
Chapter 8
Analog Subsystem
8.1 Introduction
The analog subsystem of the MC68HC705JJ7/MC68HC705P7 is based on two on-chip voltage
comparators and a selectable current charge/discharge function as shown in Figure 8-1.
This configuration provides several features:
• Two independent voltage comparators with external access to both inverting and non-inverting
inputs
• One voltage comparator can be connected as a single-slope analog-to-digital (A/D) and the other
connected as a single-voltage comparator. The possible single-slope A/D connection provides
these features:
– A/D conversions can use VDD or an external voltage as a reference with software used to
calculate ratiometric or absolute results
– Channel access of up to four inputs via multiplexer control with independent multiplexer control
allowing mixed input connections
– Access to VDD and VSS for calibration
– Divide by 2 to extend input voltage range
– Each comparator can be inverted to calculate input offsets.
– Internal sample and hold capacitor
– Direct digital output of comparator 1 to the PB4 pin
Voltages are resolved by measuring the time it takes an external capacitor to charge up to the level of the
unknown input voltage being measured. The beginning of the A/D conversion time can be started by
several means:
• Output compare from the 16-bit programmable timer
• Timer overflow from the 16-bit programmable timer
• Direct software control via a register bit
The end of the A/D conversion time can be captured by these means:
• Input capture in the 16-bit programmable timer
• Interrupt generated by the comparator output
• Software polling of the comparator output using software loop time
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
71
2 TO 1
MUX
ICF
VDD
OCF
TOF
PB3/AN3/TCAP
TCAP
ICHG
PORTB
LOGIC
CHG
CHARGE
CURRENT
CONTROL
LOGIC
ATD1
ATD2
IDISCHG
VDD
ISEN
CP2EN
CP2EN
+
ICEN
COMP2
–
INTERNAL
TEMPERATURE
DIODE
CP1EN
INV
CPIE
CPF1
CMP2
CMP1
VOFF
MUX1
100 MV
OFFSET
–+
PB1
AN1
$001E
PB2
AN2
CP1EN
MUX2
PB4
AN4
TCMP
MUX4
VAOFF
VSS
–+
VSS
AVSS = VSS = VAOFF
OPT (COPR)
HOLD
COMP1
DHOLD
–
INV
VREF
INV
VREF
MUX4
MUX3
MUX2
OLVL
PORT B
CONTROL
LOGIC
COE1
OPT (COPR)
MUX1
MUX4
MUX3
MUX2
MUX1
ANALOG
MUX REGISTER
(AMUX)
MUX3
+
CHANNEL SELECT BUS
PB3
AN3
TCAP
INTERNAL HC05 BUS
SAMPLE
CAP
CPF2
ANALOG
STATUS REGISTER
(ASR)
80 kΩ
PORTB
LOGIC
COMPARATOR
INPUT SELECT AND
SAMPLE CONTROL
80 kΩ
VREF
PORTB
LOGIC
$001D
ANALOG
INTERRUPT
VDD
PORTB
LOGIC
ANALOG
CONTROL REGISTER
(ACR)
PB0
AN0
PORTB
LOGIC
16-BIT PROG.
TIMER
Analog Subsystem
$0003
DENOTES
INTERNAL
ANALOG VSS
Figure 8-1. Analog Subsystem Block Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
72
Freescale Semiconductor
Analog Multiplex Register
8.2 Analog Multiplex Register
The analog multiplex register (AMUX) controls the general interconnection and operation. The control bits
in the AMUX are shown in Figure 8-2.
Address:
Read:
Write:
Reset:
$0003
Bit 7
6
5
4
3
2
1
Bit 0
HOLD
DHOLD
INV
VREF
MUX4
MUX3
MUX2
MUX1
1
0
0
0
0
0
0
0
Figure 8-2. Analog Multiplex Register (AMUX)
HOLD, DHOLD
These read/write bits control the source connection to the negative input of voltage comparator 2
shown in Figure 8-3. This allows the voltage on the internal temperature sensing diode, the channel
selection bus, or the divide-by-two channel selection bus to charge the internal sample capacitor and
to also be presented to comparator 2. The decoding of these sources is given in Table 8-1.
During the hold case when both the HOLD and DHOLD bits are clear, the VOFF bit in the analog status
register (ASR) can offset the VSS reference on the sample capacitor by approximately 100 mV. This
offset source is bypassed whenever the sample capacitor is being charged with either the HOLD or
DHOLD bit set. The VOFF bit must be enabled by the OPT bit in the COPR at location $1FF0.
VDD
PB0
COMP2
–
INTERNAL
TEMPERATURE
DIODE
CHANNEL
SELECTION
BUS
+
80 kΩ
80 kΩ
SAMPLE
CAP
VOFF
VSS
OFFSET
–+
OPT (MOR)
HOLD
DHOLD
Figure 8-3. Comparator 2 Input Circuit
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
73
Analog Subsystem
Table 8-1. Comparator 2 Input Sources
Case
HOLD
(AMUX)
Hold
sample
voltage
0
Divide input
0
Direct input
Internal
temperature
diode
DHOLD
(AMUX)
OPT
(MOR)
VOFF
(ASR)
0
X(1)
Voltage
Offset
Source To Negative Input
of Comparator 2
No
Sample capacitor connected to
comparator 2 negative input; very low leakage
current.
1
0
1
1
Yes
Sample capacitor connected to comparator 2
negative input; bottom of capacitor offset from VSS
by approximately 100 mV, very low leakage current.
1
X(1)
X(1)
No
Signal on channel selection bus is divided
by 2 and connected to sample capacitor
and comparator 2 negative input
1
0
X(1)
X(1)
No
Signal on channel selection bus is connected
directly to sample capacitor and comparator 2
negative input.
1
1
X(1)
X(1)
No
Internal temperature sensing diode connected
directly to sample capacitor and comparator 2
negative input.
0
1. Don’t care
During a reset, the HOLD bit is set and the DHOLD bit is cleared, which connects the internal sample
capacitor to the channel selection bus. And since a reset also clears the MUX[1:4] bits, then the
channel selection bus will be connected to VSS and the internal sample capacitor will be discharged to
VSS following the reset.
NOTE
When sampling a voltage for later conversion, the HOLD and DHOLD bits
should be cleared before making any changes in the MUX channel
selection. If the MUX channel and the HOLD/DHOLD are changed on the
same write cycle to the AMUX register, the sampled voltage may be altered
during the channel switching.
INV
This is a read/write bit that controls the relative polarity of the inherent input offset voltage of the voltage
comparators. This bit allows voltage comparisons to be made with both polarities and then averaged
together by taking the sum of the two readings and then dividing by 2 (logical shift right).
The polarity of the input offset is reversed by interchanging the internal voltage comparator inputs while
also inverting the comparator output. This interchange does not alter the action of the voltage
comparator output with respect to its port pins. That is, the output will only go high if the voltage on the
positive input (PB2 pin for comparator 1 and PB0 pin for comparator 2) is above the voltage on the
respective negative input (PB3 pin for comparator 1 and PB1 pin for comparator 2). This is shown
schematically in Figure 8-4. This bit is cleared by a reset of the device.
1 = The voltage comparators are internally inverted.
0 = The voltage comparators are not internally inverted.
NOTE
The effect of changing the state of the INV bit is to only change the polarity
of the input offset voltage. It does not change the output phase of the CPF1
or CPF2 flags with respect to the external port pins.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
74
Freescale Semiconductor
Analog Multiplex Register
RISE
WHEN
V+ > V–
V+
VIO
RISE
WHEN
V+ > V–
V+
+
COMP
–
VIO
+
COMP
–
V–
V–
INV = 0
INV = 1
Figure 8-4. INV Bit Action
NOTE
Either comparator may generate an output flag when the inputs are
exchanged due to a change in the state of the INV bit. It is therefore
recommended that the INV bit not be changed while waiting for a
comparator flag. Further, any changes to the state of the INV bit should be
followed by writing a logic 1 to both the CPFR1 and CPFR2 bits to clear any
extraneous CPF1 or CPF2 flags that may have occurred.
VREF
This read/write bit connects the channel select bus to VDD for making a reference voltage
measurement. It cannot be selected if any of the other input sources to the channel select bus are
selected as shown in Table 8-2. This bit is cleared by a reset of the device.
1 = Channel select bus connected to VDD if all MUX1:4 are cleared.
0 = Channel select bus cannot be connected to VDD.
MUX1:4
These are read/write bits that connect the analog subsystem pins to the channel select bus and voltage
comparator 2 for purposes of making a voltage measurement. They can be selected individually or
combined with any of the other input sources to the channel select bus as shown in Table 8-2.
NOTE
The VAOFF voltage source shown in Figure 8-1 depicts a small offset
voltage generated by the total chip current passing through the package
bond wires and lead frame that are attached to the single VSS pin. This
offset raises the internal VSS reference (AVSS) in the analog subsystem
with respect to the external VSS pin. Turning on the VSS MUX to the channel
select bus connects it to this internal AVSS reference line.
When making A/D conversions, this AVSS offset gets placed on the external
ramping capacitor since the discharge device on the PB0/AN0 pin
discharges the external capacitor to the internal AVSS line. Under these
circumstances, the positive input (+) to comparator 2 will always be higher
than the negative input (–) until the negative input reaches the AVSS offset
voltage plus any offset in comparator 2.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
75
Analog Subsystem
Therefore, input voltages cannot be resolved if they are less than the sum
of the AVSS offset and the comparator offset, because they will always yield
a low output from the comparator.
Table 8-2. Channel Select Bus Combinations
Analog Multiplex Register
Channel Select Bus Connected to:
VREF
MUX4
MUX3
MUX2
MUX1
VDD
PB4/AN4/
TCMP
0
0
0
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
On
X(1)
0
0
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
On
Hi-Z
X(1)
0
0
1
0
Hi-Z
Hi-Z
Hi-Z
On
Hi-Z
Hi-Z
X(1)
0
0
1
1
Hi-Z
Hi-Z
Hi-Z
On
On
Hi-Z
(1)
X
0
1
0
0
Hi-Z
Hi-Z
On
Hi-Z
Hi-Z
Hi-Z
X(1)
0
1
0
1
Hi-Z
Hi-Z
On
Hi-Z
On
Hi-Z
X(1)
0
1
1
0
Hi-Z
Hi-Z
On
On
Hi-Z
Hi-Z
(1)
X
0
1
1
1
Hi-Z
Hi-Z
On
On
On
Hi-Z
X(1)
1
0
0
0
Hi-Z
On
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X(1)
1
0
0
1
Hi-Z
On
Hi-Z
Hi-Z
On
Hi-Z
X(1)
1
0
1
0
Hi-Z
On
Hi-Z
On
Hi-Z
Hi-Z
X(1)
1
0
1
1
Hi-Z
On
Hi-Z
On
On
Hi-Z
X(1)
1
1
0
0
Hi-Z
On
On
Hi-Z
Hi-Z
Hi-Z
X(1)
1
1
0
1
Hi-Z
On
On
Hi-Z
On
Hi-Z
X(1)
1
1
1
0
Hi-Z
On
On
On
Hi-Z
Hi-Z
(1)
1
1
1
1
Hi Z
On
On
On
On
Hi Z
X
PB3/AN3/
TCAP
PB2/AN2
PB1/AN1
VSS
1. Don/t care
8.3 Analog Control Register
The analog control register (ACR) controls the power-up, interrupt, and flag operation. The analog
subsystem draws current while it is operating. The resulting power consumption can be reduced
by powering down the analog subsystem when not in use (refer to 15.5 Supply Current Characteristics
(VDD = 4.5 to 5.5 Vdc)). This can be done by clearing three enable bits (ISEN, CP1EN, and CP2EN) in
the ACR at $001D. Since these bits are cleared following a reset, the voltage comparators and the charge
current source will be powered down following a reset of the device.
The control bits in the ACR are shown in Figure 8-5. All the bits in this register are cleared by a reset of
the device.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
76
Freescale Semiconductor
Analog Control Register
Address:
Read:
Write:
Reset:
$001D
Bit 7
6
5
4
3
2
1
Bit 0
CHG
ATD2
ATD1
ICEN
CPIE
CP2EN
CP1EN
ISEN
0
0
0
0
0
0
0
0
Figure 8-5. Analog Control Register (ACR)
CHG
The CHG enable bit allows direct control of the charge current source and the discharge device and
also reflects the state of the discharge device. This bit is cleared by a reset of the device.
1 = If the ISEN bit is also set, the charge current source is sourcing current out of the PB0/AN0 pin.
Writing a logic 1 enables the charging current out of the PB0/AN0 pin.
0 = The discharge device is sinking current into the PB0/AN0 pin. Writing a logic 0 disables the
charging current and enables the discharging current into the PB0/AN0 pin, if the ISEN bit is
also set.
ATD1–ATD2
The ATD1–ATD2 enable bits select one of the four operating modes used for making A/D conversions
via the single-slope method.These four modes are given in Table 8-3. These bits have no effect if the
ISEN enable bit is cleared. These bits are cleared by a reset of the device and thereby return the
analog subsystem to the manual A/D conversion method.
Table 8-3. A/D Conversion Options
A/D
Option
Mode
Charge
Control
Disabled
Current
source and
discharge
disabled
Automatic
charge and
discharge
(OCF–ICF)
synchronized
to timer
3
A/D Options
Current Flow
to/from PB0/AN0
ISEN
ATD2
ATD1
CHG
0
X
X
X
Current control disabled,
no source or sink current
1
0
0
1
Begin sourcing current
when the CHG bit is set
and continue to source
current until the CHG bit is
cleared.
1
1
0
1
The CHG bit remains set
until the next time ICF
occurs.
1
1
1
0
The CHG bit remains
cleared until the next time
OCF occurs.
1
1
1
1
The CHG bit remains set
until the next time ICF
occurs.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
77
Analog Subsystem
ICEN
This is a read/write bit that enables a voltage comparison to trigger the input capture register of the
programmable timer when the CPF2 flag bit is set. Therefore, an A/D conversion could be started by
receiving an OCF or TOF from the programmable timer and then terminated when the voltage on the
external ramping capacitor reaches the level of the unknown voltage. The time of termination will be
stored in the 16-bit buffer located at $0014 and $0015. This bit is automatically set whenever mode 2
or 3 is selected by setting the ATD2 control bit. This bit is cleared by a reset of the device.
1 = Connects the CPF2 flag bit to the timer input capture register
0 = Connects the PB3/AN3 pin to the timer input capture register
NOTE
For the input capture to occur when the output of comparator 2 goes high,
the IEDG bit in the TCR must also be set.
When the ICEN bit is set, the input capture function of the programmable
timer is not connected to the PB3/AN3/TCAP pin but is driven by the CPF2
output flag from comparator 2. To return to capturing times from external
events, the ICEN bit must first be cleared before the timed event occurs.
CPIE
This is a read/write bit that enables an analog interrupt when either of the CPF1 or CPF2 flag bits is
set to a logic 1. This bit is cleared by a reset of the device.
1 = Enables analog interrupts when comparator flag bits are set
0 = Disables analog interrupts when comparator flag bits are set
NOTE
If both the ICEN and CPIE bits are set, they will both generate an interrupt
by different paths. One will be the programmable timer interrupt due to the
input capture and the other will be the analog interrupt due to the output of
comparator 2 going high. In this case, the input capture interrupt will be
entered first due to its higher priority. The analog interrupt will then need to
be serviced even if the comparator 2 output has been reset or the input
capture flag (ICF) has been cleared.
CP2EN
The CP2EN enable bit controls power to voltage comparator 2 in the analog subsystem. Powering
down a comparator will drop the supply current. This bit is cleared by a reset of the device.
1 = Writing a logic 1 powers up voltage comparator 2.
0 = Writing a logic 0 powers down voltage comparator 2.
NOTE
Voltage comparators power up slower than digital logic and their outputs
may go through indeterminate states which might set their respective flags
(CPF1, CPF2). It is therefore recommended to power up the charge current
source first (ISEN), then to power up any comparators, and finally clear the
flag bits by writing a logic 1 to the respective CPFR1 or CPFR2 bits in the
ACR.
CP1EN
The CP1EN enable bit will power down the voltage comparator 1 in the analog subsystem. Powering
down a comparator will drop the supply current. This bit is cleared by a reset of the device.
1 = Writing a logic 1 powers up voltage comparator 1
0 = Writing a logic 0 powers down voltage comparator 1
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
78
Freescale Semiconductor
Analog Status Register
ISEN
The ISEN enable bit will power down the charge current source and disable the discharge device in
the analog subsystem. Powering down the current source will drop the supply current by about 200
µA. This bit is cleared by a reset of the device.
1 = Writing a logic 1 powers up the ramping current source and enables the discharge device on
the PB0/AN0 pin.
0 = Writing a logic 0 powers down the ramping current source and disables the discharge device on
the PB0/AN0 pin.
NOTE
The analog subsystem has support circuitry which draws current. This
current will be powered down if both comparators and the charge current
source are powered down (ISEN, CP1EN, and CP2EN all cleared).
Powering up either comparator or the charge current source will activate
the support circuitry.
8.4 Analog Status Register
The analog status register (ASR) contains status and control of the comparator flag bits. These bits in the
ASR are shown in Figure 8-6. All the bits in this register are cleared by a reset of the device.
Address:
Read:
$001E
Bit 7
6
5
4
CPF2
CPF1
0
0
CPFR2
CPFR1
0
0
Write:
Reset:
0
0
= Unimplemented
3
2
COE1
VOFF
0
R
0
1
Bit 0
CMP2
CMP1
R
0
0
= Reserved
Figure 8-6. Analog Status Register (ASR)
CPF2
This read-only flag bit is edge sensitive to the rising output of comparator 2. It is set when the voltage
on the PB0/AN0 pin rises above the voltage on a sample capacitor which creates a positive edge on
the output of comparator 2, regardless of the state of the INV bit in the AMUX register. This bit is reset
by writing a logic 1 to the CPFR2 reset bit in the ASR. This bit is cleared by a reset of the device.
1 = A positive transition on the output of comparator 2 has occurred since the last time the CPF2
flag has been cleared.
0 = A positive transition on the output of comparator 2 has not occurred since the last time the CPF2
flag has been cleared.
CPF1
This read-only flag bit is edge sensitive to the rising output of comparator 1. It is set when the voltage
on the PB2/AN2 pin rises above the voltage on the PN3/AN3/TCAP pin which creates a positive edge
on the output of comparator 1, regardless of the state of the INV bit in the AMUX register. This bit is
reset by writing a logic 1 to the CPFR1 reset bit in the ASR. This bit is cleared by a reset of the device.
1 = A positive transition on the output of comparator 1 has occurred since the last time the CPF1
flag has been cleared.
0 = A positive transition on the output of comparator 1 has not occurred since the last time the CPF1
flag has been cleared.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
79
Analog Subsystem
CPFR2
Writing a logic 1 to this write-only flag clears the CPF2 flag in the ASR. Writing a logic 0 to this bit has
no effect. Reading the CPFR2 bit will return a logic 0. By default, this bit looks cleared following a reset
of the device.
1 = Clears the CPF2 flag bit
0 = No effect
CPFR1
Writing a logic 1 to this write-only flag clears the CPF1 flag in the ASR. Writing a logic 0 to this bit has
no effect. Reading the CPFR1 bit will return a logic 0. By default, this bit looks cleared after a reset of
the device.
1 = Clears the CPF1 flag bit
0 = No effect
NOTE
The CPFR1 and CPFR2 bits should be written with logic 1s following a
power-up of either comparator. This will clear out any latched CPF1 or
CPF2 flag bits which might have been set during the slower power-up
sequence of the analog circuitry.
If both inputs to a comparator are above the maximum common-mode input
voltage (VDD –1.5 V), the output of the comparator is indeterminate and
may set the comparator flag. Applying a reset to the device may only
temporarily clear this flag as long as both inputs of a comparator remain
above the maximum common-mode input voltages.
VOFF
This read-write bit controls the addition of an offset voltage to the bottom of the sample capacitor. It is
not active unless the OPT bit in the COPR at location $1FF0 is set. Any reads of the VOFF bit location
return a logic 0 if the OPT bit is clear. During the time that the sample capacitor is connected to an
input (either HOLD or DHOLD set), the bottom of the sample capacitor is connected to VSS. The VOFF
bit is cleared by a reset of the device. For more information, see 8.10 Sample and Hold.
1 = Enables approximately 100 mV offset to be added to the sample voltage when both the HOLD
and DHOLD control bits are cleared
0 = Connects the bottom of the sample capacitor to VSS
COE1
This read-write bit controls the output of comparator 1 to the PB4 pin. It is not active unless the OPT
bit in the COPR at location $1FF0 is set. Any reads of the COE1 bit location return a logic 0 if the OPT
bit is clear. The COE1 bit is cleared by a reset of the device.
1 = Enables the output of comparator 1 to be ORed with the PB4 data bit and OLVL bit, if the DDRB4
bit is also set
0 = Disables the output of comparator 1 from affecting the PB4 pin
CMP2
This read-only bit shows the state of comparator 2 during the time that the bit is read. This bit is
therefore the current state of the comparator without any latched history. The CMP2 bit will be high if
the voltage on the PB0/AN0 pin is greater than the voltage on the PB1/AN1 pin, regardless of the state
of the INV bit in the AMUX register. Since a reset disables comparator 2, this bit returns a logic 0
following a reset of the device.
1 = The voltage on the positive input on comparator 2 is higher than the voltage on the negative
input of comparator 2.
0 = The voltage on the positive input on comparator 2 is lower than the voltage on the negative input
of comparator 2.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
80
Freescale Semiconductor
A/D Conversion Methods
CMP1
This read-only bit shows the state of comparator 1 during the time that the bit is read. This bit is
therefore the current state of the comparator without any latched history. The CMP1 bit will be high if
the voltage on the PB2/AN2 pin is greater than the voltage on the PB3/AN3/TCAP pin, regardless of
the state of the INV bit in the AMUX register. Since a reset disables comparator 1, this bit returns a
logic 0 following a reset of the device.
1 = The voltage on the positive input on comparator 1 is higher than the voltage on the negative
input of comparator 1.
0 = The voltage on the positive input on comparator 1 is lower than the voltage on the negative input
of comparator 1.
8.5 A/D Conversion Methods
The control bits in the ACR provide various options to charge or discharge current through the PB0/AN0
pin to perform single-slope A/D conversions using an external capacitor from the PB0/AN0 pin to VSS as
shown in Figure 8-7. The various A/D conversion triggering options are given in Table 8-3.
Charge Time =
C x VX
I
VDD –1.5 Vdc
UNKNOWN VOLTAGE ON (–) INPUT
VOLTAGE ON
CAPACITOR
CONNECTED
TO (+) INPUT
CHARGE TIME
TO MATCH UNKNOWN
DISCHARGE TIME
TO RESET CAPACITOR
MAXIMUM CHARGE TIME
TO VDD –1.5 Vdc
+5V
PB4/AN4
VDD
PB3/AN3
UNKNOWN
OR REFERENCE
SIGNALS
PB2/AN2
PB1/AN1
RAMP
CAP
PB0/AN0
MC68HC705JJ7
MC68HC705JP7
VSS
Figure 8-7. Single-Slope A/D Conversion Method
The top three bits of the ACR control the charging and discharging current into or out of the PB0/AN0 pin.
These three bits will have no effect on the PB0/AN0 pin if the ISEN enable bit is cleared. Any clearing of
the ISEN bit will immediately disable both the charge current source and the discharge device. Since all
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
81
Analog Subsystem
these bits and the ISEN bit are cleared when the device is reset, the MC68HC705JJ7/MC68HC705JP7
starts with the charge and discharge function disabled.
The length of time required to reach the maximum voltage to be measured and the speed of the time
counting mechanism will determine the resolution of the reading. The time to ramp the external capacitor
voltage to match the maximum voltage is dependent on:
• Charging current to external capacitor
• Value of the external capacitor
• Clock rate for timing function
• Any prescaling of the clock to the timing function
• Desired resolution
The charging behavior is described by the general equation:
tCHG = CEXT x VX / ICHG
Where:
tCHG= Charge time (seconds)
CEXT= Capacitance (µF)
VX= Unknown voltage (volts)
ICHG= Charge current (µA)
Since the MCU can measure time in a variety of ways, the resolution of the conversion will depend on the
length of the time keeping function and its prescaling to the oscillator frequency (fOSC). Therefore, the
charge time also equals:
tCHG = P x N / fOSC
Where:
P= Prescaler value (÷ 2, ÷ 4, ÷ 8, etc.)
N= Number of counts during charge time
fOSC= Oscillator clock frequency (Hz)
NOTE
Noise on the system ground or the external ramping capacitor can cause
the comparator to trip prematurely. Therefore, in any given application it is
best to use the fastest possible ramp rate (shortest charge time).
The previous two equations for the charge time, tCHG, can be combined to form the following expression
for the full scale count (NFS) of the measured time versus the full scale unknown voltage (VFS):
NFS = CEXT x VFS x fOSC / (P x ICHG)
Since a given timing method has a fixed charge current and prescaler, then the variation in the resultant
count for a given unknown voltage is mainly dependent on the operating frequency and the capacitance
value used. The desired external capacitance for a given voltage range, fOSC, conversion method, and
resolution is defined as:
CEXT = NFS x P x ICHG / (VFS x fOSC)
NOTE
The value of any capacitor connected directly to the PB0/AN0 pin should be
limited to less than 2 microfarads. Larger capacitances will create high
discharge currents which may damage the device or create signal noise.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
82
Freescale Semiconductor
A/D Conversion Methods
The full scale voltage range for a given capacitance, fOSC, conversion method, and resolution is defined
as:
VFS = NFS x P x ICHG / (CEXT x fOSC)
Once charged to a given voltage, a finite amount of time will be required to discharge the capacitor back
to its start voltage at VSS. This discharge time will be solely based on the value of capacitance used and
the sinking current of the internal discharge device. To allow a reasonable time for the capacitor to return
to VSS levels, the discharge time should last about 10 milliseconds per microfarad of capacitance
attached to the PB0 pin. If the total charge/discharge cycle time is critical, then the discharge time should
be at least 1/10 of the most recent charge time. Shorter discharge times may be used if lesser accuracy
in the voltage measurement is acceptable.
NOTE
Sufficient time should be allowed to discharge the external capacitor or
subsequent charge times will be shortened with resultant errors in timing
conversion.
Table 8-4 gives the range of values of each parameter in the A/D timing conversion and Table 8-5 gives
some A/D conversion examples for several bit resolutions.
The mode selection bits in the ACR allow four methods of single-slope A/D conversion. Each of these
methods is shown in Figure 8-8 through Figure 8-11 using the signal names and parameters given in
Table 8-4.
• Manual start and stop (mode 0) Figure 8-8
• Manual start and automatic discharge (mode 1) Figure 8-9
• Automatic start and stop from TOF to ICF (mode 2) Figure 8-10
• Automatic start and stop from OCF to ICF (mode 3) Figure 8-11
Table 8-4. A/D Conversion Parameters
Name
VX
Function
Unknown voltage on channel selection bus
Min
VSS
Typ
Units
—
Max
VDD –1.5
—
VDD –1.5
V
V
VMAX
Maximum charging voltage on external capacitor
ICHG
Charging current on external ramping capacitor
VDD = 3 Vdc
VDD = 5 Vdc
Refer to 15.9 Analog Subsystem Characteristics (5.0 Vdc) and
15.10 Analog Subsystem Characteristics (3.0 Vdc)
IDIS
Discharge current on external ramping capacitor
Refer to 15.9 Analog Subsystem Characteristics (5.0 Vdc) and
15.10 Analog Subsystem Characteristics (3.0 Vdc)
tCHG
Time to charge external capacitor
(100 kHz < fOSC < 4.0 MHz)
4-bit result
6-bit result
8-bit result
10-bit result
12-bit result
tDIS
Time to discharge external capacitor, CEXT
—
5
10
ms/µF
CEXT
Capacitance of external ramping capacitor
0.0001
0.1
2.0
µF
1
1024
65536
Counts
N
Number of counts for ICHG to charge CEXT to VX
—
0.032
0.128
0.512
2.048
8.192
0.128
0.512
2.048
8.196
32.768
2.56
10.24
40.96
120(1)
120(1)
ms
Continued on next page
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
83
Analog Subsystem
Table 8-4. A/D Conversion Parameters (Continued)
Name
P
fOSC
Function
Prescaler into timing function (÷ P)
Using core timer
Using 16-bit programmable timer
Using software loops
Clock source frequency (excluding any
prescaling)
Min
8
8
24
Typ
Max
8
8
8
8
User defined
User defined
Refer to 15.11 Control Timing (5.0 Vdc)
and 15.12 Control Timing (3.0 Vdc)
Units
÷P
1. Limited by requirement for CEXT to be less than 2.0 µF
Table 8-5. Sample Conversion Timing (VDD = 5.0 Vdc)
Bits
4
4
6
6
8
8
10
12
Counts
16
16
64
64
256
256
1024
4096
VX
(Vdc)
A/D Method
Clock Source
Low-power oscillator
3.5
Software loop
(12 bus cycles)
(24 fOSC cycles)
Mode 0 or 1 (manual)
3.5
Programmable timer
(prescaler = 8)
Mode 2 or 3
(TOF ≥ ICF or OCF ≥ ICF)
3.5
Software loop
(12 bus cycles)
(24 fOSC cycles)
Mode 0 or 1 (manual)
3.5
Programmable timer
(prescaler = 8)
Mode 2 or 3
(TOF ≥ CF or OCF ≥ ICF)
3.5
Software loop
(12 bus cycles)
(24 fOSC cycles)
Mode 0 or 1 (manual)
3.5
Programmable timer
(prescaler = 8)
Mode 2 or 3
(TOF ≥ CF or OCF ≥ ICF)
3.5
Programmable timer
(prescaler = 8)
Mode 2 or 3
(TOF ≥ ICF or OCF ≥ ICF)
3.5
Programmable timer
(prescaler = 8)
Mode 2 or 3
(TOF ≥ ICF or OCF ≥ ICF)
External pin oscillator
Low-power oscillator
External pin oscillator
Low-power oscillator
External pin oscillator
Low-power oscillator
External pin oscillator
Low-power oscillator
External pin oscillator
Low-power oscillator
External pin oscillator
Low-power oscillator
External pin oscillator
Low-power oscillator
External pin oscillator
fOSC
(MHz)
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
0.1
1.0
2.0
4.0
tCHG
(ms)
3.840
0.384
0.192
0.096
1.280
0.128
0.064
0.032
15.36
1.536
0.768
0.384
5.120
0.512
0.256
0.128
61.44
6.144
3.072
1.536
20.48
2.048
1.024
0.512
Note 1
8.192
4.096
2.048
Note 1
32.768
16.384
8.192
CEXT (µF)
0.110
0.011
0.006
0.003
0.037
0.004
0.002
0.001
0.439
0.044
0.022
0.011
0.585
0.059
0.029
0.015
1.755
0.176
0.088
0.044
0.585
0.059
0.029
0.015
Note 1
0.234
0.117
0.059
Note 1
0.936
0.468
0.234
1. Not usable as the value of CEXT would be greater than 2.0 µF
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
84
Freescale Semiconductor
A/D Conversion Methods
tDIS
tDIS
tDIS
tMAX
(MIN)
(MIN)
VCAP
VMAX
tCHG
VX
VX =
tCHG x ICHG
CEXT
CHG
COMP2
TOF
OCF
ICF
0
2
3
4
5
1
1
Point
Action
0
Begin initial discharge and select mode 0 by
clearing the CHG, ATD2, and ATD1 control bits
in the ACR.
Software/Hardware Action
Dependent Variable(s)
Software write
Software
1
VCAP falls to VSS.
Wait out minimum tDIS time.
VMAX, IDIS, CEXT
2
Stop discharge and begin charge by setting
CHG control bit in ACR.
Software write
Software
3
VCAP rises to VX and comparator 2 output trips,
setting CPF2 and CMP2.
Wait out tCHG time.
VX, ICHG, CEXT
4
VCAP reaches VMAX.
None
VMAX, ICHG, CEXT
5
Begin next discharge by clearing the CHG
control bit in the ACR. Reset CPF2 by writing a
1 to CPFR2.
Software write
Software
Figure 8-8. A/D Conversion — Full Manual Control (Mode 0)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
85
Analog Subsystem
tDIS
tDIS
tDIS
(MIN)
(MIN)
VCAP
VMAX
tCHG
VX
VX =
tCHG x ICHG
CEXT
CHG
COMP2
TOF
OCF
ICF
0
1
2
3
1
Software/Hardware Action
2
Point
Action
0
Begin initial discharge and select mode
1 by clearing CHG and ATD2 and setting
ATD1 in the ACR.
Dependent Variable(s)
Software write
Software
1
VCAP falls to VSS.
Wait out minimum tDIS time.
VMAX, IDIS, CEXT
2
Stop discharge and begin charge by
setting CHG control bit in ACR.
Software write
Software
3
VCAP rises to VX and comparator 2
output trips, setting CPF2 and CMP2,
which clears CHG control bit in the ACR.
Reset CPF2 by writing a 1 to CPFR2.
Wait out tCHG time.
CPF2 clears CHG control bit.
VX, ICHG, CEXT
Figure 8-9. A/D Conversion — Manual/Auto Discharge Control (Mode 1)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
86
Freescale Semiconductor
A/D Conversion Methods
tDIS
tDIS
tDIS
(MIN)
(MIN)
VCAP
VMAX
tCHG
VX
VX =
tCHG x ICHG
CEXT
CHG
COMP2
(TCAP)
TOF
OCF
ICF
0
1
2
3
1
Software/Hardware Action
2
Point
Action
Dependent Variable(s)
0
Begin initial discharge and select mode 2 by
clearing CHG and ATD1 and setting ATD2 in
the ACR. Also set ICEN bit in ACR and IEDG
bit in TCR.
Software write
Software
1
VCAP falls to VSS.
Wait out minimum tDIS time.
VMAX, IDIS, CEXT
2
Stop discharge and begin charge when the
next TOF sets the CHG control bit in ACR.
Timer TOF sets the CHG control bit in
the ACR.
Free-running timer counter
overflow, fOSC
3
VCAP rises to VX and comparator 2 output
trips, setting CPF2 and CMP2, which causes
an ICF from the timer and clears the CHG
control bit in ACR. Must clear CPF2 to trap
next CPF2 flag.
Wait out tCHG time.
Timer ICF clears the CHG control bit
in the ACR.
VX, ICHG, CEXT
Figure 8-10. A/D Conversion — TOF/ICF Control (Mode 2)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
87
Analog Subsystem
tDIS
tDIS
tDIS
(MIN)
(MIN)
VCAP
VMAX
tCHG
VX
VX =
tCHG x ICHG
CEXT
CHG
COMP2
(TCAP)
TOF
OCF
ICF
0
1
2
3
1
2
Point
Action
Software/Hardware Action
Dependent Variable(s)
0
Begin initial discharge and select mode 3 by
clearing CHG and setting ATD2 and ATD1 in
the ACR. Also set ICEN bit in ACR and IEDG
bit in TCR.
Software write
Software
1
VCAP falls to VSS. Set timer output compare
registers (OCRH and OCRL) to desired
charge start time.
Wait out minimum tDIS time.
Software write to OCRH, OCRL
VMAX, IDIS, CEXT, software
2
Stop discharge and begin charge when the
next OCF sets the CHG control bit in ACR.
Timer OCF sets the CHG control bit
in the ACR.
Free-running timer
output compare, fOSC
3
VCAP rises to VX and comparator 2 output
trips, setting CPF2 and CMP2, which causes
an ICF from the timer and clears the CHG
control bit in ACR. Must clear CPF2 to trap
next CPF2 flag. Load next OCF.
Wait out tCHG time.
Timer ICF clears the CHG control bit
in the ACR.
VX, ICHG, CEXT
Figure 8-11. A/D Conversion — OCF/ICF Control (Mode 3)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
88
Freescale Semiconductor
Voltage Measurement Methods
8.6 Voltage Measurement Methods
The methods for obtaining a voltage measurement can use software techniques to express these
voltages as absolute or ratiometric readings.
In most applications the external capacitor, the clock source, the reference voltage, and the charging
current may vary between devices and with changes in supply voltage or ambient temperature. All of
these variations must be considered when determining the desired resolution of the measurement. The
maximum and minimum extremes for the full scale count will be:
NFSMIN = CEXTMIN x VFSMIN x fOSCMIN / (P x ICHGMAX)
NFSMAX = CEXTMAX x VFSMAX x fOSCMAX / (P x ICHGMIN)
The minimum count should be the desired resolution, and the counting mechanism must be capable of
counting to the maximum. The final scaling of the count will be by a math routine which calculates:
VX = VREF x (NX – NOFF) / (NREF – NOFF)
Where:
VREF = Known reference voltage
VX
= Unknown voltage between VSS and VREF
NX
= Conversion count for unknown voltage
NREF = Conversion count for known reference voltage (VREF)
NOFF = Conversion count for minimum reference voltage (VSS)
When VREF is a stable voltage source such as a zener or other reference source, then the unknown
voltage will be determined as an absolute reading. If VREF is the supply source to the device (VDD), then
the unknown voltage will be determined as a ratio of VDD, or a ratiometric reading.
If the unknown voltage applied to the comparator is greater than its common-mode range (VDD –1.5 volts),
then the external capacitor will try to charge to the same level. This will cause both comparator inputs to
be above the common-mode range and the output of the comparator will be indeterminate. In this case
the comparator output flags may also be set even if the actual voltage on the positive input (+) is less than
the voltage on the negative input (–). All A/D conversion methods should have a maximum time check to
determine if this case is occurring.
Once the maximum timeout detection has been made, the state of the comparator outputs can be tested
to determine the situation. However, such tests should be carefully designed when using modes 1, 2, or
3 as these modes cause the immediate automatic discharge of the external ramping capacitor before any
software check can be made of the output state of comparator 2.
NOTE
All A/D conversion methods should include a test for a maximum elapsed
time to detect error cases where the inputs may be outside of the design
specification.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
89
Analog Subsystem
8.6.1 Absolute Voltage Readings
The absolute value of a voltage measurement can be calculated in software by first taking a reference
reading from a fixed source and then comparing subsequent unknown voltages to that reading as a
percentage of the reference voltage multiplied times the known reference value.
The accuracy of absolute readings will depend on the error sources taken into account using the features
of the analog subsystem and appropriate software as described in Table 8-6. As can be seen from this
table, most of the errors can be reduced by frequent comparisons to a known voltage, use of the inverted
comparator inputs, and averaging of multiple samples.
8.6.1.1 Internal Absolute Reference
If a stable source of VDD is provided, the reference measurement point can be internally selected. In this
case, the reference reading can be taken by setting the VREF bit and clearing the MUX1:4 bits in the
AMUX register. This connects the channel selection bus to the VDD pin. To stay within the VMAX range,
the DHOLD bit should be used to select the 1/2 divided input.
8.6.1.2 External Absolute Reference
If a stable external source is provided, the reference measurement point can be any one of the channel
selected pins from PB1–PB4. In this case the reference reading can be taken by setting the MUX bit in
the AMUX which connects channel selection bus to the pin connected to the external reference source.
If the external reference is greater than VDD –1.5 volts, then the DHOLD bit should be used to select the
1/2 divided input.
Table 8-6. Absolute Voltage Reading Errors
Accuracy Improvements Possible
Error Source
In Hardware
In Software
Change in reference voltage Provide closer tolerance reference
Calibration and storage of reference source over
temperature and supply voltage
Change in magnitude of
ramp current source
Not adjustable
Compare unknown with recent measurement
from reference
Non-linearity of ramp
current source vs. voltage
Not adjustable
Calibration and storage of voltages at 1/4, 1/2,
3/4, and FS
Frequency shift in internal
low-power oscillator
Use external oscillator with crystal
Compare unknown with recent measurement
from reference
Sampling capacitor leakage
Use faster conversion times
Compare unknown with recent measurement
from reference
Internal voltage divider ratio
Not adjustable
Compare unknown with recent measurement
from reference OR avoid use of divided input
Input offset voltage of
comparator 2
Not adjustable
Sum two readings on reference or unknown
using INV and INV control bit and divide by 2
(average of both)
Noise internal to MCU
Close decoupling at VDD and VSS pins and
reduce supply source impedance
Average multiple readings on both the reference
and the unknown voltage
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
90
Freescale Semiconductor
Voltage Measurement Methods
8.6.2 Ratiometric Voltage Readings
The ratiometric value of a voltage measurement can be calculated in software by first taking a reference
reading from a reference source and then comparing subsequent unknown voltages to that reading as a
percentage of the reference value. The accuracy of ratiometric readings will depend on the variety of
sources, but will generally be better than for absolute readings. Many of these error sources can be
taken into account using the features of the analog subsystem and appropriate software as described in
Table 8-7. As with absolute measurements, most of the errors can be reduced by frequent comparisons
to the reference voltage, use of the inverted comparator inputs, and averaging of multiple samples.
Table 8-7. Ratiometric Voltage Reading Errors
Accuracy Improvements Possible
Error Source
In Hardware
In Software
Change in reference voltage
Not required for ratiometric
Compare unknown with recent measurement
from reference
Change in magnitude of ramp
current source
Not adjustable
Compare unknown with recent measurement
from reference
Non-linearity of ramp current
source vs. voltage
Not adjustable
Calibration and storage of voltages at 1/4,
1/2, 3/4, and FS
Frequency shift in internal
low-power oscillator
Not required for ratiometric
Compare unknown with recent measurement
from reference
Sampling capacitor leakage
Use faster conversion times
Compare unknown with recent measurement
from reference
Internal voltage divider ratio
Not adjustable
Compare unknown with recent measurement
from reference
Input offset voltage of
comparator 2
Not adjustable
Sum two readings on reference or unknown
using INV and INV control bit and divide by 2
(average of both)
Noise internal to MCU
Close decoupling at VDD and VSS pins and
reduce supply source impedance
Average multiple readings on both the
reference and the unknown voltage
8.6.2.1 Internal Ratiometric Reference
If readings are to be ratiometric to VDD, the reference measurement point can be internally selected. In
this case the reference reading can be taken by setting the VREF bit and clearing the MUX1:4 bits in the
AMUX register which connects the channel selection bus to the VDD pin. In order to stay within the VMAX
range, the DHOLD bit should be used to select the 1/2 divided input.
8.6.2.2 External Ratiometric Reference
If readings are to be ratiometric to some external source, the reference measurement point can be
connected to any one of the channel selected pins from PB1–PB4. In this case, the reference reading can
be taken by setting the MUX bit in the AMUX which connects channel selection bus to the pin connected
to the external reference source. If the external reference is greater than VDD –1.5 volts, then the DHOLD
bit should be used to select the 1/2 divided input.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
91
Analog Subsystem
8.7 Voltage Comparator Features
The two internal comparators can be used as simple voltage comparators if set up as described in
Table 8-8. Both comparators can be active in the wait mode and can directly restart the part by means of
the analog interrupt. Both comparators can also be active in the stop mode, but cannot directly restart the
part. However, the comparators can directly drive PB4 which can then be connected externally to activate
either a port interrupt on the PA0:3 pins or the IRQ/VPP pin.
Table 8-8. Voltage Comparator Setup Conditions
Comparator
Current
Source
Enable
Discharge
Device
Disable
Port B Pin
as Inputs
Port B Pin
Pulldowns
Disabled
Prog. Timer Input
Capture
Source
1
Not
affected
Not
affected
DDRB2 = 0
DDRB3 = 0
PDIB2 = 1
PDIB3 = 1
Not
affected
2
ISEN = 0
ISEN = 0
DDRB0 = 0
DDRB1 = 0
PDIB0 = 1
PDIB1 = 1
ICEN = 0
IEDG = 1
8.7.1 Voltage Comparator 1
Voltage comparator 1 is always connected to two of the port B I/O pins. These pins should be configured
as inputs and have their software programmable pulldowns disabled. Also, the negative input of voltage
comparator 1 is connected to the PB3/AN3/TCAP and shared with the input capture function of the 16-bit
programmable timer. Therefore, the timer input capture interrupt should be disabled so that changes in
the voltage on the PB3/AN3/TCAP pin do not cause unwanted input capture interrupts.
The output of comparator 1 can be connected to the port logic driving the PB4/AN4/TCMP/CMP1 pin such
that the output of the comparator is ORed with the PB4 data bit and the OLVL bit from the 16-bit timer.
This capability requires that the OPT bit is set in the COPR at location $1FF0 as in Figure 8-12, and the
COE1 bit is set in the ASR at location $001E.
Address:
Read:
Write:
Reset:
$1FF0
Bit 7
6
EPMSEC
OPT
U
U
5
4
3
2
1
Bit 0
COPC
U
= Unimplemented
U
U
U
U
U
U = Unaffected
Figure 8-12. COP and Security Register (COPR)
OPT — Optional Features Bit
The OPT bit enables two additional features: direct drive by comparator 1 output to PB4 and voltage
offset capability to sample capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
92
Freescale Semiconductor
Current Source Features
8.7.2 Voltage Comparator 2
Voltage comparator 2 can be used as a simple comparator if its charge current source and discharge
device are disabled by clearing the ISEN bit in the ACR. If the ISEN bit is set, the internal ramp discharge
device connected to PB0/AN0 may become active and try to pull down any voltage source that may be
connected to that pin. Also, since voltage comparator 2 is always connected to two of the port B I/O pins,
these pins should be configured as inputs and have their software programmable pulldowns disabled.
8.8 Current Source Features
The internal current source connected to the PB0/AN0 pin supplies about 100 µA of current when the
discharge device is disabled and the current source is active. Therefore, this current source can be used
in an application if the ISEN enable bit is set to power up the current source and by setting the A/D
conversion method to manual mode 0 (ATD1 and ATD2 cleared) and the charge current enabled (CHG
set).
8.9 Internal Temperature Sensing Diode Features
An internal diode is forward biased to VSS and will have its voltage change, VD, for each degree
centigrade rise in the temperature of the device. This temperature sensing diode is powered up from a
current source only during the time that the diode is selected. When on, this current source typically adds
about 30 µA to the IDD current.
The temperature sensing diode can be selected by setting both the HOLD and DHOLD bits in the AMUX
register (see 8.2 Analog Multiplex Register).
8.10 Sample and Hold
When using the internal sample capacitor to capture a voltage for later conversion, the HOLD or DHOLD
bit must be cleared first before changing any channel selection. If both the HOLD (or DHOLD) bit and the
channel selection are changed on the same write cycle, the sample may be corrupted during the switching
transitions.
NOTE
The sample capacitor can be affected by excessive noise created with
respect to the device’s VSS pin such that it may appear to leak down or
charge up depending on the voltage level stored on the sample capacitor.
It is recommended to avoid switching large currents through the port pins
while a voltage is to remain stored on the sample capacitor.
The additional option of adding an offset voltage to the bottom of the sample capacitor allows unknown
voltages near VSS to be sampled and then shifted up past the comparator offset and the device offset
caused by a single VSS return pin. This offset also provides a means to measure the internal VSS level
regardless of the comparator offset to determine NOFF as described in 8.6 Voltage Measurement
Methods. In either case the OPT bit must be set in the COPR located at $1FF0 as in Figure 8-12 and the
VOFF bit must be set in the ASR. It is not necessary to switch the VOFF bit during conversions, since the
offset is controlled by the HOLD and DHOLD bits when the VOFF is active. Refer to 8.2 Analog Multiplex
Register for more details on the design and decoding of the sample and hold circuit.
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Analog Subsystem
8.11 Port B Interaction with Analog Inputs
The analog subsystem is connected directly to the port B I/O pins without any intervening gates. It is,
therefore, possible to measure the voltages on port B pins set as inputs or to have the analog voltage
measurements corrupted by port B pins set as outputs.
8.12 Port B Pins as Inputs
All the port B pins will power up as inputs or return to inputs after a reset of the device since the bits in the
port B data direction register will be reset.
If any port B pins are to be used for analog voltage measurements, they should be left as inputs. In this
case, not only can the voltage on the pin be measured, but the logic state of the port B pins can be read
from location $0002.
8.13 Port B Pulldowns
All the port B pins have internal software programmable pulldown devices available dependent on the
state of the SWPDI bit in the mask option register (MOR).
If the pulldowns are enabled, they will create an approximate 100 µA load to any analog source connected
to the pin. In some cases, the analog source may be able to supply this current without causing any error
due to the analog source output impedance. Since this may not always be true, it is therefore best to
disable port B pulldowns on those pins used for analog input sources.
8.14 Noise Sensitivity
In addition to the normal effects of electrical noise on the analog input signal there can also be other
noise-related effects caused by the digital-to-analog interface. Since there is only one VSS return for both
the digital and the analog subsystems on the device, currents in the digital section may affect the analog
ground reference within the device. This can add voltage offsets to measured inputs or cause
channel-to-channel crosstalk.
To reduce the impact of these effects, there should be no switching of heavy I/O currents to or from the
device while there is a critical analog conversion or voltage comparison in process. Limiting switched I/O
currents to 2–4 mA during these times is recommended.
A noise reduction benefit can be gained with 0.1-µF bypass capacitors from each analog input (PB4:1) to
the VSS pin. Also, try to keep all the digital power supply or load currents from passing through any
conductors which are the return paths for an analog signal.
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Freescale Semiconductor
Chapter 9
Simple Synchronous Serial Interface
9.1 Introduction
The simple synchronous serial I/O port (SIOP) subsystem is designed to provide efficient serial
communications with peripheral devices or other MCUs. SIOP is implemented as a 3-wire master/slave
system with serial clock (SCK), serial data input (SDI), and serial data output (SDO). A block diagram of
the SIOP is shown in Figure 9-1.
PORTB LOGIC
OSCILLATOR
CLOCK
÷2
SPR0
SIOP
CONTROL REGISTER
(SCR)
SPR1
CLOCK
DIVIDER
AND
SELECT
CLOCK
CONTROL
PB7
SCK
CPHA
PORTB LOGIC
MSTR
SPE
LSBF
PB6
SDI
SPIR
SPIE
PORTB LOGIC
LATCH
SIOP
INTERRUPT
Q
SPIF
S
DIN
CLK
DOUT
8-BIT SHIFT
REGISTER
COMP
PB5
SDO
ERROR
R
D4
D5
D6
D7
D0
D1
D2
D3
DCOL
FORMAT CONTROL
(LSB OR MSB FIRST)
SDR0
SDR1
SDR2
SDR3
SDR4
SDR5
SDR6
SDR7
SIOP
STATUS REGISTER
(SSR)
INTERNAL M68HC05 BUS
$000A
$000B
SIOP
DATA REGISTER
(SDR)
$000C
INTERNAL M68HC05 BUS
Figure 9-1. SIOP Block Diagram
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Simple Synchronous Serial Interface
The SIOP subsystem shares its input/output pins with port B. When the SIOP is enabled (SPE bit set in
the SCR), the port B data direction and data registers are bypassed by the SIOP. The port B data direction
and data registers will remain accessible and can be altered by the application software, but these actions
will not affect the SIOP transmitted or received data.
9.2 SIOP Signal Format
The SIOP subsystem can be software configured for master or slave operation. No external mode
selection inputs are available (for instance, no slave select pin).
9.2.1 Serial Clock (SCK)
The state of the SCK output remains a fixed logic level during idle periods between data transfers. The
edges of SCK indicate the beginning of each output data transfer and latch any incoming data received.
The first bit of transmitted data is output from the SDO pin on the first falling edge of SCK. The first bit of
received data is accepted at the SDI pin on the first rising edge of SCK after the first falling edge. The
transfer is terminated upon the eighth rising edge of SCK.
The idle state of the SCK is determined by the state of the CPHA bit in the SCR. When the CPHA is clear,
SCK will remain idle at a logic 1 as shown in Figure 9-2. When the CPHA is set, SCK will remain idle at
a logic 0 as shown in Figure 9-3. In both cases, the SDO changes data on the falling edge of the SCK,
and the SDI latches data in on the rising edge of SCK.
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
SDO
SCK
(CPHA = 0)
(IDLE = 1)
100 ns
100 ns
SDI
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
Figure 9-2. SIOP Timing Diagram (CPHA = 0)
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
SDO
SCK
(CPHA = 1)
(IDLE = 0)
100 ns
100 ns
SDI
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
Figure 9-3. SIOP Timing Diagram (CPHA = 1)
The only difference in the master and slave modes of operation is the sourcing of the SCK. In master
mode, SCK is driven from an internal source within the MCU. In slave mode, SCK is driven from a source
external to the MCU. The SCK frequency is based on one of four divisions of the oscillator clock that is
selected by the SPR0 and SPR1 bits in the SCR.
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Freescale Semiconductor
SIOP Registers
9.2.2 Serial Data Input (SDI)
The SDI pin becomes an input as soon as the SIOP subsystem is enabled. New data is presented to the
SDI pin on the falling edge of SCK. Valid data must be present at least 100 nanoseconds before the rising
edge of SCK and remain valid for 100 nanoseconds after the rising edge of SCK. See Figure 9-3.
9.2.3 Serial Data Output (SDO)
The SDO pin becomes an output as soon as the SIOP subsystem is enabled. The state of the PB5/SDO
pin reflects the value of the first bit received on the previous transmission. Prior to enabling the SIOP, the
PB5/SDO can be initialized to determine the beginning state. While SIOP is enabled, the port B logic
cannot be used as a standard output since that pin is connected to the last stage of the SIOP serial shift
register. A control bit (LSBF) is included in the SCR to allow the data to be transmitted in either the MSB
first format or the LSB first format.
The first data bit will be shifted out to the SDO pin on the first falling edge of the SCK. The remaining data
bits will be shifted out to the SDI pin on subsequent falling edges of SCK. The SDO pin will present valid
data at least 100 nanoseconds before the rising edge of the SCK and remain valid for 100 nanoseconds
after the rising edge of SCK. See Figure 9-3.
9.3 SIOP Registers
The SIOP is programmed and controlled by the SIOP control register (SCR) located at address $000A,
the SIOP status register (SSR) located at address $000B, and the SIOP data register (SDR) located at
address $000C.
9.3.1 SIOP Control Register (SCR)
The SIOP control register (SCR) is located at address $000A and contains seven control bits and a
write-only reset of the interrupt flag. Figure 9-4 shows the position of each bit in the register and indicates
the value of each bit after reset.
Address:
Read:
Write:
Reset:
$000A
Bit 7
6
5
4
SPIE
SPE
LSBF
MSTR
0
0
0
0
3
0
SPIR
0
2
1
Bit 0
CPHA
SPR1
SPR0
0
0
0
Figure 9-4. SIOP Control Register (SCR)
SPIE — Serial Peripheral Interrupt Enable Bit
The SPIE bit enables the SIOP to generate an interrupt whenever the SPIF flag bit in the SSR is set.
Clearing the SPIE bit will not affect the state of the SPIF flag bit and will not terminate a serial interrupt
once the interrupt sequence has started. Reset clears the SPIE bit.
1 = Serial interrupt enabled
0 = Serial interrupt disabled
NOTE
If the SPIE bit is cleared just after the serial interrupt sequence has started
(for instance, the CPU status is being stacked), then the CPU will be unable
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Simple Synchronous Serial Interface
to determine the source of the interrupt and will vector to the reset vector
as a default.
SPE — Serial Peripheral Enable Bit
The SPE bit switches the port B interface such that SDO/PB5 is the serial data output, SDI/PB6 is the
serial data input, and SCK/PB7 is a serial clock input in the slave mode or a serial clock output in the
master mode. The port B DDR and data registers can be manipulated as usual, but these actions will
not affect the transmitted or received data. The SPE bit is readable and writable at any time, but
clearing the SPE bit while a transmission is in progress will 1) abort the transmission, 2) reset the serial
bit counter, and 3) convert port B to a general-purpose I/O port. Reset clears the SPE bit.
1 = Serial peripheral enabled (port B I/O disabled)
0 = Serial peripheral disabled (port B I/O enabled)
LSBF — Least Significant Bit First Bit
The LSBF bit controls the format of the transmitted and received data to be transferred LSB or MSB
first. Reset clears this bit.
1 = LSB transferred first
0 = MSB transferred first
MSTR — Master Mode Select Bit
The MSTR bit configures the serial I/O port for master mode. A transfer is initiated by writing to the
SDR. Also, the SCK pin becomes an output providing a synchronous data clock dependent upon the
divider of the oscillator frequency selected by the SPR0:1 bits. When the device is in master mode, the
SDO and SDI pins do not change function. These pins behave exactly the same in both the master
and slave modes. The MSTR bit is readable and writable at any time regardless of the state of the SPE
bit. Clearing the MSTR bit will abort any transfers that may have been in progress. Reset clears the
MSTR bit, placing the SIOP subsystem in slave mode.
1 = SIOP set up as master, SCK is an output
0 = SIOP set up as slave, SCK is an input
SPIR — Serial Peripheral Interrupt Reset Bit
The SPIR bit is a write-only control to reset the SPIF flag bit in the SSR. Reading the SPIR bit will return
a logic 0.
1 = Reset the SPIF flag bit
0 = No effect
CPHA — Clock Phase Bit
The CPHA bit controls the clock timing and phase in the SIOP. Data is changed on the falling edge of
SCK and data is captured (read) on the rising edge of SCK. This bit is cleared by reset.
1 = SCK is idle low
0 = SCK is idle high
SPR0:1 — Serial Peripheral Clock Rate Select Bits
The SPR0 and SPR1 bits select one of four clock rates given in Table 9-1 to be supplied on the
PB7/SCK pin when the device is configured with the SIOP as a master (MSTR = 1). The fastest rate
is when both SPR0 and SPR1 are set. Both the SPR0 and SPR1 bits are cleared by reset, which
places the SIOP clock selection at the slowest rate.
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Freescale Semiconductor
SIOP Registers
Table 9-1. SIOP Clock Rate Selection
SPR1
SPR0
SIOP Clock Rate
Oscillator Frequency
Divided by:
0
0
64
0
1
32
1
0
16
1
1
8
9.3.2 SIOP Status Register
The SIOP status register (SSR) is located at address $000B and contains two read-only bits. Figure 9-5
shows the position of each bit in the register and indicates the value of each bit after reset.
Address:
Read:
$000B
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
DCOL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 9-5. SIOP Status Register (SSR)
SPIF — Serial Port Interrupt Flag
The SPIF is a read-only status bit that is set on the last rising edge of SCK and indicates that a data
transfer has been completed. It has no effect on any future data transfers and can be ignored. The
SPIF bit can be cleared by reading the SSR followed by a read or write of the SDR or by writing a logic
1 to the SPIR bit in the SCR. If the SPIF is cleared before the last rising edge of SCK it will be set again
on the last rising edge of SCK. Reset clears the SPIF bit.
1 = Serial transfer complete, serial interrupt if the SPIE bit in SCR is set
0 = Serial transfer in progress or serial interface idle
DCOL — Data Collision Bit
The DCOL is a read-only status bit which indicates that an illegal access of the SDR has occurred. The
DCOL bit will be set when reading or writing the SDR after the first falling edge of SCK and before SPIF
is set. Reading or writing the SDR during this time will result in invalid data being transmitted or
received. The DCOL bit is cleared by reading the SSR (when the SPIF bit is set) followed by a read or
write of the SDR. If the last part of the clearing sequence is
done after another transfer has started, the DCOL bit will be set again. Reset clears the DCOL bit.
1 = Illegal access of the SDR occurred
0 = No illegal access of the SDR detected
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
99
Simple Synchronous Serial Interface
9.3.3 SIOP Data Register
The SIOP data register (SDR) is located at address $000C and serves as both the transmit and receive
data register. Writing to this register will initiate a message transmission if the node is in master mode.
The SIOP subsystem is not double buffered and any write to this register will destroy the previous
contents. The SDR can be read at any time. However, if a transfer is in progress the results may be
ambiguous. Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted
and/or received. Figure 9-6 shows the position of each bit in the register. This register is not affected by
reset.
Address:
Read:
Write:
Reset:
$000C
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Unaffected by reset
Figure 9-6. SIOP Data Register (SDR)
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Freescale Semiconductor
Chapter 10
Core Timer
10.1 Introduction
This section describes the operation of the core timer and the computer operating properly (COP)
watchdog as shown by the block diagram in Figure 10-1.
RESET
INTERNAL
CLOCK
OVERFLOW
$0009
÷4
CORE TIMER COUNTER REGISTER
÷2
BITS 0–7 OF 15-STAGE
RIPPLE COUNTER
OSC1
INTERNAL CLOCK ÷ 1024
RTIFR
RTIE
CTOFR
RTIF
CTOFE
CTOF
INTERNAL DATA BUS
CORE TIMER
INTERRUPT
REQUEST
$0008
RESET
RT0
RT1
CORE TIMER STATUS/CONTROL REGISTER
RTI RATE SELECT
$1FF0
COPR REGISTER
÷2
÷2
÷2
÷2
COPC
÷2
÷2
÷2
POWER-ON
RESET
÷2
÷2
÷2
÷2
COP
WATCHDOG
RESET
RESET
Figure 10-1. Core Timer Block Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
101
Core Timer
10.2 Core Timer Status and Control Register
The read/write core timer status and control register (CTSCR) contains the interrupt flag bits, interrupt
enable bits, interrupt flag bit resets, and the rate selects for the real-time interrupt as shown in Figure 10-2.
Address:
Read:
Write:
Reset:
$0008
Bit 7
CTOF
0
6
RTIF
5
4
CTOFE
RTIE
0
0
= Unimplemented
0
3
0
CTOFR
0
2
0
RTIFR
0
1
Bit 0
RT1
RT0
1
1
Figure 10-2. Core Timer Status and Control Register (CTSCR)
CTOF — Core Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the core timer counter roll over from $FF
to $00. The CTOF flag bit generates a timer overflow interrupt request if CTOFE is also set. The CTOF
flag bit is cleared by writing a logic 1 to the CTOFR bit. Writing to CTOF has no effect. Reset clears
CTOF.
1 = Overflow in core timer has occurred.
0 = No overflow of core timer since CTOF last cleared
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected real-time interrupt (RTI) output becomes active.
RTIF generates a real-time interrupt request if RTIE is also set. The RTIF enable bit is cleared by
writing a logic 1 to the RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF.
1 = Overflow in real-time counter has occurred.
0 = No overflow of real-time counter since RTIF last cleared
CTOFE — Core Timer Overflow Interrupt Enable Bit
This read/write bit enables core timer overflow interrupts. Reset clears CTOFE.
1 = Core timer overflow interrupts enabled
0 = Core timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
CTOFR — Core Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the CTOF bit. CTOFR always reads as a logic 0. Reset
does not affect CTOFR.
1 = Clear CTOF flag bit
0 = No effect on CTOF flag bit
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR always reads as a logic 0. Reset does
not affect RTIFR.
1 = Clear RTIF flag bit
0 = No effect on RTIF flag bit
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select one of four real-time interrupt rates, as shown in Table 10-1. Because the
selected RTI output drives the COP watchdog, changing the real -time interrupt rate also changes the
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Freescale Semiconductor
Core Timer Counter Register
counting rate of the COP watchdog. Reset sets RT1 and RT0, selecting the longest COP timeout
period and longest real-time interrupt period.
NOTE
Changing RT1 and RT0 when a COP timeout is imminent or uncertain may
cause a real-time interrupt request to be missed or an additional real-time
interrupt request to be generated. Clear the COP timer just before changing
RT1 and RT0.
Table 10-1. Core Timer Interrupt Rates and COP Timeout Selection
Timer Overflow
Interrupt Period
TOF = 1/(fOSC ÷ 211)
(Microseconds)
@ fOSC (MHz)
4.2
MHz
2.0
MHz
RT1
RT0
1.0
MHz
1024
2048
COP Timeout Period
COP = 7-to-8 RTI Periods
(Milliseconds)
@ fOSC (MHz)
@ fOSC (MHz)
4.2
MHz
2.0
MHz
1.0
MHz
4.2 MHz
Min
Max
2.0 MHz
Min
Max
1.0 MHz
Min
Max
0
215
7.80
16.4
32.8
54.6
62.4
115
131
229
262
1
216
15.6
32.8
65.5
109
125
229
262
459
524
1
0
217
31.2
65.5
131
218
250
459
524
918
1049
1
1
218
62.4
131
262
437
499
918
1049
1835
2097
0
488
RTI
Rate
= fOSC
divided
by:
Real-Time
Interrupt Period
(RTI)
(Milliseconds)
0
10.3 Core Timer Counter Register
A 15-stage ripple counter driven by a divide-by-eight prescaler is the basis of the core timer. The value of
the first eight stages is readable at any time from the read-only timer counter register as shown in
Figure 10-3.
Address:
Read:
Write:
Reset:
$0009
Bit 7
Bit 7
0
6
6
5
5
0
0
= Unimplemented
4
4
3
3
2
2
1
1
Bit 0
Bit 0
0
0
0
0
0
Figure 10-3. Core Timer Counter Register (CTCR)
Power-on clears the entire counter chain and begins clocking the counter. After the startup delay (16 or
4064 internal bus cycles depending on the DELAY bit in the mask option register (MOR)), the power-on
reset circuit is released, clearing the counter again and allowing the MCU to come out of reset.
Each count of the timer counter register takes eight oscillator cycles or four cycles of the internal bus. A
timer overflow function at the eighth counter stage allows a timer interrupt every 2048 oscillator clock
cycles or every 1024 internal bus cycles.
10.4 COP Watchdog
Four counter stages at the end of the core timer make up the computer operating properly (COP)
watchdog which can be enabled by the COPEN bit in the MOR. The COP watchdog is a software error
detection system that automatically times out and resets the MCU if the COP watchdog is not cleared
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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103
Core Timer
periodically by a program sequence. Writing a logic 0 to COPC bit in the COPR register clears the COP
watchdog and prevents a COP reset.
Address:
Read:
Write:
Reset:
$1FF0
Bit 7
EPMSEC
6
5
4
3
2
1
Bit 0
OPT
COPC
Unaffected by reset
= Unimplemented
Figure 10-4. COP and Security Register (COPR)
EPMSEC — EPROM Security((1)) Bit
The EPMSEC bit is a write-only security bit to protect the contents of the user EPROM code stored in
locations $0700–$1FFF.
OPT — Optional Features Bit
The OPT bit enables two additional features: direct drive by comparator outputs to port A and voltage
offset capability to sample capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. The COP watchdog is active in the run, wait, and halt
modes of operation if the COP is enabled by setting the COPEN bit in the MOR. The STOP instruction
disables the COP watchdog by clearing the counter and turning off its clock source.
In applications that depend on the COP watchdog, the STOP instruction can be disabled by setting the
SWAIT bit in the MOR. In applications that have wait cycles longer than the COP timeout period, the
COP watchdog can be disabled by clearing the COPEN bit. Table 10-2 summarizes recommended
conditions for enabling and disabling the COP watchdog.
NOTE
If the voltage on the IRQ/VPP pin exceeds 1.5 × VDD, the COP watchdog
turns off and remains off until the IRQ/VPP pin voltage falls below
1.5 × VDD.
Table 10-2. COP Watchdog Recommendations
SWAIT
(in MOR)(1)
Wait/Halt Time
Recommended COP
Watchdog Condition
Less than 1.5 × VDD
1
Less than COP
timeout period
Enabled(2)
Less than 1.5 × VDD
1
Greater than COP
timeout period
Disabled
Less than 1.5 × VDD
0
X(3)
Disabled
More than 1.5 × VDD
X
X(3)
Disabled
Voltage on
IRQ/VPP Pin
1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions.
2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
3. Don’t care
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
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104
Freescale Semiconductor
Chapter 11
Programmable Timer
11.1 Introduction
The MC68HC705JJ7/MC68HC705JP7 MCU contains a 16-bit programmable timer with an input capture
function and an output compare function as shown by the block diagram in Figure 11-1.
The basis of the capture/compare timer is a 16-bit free-running counter which increases in count with
every four internal bus clock cycles. The counter is the timing reference for the input capture and output
compare functions. The input capture and output compare functions provide a means to latch the times
at which external events occur, to measure input waveforms, and to generate output waveforms and
timing delays. Software can read the value in the 16-bit free-running counter at any time without affecting
the counter sequence.
The input/output (I/O) registers for the input capture and output compare functions are pairs of 8-bit
registers, because of the 16-bit timer architecture used. Each register pair contains the high and low bytes
of that function. Generally, accessing the low byte of a specific timer function allows full control of that
function; however, an access of the high byte inhibits that specific timer function until the low byte is also
accessed.
Because the counter is 16 bits long and preceded by a fixed divide-by-four prescaler, the counter rolls
over every 262,144 internal clock cycles (every 524,288 oscillator clock cycles). Timer resolution with a
4-MHz crystal oscillator is 2 microseconds/count.
The interrupt capability, the input capture edge, and the output compare state are controlled by the timer
control register (TCR) located at $0012, and the status of the interrupt flags can be read from the timer
status register (TSR) located at $0013.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
105
Programmable Timer
PB3
AN3
TCAP
EDGE
SELECT
& DETECT
LOGIC
ICRH ($0014)
ICRL ($0015)
TMRH ($0018)
TMRL ($0019)
ICF
INPUT
SELECT
MUX
ACRH ($001A)
ACRL ($001B)
IEDG
CPF2
FLAG
BIT
FROM
ANALOG
SUBSYSTEM
÷4
16-BIT COUNTER
ICEN
CONTROL
BIT
INTERNAL
CLOCK
(OSC ÷ 2)
OVERFLOW (TOF)
16-BIT COMPARATOR
D Q
OCRL ($0017)
OLVL
C
OCF
OCRH ($0016)
PB4
AN4
TCMP
PIN I/O
LOGIC
ANALOG
COMP 1
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
$0012
TOF
OCF
ICF
OLVL
IEDG
TOIE
OCIE
ICIE
RESET
TIMER STATUS REGISTER
$0013
INTERNAL DATA BUS
Figure 11-1. Programmable Timer Overall Block Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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Freescale Semiconductor
Timer Registers
11.2 Timer Registers
The functional block diagram of the 16-bit free-running timer counter and timer registers is shown in
Figure 11-2. The timer registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
LATCH
READ
TMRH
READ
RESET
$FFFC
READ
TMRL
TMRL ($0019)
TMRH ($0018)
TMR LSB
INTERNAL
CLOCK
(OSC ÷ 2)
÷4
16-BIT COUNTER
TIMER
INTERRUPT
REQUEST
TOF
TOIE
OVERFLOW (TOF)
TIMER CONTROL REG.
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 11-2. Programmable Timer Block Diagram
The timer registers (TMRH and TMRL) shown in Figure 11-3 are read-only locations which contain the
current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect.
Reset of the device presets the timer counter to $FFFC.
The TMRL latch is a transparent read of the LSB until a read of the TMRH takes place. A read of the
TMRH latches the LSB into the TMRL location until the TMRL is again read. The latched value remains
fixed even if multiple reads of the TMRH take place before the next read of the TMRL. Therefore, when
reading the MSB of the timer at TMRH, the LSB of the timer at TMRL must also be read to complete the
read sequence.
During power-on reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator
startup delay. Because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Address:
Read:
Write:
Reset:
Address:
Read:
Write:
Reset:
$0018
Bit 7
Bit 15
1
$0018
Bit 7
Bit 7
1
6
14
5
13
4
12
3
11
2
10
1
9
Bit 0
Bit 8
1
1
1
1
1
1
1
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
1
1
= Unimplemented
1
1
1
0
0
Figure 11-3. Programmable Timer Registers (TMRH and TMRL)
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
107
Programmable Timer
When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) is set in
the TSR. When the TOF is set, it can generate an interrupt if the timer overflow interrupt enable bit (TOIE)
is also set in the TCR. The TOF flag bit can only be reset by reading the TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and TMRL in any order or any number of
times does not have any effect on the 16-bit free-running counter.
NOTE
To prevent interrupts from occurring between readings of the TMRH and
TMRL, set the I bit in the condition code register (CCR) before reading
TMRH and clear the I bit after reading TMRL.
11.3 Alternate Counter Registers
The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is
shown in Figure 11-4. The alternate counter registers behave the same as the timer registers, except that
any reads of the alternate counter will not have any effect on the TOF flag bit and timer interrupts. The
alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
INTERNAL
DATA
BUS
LATCH
READ
ACRH
READ
RESET
$FFFC
READ
ACRL
ACRL ($001B)
ACRH ($001A)
TMR LSB
INTERNAL
CLOCK
(OSC ÷ 2)
÷4
16-BIT COUNTER
Figure 11-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH and ACRL) shown in Figure 11-5 are read-only locations which
contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter
registers has no effect. Reset of the device presets the timer counter to $FFFC.
Address:
Read:
Write:
Reset:
Address:
Read:
Write:
Reset:
$001A
Bit 7
Bit 15
1
$001B
Bit 7
Bit 7
1
6
14
5
13
4
12
3
11
2
10
1
9
Bit 0
Bit 8
1
1
1
1
1
1
1
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
1
1
= Unimplemented
1
1
1
0
0
Figure 11-5. Alternate Counter Registers (ACRH and ACRL)
The ACRL latch is a transparent read of the LSB until a read of the ACRH takes place. A read of the ACRH
latches the LSB into the ACRL location until the ACRL is again read. The latched value remains fixed even
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
108
Freescale Semiconductor
Input Capture Registers
if multiple reads of the ACRH take place before the next read of the ACRL. Therefore, when reading the
MSB of the timer at ACRH, the LSB of the timer at ACRL must also be read to complete the read
sequence.
During power-on reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator
startup delay. Because the counter is 16 bits and preceded by a fixed prescaler, the value in the counter
repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles).
Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit
free-running counter or the TOF flag bit.
NOTE
To prevent interrupts from occurring between readings of the ACRH and
ACRL, set the I bit in the condition code register (CCR) before reading
ACRH and clear the I bit after reading ACRL.
11.4 Input Capture Registers
The input capture function is a means to record the time at which an event occurs. The source of the event
can be the change on an external pin (PB3/AN3/TCAP) or the CPF2 flag bit of voltage comparator 2 in
the analog subsystem. The ICEN bit in the analog subsystem control register (ACR) at $001D selects
which source is the input signal. When the input capture circuitry detects an active edge on the selected
source, it latches the contents of the free-running timer counter registers into the input capture registers
as shown in Figure 11-6.
NOTE
Both the ICEN bit in the ACR and the IEDG bit in the TCR must be set when
using voltage comparator 2 to trigger the input capture function.
INTERNAL
DATA
BUS
READ
ICRH
RESET
ICRH ($0014)
16-BIT COUNTER
READ
ICRL
INTERNAL
CLOCK
(OSC ÷ 2)
÷4
INPUT CAPTURE (ICF)
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REG.
$0012
ICRL ($0015)
ICF
LATCH
IEDG
ICEN
CONTROL
BIT
ICIE
CPF2
FLAG
BIT
FROM
ANALOG
SUBSYSTEM
EDGE
SELECT
& DETECT
LOGIC
IEDG
INPUT
SELECT
MUX
$FFFC
PB3
AN3
TCAP
TIMER STATUS REG.
$0013
INTERNAL
DATA
BUS
Figure 11-6. Timer Input Capture Block Diagram
Latching values into the input capture registers at successive edges of the same polarity measures the
period of the selected input signal. Latching the counter values at successive edges of opposite polarity
measures the pulse width of the signal.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
109
Programmable Timer
The input capture registers are made up of two 8-bit read-only registers (ICRH and ICRL) as shown in
Figure 11-7. The input capture edge detector contains a Schmitt trigger to improve noise immunity. The
edge that triggers the counter transfer is defined by the input edge bit (IEDG) in the TCR. Reset does not
affect the contents of the input capture registers.
Address:
Read:
Write:
Reset:
Address:
Read:
Write:
Reset:
$0014
Bit 7
Bit 15
6
14
5
13
4
12
3
11
2
10
1
9
Bit 0
Bit 8
2
2
1
1
Bit 0
Bit 0
Unaffected by reset
$0015
Bit 7
Bit 7
6
6
5
5
4
4
3
3
Unaffected by reset
= Unimplemented
Figure 11-7. Input Capture Registers (ICRH and ICRL)
The result obtained by an input capture will be one count higher than the value of the free-running timer
counter preceding the external transition. This delay is required for internal synchronization. Resolution
is affected by the prescaler, allowing the free-running timer counter to increment once every four internal
clock cycles (eight oscillator clock cycles).
Reading the ICRH inhibits future captures until the ICRL is also read. Reading the ICRL after reading the
timer status register (TSR) clears the ICF flag bit. There is no conflict between reading the ICRL and
transfers from the free-running timer counters. The input capture registers always contain the free-running
timer counter value which corresponds to the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICRH and
ICRL, set the I bit in the condition code register (CCR) before reading ICRH
and clear the I bit after reading ICRL.
11.5 Output Compare Registers
The output compare function is a means of generating an output signal when the 16-bit timer counter
reaches a selected value as shown in Figure 11-8. Software writes the selected value into the output
compare registers. On every fourth internal clock cycle (every eight oscillator clock cycles) the output
compare circuitry compares the value of the free-running timer counter to the value written in the output
compare registers. When a match occurs, the timer transfers the output level (OLVL) from the timer
control register (TCR) to the PB4/AN4/TCMP pin.
Software can use the output compare register to measure time periods, to generate timing delays, or to
generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the
PB4/AN4/TCMP pin.
The planned action on the PB4/AN4/TCMP pin depends on the value stored in the OLVL bit in the TCR,
and it occurs when the value of the 16-bit free-running timer counter matches the value in the output
compare registers shown in Figure 11-9. These registers are read/write bits and are unaffected by reset.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
110
Freescale Semiconductor
Output Compare Registers
R/W
OCRH
R/W
OCRL
OCRL ($0017)
OCRH ($0016)
EDGE
SELECT
DETECT
LOGIC
OLVL
16-BIT COMPARATOR
$FFFC
÷4
16-BIT COUNTER
RESET
INTERNAL
CLOCK
(OSC ÷ 2)
TIMER
INTERRUPT
REQUEST
OCF
OCIE
OLVL
OUTPUT COMPARE
(OCF)
PB4
AN4
TCMP
TIMER CONTROL REG.
TIMER STATUS REG.
$0012
$0013
INTERNAL
DATA
BUS
Figure 11-8. Timer Output Compare Block Diagram
Address:
Read:
Write:
Reset:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Unaffected by reset
Address:
Read:
Write:
Reset:
$0017
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
Unaffected by reset
Figure 11-9. Output Compare Registers (OCRH and OCRL)
Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written.
Reading or writing to the OCRL after reading the TCR will clear the output compare flag bit (OCF). The
output compare OLVL state will be clocked to its output latch regardless of the state of the OCF.
To prevent OCF from being set between the time it is read and the time the output compare registers are
updated, use this procedure:
1. Disable interrupts by setting the I bit in the condition code register.
2. Write to the OCRH. Compares are now inhibited until OCRL is written.
3. Read the TSR to arm the OCF for clearing.
4. Enable the output compare registers by writing to the OCRL. This also clears the OCF flag bit in
the TSR.
5. Enable interrupts by clearing the I bit in the condition code register.
A software example of this procedure is shown in Table 11-1.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
111
Programmable Timer
Table 11-1. Output Compare Initialization Example
9B
...
...
B7
B6
BF
...
...
9A
SEI
...
...
STA
LDA
STX
...
...
CLI
16
13
17
OCRH
TSR
OCRL
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
11.6 Timer Control Register
The timer control register (TCR) shown in Figure 11-10, performs the following functions:
• Enables input capture interrupts
• Enables output compare interrupts
• Enables timer overflow interrupts
• Controls the active edge polarity of the TCAP signal
• Controls the active level of the TCMP output
Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected.
Address:
Read:
Write:
Reset:
$0012
Bit 7
6
5
ICIE
OCIE
TOIE
0
0
0
= Unimplemented
4
3
2
0
0
0
0
0
0
1
Bit 0
IEDG
OLVL
U
0
U = Unaffected
Figure 11-10. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on the TCAP pin or from CPF2 flag
bit of the analog subsystem voltage comparator 2. Reset clears the ICIE bit.
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
OCIE — Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active match of the output compare function. Reset
clears the OCIE bit.
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
TOIE — Timer Overflow Interrupt Enable
This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
112
Freescale Semiconductor
Timer Status Register
IEDG — Input Capture Edge Select
The state of this read/write bit determines whether a positive or negative transition triggers a transfer
of the contents of the timer register to the input capture register. This transfer can occur due to
transitions on the TCAP pin or the CPF2 flag bit of voltage comparator 2. Resets have no effect on the
IEDG bit.
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
NOTE
The IEDG bit must be set when either mode 2 or 3 of the analog subsystem
is being used for A/D conversions. Otherwise, the input capture will not
occur on the rising edge of the comparator 2 flag.
OLVL — Output Compare Output Level Select
The state of this read/write bit determines whether a logic 1 or a logic 0 is transferred to the TCMP pin
when a successful output compare occurs. Reset clears the OLVL bit.
1 = Signal to TCMP pin goes high on output compare.
0 = Signal to TCMP pin goes low on output compare.
11.7 Timer Status Register
The timer status register (TSR) shown in Figure 11-11 contains flags for these events:
• An active signal on the TCAP pin or the CPF2 flag bit of voltage comparator 2 in the analog
subsystem, transferring the contents of the timer registers to the input capture registers
• A match between the 16-bit counter and the output compare registers, transferring the OLVL bit to
the PB4/AN4/TCMP pin if that pin is set as an output
• An overflow of the timer registers from $FFFF to $0000
Writing to any of the bits in the TSR has no effect. Reset does not change the state of any of the flag bits
in the TSR.
Address:
Read:
$0013
Bit 7
6
5
4
3
2
1
Bit 0
ICF
OCF
TOF
0
0
0
0
0
U
U
0
0
0
0
0
Write:
Reset:
U
= Unimplemented
U = Unaffected
Figure 11-11. Timer Status Register (TSR)
ICF — Input Capture Flag
The ICF bit is automatically set when an edge of the selected polarity occurs on the TCAP pin. Clear
the ICF bit by reading the timer status register with the ICF set, and then reading the low byte (ICRL,
$0015) of the input capture registers. Resets have no effect on ICF.
OCF — Output Compare Flag
The OCF bit is automatically set when the value of the timer registers matches the contents of the
output compare registers. Clear the OCF bit by reading the timer status register with the OCF set and
then accessing the low byte (OCRL, $0017) of the output compare registers. Resets have no effect on
OCF.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
113
Programmable Timer
TOF — Timer Overflow Flag
The TOF bit is automatically set when the 16-bit timer counter rolls over from $FFFF to $0000. Clear
the TOF bit by reading the timer status register with the TOF set and then accessing the low byte
(TMRL, $0019) of the timer registers. Resets have no effect on TOF.
11.8 Timer Operation during Wait Mode
During wait mode, the 16-bit timer continues to operate normally and may generate an interrupt to trigger
the MCU out of wait mode.
11.9 Timer Operation during Stop Mode
When the MCU enters stop mode, the free-running counter stops counting (the internal processor clock
is stopped). It remains at that particular count value until stop mode is exited by applying a low signal to
the IRQ/VPP pin, at which time the counter resumes from its stopped value as if nothing had happened.
If stop mode is exited via an external reset (logic low applied to the RESET pin), the counter is forced to
$FFFC.
If a valid input capture edge occurs during stop mode, the input capture detect circuitry will be armed. This
action does not set any flags or wake up the MCU, but when the MCU does wake up there will be an active
input capture flag (and data) from the first valid edge. If the stop mode is exited by an external reset, no
input capture flag or data will be present even if a valid input capture edge was detected during stop mode.
11.10 Timer Operation during Halt Mode
When the MCU enters halt mode, the functions and states of the 16-bit programmable timer are the same
as for wait mode described in 11.8 Timer Operation during Wait Mode.
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Freescale Semiconductor
Chapter 12
Personality EPROM (PEPROM)
12.1 Introduction
This section describes how to program the 64-bit personality erasable programmable read-only memory
(PEPROM). Figure 12-1 shows the structure of the PEPROM subsystem.
NOTE
In packages with no quartz window, the PEPROM functions as one-time
programmable ROM (OTPROM).
INTERNAL DATA BUS
$000F
RESET
PEPRZF
0
0
0
0
0
PEPGM
SINGLE
SENSE
AMPLIFIER
PEDATA
PEPROM STATUS/CONTROL REGISTER
VPP
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
COL 7
COL 6
COL 5
COL 4
COL 3
COL 2
COL 1
COL 0
ROW 7
8-TO-1 ROW DECODER
AND MULTIPLEXER
PEPROM BIT SELECT REGISTER
$000E
INTERNAL DATA BUS
VPP SWITCH
ROW ZERO
DECODER
PEB0
PEB1
PEB2
PEB3
PEB4
PEB5
0
0
8-TO-1 COLUMN DECODER
AND MULTIPLEXER
VPP SWITCH
RESET
Figure 12-1. Personality EPROM Block Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
115
Personality EPROM (PEPROM)
12.2 PEPROM Registers
Two I/O registers control programming and reading of the PEPROM:
• The PEPROM bit select register (PEBSR)
• The PEPROM status and control register (PESCR)
12.2.1 PEPROM Bit Select Register
The PEPROM bit select register (PEBSR) selects one of 64 bits in the PEPROM array. Reset clears all
the bits in the PEPROM bit select register.
Address:
Read:
Write:
Reset:
$000E
Bit 7
6
5
4
3
2
1
Bit 0
PEB7
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
0
0
0
0
0
0
0
0
Figure 12-2. PEPROM Bit Select Register (PEBSR)
PEB7 and PEB6 — Not connected to the PEPROM array
These read/write bits are available as storage locations. Reset clears PEB7 and PEB6.
PEB5–PEB0 — PEPROM Bit Selects
These read/write bits select one of 64 bits in the PEPROM as shown in Table 12-1. Bits PEB2–0 select
the PEPROM row, and bits PEB5–PEB3 select the PEPROM column. Reset clears PEB5–PEB0,
selecting the PEPROM bit in row zero, column zero.
12.2.2 PEPROM Status and Control Register
The PEPROM status and control register (PESCR) controls the PEPROM programming voltage. This
register also transfers the PEPROM bits to the internal data bus and contains a flag bit when row zero is
selected.
Address:
Read:
$000F
Bit 7
6
PEDATA
0
Write:
Reset:
U
0
5
PEPGM
0
= Unimplemented
4
3
2
1
Bit 0
0
0
0
0
PEPRZF
R
R
R
0
0
0
R
= Reserved
0
1
U = Unaffected
Figure 12-3. PEPROM Status and Control Register (PESCR)
PEDATA — PEPROM Data Bit
This read-only bit is the output state of the PEPROM sense amplifier and shows the state of the
currently selected bit. The state of the PEDATA bit does not affect the programming of the bit selected
by the PEBSR. Reset does not affect the PEDATA bit.
1 = PEPROM data is a logic 1.
0 = PEPROM data is a logic 0.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
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Freescale Semiconductor
PEPROM Programming
PEPGM — PEPROM Program Control Bit
This read/write bit controls the switches that apply the programming voltage from the IRQ/VPP pin to
the selected PEPROM bit cell. When the PEPGM bit is set, the selected bit cell will be programmed to
a logic 1, regardless of the state of the PEDATA bit. Reset clears the PEPGM bit.
1 = Programming voltage applied to array bit
0 = Programming voltage not applied to array bit
PEPRZF — PEPROM Row Zero Flag
This read-only bit is set when the PEPROM bit select register selects the first row (row zero) of the
PEPROM array. Selecting any other row clears PEPRZF. Monitoring PEPRZF can reduce the code
needed to access one byte of eight PEPROM locations. Reset clears the PEPROM bit select register,
thereby setting the PEPRZF bit by default.
1 = Row zero selected
0 = Row zero not selected
Table 12-1. PEPROM Bit Selection
PEBSR
$00
$01
|
V
$07
$08
$09
|
V
$37
$38
$39
|
V
$3E
$3F
PEPROM Bit Selected
Row 0
Column 0
Row 1
Column 0
|
|
V
V
Row 7
Column 0
Row 0
Column 1
Row 1
Column 1
|
|
V
V
Row 7
Column 6
Row 0
Column 7
Row 1
Column 7
|
|
V
V
Row 6
Column 7
Row 7
Column 7
12.3 PEPROM Programming
Factory-provided software for programming the PEPROM is available on the World Wide Web at:
http://www.freescale.com
NOTE
While the PEPGM bit is set and the VPP voltage level is applied to the
IRQ/VPP pin, do not access bits that are to be left unprogrammed (erased).
To program the PEPROM bits properly, the VDD voltage must be greater
than 4.5 Vdc.
The PEPROM can also be programmed by user software with the VPP voltage level applied to the
IRQ/VPP pin. This sequence shows how to program each PEPROM bit:
1. Select a PEPROM bit by writing to the PEBSR.
2. Set the PEPGM bit in the PESCR.
3. Wait for the programming time, tEPGM.
4. Clear the PEPGM bit.
5. Move to next PEPROM bit to be programmed in step 1.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
117
Personality EPROM (PEPROM)
12.4 PEPROM Reading
This sequence shows how to read the PEPROM:
1. Select a bit by writing to the PEBSR.
2. Read the PEDATA bit in the PESCR.
3. Store the PEDATA bit in RAM or in a register.
4. Select another bit by changing the PEBSR.
5. Continue reading and storing the PEDATA bits until the required personality EPROM data is
retrieved and stored.
Reading the PEPROM is easiest when each PEPROM column contains one byte. Selecting a row 0 bit
selects the first bit, and incrementing the PEPROM bit select register (PEBSR) selects the next bit in row
1 from the same column. Incrementing PEBSR seven more times selects the remaining bits of the column
and ends up selecting the bit in row 0 of the next column, thereby setting the row 0 flag, PEPRZF.
NOTE
A PEPROM byte that has been read can be transferred to the personality
EPROM bit select register (PEBSR) as a temporary storage location such
that subsequent reads of the PEBSR quickly yield that PEPROM byte.
12.5 PEPROM Erasing
MCUs with windowed packages permit PEPROM erasing with ultraviolet light. Erase the PEPROM by
exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet
light source 1 inch from the window. Do not use a shortwave filter. The erased state of a PEPROM bit is
a logic 0.
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Chapter 13
EPROM/OTPROM
13.1 Introduction
This section describes how to program the 6160-byte erasable programmable read-only
memory/one-time programmable read-only memory (EPROM/OTPROM), the mask option register
(MOR), and the EPROM security bit (EPMSEC).
NOTE
In packages with no quartz window, the EPROM functions as one-time
programmable ROM (OTPROM).
13.2 EPROM Registers
The EPROM programming register (EPROG) controls the actual programming of the EPROM bytes and
the mask option register (MOR). The MOR controls eight mask options found on the read-only memory
(ROM) version of this microcontroller unit (MCU). There is an additional EPROM bit (EPMSEC) located
at the computer operating properly (COP) address to provide EPROM array security.
13.2.1 EPROM Programming Register
The EPROM programming register (EPROG) shown in Figure 13-1 contains the control bits for
programming the EPROM. In normal operation, the EPROM programming register contains all logic 0s.
Address:
Read:
$001C
Bit 7
6
5
4
3
0
0
0
0
0
R
R
R
R
0
0
0
Write:
Reset:
0
= Unimplemented
0
R
2
1
Bit 0
ELAT
MPGM
EPGM
0
0
0
= Reserved for test
Figure 13-1. EPROM Programming Register (EPROG)
EPGM — EPROM Programming Bit
This read/write bit applies the voltage from the IRQ/VPP pin to the EPROM. To write the EPGM bit, the
ELAT bit must already be set. Clearing the ELAT bit also clears the EPGM bit. Reset clears EPGM.
1 = EPROM programming power switched on
0 = EPROM programming power switched off
MPGM — Mask Option Register (MOR) Programming Bit
This read/write bit applies programming power from the IRQ/VPP pin to the MOR. Reset clears MPGM.
1 = MOR programming power switched on
0 = MOR programming power switched off
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EPROM/OTPROM
ELAT — EPROM Bus Latch Bit
This read/write bit configures address and data buses for programming the EPROM array. EPROM
data cannot be read when ELAT is set. Clearing the ELAT bit also clears the EPGM bit. Reset clears
ELAT.
1 = Address and data buses configured for EPROM programming of the array. The address and
data buses are latched in the EPROM array when a subsequent write to the array is made. Data
in the EPROM array cannot be read.
0 = Address and data buses configured for normal operation
Whenever the ELAT bit is cleared, the EPGM bit is also cleared. Both the EPGM and the ELAT bit cannot
be set using the same write instruction. Any attempt to set both the ELAT and EPGM bit on the same write
instruction cycle will result in the ELAT bit being set and the EPGM bit being cleared. To program a byte
of EPROM, manipulate the EPROG register as follows:
1. Set the ELAT bit in the EPROG register.
2. Write the desired data to the desired EPROM address.
3. Set the EPGM bit in the EPROG register for the specified programming time, tEPGM.
4. Clear the ELAT and EPGM bits in the EPROG register.
13.2.2 Mask Option Register
The mask option register (MOR) shown in Figure 13-2 is an EPROM byte that controls eight mask options.
The MOR is unaffected by reset. The erased state of the MOR is $00. The options that can be
programmed by the MOR are:
1. Port software programmable pulldown devices (enable or disable)
2. Startup delay after stop (16 or 4064 cycles)
3. Oscillator shunt resistor (2 MΩ or open)
4. STOP instruction (enable or disable)
5. Low-voltage reset (enable or disable)
6. Port A external interrupt function (enable or disable)
7. IRQ trigger sensitivity (edge-triggered only or both edge- and level-triggered)
8. COP watchdog (enable or disable)
Address:
Read:
Write:
$1FF1
Bit 7
6
5
4
3
2
1
Bit 0
SWPDI
DELAY
OSCRES
SWAIT
LVREN
PIRQ
LEVEL
COPEN
0
0
0
Reset:
Erased:
Unaffected by reset
0
0
0
0
0
Figure 13-2. Mask Option Register (MOR)
SWPDI — Software Pulldown Inhibit Bit
This EPROM bit inhibits software control of the port A and port B pulldown devices.
1 = Software pulldown inhibited
0 = Software pulldown enabled
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EPROM Registers
DELAY — Stop Startup Delay Bit
This EPROM bit selects the number of bus cycles that must elapse before bus activity begins following
a restart from the stop mode.
1 = Startup delay is 4064 bus cycles.
0 = Startup delay is 16 bus cycles.
CAUTION
The 16-cycle delay option will work properly in devices with the internal
low-power oscillator or with a steady external clock source. Check
crystal/ceramic resonator specifications carefully before using the 16-cycle
delay option with a crystal or ceramic resonator.
OSCRES — Oscillator Resistor Bit
This EPROM bit configures the internal shunt resistor.
1 = Oscillator configured with 2 M¾ shunt resistor
0 = Oscillator configured without a shunt resistor
NOTE
The optional oscillator resistor is NOT recommended for devices that use
an external RC oscillator. For such devices, this bit should be left erased as
a 0.
SWAIT — STOP Conversion to WAIT Bit
This EPROM bit disables the STOP instruction and prevents inadvertently turning off the COP
watchdog with a STOP instruction. When the SWAIT bit is set, a STOP instruction puts the MCU in
halt mode. Halt mode is a wait-like low-power state. The internal oscillator and timer clock continue to
run, but the CPU clock stops. When the SWAIT bit is clear, a STOP instruction stops the internal
oscillator, the internal clock, the CPU clock, the timer clock, and the COP watchdog timer.
1 = STOP instruction converted to WAIT instruction
0 = STOP instruction not converted to WAIT instruction
LVREN — Low-Voltage Reset Enable Bit
This EPROM bit enables the low-voltage reset (LVR) function.
1 = LVR function enabled
0 = LVR function disabled
PIRQ — Port A IRQ Enable Bit
This EPROM bit enables the PA3–PA0 pins to function as external interrupt sources.
1 = PA3–PA0 enabled as external interrupt sources
0 = PA3–PA0 not enabled as external interrupt sources
LEVEL — External Interrupt Sensitivity Bit
This EPROM bit makes the external interrupt inputs level-triggered as well as edge-triggered
1 = IRQ/VPP pin negative-edge triggered and low-level triggered;
PA3–PA0 pins positive-edge triggered and high-level triggered
0 = IRQ/VPP pin negative-edge triggered only; PA3–PA0 pins positive-edge triggered only
COPEN — COP Watchdog Enable Bit
This EPROM bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
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EPROM/OTPROM
13.2.3 EPROM Security Bit
An EPROM programmable bit is provided at the location of the COP watchdog register at $1FF0 as shown
in Figure 13-3. This bit allows control of access to the EPROM array. Any accesses of the EPROM
locations will return undefined results when the EPMSEC bit is set. Refer to 13.3.2 EPMSEC
Programming for programming instructions.
Address:
$1FF0
Bit 7
Read:
Write:
EPMSEC
6
5
3
2
1
Bit 0
OPT
COPC
Reset:
Erased:
4
Unaffected by reset
0
—
—
—
—
—
—
—
= Unimplemented
Figure 13-3. EPROM Security in COP and Security Register (COPR)
EPMSEC — EPROM Security(1)
This EPROM write-only bit enables the access to the EPROM array.
1 = Access to the EPROM array in non-user modes is denied.
0 = Access to the EPROM array in non-user modes is enabled.
13.3 EPROM Programming
A programming board is available from Freescale to download to the on-chip EPROM/OTPROM using
the factory-provided programming software. Factory-provided software for programming the PEPROM is
available on the World Wide Web at:
http://www.freescale.com
The programming software copies to the 6144-byte space located at EPROM addresses $0700–$1EFF
and to the 16-byte space at addresses $1FF0–$1FFF which includes the mask option register at address
$1FF1, and the security bit at address $1FF0.
NOTE
To program the EPROM/OTPROM, MOR, or EPMSEC bits properly, the
VDD voltage must be greater than 4.5 volts.
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
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EPROM Erasing
13.3.1 MOR Programming
The contents of the MOR should be programmed using the programmer board. To program any bits in
the MOR, the desired bit states must be written to the MOR address and then the MPGM bit in the EPROG
register must be used. The following sequence will program the MOR:
1. Write the desired data to the MOR location ($1FF1).
2. Apply the programming voltage to the IRQ/VPP pin.
3. Set the MPGM bit in the EPROG.
4. Wait for the programming time, tMPGM.
5. Clear the MPGM bit in the EPROG.
6. Remove the programming voltage from the IRQ/VPP pin.
Once the MOR bits have been programmed, some of the options may experience glitches in operation
after removal of the programming voltage. It is recommended that the part be reset before trying to verify
the contents of the user EPROM or the MOR itself.
NOTE
The contents of the EPROM or the MOR cannot be accessed if the
EPMSEC bit in the COPR register has been set.
13.3.2 EPMSEC Programming
The EPMSEC bit is programmable. To program the EPMSEC bit, the desired state must be written to the
COP address and then the MPGM bit in the EPROG register must be used. The following sequence will
program the EPMSEC bit:
1. Write the desired data to bit 7 of the COPR location ($1FF0).
2. Apply the programming voltage to the IRQ/VPP pin.
3. Set the MPGM bit in the EPROG.
4. Wait for the programming time, tMPGM.
5. Clear the MPGM bit in the EPROG.
6. Remove the programming voltage from the IRQ/VPP pin.
Once the EPMSEC bit has been programmed to a logic 1, access to the contents of the EPROM and MOR
in the expanded non-user modes will be denied. It is therefore recommended that the user EPROM and
MOR in the part first be programmed and fully verified before setting the EPMSEC bit.
13.4 EPROM Erasing
MCUs with windowed packages permit EPROM erasing with ultraviolet light. Erase the EPROM by
exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet
light source 1 inch from the window. Do not use a shortwave filter. The erased state of an EPROM bit is
a logic 0.
NOTE
Unlike many commercial EPROMs, an erased EPROM byte in the MCU will
read as $00. All unused locations should be programmed as 0s.
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EPROM/OTPROM
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Chapter 14
Instruction Set
14.1 Introduction
The microcontroller unit (MCU) instruction set has 62 instructions and uses eight addressing modes. The
instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL)
instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and
the index register (X). The high-order product is stored in the index register, and the low-order product is
stored in the accumulator.
14.2 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide
eight different ways for the CPU to find the data required to execute an instruction. The eight addressing
modes are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
14.2.1 Inherent
Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP).
Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand address and are one byte long.
14.2.2 Immediate
Immediate instructions are those that contain a value to be used in an operation with the value in the
accumulator or index register. Immediate instructions require no operand address and are two bytes long.
The opcode is the first byte, and the immediate data value is the second byte.
14.2.3 Direct
Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the
opcode, and the second is the low byte of the operand address. In direct addressing, the CPU
automatically uses $00 as the high byte of the operand address.
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Instruction Set
14.2.4 Extended
Extended instructions use three bytes and can access any address in memory. The first byte is the
opcode; the second and third bytes are the high and low bytes of the operand address.
When using the Freescale assembler, the programmer does not need to specify whether an instruction is
direct or extended. The assembler automatically selects the shortest form of the instruction.
14.2.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses
within the first 256 memory locations. The index register contains the low byte of the effective address of
the operand. The CPU automatically uses $00 as the high byte, so these instructions can address
locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of
a frequently used random-access memory (RAM) or input/output (I/O) location.
14.2.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses
within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the
unsigned byte following the opcode. The sum is the effective address of the operand. These instructions
can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table
can begin anywhere within the first 256 memory locations and could extend as far as location 510
($01FE). The k value is typically in the index register, and the address of the beginning of the table is in
the byte following the opcode.
14.2.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at
any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand. The first byte after the opcode is
the high byte of the 16-bit offset; the second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere
in memory.
As with direct and extended addressing, the Freescale assembler determines the shortest form of
indexed addressing.
14.2.8 Relative
Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the
effective branch destination by adding the signed byte following the opcode to the contents of the program
counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed,
two’s complement byte that gives a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Freescale assembler, the programmer does not need to calculate the offset, because the
assembler determines the proper offset and verifies that it is within the span of the branch.
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Instruction Types
14.3 Instruction Types
The MCU instructions fall into the following five categories:
• Register/memory instructions
• Read-modify-write instructions
• Jump/branch instructions
• Bit manipulation instructions
• Control instructions
14.3.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations. Most of them use two operands. One
operand is in either the accumulator or the index register. The CPU finds the other operand in memory.
Table 14-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Mnemonic
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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Instruction Set
14.3.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its contents, and write the modified value
back to the memory location or to the register.
NOTE
Do not use read-modify-write operations on write-only registers.
Table 14-2. Read-Modify-Write Instructions
Instruction
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
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Instruction Types
14.3.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The
unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register
operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter
when a test condition is met. If the test condition is not met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first
256 memory locations. These 3-byte instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte
is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of
the opcode. The span of branching is from –128 to +127 from the address of the next location after the
branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code
register.
Table 14-3. Jump and Branch Instructions
Instruction
Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ/VPP Pin High
BIH
Branch if IRQ/VPP Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
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Instruction Set
14.3.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers
and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 14-4. Bit Manipulation Instructions
Instruction
Bit Clear
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Bit Set
BSET
14.3.5 Control Instructions
These instructions act on central processor unit (CPU) registers and control CPU operation during
program execution.
Table 14-5. Control Instructions
Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ/VPP Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
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Instruction Set Summary
14.4 Instruction Set Summary
.
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
BHCS rel
BHI rel
AB
BB
CB
DB
EB
FB
A4
B4
C4
D4
E4
F4
2
3
4
5
4
3
2
3
4
5
4
3
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
38
48
58
68
78
37
47
57
67
77
Arithmetic Shift Left
(Same as LSL)
REL
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Branch if Carry Bit Set
(Same as BLO)
Branch if Equal
Branch if Half-Carry
Bit Clear
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
Branch if Half-Carry
Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 0
— — — — —
REL
22
rr
3
— — —
0
b7
— — b0
C
b7
Clear Bit n
— A ← (A) ∧ (M)
C
N Z C
— A ← (A) + (M)
Logical AND
I
— — b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
ii
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
dd
ff
dd
ff
Cycles
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
A ← (A) + (M) + (C)
Add without Carry
Branch if Carry Bit
Clear
BHCC rel
2
3
4
5
4
3
Add with Carry
BCC rel
BEQ rel
A9
ii
B9 dd
C9 hh ll
D9 ee ff
E9
ff
F9
Effect
on CCR
Description
H
Arithmetic Shift Right
BCS rel
IMM
DIR
EXT
IX2
IX1
IX
Operation
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
BCLR n opr
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Address
Mode
Source
Form
Operand
Table 14-6. Instruction Set Summary (Sheet 1 of 6)
5
3
3
6
5
5
3
3
6
5
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Instruction Set
BIH rel
Branch if IRQ Pin High
BIL rel
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Branch if IRQ Pin Low
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
BRCLR n opr rel
Bit Test
Accumulator with
Memory Byte
Branch if Lower
(Same as BCS)
Branch if Lower or
Same
Branch if Interrupt
Mask Clear
Branch if Minus
Branch if Interrupt
Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
Branch if bit n clear
BRSET n opr rel
Branch if Bit n Set
BRN rel
Branch Never
BSET n opr
Cycles
Branch if Higher or
Same
BLS rel
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
— — — — —
REL
REL
2F
2E
rr
rr
3
3
(A) ∧ (M)
— — —
IMM
DIR
EXT
IX2
IX1
IX
A5
ii
B5 dd
C5 hh ll
D5 ee ff
E5
ff
F5
p
2
3
4
5
4
3
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1
— — — — —
REL
23
rr
3
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
— — — — —
— — — — —
Effect
on CCR
Description
H
BHS rel
BLO rel
N Z C
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 14-6. Instruction Set Summary (Sheet 2 of 6)
Set Bit n
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? Mn = 1
PC ← (PC) + 2 + rel ? 1 = 0
Mn ← 1
I
REL
REL
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
26
2A
20
rr
rr
rr
3
3
3
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
— — — — —
21
rr
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
3
5
5
5
5
5
5
5
5
REL
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
132
Freescale Semiconductor
Instruction Set Summary
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Cycles
CLC
CLI
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
N Z C
Operand
BSR rel
Operation
Opcode
Source
Form
Address
Mode
Table 14-6. Instruction Set Summary (Sheet 3 of 6)
— — — — —
REL
AD
rr
6
— — — — 0
— 0 — — —
INH
INH
DIR
INH
INH
IX1
IX
98
9A
3F
4F
5F
6F
7F
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
A1
ii
B1 dd
C1 hh ll
D1 ee ff
E1
ff
F1
33 dd
43
53
63
ff
73
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
A3
ii
B3 dd
C3 hh ll
D3 ee ff
E3
ff
F3
3A dd
4A
5A
ff
6A
7A
2
3
4
5
4
3
5
3
3
6
5
IMM
DIR
EXT
IX2
IX1
IX
A8
ii
B8 dd
C8 hh ll
D8 ee ff
E8
ff
F8
3C dd
4C
5C
6C
ff
7C
2
3
4
5
4
3
5
3
3
6
5
BC dd
CC hh ll
DC ee ff
EC ff
FC
2
3
4
3
2
Effect
on CCR
Description
H
Branch to
Subroutine
Clear Carry Bit
Clear Interrupt Mask
Clear Byte
Compare
Accumulator with
Memory Byte
Complement Byte
(One’s Complement)
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
C←0
I←0
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
Compare Index
Register with
Memory Byte
(X) – (M)
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
EXCLUSIVE OR
Accumulator with
Memory Byte
Increment Byte
Unconditional Jump
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
I
— — 0
1 —
— — — — — — 1
1
— — —
— — —
— — —
— — — — —
DIR
INH
INH
IX1
IX
DIR
EXT
IX2
IX1
IX
dd
ff
2
2
5
3
3
6
5
2
3
4
5
4
3
5
3
3
6
5
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
133
Instruction Set
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
H
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
Load Accumulator with
Memory Byte
A ← (M)
Load Index Register
with Memory Byte
Logical Shift Left
(Same as ASL)
Logical Shift Right
0
Negate Byte
(Two’s Complement)
C
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
No Operation
Rotate Byte Left
through Carry Bit
A ← (A) ∨ (M)
C
b7
5
6
7
6
5
A6
B6
C6
D6
E6
F6
AE
BE
CE
DE
EE
FE
2
3
4
5
4
3
2
3
4
5
4
3
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
INH
DIR
INH
INH
IX1
IX
38
48
58
68
78
34
44
54
64
74
42
30
40
50
60
70
— — — — —
INH
9D
5
3
3
6
5
5
3
3
6
5
11
5
3
3
6
5
2
— — —
IMM
DIR
EXT
IX2
IX1
IX
AA
ii
BA dd
CA hh ll
DA ee ff
EA
ff
FA
2
3
4
5
4
3
— — DIR
INH
INH
IX1
IX
39
49
59
69
79
5
3
3
6
5
— — — — —
— — ⋅
— — 0
b0
X : A ← (X) × (A)
Logical OR
Accumulator with
Memory
BD dd
CD hh ll
DD ee ff
ED ff
FD
b0
0
Unsigned Multiply
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
IMM
DIR
EXT
IX2
IX1
IX
— — —
C
b7
N Z C
— — —
X ← (M)
b7
I
b0
Cycles
Effect
on CCR
Description
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 14-6. Instruction Set Summary (Sheet 4 of 6)
0 — — — 0
— — ii
dd
hh ll
ee ff
ff
ii
dd
hh ll
ee ff
ff
dd
ff
dd
ff
ii
ff
dd
ff
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
134
Freescale Semiconductor
Instruction Set Summary
Reset Stack Pointer
RTS
Return from
Subroutine
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SWI
Cycles
Rotate Byte Right
through Carry Bit
Return from Interrupt
STOP
36
46
56
66
76
9C
dd
— — — — —
DIR
INH
INH
IX1
IX
INH
5
3
3
6
5
2
INH
80
6
IMM
DIR
EXT
IX2
IX1
IX
INH
INH
A2
ii
B2 dd
C2 hh ll
D2 ee ff
E2
ff
F2
99
9B
2
3
4
5
4
3
2
2
— — —
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
E7
ff
F7
4
5
6
5
4
— 0 — — —
INH
8E
2
— — —
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
EF
ff
FF
4
5
6
5
4
— — IMM
DIR
EXT
IX2
IX1
IX
A0
ii
B0 dd
C0 hh ll
D0 ee ff
E0
ff
F0
2
3
4
5
4
3
— 1 — — —
INH
83
10
Effect
on CCR
Description
H
RTI
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SEC
SEI
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Operand
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
RSP
Operation
Opcode
Source
Form
Address
Mode
Table 14-6. Instruction Set Summary (Sheet 5 of 6)
Subtract Memory Byte
and Carry Bit from
Accumulator
Set Carry Bit
Set Interrupt Mask
Store Accumulator in
Memory
C
b7
Subtract Memory Byte
from
Accumulator
Software Interrupt
N Z C
— — b0
SP ← $00FF
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
A ← (A) – (M) – (C)
C←1
I←1
M ← (A)
Stop Oscillator and
Enable IRQ Pin
Store Index
Register In Memory
I
M ← (X)
A ← (A) – (M)
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Þ
ff
INH
— — — — — — 1
— 1 — — —
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
135
Instruction Set
TST opr
TSTA
TSTX
TST opr,X
TST ,X
— — — — —
INH
97
— — — — —
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
— — — — —
INH
9F
2
— — — —
INH
8F
2
Effect
on CCR
Description
H
Transfer
Accumulator to Index
Register
Test Memory Byte for
Negative or Zero
X ← (A)
(M) – $00
Transfer Index
Register to
A ← (X)
Accumulator
Stop CPU Clock and
WAIT
Enable
Interrupts
A
Accumulator
C
Carry/borrow flag
CCR Condition code register
dd
Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DIR Direct addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
ff
Offset byte in indexed, 8-bit offset addressing
H
Half-carry flag
hh ll High and low bytes of operand address in extended addressing
I
Interrupt mask
ii
Immediate operand byte
IMM Immediate addressing mode
INH Inherent addressing mode
IX
Indexed, no offset addressing mode
IX1
Indexed, 8-bit offset addressing mode
IX2
Indexed, 16-bit offset addressing mode
M
Memory location
N
Negative flag
n
Any bit
TXA
I
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
—
Cycles
N Z C
Opcode
TAX
Operation
Address
Mode
Source
Form
Operand
Table 14-6. Instruction Set Summary (Sheet 6 of 6)
2
dd
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
14.5 Opcode Map
See Table 14-7.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
136
Freescale Semiconductor
Bit Manipulation
DIR
DIR
MSB
LSB
0
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
Table 14-7. Opcode Map
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
Branch
REL
DIR
2
3
Read-Modify-Write
INH
INH
IX1
4
5
6
IX
7
5
5
3
5
3
3
6
5
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BCLR0
BRN
3
DIR 2
1
DIR 2
REL
5
5
3
11
BRSET1
BSET1
BHI
MUL
3
DIR 2
DIR 2
REL
1
INH
5
5
3
5
3
3
6
5
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BCLR5
BMI
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BCLR6
BMS
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BSET7
BIL
3
DIR 2
DIR 2
REL
1
5
5
3
5
3
3
6
5
BRCLR7
BCLR7
BIH
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
8
9
9
RTI
INH
6
RTS
INH
2
2
2
10
SWI
INH
2
2
2
2
1
1
1
1
1
1
1
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
2
STOP
INH
2
2
WAIT
TXA
INH 1
INH
IMM
DIR
A
B
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
MSB
LSB
LSB of Opcode in Hexadecimal
0
Register/Memory
EXT
IX2
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
0
C
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
D
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
IX1
IX
E
F
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
MSB
LSB
3
SUB
1
CMP
IX
3
SBC
IX
3
CPX
2
3
IX
3
4
AND
IX
3
BIT
5
IX
3
6
LDA
IX
4
7
STA
IX
3
EOR
8
IX
3
9
ADC
IX
3
A
ORA
IX
3
ADD
B
IX
2
C
JMP
IX
5
JSR
IX
3
LDX
D
E
IX
4
F
STX
IX
MSB of Opcode in Hexadecimal
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
0
IX
3
137
Opcode Map
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
Control
INH
INH
Instruction Set
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Freescale Semiconductor
Chapter 15
Electrical Specifications
15.1 Introduction
This section contains the electrical and timing specifications.
15.2 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging
it.
The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do
not apply voltages higher than those shown in the table below. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD.
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +7.0
V
Bootloader/self-check mode (IRQ/VPP pin only)
VIn
VSS –0.3 to 17
V
I
25
mA
TJ
+150
°C
Tstg
–65 to +150
°C
Current drain per pin excluding VDD and VSS
Operating junction temperature
Storage temperature range
NOTE
This device is not guaranteed to operate properly at the maximum ratings.
Refer to 15.7 DC Electrical Characteristics (5.0 Vdc) and 15.8 DC Electrical
Characteristics (3.0 Vdc) for guaranteed operating conditions.
15.3 Operating Temperature Range
Characteristic
Operating temperature range
Extended
Symbol
Value
Unit
TA
TL to TH
–40 to +85
°C
Symbol
Value
Unit
θJA
60
°C/W
15.4 Thermal Characteristics
Characteristic
Thermal resistance
Plastic DIP
SOIC
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
139
Electrical Specifications
15.5 Supply Current Characteristics (VDD = 4.5 to 5.5 Vdc)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
—
—
—
150
375
3.00
568
1100
5.20
µA
µA
mA
—
—
—
45
75
1.00
85
375
2.20
µA
µA
mA
RUN(3) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 4.2 MHz
IDD
WAIT(4) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 4.2 MHz
IDD
STOP(5) (analog and LVR disabled)
Typical
–40°C to 85°C
IDD
—
—
2
4
10
20
µA
Incremental IDD for enabled modules
LVR
Analog subsystem
IDD
—
—
5
380
15
475
µA
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only
3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all
inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc, OSC1 = VDD.
15.6 Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc)
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
—
—
—
70
320
1.25
320
800
2.60
µA
µA
mA
—
—
—
20
40
0.50
65
250
1.10
µA
µA
mA
RUN(3) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 2.1 MHz
IDD
WAIT(4) (analog and LVR disabled)
Internal low-power oscillator at 100 kHz
Internal low-power oscillator at 500 kHz
External oscillator running at 2.1 MHz
IDD
STOP(5) (analog and LVR disabled)
25°C
–40°C to 85°C
IDD
—
—
1
2
5
10
µA
Incremental IDD for enabled modules
LVR
Analog subsystem
IDD
—
—
5
380
15
475
µA
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted. All values shown reflect average measurements.
2. Typical values at midpoint of voltage range, 25°C only.
3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 pin or internal oscillator, all
inputs 0.2 Vdc from either supply rail (VDD or VSS); no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD –0.2 Vdc, OSC1 = VDD.
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Freescale Semiconductor
Supply Current Characteristics (VDD = 2.7 to 3.3 Vdc)
3.50E–03
SUPPLY CURRENT IN AMPS
3.00E–03
2.50E–03
5.5 V
2.00E–03
4.5 V
1.50E–03
3.3 V
2.7 V
1.00E–03
5.00E–04
0.00E+00
0
0.5
1
1.5
2
2.5
FREQUENCY IN MHz
Figure 15-1. Typical Run IDD versus Internal Clock Frequency at 25°C
1.60E–03
SUPPLY CURRENT IN AMPS
1.40E–03
1.20E–03
1.00E–03
5.5 V
8.00E–04
4.5 V
6.00E–04
3.3 V
2.7 V
4.00E–04
2.00E–04
0.00E+00
0
0.5
1
1.5
2
2.5
FREQUENCY IN MHz
Figure 15-2. Typical Wait IDD versus Internal Clock Frequency at 25°C
SUPPLY CURRENT IN AMPS
3.50E–03
3.00E–03
2.50E–03
–40°C
25°C
85°C
2.00E–03
1.50E–03
1.00E–03
5.00E–04
2.5
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE IN VOLTS
Figure 15-3. Typical Run IDD with External Oscillator
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
141
Electrical Specifications
1.80E–03
SUPPLY CURRENT IN AMPS
1.60E–03
1.40E–03
1.20E–03
–40°C
25°C
85°C
1.00E–03
8.00E–04
6.00E–04
4.00E–04
2.00E–04
2.5
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE IN VOLTS
SUPPLY CURRENT IN AMPS
Figure 15-4. Typical Wait IDD with External Oscillator
4.50E–06
4.00E–06
3.50E–06
3.00E–06
2.50E–06
2.00E–06
1.50E–06
1.00E–06
5.00E–07
0.00E+00
2.5
–40°C
25°C
85°C
3
3.5
4
4.5
5
SUPPLY VOLTAGE IN VOLTS
5.5
6
Figure 15-5. Typical Stop IDD with Analog and LVR Disabled
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Freescale Semiconductor
DC Electrical Characteristics (5.0 Vdc)
15.7 DC Electrical Characteristics (5.0 Vdc)
Characteristic(1), (2)
Symbol
Min
Typ(3)
Max
Unit
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
VOH
VDD –0.8
VDD –0.8
—
—
—
—
V
—
—
—
—
—
—
0.4
0.4
1.5
Output voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Output high voltage
(ILoad = –0.8 mA) PB0–PB7
(4)
(ILoad = –4.0 mA) PA0–PA5, PB4, PC0–PC7
Output low voltage
(ILoad = 1.6 mA) PB0–PB7, RESET
(ILoad = 10 mA) PA0–PA5, PB4, PC0–PC7(4)
VOL
(ILoad = 15 mA) PA0–PA5, PB4, PC0–PC7(4)
V
High source current
Total for all (6) PA0–PA5 pins and PB4
Total for all (8) PC0–PC7(4) pins
IOH
—
—
—
—
20
30
mA
High sink current
Total for all (6) PA0–PA5 pins and PB4
Total for all (8) PC0–PC7(4) pins
IOL
—
—
—
—
40
60
mA
Input high voltage
PA0–PA5, PB0–PB7, PC0–PC7(4), RESET, OSC1, IRQ/VPP
VIH
0.7 x VDD
—
VDD
V
Input low voltage
PA0–PA5, PB0–PB7, PC0–PC7(4), RESET, OSC1, IRQ/VPP
VIL
VSS
—
0.3 x VDD
V
Input current
OSC1, IRQ/VPP
IIn
–1
—
1
µA
Input current
RESET (pullup, source)
RESET (pulldown, sink)
IIn
10
–6
—
—
—
—
µA
mA
I/O ports hi-Z leakage current (pulldowns off)
PA0–PA6, PB0–PB7, PC0–PC7(4)
IOZ
–2
—
2
µA
IIL
40
25
100
65
280
190
µA
Input pulldown current
PA0–PA5, PB0–PB7, PC0–PC7(4) (VIn ; VIH = 0.7 x VDD)
PA0–PA5, PB0–PB7,
PC0–PC7(4)
(VIn ; VIL = 0.3 x VDD)
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25°C only.
4. PC0–PC7 parameters only apply to MC68HC705JP7.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
143
Electrical Specifications
15.8 DC Electrical Characteristics (3.0 Vdc)
Characteristic(1), (2)
Symbol
Min
Typ(3)
Max
Unit
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
VOH
VDD –0.8
VDD –0.8
—
—
—
—
V
VOL
—
—
—
—
0.3
0.3
V
High source current
Total for all (6) PA0–PA5 pins and PB4
Total for all (8) PC0–PC7(4) pins
IOH
—
—
—
—
20
30
mA
High sink current
Total for all (6) PA0–PA5 pins and PB4
Total for all (8) PC0–PC7(4) pins
IOL
—
—
—
—
40
60
mA
Input high voltage
PA0–PA5, PB0–PB7, PC0–PC7(4), RESET, OSC1, IRQ/VPP
VIH
0.7 x VDD
—
VDD
V
Input low voltage
PA0–PA5, PB0–PB7, PC0–PC7(4), RESET, OSC1, IRQ/VPP
VIL
VSS
—
0.2 x VDD
V
Input current
OSC1, IRQ/VPP
IIn
–1
—
1
µA
Input current
RESET (pullup, source)
RESET (pulldown, sink)
IIn
5
–3
—
—
—
—
µA
mA
I/O ports hi-Z leakage current (pulldowns off)
PA0–PA6, PB0–PB7, PC0–PC7(4)
IOZ
–2
—
2
µA
IIL
10
4
25
20
75
40
µA
Output voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Output high voltage
(ILoad = –0.2 mA) PB0–PB7
(4)
(ILoad = –2.0 mA) PA0–PA5, PB4, PC0–PC7
Output low voltage
(ILoad = 1.6 mA) PB0–PB7, RESET
(ILoad = 5 mA) PA0–PA5, PB4, PC0–PC7(4)
Input pulldown current
PA0–PA5, PB0–PB7, PC0–PC7(4) (VIn ; VIH = 0.7 x VDD)
PA0–PA5, PB0–PB7,
PC0–PC7(4)
(VIn ; VIL = 0.3 x VDD)
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. All values shown reflect average measurements.
3. Typical values at midpoint of voltage range, 25°C only.
4. PC0–PC7 parameters only apply to MC68HC705JP7.
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Freescale Semiconductor
Analog Subsystem Characteristics (5.0 Vdc)
15.9 Analog Subsystem Characteristics (5.0 Vdc)
NOTE
See Figure 15-6.
Characteristic(1)
Symbol
Min
Max
Unit
VIO
VCMR
ZIn
—
—
800
15
VDD –1.5
—
mV
V
kΩ
ZIn
ZIn
800
80
—
—
kΩ
kΩ
RDIV
0.49
0.51
Analog subsystem internal VSS offset
Sum of comparator offset and IR drop through VSS
VAOFF
20
40
mV
Channel selection multiplexer switch resistance
RMUX
—
3
kΩ
External current source (PB0/AN0)
Source current (VOut = VDD/2)
Source current linearity (VOut = 0 to VDD –1.5 Vdc)
Discharge sink current (VOut = 0.4 V)
ICHG
ICHG
IDIS
85
—
1.1
113
±1
—
µA
%FS
mA
External capacitor (connected to PB0/AN0)
Voltage range
Discharge time
Value of external ramping capacitor
VCAP
tDIS
CEXT
VSS
5
—
VDD –1.5
10
2
V
ms/µF
µF
CSH
8
13
pF
tSHCHG
tSHDCHG
tSHTCHG
CSHDIS
1
2
1
—
—
—
—
0.2
µs
µs
µs
V/sec
VD
TCD
0.65
1.8
0.71
2.0
V
mV/°C
Voltage comparators
Input offset voltage
Common-mode range
Comparator 1 input impedance
Comparator 2 input impedance
Direct input to comparator 2 (HOLD = 1, DHOLD = 0)
Divider input to comparator 2 (HOLD = 0, DHOLD = 1)
Input divider ratio (comparator 2, HOLD = 0, DHOLD =1)
VIn = 0 to VDD –1.5 V
Internal sample and hold capacitor
Capacitance
Charge/discharge time (0 to 3.5 Vdc)
Direct connection (HOLD = 1, DHOLD = 0)
Divided connection (HOLD = 0, DHOLD = 1)
Temperature diode connection (HOLD = 1, DHOLD = 1)
Leakage discharge rate
Internal temperature sensing diode
Voltage at TJ = 25°C
Temperature change in voltage
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
145
Electrical Specifications
15.10 Analog Subsystem Characteristics (3.0 Vdc)
NOTE
See Figure 15-6.
Characteristic(1)
Symbol
Min
Max
Unit
VIO
VCMR
ZIn
—
—
800
15
VDD –1.5
—
mV
V
kΩ
ZIn
ZIn
800
80
—
—
kΩ
kΩ
RDIV
0.49
0.51
Analog subsystem internal VSS offset
VAOFF
10
30
mV
Multiplexer switch resistance
RMUX
—
5
kΩ
External current source (PB0/AN0)
Source current (VOut = VDD/2)
Source current linearity (VOut = 0 to VDD –1.5 Vdc)
Discharge sink current (VOut = 0.4 V)
ICHG
ICHG
IDIS
75
—
1
104
±1
—
µA
%FS
mA
External capacitor (connected to PB0/AN0)
Voltage range
Discharge time
Value of external ramping capacitor
VCAP
tDIS
CEXT
VSS
5
—
VDD –1.5
10
2
V
ms/µF
µF
CSH
8
13
pF
tSHCHG
tSHDCHG
tSHTCHG
CSHDIS
1
2
1
—
—
—
—
0.1
µs
µs
µs
V/sec
VD
TCD
0.65
1.8
0.71
2.0
V
mV/°C
Voltage comparators
Input offset voltage
Common-mode range
Comparator 1 input impedance
Comparator 2 input impedance
Direct input to comparator 2 (HOLD = 1, DHOLD = 0)
Divider input to comparator 2 (HOLD = 0, DHOLD = 1)
Input divider ratio (comparator 2, HOLD = 0, DHOLD =1)
VIn = 0 to VDD –1.5 V
Internal sample and hold capacitor
Capacitance
Charge/discharge time (0 to 3.5 Vdc)
Direct connection (HOLD = 1, DHOLD = 0)
Divided connection (HOLD = 0, DHOLD = 1)
Temperature diode connection (HOLD = 1, DHOLD = 1)
Leakage discharge rate
Internal temperature sensing diode
Voltage at TJ = 25°C
Temperature change in voltage
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
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Freescale Semiconductor
T DIODE IN mV
Analog Subsystem Characteristics (3.0 Vdc)
820
800
780
760
740
720
700
680
660
640
620
600
580
560
–45
–35
–25
–15
–5
5
15
25
35
45
55
65
75
85
95
TEMPERATURE IN °C
Figure 15-6. Typical Temperature Diode Performance
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
147
Electrical Specifications
15.11 Control Timing (5.0 Vdc)
Characteristic(1)
Frequency of oscillation (OSC)
RC oscillator option
Crystal oscillator option
External clock source
Internal low-power oscillator
Standard product (100 kHz nominal)
Mask option (500 kHz nominal, see Note 3)
Symbol
Min
Max
Unit
fOSC
—
0.1
dc
4.2
4.2
4.2
MHz
MHz
MHz
60
300
140
700
kHz
kHz
—
0.05
dc
2.1
2.1
2.1
MHz
MHz
MHz
30
150
75
350
kHz
kHz
476
—
ns
14.29
2.86
33.33
6.67
µs
µs
tRESL
tTH, tTL
4.0
284
—
—
tcyc
ns
tILIH
284
—
ns
tILIL
(3)
—
tcyc
tOH, tOL
110
—
ns
tCPROP
tCDELAY
—
—
2
2
µs
µs
tISTART
tIDELAY
tBDELAY
—
—
—
1
2
2
µs
µs
µs
Internal operating frequency, crystal, or external clock (fOSC/2)
RC oscillator option
Crystal oscillator option
External clock source
Internal low-power oscillator
Standard product (100 kHz nominal)
Mask option (500 kHz nominal(2))
fOP
Cycle time (1/fOP)
External oscillator or clock source
Internal low-power oscillator
Standard product (100 kHz nominal)
Mask option (500 kHz nominal(2))
tcyc
16-bit timer
Resolution
Input capture (TCAP) pulse width
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
OSC1 pulse width (external clock input)
Analog subsystem response
Voltage comparators
Switching time (10 mV overdrive, either input)
Comparator power-up delay (bias circuit already powered up)
External current source (PB0/AN0)
Switching time (IDIS to IRAMP)
Power-up delay (bias circuit already powered up)
Bias circuit power-up delay
1. VDD = 4.5 to 5.5 Vdc, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. The 500-kHz nominal mask option is available through special order only. Contact your local Freescale sales representative for detailed ordering information. Not offered with the RC oscillator.
3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 21 tcyc.
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148
Freescale Semiconductor
Control Timing (3.0 Vdc)
15.12 Control Timing (3.0 Vdc)
Characteristic(1)
Frequency of oscillation (OSC)
RC oscillator option
Crystal oscillator option
External clock source
Internal low-power oscillator
Standard product (100 kHz nominal)
Mask option (500 kHz nominal, see Note 3))
Symbol
Min
Max
Unit
fOSC
—
0.1
dc
2.1
2.1
2.1
MHz
MHz
MHz
60
300
140
700
kHz
kHz
—
0.05
dc
1.05
1.05
1.05
MHz
MHz
MHz
30
150
70
350
kHz
kHz
952
—
ns
14.29
2.86
33.33
6.67
µs
µs
tRESL
tTH, tTL
4.0
284
—
—
tcyc
ns
tILIH
284
—
ns
tILIL
(3)
—
tcyc
tOH, tOL
110
—
ns
tCPROP
tCDELAY
—
—
2
2
µs
µs
tISTART
tIDELAY
tBDELAY
—
—
—
1
2
2
µs
µs
µs
Internal operating frequency, crystal, or external clock (fOSC/2)
RC oscillator option
Crystal oscillator option
External clock source
Internal low-power oscillator
Standard product (100 kHz nominal)
Mask option (500 kHz nominal(2))
fOP
Cycle time (1/fOP)
External oscillator or clock source
Internal low-power oscillator
Standard product (100 kHz nominal)
Mask option (500 kHz nominal(2))
tcyc
16-bit timer
Resolution
Input capture (TCAP) pulse width
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
OSC1 pulse width (external clock input)
Analog subsystem response
Voltage comparators
Switching time (10 mV overdrive, either input)
Comparator power-up delay (bias circuit already powered up)
External current source (PB0/AN0)
Switching time (IDIS to IRAMP)
Power-up delay (bias circuit already powered up)
Bias circuit power-up delay
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. The 500 kHz nominal mask option is available through special order only. Contact your local Freescale sales representative
for detailed ordering information. Not offered with the RC oscillator option.
3. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine
plus 21 tcyc.
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Freescale Semiconductor
149
Electrical Specifications
510000
500000
FREQUENCY IN Hz
490000
480000
470000
460000
450000
440000
430000
420000
–45
–35
–25
–15
–5
5
15
25
35
45
55
65
75
85
95
85
95
TEMPERATURE IN °C
Figure 15-7. Typical 500 kHz External Low-Power
Oscillator Frequency
114000
FREQUENCY IN Hz
113500
113000
112500
112000
111500
111000
110500
110000
109500
–45
–35
–25
–15
–5
5
15
25
35
45
55
65
75
TEMPERATURE IN °C
Figure 15-8. Typical 100 kHz External Low-Power
Oscillator Frequency
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Freescale Semiconductor
Control Timing (3.0 Vdc)
INTERNAL BUS FREQUENCY (MHz)
2.5
2
1.5
VDD = 5.5 V
VDD = 4.5 V
1
0.5
0
12.1
24.9
49.9
EXTERNAL RESISTOR VALUE (kΩ)
Figure 15-9. Typical RC Oscillator Internal Operating
Frequency Range versus Resistance for High VDD
Operating Range at T = 25°C
INTERNAL BUS FREQUENCY (MHz)
2
1.5
VDD = 3.3 V
VDD = 2.7 V
1
0.5
0
12.1
24.9
49.9
EXTERNAL RESISTOR VALUE (kΩ)
Figure 15-10. Typical RC Oscillator Internal Operating
Frequency Range versus Resistance for Low VDD
Operating Range at T = 25°C
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
151
Electrical Specifications
15.13 PEPROM and EPROM Programming Characteristics
Characteristic(1)
Symbol
Min
Typ
Max
Unit
PEPROM programming voltage (IRQ/VPP)
VPP
16.0
16.5
17.0
V
PEPROM programming voltage (IRQ/VPP)
IPP
—
3.0
5.0
mA
tEPGM
4.0
—
—
ms
EPROM/MOR programming voltage (IRQ/VPP)
VPP
16.0
16.5
17.0
V
EPROM/MOR programming current (IRQ/VPP)
IPP
—
3.0
5.0
mA
EPROM programming time per byte
tEPGM
4.0
—
—
ms
MOR programming time
tMPGM
10.0
—
—
ms
PEPROM programming time per bit
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
NOTE
To program the EPROM/OTPROM, MOR, or EPMSEC bits, the voltage on
VDD must be greater than 4.5 volts.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
152
Freescale Semiconductor
SIOP Timing (VDD = 5.0 Vdc)
15.14 SIOP Timing (VDD = 5.0 Vdc)
Characteristic(1)
Symbol
Min
Typ
Max
Unit
Frequency of operation
Master
Slave
fSIOP(M)
fSIOP(S)
0.25 x fOP
dc
0.25 x fOP
—
0.25 x fOP
1050
kHz
Cycle time
Master
Slave
tSCK(M)
tSCK(M)
4.0 x tcyc
—
4.0 x tcyc
—
4.0 x tcyc
3.8
µs
tSCKL
952
—
—
ns
tV
—
—
200
ns
SDO hold time
tHO
0
—
—
ns
SDI setup time
tS
100
—
—
ns
SDI hold time
tH
100
—
—
ns
Clock (SCK) low time (fOP = 4.2 MHz)
SDO data valid time
1. +4.5 ≤ VDD ≤ +5.5 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
tSCK
tSCKL
SCK
tV
SDO
tHO
MSB
BIT 1
LSB
tS
MSB
SDI
VALID DATA
LSB
tH
Figure 15-11. SIOP Timing Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
153
Electrical Specifications
15.15 SIOP Timing (VDD = 3.0 Vdc)
Characteristic(1)
Symbol
Min
Typ
Max
Unit
Frequency of operation
Master
Slave
fSIOP(M)
fSIOP(S)
0.25 x fOP
dc
0.25 x fOP
—
0.25 x fOP
525
kHz
Cycle time
Master
Slave
tSCK(M)
tSCK(M)
4.0 x tcyc
—
4.0 x tcyc
—
4.0 x tcyc
1.9
µs
tSCKL
1905
—
—
ns
tV
—
—
400
ns
SDO hold time
tHO
0
—
—
ns
SDI setup time
tS
200
—
—
ns
SDI hold time
tH
200
—
—
ns
Symbol
Min
Typ
Max
Unit
Low-voltage reset
Rising recovery voltage
Falling reset voltage
LVR hysteresis
VLVRR
VLVRF
VLVRH
2.4
2.3
30
3.4
3.3
70
4.4
4.3
—
V
V
mV
POR recovery voltage(2)
VPOR
0
—
100
mV
SVDDR
SVDDF
—
—
—
—
0.1
0.05
V/µs
tRL
1.5
—
—
tCYC
tRPD
3
—
4
tCYC
Clock (SCK) low time (fOP = 2.1 MHz)
SDO data valid time
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
15.16 Reset Characteristics
Characteristic(1)
POR VDD slew rate(2)
Rising(2)
Falling(2)
RESET pulse width (when bus clock active)
RESET pulldown pulse width from internal reset
RESET VOLTAGE IN VOLTS
1. +2.7 ≤ VDD ≤ +3.3 V, VSS = 0 V, TL ≤ TA ≤ TH, unless otherwise noted
2. By design, not tested
4.5
4
3.5
3
2.5
–45
–35
–25
–15
–5
5
15
25
35
45
55
65
75
85
95
TEMPERATURE IN °C
Figure 15-12. Typical Falling Low Voltage Reset
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
154
Freescale Semiconductor
Reset Characteristics
OSC1
1
t
RL
RESET
4064 or 16 t
(2)
cyc
INTERNAL
CLOCK(3)
INTERNAL
ADDRESS
BUS(3)
1FFE
INTERNAL
DATA
BUS(3)
1FFF
NEW
PCH
NEW PCH
NEW
PCL
NEW PCL
Op
code
Notes:
1. Represents the internal gating of the OSC1 pin
2. Normal delay of 4064 tcyc or short delay option of 16 tcyc
3. Internal timing signal and data information not available externally
Figure 15-13. Stop Recovery Timing Diagram
INTERNAL
RESET1
RESET
PIN
tRPD
4064 or 16 tcyc(2)
INTERNAL
CLOCK(3)
INTERNAL
ADDRESS
BUS(3)
1FFE
INTERNAL
DATA
BUS(3)
1FFF
NEW
PCH
NEW PCH
NEW PCL
NEW
PCL
Notes:
1.Represents the internal reset from low-voltage reset, illegal opcode fetch or COP watchdog timeout
2.Only if reset occurs during normal delay of 4064 tCYC or short delay option of 16 tCYC for initial power-up
or stop recovery.
3.Internal timing signal and data information not available externally
Figure 15-14. Internal Reset Timing Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
155
Electrical Specifications
VDD
VLVRR
VLVRF
LOW
VOLTAGE
RESET
RESET
PIN1
tRPD
4064 or 16 tcyc(2)
INTERNAL
CLOCK3
INTERNAL
ADDRESS
BUS(3)
1FFE
INTERNAL
DATA
BUS(3)
NEW
PCH
1FFF
NEW PCH
NEW PCL
NEW
PCL
Notes:
1.RESET pin pulled down by internal device
2 Only if LVR occurs during normal delay of 4064 tcyc or short delay option of 16 tcyc for initial power-up
or stop recovery.
3 Internal timing signal and data information not available externally
Figure 15-15. Low-Voltage Reset Timing Diagram
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
156
Freescale Semiconductor
Chapter 16
Mechanical Specifications
16.1 Introduction
The MC68HC705JJ7 is available in:
• 20-pin plastic dual in-line package (PDIP)
• 20-pin small outline integrated circuit (SOIC) package
• 20-pin windowed ceramic package
The MC68HC705JP7 is available in:
• 28-pin plastic dual in-line package (PDIP)
• 28-pin small outline integrated circuit (SOIC) package
• 28-pin windowed ceramic package
The following figures show the latest package drawings at the time of this publication. To make sure that
you have the latest package specifications, contact your local Freescale Sales Office.
16.2 20-Pin Plastic Dual In-Line Package (Case 738)
-A20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
C
-T-
L
K
SEATING
PLANE
M
E
G
N
F
J 20 PL
0.25 (0.010)
D 20 PL
0.25 (0.010)
M
T A
M
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
15°
0°
0.020 0.040
MILLIMETERS
MIN
MAX
25.66 27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0°
15°
0.51
1.01
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
157
Mechanical Specifications
16.3 20-Pin Small Outline Integrated Circuit (Case 751D)
-A20
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
11
-B-
P 10 PL
0.010 (0.25)
1
M
B
M
10
D
20 PL
0.010 (0.25)
M
T A
B
S
J
S
DIM
A
B
C
D
F
G
J
K
M
P
R
F
R X 45°
C
-TG
K
18 PL
M
SEATING
PLANE
MILLIMETERS
MIN
MAX
12.65 12.95
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0°
7°
10.05 10.55
0.25
0.75
INCHES
MIN
MAX
0.499 0.510
0.292 0.299
0.093 0.104
0.014 0.019
0.020 0.035
0.050 BSC
0.010 0.012
0.004 0.009
0°
7°
0.395 0.415
0.010 0.029
16.4 28-Pin Plastic Dual In-Line Package (Case 710)
28
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND
EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
15
B
1
14
A
L
C
N
H
G
F
D
K
SEATING
PLANE
M
J
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MILLIMETERS
MIN
MAX
36.45 37.21
13.72 14.22
3.94
5.08
0.36
0.56
1.02
1.52
2.54 BSC
1.65
2.16
0.20
0.38
2.92
3.43
15.24 BSC
0°
15°
0.51
1.02
INCHES
MIN
MAX
1.435 1.465
0.540 0.560
0.155 0.200
0.014 0.022
0.040 0.060
0.100 BSC
0.065 0.085
0.008 0.015
0.115 0.135
0.600 BSC
0°
15°
0.020 0.040
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
158
Freescale Semiconductor
28-Pin Small Outline Integrated Circuit (Case 751F)
16.5 28-Pin Small Outline Integrated Circuit (Case 751F)
-A28
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
15
14X
-B1
P
0.010 (0.25)
M
B
M
14
28X D
0.010 (0.25)
M
T
A
B
S
M
S
R X 45°
DIM
A
B
C
D
F
G
J
K
M
P
R
C
-T-
-T-
G
26X
SEATING
PLANE
K
F
J
MILLIMETERS
MIN
MAX
17.80 18.05
7.60
7.40
2.65
2.35
0.49
0.35
0.90
0.41
1.27 BSC
0.32
0.23
0.29
0.13
8°
0°
10.05 10.55
0.75
0.25
INCHES
MIN
MAX
0.701 0.711
0.292 0.299
0.093 0.104
0.014 0.019
0.016 0.035
0.050 BSC
0.009 0.013
0.005 0.011
8°
0°
0.395 0.415
0.010 0.029
16.6 20-Pin Windowed Ceramic Integrated Circuit (Case 732)
20
11
1
10
NOTES:
1. LEADS WITHIN 0.010 DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
A
L
C
F
N
H
D
G
K
J
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.940
0.990
0.260
0.295
0.150
0.200
0.015
0.022
0.055
0.065
0.100 BSC
0.020
0.050
0.008
0.012
0.125
0.160
0.300 BSC
0_
15_
0.010
0.040
SEATING
PLANE
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
159
Mechanical Specifications
16.7 28-Pin Windowed Ceramic Integrated Circuit (Case 733A)
28
15
1
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION A AND B INCLUDE MENISCUS.
4. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B
M
–A–
L
N
C
–T–
SEATING
PLANE
J
K
G
F
D 28 PL
0.25 (0.010)
M
T A
DIM
A
B
C
D
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.435
1.490
0.500
0.605
0.160
0.240
0.015
0.022
0.050
0.065
0.100 BSC
0.008
0.012
0.125
0.160
0.600 BSC
0_
15 _
0.020
0.050
MILLIMETERS
MIN
MAX
36.45
37.84
12.70
15.36
4.06
6.09
0.38
0.55
1.27
1.65
2.54 BSC
0.20
0.30
3.17
4.06
15.24 BSC
0_
15 _
0.51
1.27
M
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
160
Freescale Semiconductor
Chapter 17
Ordering Information
17.1 Introduction
This section contains instructions for ordering the various erasable programmable read-only memory
(EPROM) versions of the MC68HC05JJ/JP Family of microcontrollers.
17.2 MC68HC705JJ7 Order Numbers
MC order numbers for the available 20-pin package types are shown here.
EPO
Oscillator
Type(1)
LPO
Frequency
(kHz)
Operating
Temperature
Range
Plastic DIP(2)
XTAL
100
–40 to 85°C
MC68HC705JJ7CP
SOIC(3)
XTAL
100
–40 to 85°C
MC68HC705JJ7CDW
CERDIP(4), (5)
XTAL
100
–40 to 85°C
MC68HC705JJ7S
Plastic DIP
RC
100
–40 to 85°C
MC68HRC705JJ7CP
SOIC
RC
100
–40 to 85°C
MC68HRC705JJ7CDW
CERDIP(5)
RC
100
–40 to 85°C
MC68HRC705JJ7S
Plastic DIP
XTAL
500
–40 to 85°C
MC68HC705SJ7CP
SOIC
XTAL
500
–40 to 85°C
MC68HC705SJ7CDW
CERDIP(5)
XTAL
500
–40 to 85°C
MC68HC705SJ7S
Package Type
Order Number
1. Crystal/ceramic resonator or RC oscillator
2. Plastic dual in-line package (P, case outline 738)
3. Small outline integrated circuit package (DW, case outline 751D)
4. Windowed ceramic dual in-line package (S, case outline 732)
5. CERDIP parts are only guaranteed at room temperature and are for evoluation purposes only.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
161
Ordering Information
17.3 MC68HC705JP7 Order Numbers
MC order numbers for the available 28-pin package types are shown here.
EPO
Oscillator
Type(1)
LPO
Frequency
(kHz)
Operating
Temperature
Range
Plastic DIP(2)
XTAL
100
–40 to 85°C
MC68HC705JP7CP
SOIC(3)
XTAL
100
–40 to 85°C
MC68HC705JP7CDW
XTAL
100
–40 to 85°C
MC68HC705JP7S
Plastic DIP
RC
100
–40 to 85°C
MC68HRC705JP7CP
SOIC
RC
100
–40 to 85°C
MC68HRC705JP7CDW
CERDIP(5)
RC
100
–40 to 85°C
MC68HRC705JP7S
Plastic DIP
XTAL
500
–40 to 85°C
MC68HC705SP7CP
SOIC
XTAL
500
–40 to 85°C
MC68HC705SP7CDW
CERDIP(5)
XTAL
500
–40 to 85°C
MC68HC705SP7S
Package Type
(4), (5)
CERDIP
Order Number
1. Crystal/ceramic resonator or RC oscillator
2. Plastic dual in-line package (P, case outline 710)
3. Small outline integrated circuit package (DW, case outline 751F)
4. Windowed ceramic dual in-line package (S, case outline 733A)
5. CERDIP parts are only guaranteed at room temperature and are for evoluation purposes only.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
162
Freescale Semiconductor
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MC68HC705JJ7
Rev. 4.1, 09/2005
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