Zarlink MT352CGGP1Q Cofdm demodulator Datasheet

MT352
COFDM Demodulator
Data Sheet
Features
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February 2005
Nordig II and ETSI 300 744 compliant
Superior Single Frequency Network performance
Unique active Impulse-Noise filtering
Single SAW operation
Automatic co-channel and adjacent-channel
interference suppression
Clock generation from single low-cost 20.48 MHz
crystal or external 4 or 27 MHz clock
IF sampling at 4.57, 36.17 or 43.5 MHz from a
single crystal frequency
Channel bandwidth of 6, 7 & 8 MHz
Blind acquisition capability (including 2 K / 8 K
mode detect)
Automatic spectral inversion detection
Fast auto-scan and acquisition technology
Very low software overhead
Dual AGC control option
Access to channel SNR, pre- and post-Viterbi bit
error rates
Compact 64 pin LQFP
Less than 0.22 W power consumption
Standby and sleep options
Ordering Information
MT352/CG/GP1N
64 Pin LQFP Trays
MT352/CG/GP1Q 64 Pin LQFP Tape & Reel
MT352/CG/GP2Q
64 Pin LQFP* Tape & Reel
MT352/CG/GP2N
64 Pin LQFP* Trays
* Pb Free Matte Tin
0o C to +70oC
Zarlink evaluation kits include application board, TNIM
and supporting software based on industry standard
operating systems. Device drivers are also available
enabling rapid product development and reduction in
time to market.
Description
MT352 is a superior third generation Coded
Orthogonal Frequency Division Multiplex (COFDM)
television demodulator that is both Nordig II and DVB
(as defined in ETS 300 744 specification) compliant. It
can be used in either 2 K or 8 K modes with 6, 7 or
8 MHz channels and is capable of addressing all
modes of transmission.
The device includes a high performance 10-bit A/D
converter capable of accepting direct IF at 36.17 or
43.75 MHz. Sampling rates required for both these
frequencies in 6,7 or 8 MHz OFDM channels can be
generated from a single 20.48 MHz crystal.
Alternatively, there is provision to replace this crystal
with a 4 or 27 MHz external clock input.
Applications
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Set-top boxes
Integrated digital televisions
Personal video recorders
Terrestrial PC reception
Mobile and portable applications
RF in
ADC
IF to
Baseband
conversion &
Interpolator
Pilot &
Channel
Processor
FFT
Symbol & Bit
De-interleaver
& Demapper
FEC
MPEG
TS
AGC
Impulse
Suppression
Secondary
2-wire bus
Symbol,
Carrier &
Timing
Recovery
Control
engine
Tuner control
Primary
2-wire bus
Figure 1 - Block Diagram
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Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT352
Data Sheet
Unique algorithms that actively filter out impulse noise, without affecting normal performance, have been
implemented. This reduces the interference effect from vehicles and electrical appliances, which is known to have
significant detrimental effect on the quality of digital TV reception.
Programming is simplified utilizing a high level command driven interface. A sophisticated engine controls all
acquisition and tracking operations as well as controlling the tuner via a 2-wire bus. Any frequency range can be
automatically scanned for digital TV channels. This mechanism ensures minimal interaction, maximum flexibility,
fastest acquisition and the fastest auto scan capability of any chip in the market.
Blind acquisition mode enables automatic detection of all OFDM signal parameters, including mode, guard and
spectral inversion. The frequency capture range is sufficient to compensate for the combined offset introduced by
the tuner and broadcaster.
The device is packaged in a 64 pin LQFP and consumes less than 220 mW of power.
MT352 CG
YYWW*W
∆
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Pin 1 Corner
Figure 2 - Package Outline
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Zarlink Semiconductor Inc.
MT352
Data Sheet
Pin Description
Pin Description Table
Pin No
Name
Description
I/O
Type
V
mA
MPEG pins
47
MOSTRT
MPEG packet start
O
3·3
1
48
MOVAL
MPEG data valid
O
3·3
1
49-53, 56-58
MDO(0:7)
MPEG data bus
O
3·3
1
61
MOCLK
MPEG clock out
O
3·3
1
62
BKERR
Block error
O
3·3
1
63
MICLK
MPEG clock in
I
11
STATUS
Status output
O
6
IRQ
Interrupt output
O
4
CLK1
Serial clock
5
DATA1
23
XTI
24
XTO
10
SLEEP
Device power down
I
3·3
12, 15-18
SADD(4:0)
Serial address set
I
3·3
44
SMTEST
Scan mode enable
I
3·3
35
CLK2/GPP0
Serial clock tuner
I/O
5
6
36
DATA2/GPP1
Serial data tuner
I/O
5
6
42
AGC1
Primary AGC
O
5
6
41
AGC2/GPP2
Secondary AGC
I/O
5
6
43
GPP(3)
General purpose I/O
I/O
5
6
9
RESET
Device reset
I
CMOS
5
27
OSCMODE
Crystal oscillator mode
I
CMOS
3·3
26
PLLTEST
PLL analogue test
O
30
VIN
positive input
I
31
VIN
negative input
I
CMOS Tristate
CMOS
3·3
3·3
1
Open drain
5
6
I
CMOS
5
Serial data
I/O
Open drain
5
Low phase noise
oscillator
I
Control pins
O
Analog inputs
Supply pins
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6
CMOS
Open drain
MT352
Data Sheet
Pin Description Table (continued)
Pin No
Name
21
PLLVDD
22
PLLGND
7, 19, 37, 39, 59, 64
CVDD
2, 13, 45, 54,
Description
PLL supply
I/O
Type
V
S
1·8
S
0
Core logic power
S
1·8
VDD
I/O ring power
S
3·3
1, 3, 8, 14, 20, 25, 38,
40, 46, 55, 60
GND
Core and I/O ground
S
0
28
AVDD
ADC analog supply
S
1·8
29, 32
AGND
S
0
33
DVDD
S
1·8
34
DGND
S
0
ADC digital supply
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Zarlink Semiconductor Inc.
mA
MT352
Data Sheet
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1 Analogue-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 IF to Baseband Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Adjacent Channel Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Interpolation and Clock Synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Carrier Frequency Synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 Symbol Timing Synchronisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8 Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.9 Common Phase Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.10 Channel Equalisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.11 Impulse Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.12 Transmission Parameter Signalling (TPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.13 De-Mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.14 Symbol and Bit De-Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.15 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.16 MPEG Frame Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.17 De-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.18 Reed-Solomon Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.19 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.20 MPEG Transport Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0 Software control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.0 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 Examples of 2-Wire Bus Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3 Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 MPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 Data Output Header Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.2 MPEG data output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.3 MPEG Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.3.1 MOCLKINV = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3.2 MOCLKINV = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.4 Crystal Specification and External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.0 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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MT352
Data Sheet
List of Figures
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3 - OFDM Demodulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4 - FEC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5 - Primary Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8 - MPEG Output Data Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9 - MPEG Timing - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10 - MPEG Timing - MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11 - Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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MT352
Data Sheet
List of Tables
Table 1 - Programmable Address Details for 2-Wire Bus in TNIM Evaluation Application. . . . . . . . . . . . . . . . . . . 13
Table 2 - Timing of 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3 - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 4 - MDOSWAP = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5 - MDOSWAP = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Zarlink Semiconductor Inc.
MT352
1.0
Data Sheet
Functional Description
A functional block diagram of the MT352 OFDM demodulator is shown in Figure 3. This accepts an IF analogue
signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and
frequency synchronization operations are all digital and there are no analogue control loops except the AGC. The
frequency capture range is large enough for all practical applications. This demodulator has novel algorithms to
combat impulse noise as well as co-channel and adjacent channel interference. If the modulation is hierarchical,
the OFDM outputs both high and low priority data streams. Only one of these streams is FEC-decoded, but the FEC
can be switched from one stream to another with minimal interruption to the transport stream.
Figure 3 - OFDM Demodulator Diagram
The FEC module shown in Figure 4 consists of a concatenated convolutional (Viterbi) and Reed-Solomon decoder
separated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions to
provide the best performance over a wide range of channel conditions. The trace-back depth of 128 ensures
minimum loss of performance due to inevitable survivor truncation, especially at high code rates. Both the Viterbi
and Reed-Solomon decoders are equipped with bit-error monitors. The former provides the bit error rate (BER) at
the OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collecting
intervals of these are programmable over a very wide range.
Figure 4 - FEC Block Diagram
The FSM controller shown in Figure 3 above controls both the demodulator and the FEC. It also drives the 2-wire
bus to the tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of
the received signal. It can also be used to scan any defined frequency range searching for OFDM channels. This
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Zarlink Semiconductor Inc.
MT352
Data Sheet
mechanism provides the fast channel scan and acquisition performance, whilst requiring minimal software
overhead in the host driver.
The algorithms and architectures used in the MT352 have been heavily optimized to minimize hardware and chip
area. This is proven by its 220 mW (typical) power consumption, which is the lowest of any OFDM device in the
market today.
1.1
Analogue-to-Digital Converter
The MT352 has a high performance 10-bit analogue-to-digital converter (ADC) which can sample a 6, 7 or 8 MHz
bandwidth OFDM signal, with its spectrum centred at:
•
•
•
4.57 MHz near-zero IF
36.17 MHz IF
43.75 MHz IF
The ADC can be clocked using:
•
•
Crystal oscillator with a 20.48 MHz crystal
4 MHz or 27 MHz clock input
An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The crystal
frequency of 20.48 MHz is used for 36.17 MHz IF sampling and 19.6267 MHz is used for 43.75 MHz IF sampling.
Note that this 19.6267 MHz sampling clock can be generated from the 20.48 MHz crystal by appropriately
programming the PLL. Hence the same 20.48 MHz crystal can support 6, 7 and 8 MHz OFDM as well as 36.17 and
43.75 MHz IF.
1.2
Automatic Gain Control
An AGC module compares the absolute value of the digitized signal with a programmable reference. The error
signal is filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, which
has to be RC low-pass filtered to obtain the voltage to control the amplifier. Upper and lower limits can be set to the
AGC control voltage using registers.
The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC
clipping and a small value results in excessive quantization noise. Hence the optimum value has been determined
assuming the input signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit
theorem in statistics to the OFDM signal, which consists of a large number of randomly modulated carriers. This
reference or target value may have to be lowered slightly for some applications. Slope control bits have been
provided for the AGCs and these have to be set correctly depending on the Gain-versus-Voltage slope of the gain
control amplifiers.
The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking.
The AGC is free running during OFDM channel changes and locks to the new channel while the tuner lock is being
established. This is one of the features of MT352 used to minimize acquisition time. A robust AGC lock mechanism
is provided and the other parts of the MT352 begin to acquire only after the AGC has locked. Two AGC control
outputs are available, one to drive an RF amplifier and the other to control an IF amplifier. The parameters for both
loops are programmable. In the default mode, only the IF AGC loop is activated.
1.3
IF to Baseband Conversion
Sampling a 36.17 MHz IF signal at 20.48 MHz results in a spectrally inverted OFDM signal centred at 4.79 MHz.
Sampling a 43.75 MHz IF signal at 19.6267 MHz gives a non-inverted signal at 4.5 MHz. The first step of the
demodulation process is to convert this signal to a complex (in-phase and quadrature) signal in baseband. A
correction for spectral inversion is implemented during this conversion process. Note also that the MT352 has
control mechanisms to search automatically for an unknown spectral inversion status.
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MT352
1.4
Data Sheet
Adjacent Channel Filtering
Adjacent channels, in particular the Nicam digital sound signal associated with analogue channels, are filtered prior
to the FFT.
1.5
Interpolation and Clock Synchronisation
MT352 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC samples the
signal at a fixed rate, for example, 20.48 MHz. Conversion of the 20.48 MHz signal to the OFDM sample rate is
achieved using the time-varying interpolator. The OFDM sample rate is 64/7 MHz for 8 MHz and this is scaled by
factors 6/8 and 7/8 for 6 and 7 MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate is
programmed in a MT352 register (defaults are for 20.48 MHz sampling and 8 MHz OFDM). The clock recovery
phase locked loop in the MT352 compensates for inaccuracies in this ratio due to uncertainties of the frequency of
the sampling clock.
1.6
Carrier Frequency Synchronisation
There can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and partly due to
broadcast frequency shifts, typically 1/6 MHz. These are tracked out digitally, without the need for an analogue
frequency control (AFC) loop.
The default frequency capture range has been set to ±285 kHz in the 2 K mode and ±142 kHz in the 8 K mode.
However, these values can be doubled, if necessary, by programming an on-chip register. It is recommended that
this larger capture range be used for channel scan in order to find channels with broadcast frequency shifts, without
having to adjust the tuner.
After the OFDM module has locked, the frequency offset can be read from an on-chip register.
1.7
Symbol Timing Synchronisation
This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize intersymbol interference in the presence of multi-path distortion. Furthermore, this trigger point is continuously updated
to dynamically adapt to time-variations in the transmission channel.
1.8
Fast Fourier Transform
The FFT module uses the trigger information from the timing synchronization module to set the start point for an
FFT. It then uses either a 2 K or 8K FFT to transform the data from the time domain to the frequency domain. An
extremely hardware-efficient and highly accurate algorithm has been used for this purpose.
1.9
Common Phase Error Correction
This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of
the tuner phase noise on system performance.
1.10
Channel Equalisation
This consists of two parts. The first part involves estimating the channel frequency response from pilot information.
Efficient algorithms have been used to track time-varying channels with a minimum of hardware. The second part
involves applying a correction to the data carriers based on the estimated frequency response of the channel. This
module also generates dynamic channel state information (CSI) for every carrier in every symbol.
1.11
Impulse Filtering
MT352 contains several mechanisms to reduce the impact of impulse noise on system performance.
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MT352
1.12
Data Sheet
Transmission Parameter Signalling (TPS)
An OFDM frame consists of 68 symbols and a superframe is made up of four such frames. There is a set of TPS
carriers in every symbol and all these carry one bit of TPS. These bits, when combined, include information about
the transmission mode, guard ratio, constellation, hierarchy and code rate, as defined in ETS 300 744. In addition,
the first eight bits of the cell identifier are contained in even frames and the second eight bits of the cell identifier are
in odd frames. The TPS module extracts all the TPS data, and presents these to the host processor in a structured
manner.
1.13
De-Mapper
This module generates soft decisions for demodulated bits using the channel-equalized in-phase and quadrature
components of the data carriers as well as per-carrier channel state information (CSI). The de-mapping algorithm
depends on the constellation (QPSK, 16QAM or 64QAM) and the hierarchy α = 0, 1, 2 or 3). Soft decisions for both
low- and high-priority data streams are generated.
1.14
Symbol and Bit De-Interleaving
The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The deinterleaver modules consist largely of memory to invert these interleaving functions and present the soft decisions
to the FEC in the original order.
1.15
Viterbi Decoder
The Viterbi decoder accepts the 5-bit soft decision data from the OFDM demodulator and outputs a decoded bitstream. The decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the
branch metrics and passes these to a 64-state path-metric updating unit, which in turn outputs a 64-bit word to the
survivor memory. The Viterbi decoded bits are obtained by tracing back the survivor paths in this memory. A traceback depth of 128 is used to minimize any loss in performance, especially at high code rates.
The decoder re-encodes the decoded bits and compares these with received data (delayed) to compute bit errors
at its input, on the assumption that the Viterbi output BER is significantly lower than its input BER.
1.16
MPEG Frame Aligner
The Viterbi decoded bit stream is aligned into 204-byte frames. A robust synchronization algorithm is used to
ensure correct lock and to prevent loss of lock due to noise impulses.
1.17
De-interleaver
Errors at the Viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over a
number of 204-byte frames to give the Reed-Solomon decoder a better chance of correcting these. The deinterleaver is a memory unit which implements the inverse of the convolutional interleaving function introduced by
the transmitter.
1.18
Reed-Solomon Decoder
Every 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of a
systematic (255,239) Reed-Solomon code. The corresponding (204,188) Reed-Solomon decoder is capable of
correcting up to eight byte errors in a 204-byte frame. It may also detect frames with more than eight byte errors. In
addition to efficiently performing this decoding function, the Reed-Solomon decoder in MT352 keeps a count of the
number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This
information can be used to compute the post-Viterbi BER.
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MT352
1.19
Data Sheet
De-scrambler
The de-scrambler de-randomizes the Reed-Solomon decoded data by generating the exclusive-OR of this with a
pseudo-random bit sequence (PRBS). This outputs 188-byte MPEG transports packets. The TEI bit of the packet
header is set to indicate uncorrectable packets.
1.20
MPEG Transport Interface
MPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to present
the MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard
ratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the MT352
with a clock provided by the user.
2.0
Software control
Acquisition of an OFDM channel and frequency scan for OFDM channels are controlled by an on-chip state
machine, which minimizes the software requirement in the host processor. To acquire a channel, the host programs
the channel frequency in the MT352. The on-chip state machine then writes the frequency information to the tuner,
awaits tuner lock and acquires the OFDM channel to generate the transport stream. The controller can be made to
automatically search for every parameter in the OFDM signal, including spectral inversion status. Furthermore, this
controller will re-acquire the channel in the event of an interruption to the incoming signal.
To scan a frequency range, the host programs the start and end frequencies for the search as well as the step size,
which defaults to 8 MHz. The MT352 then automatically scans the frequency range by appropriately programming
the tuner and searching for OFDM signals. Once a channel has been located, the host is interrupted to read the
channel information from the MT352. Then MT352 continues the search. By default, only the channels which can
generate a reliable transport stream are reported, but there is also provision for locating very weak channels. The
frequency capture range of MT352 can be maximized to capture channels with frequency offsets without reprogramming the tuner, in both 2 K and 8 K modes.
The above approach to channel acquisition and scan has resulted in very fast acquisition and scan times whilst
minimizing software overhead in the host processor. Furthermore, all this functionality has very efficiently been
mapped into hardware to result in a device consuming less than 220 mW of power.
3.0
Interfaces
Figure 5 - Primary Interfaces
The MT352 interfaces to other parts of a terrestrial receiver system can be partitioned into three groups: the host
controller, the tuner and the MPEG decoder. One other pin, the Status output, is multi-functional and can directly
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MT352
Data Sheet
drive a LED to show the status of a range of different internal lock flags. Alternatively, it can drive an audio
transducer to give an audio frequency that is dependent upon the error rate of the received signal.
This feature can be used for faster installation of a system where the aerial may need to be adjusted, as signal
strength is not the best guide for the optimum aerial position for COFDM reception.
3.1
2-Wire Bus
3.2
Host
The primary 2-wire bus serial interface uses pins:
•
•
DATA1 (pin 5) serial data, the most significant bit is sent first.
CLK1 (pin 4) serial clock.
The 2-wire bus address is determined by applying VDD or VSS to the SADD[4:0] pins.
In the current TNIM evaluation application, the 2-wire bus address is 0001 111 R/ W with the pins connected as
follows:
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
Not programmable
SADD[4]
SADD[3]
SADD[2]
SADD[1]
SADD[0]
VSS
VSS
VDD
VDD
VDD
VDD
VSS
Table 1 - Programmable Address Details for 2-Wire Bus in TNIM Evaluation Application
When the MT352 is powered up, the RESET pin 28 should be held low for at least 50ms after VDD has reached
normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus
address. ADDR[0] is the R/ W bit.
The circuit works as a slave transmitter with the lsb set high or as a slave receiver with the lsb set low. In receive
mode, the first data byte is written to the RADD virtual register, which forms the register sub-address. The RADD
register takes an 8-bit value that determines which of 256 possible register addresses is written to by the following
byte. Not all addresses are valid and many are reserved registers that must not be changed from their default
values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to access
the reserved registers accidentally.
Following a valid chip address, the 2-wire bus STOP command resets the RADD register to 00. If the chip address
is not recognized, the MT352 will ignore all activity until a valid chip address is received. The 2-wire bus START
command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a
particular read register with a write command, followed immediately with a read data command. If required, this
could next be followed with a write command to continue from the latest address. RADD would not be sent in this
case. Finally, a STOP command should be sent to free the bus.
When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out
is the contents of register 00.
3.2.1
Tuner
The MT352 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. Master control
mode is selected by a single register control bit.
The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2.
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MT352
3.2.2
Data Sheet
Examples of 2-Wire Bus Messages
KEY:
S
Start Condition
W
Write (=0)
P
Stop condition
R
Read (= 1)
A
Acknowledge
NA
Italics
MT352 output
RADD
NOT Acknowledge
Register Address
Write operation - as a slave receiver:
S
DEVICE
W
A
RADD
ADDRESS
A
(n)
DATA
A
(reg n)
DATA
A
P
(reg n+1)
Read operation - MT352 as a slave transmitter:
S
DEVICE
R
A
ADDRESS
DATA
A
(reg 0)
DATA
A
(reg 1)
DATA
NA
P
(reg 2)
Write/read operation with repeated start - MT352 as a slave transmitter:
S
DEVICE
W
ADDRESS
3.2.3
A
RADD
(n)
A
S
DEVICE
R
ADDRESS
A
DATA
(reg n)
Primary 2-Wire Bus Timing
Figure 6 - Primary 2-Wire Bus Timing
Where:
S = Start
Sr = Restart, i.e., start without stopping first.
P = Stop.
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A
DATA
(reg n+1)
NA
P
MT352
Data Sheet
Parameter
Value
Symbol
Min.
Unit
Max.
CLK clock frequency (Primary)
fCLK
0
450
Bus free time between a STOP and START condition
tBUFF
200
ns
Hold time (repeated) START condition
tHD;STA
200
ns
LOW period of CLK clock
tLOW
1300
ns
HIGH period of CLK clock
tHIGH
600
ns
Set-up time for a repeated START condition
tSU;STA
200
ns
Data hold time (when input)
tHD;DAT
100
ns
Data set-up time
tSU;DAT
100
ns
Rise time of both CLK and DATA signal.
tR
Fall time of both CLK and DATA signals, (100 pF to ground)
tF
20
ns
Set-up time for a STOP condition
tSU;STO
200
ns
note 1
kHz
ns
Table 2 - Timing of 2-Wire Bus
Note 1. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
3.3
3.3.1
MPEG
Data Output Header Format
Figure 7 - DVB Transport Packet Header Byte
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Zarlink Semiconductor Inc.
MT352
Data Sheet
After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.
Additionally when the ENTEI bit in the CONFIG register (0x8A) is set high (default), the TEI bit of any uncorrectable
packet will automatically be set to '1'. If ENTEI bit is low then TEI bit will not be changed (but note that if this bit is
already 1, for example, due to a channel error which has not been corrected, it will remain high at output).
3.3.2
MPEG data output signals
The MPEGEN bit in the CONFIG register must be set low to enable the MPEG data. The maximum movement in
the packet synchronization byte position is limited to ±1 output clock period. MOCLK will be a continuously running
clock once symbol lock has been achieved, and is derived from the symbol clock. In Figure 8, MOCLK is shown in
with MOCLKINV = '1', the default state.
All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK
(MOCLKINV = 1) to present stable data and signals on the positive edge of the clock.
A complete packet is output on MDO[7:0] on 188 consecutive clocks and the MDO[7:0] pins will remain low during
the inter-packet gaps. MOSTRT goes high for the first byte clock of a packet. MOVAL goes high on the first byte of
a packet and remains high until the last byte has been clocked out. BKERR goes low on the first byte of a packet
where uncorrectable bytes are detected and will remain low until the last byte has been clocked out.
Figure 8 - MPEG Output Data Waveforms
3.3.3
MPEG Output Timing
Maximum delay conditions: VDD = 3.0 V, CVDD = 1.62 V, Tamb = 70oC, Output load = 10 pF
Minimum delay conditions: VDD = 3.6 V, CVDD = 1.98 V, Tamb = 0oC, Output load = 10 pF
MOCLK frequency = 61.44 MHz.
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MT352
3.3.3.1
Data Sheet
MOCLKINV = 1
Parameter
Maximum Delay Conditions
Minimum Delay Conditions
Data output
delay tD
7 ns
0.3 ns
Setup Time
tSU
0.5 ns
5 ns
Hold Time tH
8 ns
8 ns
Table 3 - MOCLKINV = 1
The setup time is due to the delay on MOSTRT, MOVAL and BKERR. MDO[0] is faster since it uses a stronger
output driver cell.
Figure 9 - MPEG Timing - MOCLKINV = 1
3.3.3.2
MOCLKINV = 0
MDOSWAP = 0
Parameter
Maximum Delay Conditions
Minimum Delay Conditions
Data output delay tD
8 ns
0.7 ns
Setup Time tSU
8 ns
15 ns
Hold Time tH
1.5 ns
0.5 ns
Table 4 - MDOSWAP = 0
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MT352
Data Sheet
The hold time is due to the fast output on MDO[0]. If MDOSWAP is set to 1 the data output is on MDO[7] which has
a slower driver. This improves the hold time:
MDOSWAP = 1
Parameter
Maximum Delay Conditions
Minimum Delay Conditions
Data output delay tD
8 ns
0.7 ns
Setup Time tSU
8 ns
15 ns
Hold Time tH
3 ns
1.2 ns
Table 5 - MDOSWAP = 1
Figure 10 - MPEG Timing - MOCLKINV = 0
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MT352
4.0
Electrical Characteristics
4.1
Recommended Operating Conditions
Data Sheet
Recommended Operating Conditions Table
Parameter
Power supply voltage:
Power supply current:
Symbol
Min.
Typ.
Max.
Units
periphery
VDD
3·0
3·3
3·6
V
core
CVDD
1·62
1·8
1·98
V
periphery 1
IDDP
1
mA
core
IDDC
120
mA
Input clock frequency 2
XTI
CLK1 primary serial clock frequency
fCLK
16·00
Ambient operating temperature
20·48
0
ADC Input Impedance @ 36 MHz
25·00
MHz
450
kHz
70
°C
2
kΩ
1. Current from the 3·3 VV supply will be mainly dependent on the external loads.
2. The min/max frequencies given are those supported by the oscillator cell. Frequencies outside these limits are acceptable with an
external clock signal.
4.2
Absolute maximum ratings
Absolute Maximum Ratings Table
Parameter
Symbol
Power supply
Min.
Max.
Unit
VDD
-0.3
+3.6
V
CVDD
-0.3
+2.0
V
Voltage on input pins (5 V rated)
VI
-0.3
5.5
V
Voltage on input pins (3.3 V rated)
VI
-0.3
VDD + 0.3
V
Voltage on output pins (5 V rated)
VO
-0.3
5.5
V
Voltage on output pins (3.3 V rated)
VO
-0.3
VDD + 0.3
V
Storage temperature
TSTG
-55
150
°C
Operating ambient temperature
TOP
0
70
°C
Junction temperature
TJ
125
°C
Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. Exposure to absolute maximum ratings for
extended periods may reduce reliability. Functionality at or above these conditions is not implied.
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MT352
4.3
Data Sheet
DC Electrical Characteristics
Parameter
Operating
Conditions
Pins
Symbol
Min.
periphery
VDD
3.0
core
CVDD
1.62
Typ.
Max.
Unit
3.3
3.6
V
1.8
1.98
V
voltage
Supply current
1.62 > CVDD >
1.98
IDDCORE
Supply current sleep mode
120
mA
200
µA
Outputs
Output levels
IOH 2 mA
MDO(7:0), MOVAL,
3.0 > VDD > 3.6
MOSTRT, MOCLK,
STATUS, BKERR
IOL 2 mA
VOH
2.4
V
VOL
0.4
V
VOL
0.4
V
3.0 > VDD > 3.6
IOL 6 mA
3.0 > VDD > 3.6
GPP(3:0), DATA1,
AGC1, AGC2, IRQ
MDO(7:0), MOVAL,
3.0
pF
3.6
pF
MOSTRT, MOCLK,
Output capacitance
Not including
track
STATUS, BKERR
GPP(3:0), DATA1,
AGC1, AGC2 IRQ
Output leakage (tri-state)
1
µA
Inputs
Input levels
3.0 > VDD > 3.6
-0.5 ≥ Vin ≥
VDD+0.5 V
Input levels
3.0 > VDD > 3.6
-0.5 ≥ Vin ≥
MICLK, SADD(4:0),
SLEEP, OSCMODE
VIH
2.0
V
GPP(3:0), CLK1,
DATA1, RESET
VIH
2.0
V
All inputs
VIL
+5.5 V
Input levels
Input leakage Current
Input capacitance
Input capacitance
3.0 > VDD >
3.6
Capacitances
do not include
track
SLEEP, SMTEST,
MICLK, CLK1,
OSCMODE
SADD(4:0), DATA1,
GPP(3:0)
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0.8
V
±1
µA
1.8
pF
3.6
pF
MT352
4.4
Data Sheet
Crystal Specification and External Clocking
Parallel resonant fundamental frequency (preferred)
20.4800 MHz
Tolerance over operating temperature range
± 25 ppm
Tolerance overall
± 50 ppm
Typical load capacitance
27 pF
Drive level
0.4 mW max.
Equivalent series resistance
<50 Ω
XTI
XTO
OSCMODE
XT1
C1
C2
Figure 11 - Crystal Oscillator Circuit
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MT352
5.0
Application Circuit
Figure 12 - Typical Application Circuit
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Zarlink Semiconductor Inc.
Data Sheet
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