CY7S1049G CY7S1049GE 4-Mbit (512K words × 8 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC) 4-Mbit (512K words × 8 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC) Features embedded ECC. logic which can detect and correct single-bit errors in the accessed location. Deep-Sleep input (DS) must be deasserted HIGH for normal operating mode. ■ High speed ❐ Access time (tAA) = 10 ns / 15 ns ■ Ultra-low power Deep-Sleep (DS) current ❐ IDS = 15 µA ■ Low active and standby currents ❐ Active Current ICC = 38-mA typical ❐ Standby Current ISB2 = 6-mA typical ■ Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V ■ Embedded ECC for single-bit error correction ■ Error indication (ERR) pin to indicate 1-bit error detection and correction ■ 1.0-V data retention ■ TTL- compatible inputs and outputs ■ Available in Pb-free 44-pin TSOP II, and 36-pin (400-mil) molded SOJ To perform data writes, assert the Chip Enable (CE) and Write Enable (WE) inputs LOW, and provide the data and address on device data pins (I/O0 through I/O7) and address pins (A0 through A18) respectively. To perform data reads, assert the Chip Enable (CE) and Output Enable (OE) inputs LOW and provide the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O7). The device is placed in a low-power Deep-Sleep mode when the Deep-Sleep input (DS) is asserted LOW. In this state, the device is disabled for normal operation and is placed in a low power data retention mode. The device can be activated by deasserting the Deep-Sleep input (DS) to HIGH. The CY7S1049G is available in 44-pin TSOP II, and 36-pin Molded SOJ (400 Mils). Functional Description The CY7S1049G/CY7S1049GE is a high-performance PowerSnooze™ static RAM organized as 512K words × 8 bits. This device features fast access times (10 ns) and a unique ultra-low power Deep-Sleep mode. With Deep-Sleep mode currents as low as 15 µA, the CY7S1049G/CY7S1049GE devices combine the best features of fast and low- power SRAMs in industry-standard package options. The device also features Product Portfolio Power Dissipation Product [1] CY7S1049G(E)18 Range Industrial CY7S1049G(E)30 VCC Range (V) Speed (ns) Operating ICC, (mA) f = fmax Deep-Sleep current (µA) Typ [2] Max Typ [2] Max Typ [2] Max 6 8 – 15 1.65 V–2.2 V 15 – 40 2.2 V–3.6 V 10 38 45 4.5–5.5 V 10 38 45 CY7S1049G(E) Standby, ISB2 (mA) Notes 1. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V (for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C. Cypress Semiconductor Corporation Document Number: 001-95414 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 18, 2016 CY7S1049G CY7S1049GE Logic Block Diagram – CY7S1049G SENSE AMPLIFIERS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ECC DECODER DATAIN DRIVERS ECC ENCODER 512K x 8 RAM ARRAY I/O0‐I/O7 COLUMN DECODER A10 A11 A12 A13 A14 A15 A16 A17 A18 WE OE DS CE Power Management Block Logic Block Diagram – CY7S1049GE I/O0‐I/O7 ERR WE OE CE A10 A11 A12 A13 A14 A15 A16 A17 A18 COLUMN DECODER ECC DECODER 512K x 8 RAM ARRAY DATAIN DRIVERS SENSE AMPLIFIERS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER ECC ENCODER DS Power Management Block Document Number: 001-95414 Rev. *C Page 2 of 21 CY7S1049G CY7S1049GE Contents Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 DC Electrical Characteristics .......................................... 6 Capacitance ...................................................................... 7 Thermal Resistance .......................................................... 7 AC Test Loads and Waveforms ....................................... 8 Data Retention Characteristics ....................................... 9 Data Retention Waveform ................................................ 9 Deep-Sleep Mode Characteristics ................................. 10 AC Switching Characteristics ....................................... 11 Switching Waveforms .................................................... 12 Truth Table ...................................................................... 16 ERR Output – CY7S1049GE ........................................... 16 Document Number: 001-95414 Rev. *C Ordering Information ...................................................... 17 Ordering Code Definitions ......................................... 17 Package Diagrams .......................................................... 18 Acronyms ........................................................................ 19 Document Conventions ................................................. 19 Units of Measure ....................................................... 19 Document History Page ................................................. 20 Sales, Solutions, and Legal Information ...................... 21 Worldwide Sales and Design Support ....................... 21 Products .................................................................... 21 PSoC® Solutions ...................................................... 21 Cypress Developer Community ................................. 21 Technical Support ..................................................... 21 Page 3 of 21 CY7S1049G CY7S1049GE Pin Configurations Figure 1. 44-pin TSOP II pinout without ERR [3] NC NC A0 A1 A2 A3 A4 /CE I/O0 I/O1 VCC VSS I/O2 I/O3 /WE A5 A6 A7 A8 A9 NC NC 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 44-pin TSOP II 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 NC NC DS A18 A17 A16 A15 /OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC Figure 2. 44-pin TSOP II pinout with ERR [3, 4] NC NC A0 A1 A2 A3 A4 /CE I/O0 I/O1 VCC VSS I/O2 I/O3 /WE A5 A6 A7 A8 A9 NC NC 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 44-pin TSOP II 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 NC NC DS A18 A17 A16 A15 /OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC ERR NC Notes 3. NC pins are not connected internally to the die. 4. ERR is an output pin. Document Number: 001-95414 Rev. *C Page 4 of 21 CY7S1049G CY7S1049GE Pin Configurations (continued) Figure 3. 36-pin SOJ pinout without ERR [5] A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SOJ 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 DS A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC Figure 4. 36-pin SOJ pinout with ERR [5, 6] A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SOJ 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 DS A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 ERR Notes 5. NC pins are not connected internally to the die. 6. ERR is an output pin. Document Number: 001-95414 Rev. *C Page 5 of 21 CY7S1049G CY7S1049GE DC input voltage [7] ............................. –0.5 V to VCC + 0.5 V Maximum Ratings Current into outputs (LOW) ........................................ 20 mA Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static discharge voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Storage temperature ................................ –65 C to +150 C Latch-up current .................................................... > 140 mA Ambient temperature with power applied .......................................... –55 C to +125 C Operating Range Supply voltage on VCC relative to GND [7] ............................... –0.5 V to VCC + 0.5 V DC voltage applied to outputs in HI-Z State [7] ................................... –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Industrial –40 C to +85 C 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V DC Electrical Characteristics Over the Operating Range of –40 C to +85 C Parameter VOH VOL VIH[7, 10] VIL [7, 10] Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions 10 ns/ 15 ns Min Typ [8] Max Unit 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – 2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – – 2.7 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.2 – – 4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – – 4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.5 [9] – – 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4 4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4 1.65 V to 2.2 V – 1.4 – VCC + 0.2 2.2 V to 2.7 V – 2 – VCC + 0.3 2.7 V to 3.6 V – 2 – VCC + 0.3 4.5 V to 5.5 V – 2.2 – VCC + 0.5 1.65 V to 2.2 V – –0.2 – 0.4 2.2 V to 2.7 V – –0.3 – 0.6 2.7 V to 3.6 V – –0.3 – 0.8 4.5 V to 5.5 V – –0.5 – 0.8 GND < VIN < VCC –1 – +1 A A V V V V IIX Input leakage current IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 VCC operating supply current VCC = Max, IOUT = 0 mA, CMOS levels f = 100 MHz – 38 45 f = 66.7 MHz – – 40 mA Standby current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – – 15 mA ICC ISB1 Notes 7. VIL (min) = –2.0 V and VIH (max) = VCC + 2 V for pulse durations of less than 2 ns. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V (for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C. 9. Guaranteed by design and not tested. 10. For the DS pin, VIH (min) is VCC – 0.2 V and VIL (max) is 0.2 V. Document Number: 001-95414 Rev. *C Page 6 of 21 CY7S1049G CY7S1049GE DC Electrical Characteristics (continued) Over the Operating Range of –40 C to +85 C Parameter Description Test Conditions ISB2 Standby current – CMOS inputs Max VCC, CE > VCC – 0.2 V, DS > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 IDS Deep-Sleep current Max VCC, CE > VCC – 0.2 V, DS < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 10 ns/ 15 ns Unit Min Typ [8] Max – 6 8 mA – – 15 µA Capacitance Parameter [11] Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC(typ) All packages Unit 10 pF 10 pF Thermal Resistance Parameter [11] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) 44-pin TSOP II Unit Package Test Conditions 36-pin SOJ Package Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 59.52 68.85 C/W 31.48 15.97 C/W Note 11. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-95414 Rev. *C Page 7 of 21 CY7S1049G CY7S1049GE AC Test Loads and Waveforms Figure 5. AC Test Loads and Waveforms [12] HI-Z Characteristics: VCC 50 Output VTH Z0 = 50 R1 Output 30 pF* * Including JIG and Scope (a) * Capacitive Load Consists of all Components of the Test Environment (b) All Input Pulses VHIGH GND R2 5 pF* 90% 90% 10% Rise Time: > 1 V/ns 10% (c) Fall Time: > 1 V/ns Parameters 1.8 V 3.0 V 5.0 V Unit R1 1667 317 317 R2 1538 351 351 VTH VCC/2 1.5 1.5 V VHIGH 1.8 3.0 3.0 V Note 12. Full-device AC operation assumes a 100-s ramp time from 0 to VCC(min) or 100-s wait time after VCC stabilization. Document Number: 001-95414 Rev. *C Page 8 of 21 CY7S1049G CY7S1049GE Data Retention Characteristics Over the Operating Range of –40C to +85 C Parameter Conditions [13] Description Min Max Unit 1.0 – V – 8 mA 0 – ns 2.2 V < VCC < 5.5 V 10 – ns VCC < 2.2 V 15 – ns VDR VCC for data retention – ICCDR Data retention current VCC = VDR, CE > VCC – 0.2 V, DS > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V tCDR [14] Chip deselect to data retention time tR[14, 15] Operation recovery time – Data Retention Waveform Figure 6. Data Retention Waveform [15] VCC VCC(min) DATA RETENTION MODE VDR = 1.0 V tCDR VCC(min) tR CE Notes 13. DS signal must be HIGH during Data Retention Mode. 14. These parameters are guaranteed by design. 15. Full-device operation requires linear VCC ramp from VDR to VCC(min.) 100 s or stable at VCC(min.) 100 s. Document Number: 001-95414 Rev. *C Page 9 of 21 CY7S1049G CY7S1049GE Deep-Sleep Mode Characteristics Over the Operating Range of –40 C to +85 C Parameter Description Conditions VCC = VCC (max), DS < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Min Max Unit – 15 µA IDS Deep-Sleep mode current tPDS[16] Minimum time for DS to be LOW for part to successfully exit – Deep-Sleep mode 100 – ns tDS[17] DS assertion to Deep-Sleep – mode transition time – 1 ms tDSCD[16] DS deassertion to chip disable If tPDS > tPDS(min) – 100 s If tPDS < tPDS(min) – 0 s tDSCA DS deassertion to chip access If tPDS > tPDS(min) (Active/Standby) If tPDS < tPDS(min) 300 – s Figure 7. Active, Standby, and Deep-Sleep Operation Modes Chip Access Allowed Not Allowed CE ENABLE/ DISABLE DON’T CARE Allowed DISABLE ENABLE/ DISABLE tPDS DS tDSCD tDS Mode Active/Standby Mode Standby Mode Deep Sleep Mode tDSCA Standby Mode Active/Standby Mode Note 16. CE must be pulled HIGH within tDSCD time of DS de-assertion to avoid SRAM data loss. 17. After assertion of DS signal, device will take a maximum of tDS time to stabilize to Deep-Sleep current IDS. During this period, DS signal must continue to be asserted to logic level LOW to keep the device in Deep-Sleep mode. Document Number: 001-95414 Rev. *C Page 10 of 21 CY7S1049G CY7S1049GE AC Switching Characteristics Over the Operating Range of –40 C to +85 C Parameter [18] Description 10 ns 15 ns Min Max Min Max Unit Read Cycle tRC Read cycle time 10 – 15 – ns tAA Address to data valid – 10 – 15 ns tOHA Data hold from address change 3 – 3 – ns tACE CE LOW to data valid – 10 – 15 ns tDOE OE LOW to data valid – 4.5 – 8 ns 0 – 0 – ns – 5 – 8 ns 3 – 3 – ns – 5 – 8 ns 0 – 0 – ns – 10 – 15 ns tLZOE OE LOW to low impedance tHZOE [19, 20, 21] OE HIGH to HI-Z tLZCE CE LOW to low impedance tHZCE CE HIGH to HI-Z [19, 20, 21] tPU tPD Write Cycle CE LOW to power-up [19, 20, 21] [19, 20, 21] [21] CE HIGH to power-down [21] [22, 23] tWC Write cycle time 10 – 15 – ns tSCE CE LOW to write end 7 – 12 – ns tAW Address setup to write end 7 – 12 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7 – 12 – ns tSD Data setup to write end 5 – 8 – ns tHD Data hold from write end 0 – 0 – ns tLZWE WE HIGH to low impedance [19, 20, 21] 3 – 3 – ns – 5 – 8 ns tHZWE WE LOW to HI-Z [19, 20, 21] Notes 18. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in part (a) of Figure 5 on page 8, unless specified otherwise. 19. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 8. Transition is measured 200 mV from steady state voltage. 20. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 21. These parameters are guaranteed by design. 22. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and WE, CE, signals must be LOW and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, signals or LOW transition on DS signal can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 23. The minimum write pulse width for Write Cycle No. 2 (WE controlled, OE LOW) should be the sum of tHZWE and tSD. Document Number: 001-95414 Rev. *C Page 11 of 21 CY7S1049G CY7S1049GE Switching Waveforms Figure 8. Read Cycle No. 1 of CY7S1049G (Address Transition Controlled) [24, 25, 26] tRC ADDRESS tAA tOHA PREVIOUS DATAOUT VALID DATA I/O DATAOUT VALID Figure 9. Read Cycle No. 2 of CY7S1041GE (Address Transition Controlled) [24, 25, 26] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID tAA tOHA ERR PREVIOUS ERR VALID ERR VALID Notes 24. The device is continuously selected. OE = VIL, CE = VIL. 25. WE is HIGH for read cycle. 26. DS is HIGH for chip access. Document Number: 001-95414 Rev. *C Page 12 of 21 CY7S1049G CY7S1049GE Switching Waveforms (continued) Figure 10. Read Cycle No. 3 (OE Controlled) [27, 28, 29] ADDRESS tRC CE tPD t HZCE t ACE OE t HZOE t DOE t LZOE DATA I /O HIGH IMPEDANCE DATA OUT VALID HIGH IMPEDANCE t LZCE tPU VCC SUPPLY CURRENT ISB Notes 27. WE is HIGH for read cycle. 28. Address valid prior to or coincident with CE LOW transition. 29. DS must be HIGH for chip access Document Number: 001-95414 Rev. *C Page 13 of 21 CY7S1049G CY7S1049GE Switching Waveforms (continued) Figure 11. Write Cycle No. 1 (CE Controlled) [30, 31, 32] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE OE tHZOE tHD tSD DATA I/O DATAIN VALID Figure 12. Write Cycle No. 2 (WE Controlled, OE LOW) [30, 31, 32, 33] tW C AD D R ES S t S CE CE tS A tA W tH A tP W E WE t H ZW E D ATA I/O tS D t LZW E tH D D A TA IN VA LID Notes 30. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, DS = VIH and WE, CE signals must be LOW and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE signals or LOW transition on DS signal can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 31. Data I/O is in HI-Z state if CE = VIH, or OE = VIH. 32. DS must be HIGH for chip access. 33. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 001-95414 Rev. *C Page 14 of 21 CY7S1049G CY7S1049GE Switching Waveforms (continued) Figure 13. Write Cycle No. 3 (WE Controlled) [34, 35, 36] tW C ADDRESS tS C E CE tA W tS A tH A tP W E WE OE tH Z O E D A T A I/O tH D tS D D A T A IN V A L ID Note 37 Notes 34. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, DS = VIH and WE, CE, signals must be LOW and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, signals or LOW transition on DS signal can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 35. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or DS = VIL. 36. DS must be HIGH for chip access. 37. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-95414 Rev. *C Page 15 of 21 CY7S1049G CY7S1049GE Truth Table DS CE OE [38] X WE I/O0–I/O7 Mode Power [38] HIGH-Z Standby Standby (ISB) H H X H L L H Data out Read all bits Active (ICC) H L X L Data in Write all bits Active (ICC) H L H H HI-Z Selected, outputs disabled Active (ICC) L[39] X X X HI-Z Deep-Sleep Deep-Sleep Ultra Low Power (IDS) ERR Output – CY7S1049GE Output [40] Mode 0 Read operation, no single-bit error in the stored data. 1 Read operation, single-bit error detected and corrected. High-Z Device deselected / outputs disabled / Write operation Notes 38. The input voltage levels on these pins should be either at VIH or VIL. 39. VIL on DS must be < 0.2 V. 40. ERR is an Output pin.If not used, this pin should be left floating. Document Number: 001-95414 Rev. *C Page 16 of 21 CY7S1049G CY7S1049GE Ordering Information Speed (ns) 10 Voltage Range 2.2 V–3.6 V Ordering Code CY7S1049G30-10VXI Package Diagram Package Type (All Pb-free) 51-85090 36-pin SOJ CY7S1049GE30-10VXI Operating Range Industrial 36-pin SOJ, With ERR pin Ordering Code Definitions CY 7 S 1 04 9 G X XX - XX XX X X Temperature Range: X = I I = Industrial Pb-free Package Type: XX = V V = 36-pin SOJ Speed: XX = 10 10 = 10 ns Voltage Range: XX = 30 30 = 2.2 V to 3.6 V X = blank or E; blank= without ERR output, E = with ERR pin Process Technology: Revision Code “G” = 65 nm Technology Data width: 9 = × 8-bits Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family S = Deep-Sleep feature Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-95414 Rev. *C Page 17 of 21 CY7S1049G CY7S1049GE Package Diagrams Figure 14. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090 51-85090 *G Figure 15. 44-pin TSOP II Package Outline, 51-85087 51-85087 *E Document Number: 001-95414 Rev. *C Page 18 of 21 CY7S1049G CY7S1049GE Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C Degrees Celsius ECC error correcting code MHz megahertz I/O input/output A microamperes OE output enable s microseconds SOJ small outline J-lead mA milliamperes SRAM static random access memory mm millimeters TSOP thin small outline package ns nanoseconds TTL transistor-transistor logic ohms WE write enable % percent pF picofarads V volts W watts Document Number: 001-95414 Rev. *C Symbol Unit of Measure Page 19 of 21 CY7S1049G CY7S1049GE Document History Page Document Title: CY7S1049G/CY7S1049GE, 4-Mbit (512K words × 8 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC) Document Number: 001-95414 Rev. ECN No. Orig. of Change Submission Date *B 5025315 VINI 11/24/2015 Changed status from Preliminary to Final. *C 5090263 NILE 01/18/2016 Updated Ordering Information: Updated part numbers. Completing Sunset Review. Document Number: 001-95414 Rev. *C Description of Change Page 20 of 21 CY7S1049G CY7S1049GE Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2015-2016. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-95414 Rev. *C Revised January 18, 2016 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 21 of 21