TI1 LP87524B-Q1 4-a 2.5-a two 1.5-a buck converters with integrated switch Datasheet

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LP87524B-Q1, LP87524J-Q1
SNVSAW2A – APRIL 2017 – REVISED NOVEMBER 2017
LP87524B/J-Q1 4-A + 2.5-A + Two 1.5-A Buck Converters With Integrated Switches
1 Features
3 Description
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•
The LP87524B/J-Q1 is designed to meet the power
management requirements of the latest processors
and platforms in various automotive power
applications. The device contains four step-down DCDC converter cores, which are configured as 4 single
phase outputs. The device is controlled by an I2Ccompatible serial interface and by enable signals.
1
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•
•
•
•
•
•
•
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Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Input Voltage: 2.8 V to 5.5 V
Output Voltage: 0.6 V to 3.36 V
Four High-Efficiency Step-Down DC-DC Converter
Cores:
– Total Output Current Up To 10 A
– Output Voltage Slew-Rate 3.8 mV/µs
4-MHz Switching Frequency
Spread-Spectrum Mode and Phase Interleaving
Configurable General Purpose I/O (GPIOs)
I2C-Compatible Interface which Supports Standard
(100 kHz), Fast (400 kHz), Fast+ (1 MHz), and
High-Speed (3.4 MHz) Modes
Interrupt Function with Programmable Masking
Programmable Power Good Signal (PGOOD)
Output Short-Circuit and Overload Protection
Overtemperature Warning and Protection
Overvoltage Protection (OVP) and Undervoltage
Lockout (UVLO)
The automatic PFM/PWM (AUTO mode) operation
maximizes efficiency over a wide output-current
range. The LP87524B/J-Q1 supports remote voltage
sensing to compensate IR drop between the regulator
output and the point-of-load (POL) thus improving the
accuracy of the output voltage. In addition the
switching clock can be forced to PWM mode and also
synchronized to an external clock to minimize the
disturbances.
The LP87524B/J-Q1 device supports load-current
measurement without the addition of external currentsense resistors. In addition, the LP87524B/J-Q1
supports programmable start-up and shutdown
delays and sequences synchronized to enable
signals. The sequences can also include GPIO
signals to control external regulators, load switches
and processor reset. During start-up and voltage
change, the device controls the output slew rate to
minimize output voltage overshoot and the in-rush
current.
2 Applications
Automotive Infotainment, Cluster, Radar, and
Camera Power Applications
space
space
Simplified Schematic
Device Information(1)
PART NUMBER
LP87524B-Q1
LP87524J-Q1
VIN_B0
FB_B0
VIN_B2
VANA
VOUT2
SW_B1
PART NUMBER
Buck2 1.8 V, Buck3 2.3 V
LP87524J-Q1
Buck2 1 V, Buck3 1.8 V
LOAD
FB_B1
Efficiency vs Output Current
SDA
nINT
VOLTAGE
LP87524B-Q1
NRST
SCL
4.50 mm × 4.00 mm
Output Voltage Options
LOAD
VIN_B1
VIN_B3
VQFN-HR (26)
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
VOUT1
SW_B0
VIN
PACKAGE
100
VOUT3
SW_B2
LOAD
90
FB_B2
EN1 (GPIO1)
VOUT4
EN2 (GPIO2)
SW_B3
EN3 (GPIO3)
FB_B3
LOAD
Efficiency (%)
CLKIN
80
70
PGOOD
GNDs
Copyright © 2017, Texas Instruments Incorporated
60
50
0.001
1PH, VOUT = 1V, AUTO
1PH, VOUT = 1.8V, AUTO
1PH, VOUT = 2.5V, AUTO
0.01
0.1
Output Current (A)
1
5
D922
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP87524B-Q1, LP87524J-Q1
SNVSAW2A – APRIL 2017 – REVISED NOVEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
1
1
1
2
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
I2C Serial Bus Timing Requirements...................... 10
Typical Characteristics ............................................ 12
7.5 Programming........................................................... 31
7.6 Register Maps ......................................................... 34
8
8.1 Application Information............................................ 56
8.2 Typical Application .................................................. 56
9 Power Supply Recommendations...................... 62
10 Layout................................................................... 63
10.1 Layout Guidelines ................................................. 63
10.2 Layout Example .................................................... 64
11 Device and Documentation Support ................. 65
11.1
11.2
11.3
11.4
11.5
11.6
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Descriptions ...............................................
Device Functional Modes........................................
13
14
14
29
Application and Implementation ........................ 56
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
65
65
65
65
65
65
12 Mechanical, Packaging, and Orderable
Information ........................................................... 65
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (April 2017) to Revision A
•
2
Page
Added LP87524J-Q1 GPN to SNVSAW2 data sheet ........................................................................................................... 1
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LP87524J-Q1
LP87524B-Q1, LP87524J-Q1
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SNVSAW2A – APRIL 2017 – REVISED NOVEMBER 2017
5 Pin Configuration and Functions
RNF Package
26-Pin VQFN With Thermal Pad
Top View
VIN_B3
3
22
SW_B3
EN3
23
PGND_B23
2
24
SW_B2
FB_B2
25
VIN_B2
1
26
FB_B3
21
NRST
20
CLKIN
nINT
19
4
AGND
VANA
18
5
SCL
AGND
17
6
SDA
PGOOD
16
7
EN1
EN2
15
8
FB_B0
FB_B1
14
AGND
VIN_B0
SW_B0
PGND_B01
SW_B1
VIN_B1
9
10
11
12
13
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Pin Functions
PIN
TYPE
DESCRIPTION
NUMBER
NAME
1
FB_B2
A
2
EN3
D/I/O
3
CLKIN
D/I
External clock input. Connect to ground if external clock is not used.
4, 17,
Thermal Pad
AGND
G
Ground
Serial interface clock input for I2C access. Connect a pullup resistor.
Output voltage feedback (positive) for Buck2.
Programmable enable signal for buck regulators (can be also configured to select between two
buck output voltage levels). Alternative function is GPIO3.
5
SCL
D/I
6
SDA
D/I/O
Serial interface data input and output for I2C access. Connect a pullup resistor.
7
EN1
D/I/O
Programmable Enable signal for buck regulators (can be also configured to select between two
buck output voltage levels). Alternative function is GPIO1.
8
FB_B0
A
Output voltage feedback (positive) for Buck0
9
VIN_B0
P
Input for Buck0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
10
SW_B0
A
Buck0 switch node
11
PGND_B01
G
Power ground for Buck0 and Buck1
12
SW_B1
A
Buck1 switch node
13
VIN_B1
P
Input for Buck1. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
14
FB_B1
A
Output voltage feedback (positive) for Buck1.
15
EN2
D/I/O
Programmable enable signal for Buck regulators (can be also configured to select between two
buck output voltage levels). Alternative function is GPIO2.
16
PGOOD
D/O
Power Good indication signal
18
VANA
P
19
nINT
D/O
Open-drain interrupt output, active LOW
20
NRST
D/I
Reset signal for the device.
21
FB_B3
A
Output voltage feedback (positive) for Buck3.
22
VIN_B3
P
Input for Buck3. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
Supply voltage for analog and digital blocks. Must be connected to same node as with VIN_Bx.
23
SW_B3
A
Buck3 switch node
24
PGND_B23
G
Power Ground for Buck2 and Buck3
25
SW_B2
A
Buck2 switch node
26
VIN_B2
P
Input for Buck2. The separate power pins VIN_Bx are not connected together internally – VIN_Bx
pins must be connected together in the application and be locally bypassed.
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
4
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
UNIT
Voltage on power connections
VIN_Bx, VANA
–0.3
6
V
Voltage on buck switch nodes
SW_Bx
–0.3
(VIN_Bx + 0.3 V) with 6 V
maximum
V
Voltage on buck voltage sense nodes
FB_Bx
–0.3
(VANA + 0.3 V) with 6 V
maximum
V
Voltage on NRST input
NRST
–0.3
6
V
Voltage on logic pins
(input or output pins)
SDA, SCL, nINT, CLKIN
–0.3
6
V
Voltage on logic pins
(input or output pins)
EN1 (GPIO1), EN2 (GPIO2), EN3
(GPIO3), PGOOD
–0.3
(VANA + 0.3 V) with 6 V
maximum
V
Junction temperature, TJ-MAX
−40
150
°C
Storage temperature, Tstg
–65
150
°C
260
°C
Maximum lead temperature (soldering, 10 sec.)
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002 (1)
V(ESD)
(1)
Electrostatic
discharge
Charged-device model (CDM), per AEC Q100-011
UNIT
±2000
All pins
±500
Corner pins (1, 8, 14 and 21)
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
INPUT VOLTAGE
Voltage on power connections
VIN_Bx, VANA
2.8
5.5
V
Voltage on NRST
NRST
1.65
VANA with 5.5 V
maximum
V
Voltage on logic pins
nINT, CLKIN
1.65
5.5
V
Voltage on logic pins
(input or output pins)
ENx, PGOOD
0
VANA with 5.5 V
maximum
V
1.65
1.95
V
3.1
VANA with 3.6 V
maximum
V
Junction temperature, TJ
−40
140
°C
Ambient temperature, TA
−40
125
°C
Voltage on I2C interface, standard (100
kHz), fast (400 khz), fast+ (1 MHz), and
high-speed (3.4 MHz) modes
Voltage on I2C interface, standard (100
kHz), fast (400 kHz), and fast+ (1 MHz)
modes
SCL, SDA
TEMPERATURE
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6.4 Thermal Information
LP875xx-Q1
THERMAL METRIC (1)
RNF (VQFN)
UNIT
26 PINS
RθJA
Junction-to-ambient thermal resistance
34.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
16.5
°C/W
RθJB
Junction-to-board thermal resistance
4.7
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
4.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EXTERNAL COMPONENTS
CIN
Input filtering
capacitance
Connected from VIN_Bx to PGND_Bx
1.9
10
µF
COUT
Output filtering
Capacitance, local
Capacitance per phase
10
22
µF
CPOL
Point-of-Load (POL)
capacitance
Optional POL capacitance per phase
22
µF
COUT-
Output capacitance,
total (local and POL)
Total output capacitance, 1-phase output
ESRC
Input and output
capacitor ESR
[1-10] MHz
L
Inductor
Inductance of the inductor
DCRL
Inductor DCR
TOTAL
2
100
µF
10
mΩ
0.47
–30%
µH
30%
25
mΩ
BUCK REGULATOR
VVIN_Bx
Input voltage range
VVOUT_Bx
Output voltage
2.8
3.36
Programmable voltage range, 2.8 V ≤
VVIN_Bx ≤ 5.5 V
1.0
3.36
10
Step size, 0.73 V ≤ VOUT < 1.4 V
5
Step size, 1.4 V ≤ VOUT ≤ 3.36 V
20
(1)
(2)
(3)
6
mV
1.5 (3)
Buck2: VIN ≥ 3 V
4 (3)
Buck2: 2.8 V ≤ VIN < 3 V
3 (3)
A
2.5 (3)
Buck3
Input and output
voltage difference
V
V
Buck0, Buck1
Output current
5.5
0.6
Step size, 0.6 V ≤ VOUT < 0.73 V
IOUT
3.7
Programmable voltage range, 2.8 V ≤
VVIN_Bx ≤ 4 V
Minimum voltage between VIN_x and
VOUT to fulfill the electrical characteristics
0.5
V
All voltage values are with respect to network ground.
Minimum (Min) and Maximum (Max) limits are specified by design, test, or statistical analysis. Typical (Typ) numbers are not verified, but
do represent the most likely norm.
The maximum output current can be limited by the forward current limit ILIM FWD and by the junction temperature. The power dissipation
inside the die depends on the length of the current pulse and efficiency and the junction temperature may increase to thermal shutdown
level if the board and ambient temperatures are high.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
PARAMETER
VVOUT_DC
DC output voltage
accuracy, includes
voltage reference, DC
load and line
regulations, process
and temperature
Ripple voltage
TEST CONDITIONS
VOUT ≥ 1 V, PWM mode
–2%
2%
VOUT < 1 V, PFM mode
–20
40
VOUT ≥ 1 V, PFM mode
–2%
2% + 20 mV
PWM mode, ESRC < 2 mΩ, L = 0.47 µH
14
0.1
DCLDR
DC load regulation in
PWM mode
VOUT = 1 V, IOUT from 0 to IOUT(max)
ILIM
ILIM
FWD
NEG
RDS(ON) HS
FET
RDS(ON) LS
FET
Transient line response
Forward current limit
(peak for every
switching cycle)
UNIT
mV
mV
mVp-p
%/V
0.8%
–3%
3%
mV
IOUT = 0.1 A to 2 A, TR = TF = 1 µs, PWM
mode, COUT = 22 µF, L = 0.47 µH, CPOL =
22 µF
±40
VVIN_Bx stepping 3 V ↔ 3.5 V, TR = TF = 10
µs, IOUT = IOUT(max)
±5
mV
Buck0, Buck1: VVIN_Bx ≥ 3 V
2.3
2.7
3.0
Buck0, Buck1: 2.8 V ≤ VVIN_Bx < 3 V
2.0
2.7
3.0
Buck2: VVIN_Bx ≥ 3 V
4.7
5.4
6.0
Buck2: 2.8 V ≤ VVIN_Bx < 3 V
4.0
5.4
6.0
Buck3: VVIN_Bx ≥ 3 V
4.2
4.8
5.4
Buck3: 2.8 V ≤ VVIN_Bx < 3 V
3.6
4.8
5.4
1.6
2
2.4
A
29
65
mΩ
17
35
mΩ
Each phase, between VIN_Bx and SW_Bx
pins (I = 1 A)
On-resistance, low-side Each phase, between SW_Bx and
FET
PGND_Bx pins (I = 1 A)
Switching frequency,
PWM mode
fSW
IOUT = 0 A to 2 A, TR = TF = 10 µs, PWM
mode, COUT = 22 µF, L = 0.47 µH, CPOL =
22 µF
Negative current limit /
phase (peak for every
switching cycle)
On-resistance, highside FET
4
PFM mode, L = 0.47 µH
IOUT = IOUT(max)
TLNSR
MAX
20
DC line regulation
TLDSR
TYP
–20
DCLNR
Transient load step
response
MIN
VOUT < 1 V, PWM mode
VOUT > 0.8
3.6
4
4.4
0.6 < VOUT ≤ 0.8
2.7
3
3.3
VOUT = 0.6
1.8
2
2.2
From ENx to VOUT = 0.35 V (slew-rate
Start-up time (soft start)
control begins), COUT_TOTAL = 44 µF / phase
Output voltage slewrate (4)
200
3.23
3.8
A
MHz
µs
4.4
mV/µs
IPFM-PWM
PFM-to-PWM - current
threshold (5)
600
mA
IPWM-PFM
PWM-to-PFM - current
threshold (5)
200
mA
Output pulldown
resistance
(4)
(5)
Regulator disabled
160
230
300
Ω
Output capacitance, forward and negative current limits and load current may limit the maximum and minimum slew rates.
The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and
the inductor current level.
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
PARAMETER
Output voltage
monitoring for PGOOD
pin
Powergood threshold
for interrupt
BUCKx_PG_INT,
difference from final
voltage
Powergood threshold
for status bit
BUCKx_PG_STAT
MIN
TYP
MAX
Overvoltage monitoring (compared to DC
output voltage level, VVOUT_DC)
TEST CONDITIONS
39
50
64
Undervoltage monitoring (compared to DC
output voltage level, VVOUT_DC)
–53
–40
–29
mV
Debounce time during regulator enable
PGOOD_SET_DELAY = 0
4
Debounce time during regulator enable
PGOOD_SET_DELAY = 1
10
Deglitch time during operation and after
voltage change
4
Rising ramp voltage, enable or voltage
change
UNIT
11
10
µs
13
ms
10
µs
–20
–14
–8
8
14
20
–20
–14
–8
mV
Falling ramp voltage, voltage change
During operation, status signal is forced to
'0' during voltage change
mV
EXTERNAL CLOCK AND PLL
Nominal frequency
External input clock
1
Nominal frequency step size
Required accuracy from nominal frequency
24
1
–30%
MHz
10%
External clock
detection
Delay for missing clock detection
1.8
Delay and debounce for clock detection
20
Clock change delay
(internal to external)
Delay from valid clock detection to use of
external clock
600
µs
PLL output clock jitter
Cycle to cycle
300
ps, p-p
µs
PROTECTION FUNCTIONS
Thermal warning
Temperature rising, TDIE_WARN_LEVEL =
0
115
125
135
Temperature rising, TDIE_WARN_LEVEL =
1
127
137
147
140
150
Hysteresis
Thermal shutdown
VANAOVP
VANA overvoltage
VANAUVLO
VANA undervoltage
lockout
°C
20
Temperature rising
Hysteresis
160
20
Voltage rising
5.6
5.8
6.1
Voltage falling
5.45
5.73
5.96
Hysteresis
40
°C
V
mV
Voltage rising
2.51
2.63
2.75
Voltage falling
2.5
2.6
2.7
V
LOAD CURRENT MEASUREMENT
Current measurement
range
Output current for maximum code
Resolution
LSB
20
Measurement accuracy IOUT > 1 A
Measurement time
20.47
A
mA
<10%
PFM mode (automatically changing to PWM
mode for the measurement)
PWM mode
45
µs
4
CURRENT CONSUMPTION
8
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +140°C, CPOL = 22 µF / phase, specified VVANA, VVIN_Bx , VNRST,
VVOUT_Bx and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = 3.7 V, and VOUT = 1 V,
unless otherwise noted.(1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
Shutdown current
consumption
From VANA and VIN_Bx pins: NRST = 0 V,
VANA = VIN_Bx = 3.7 V
1.4
Standby current
consumption,
regulators disabled
From VANA and VIN_Bx pins: NRST = 1.8
V, VANA = VIN_Bx = 3.7 V
6.7
Active current
consumption in PFM
mode, one regulator
enabled, internal RC
oscillator, PGOOD
monitoring enabled
UNIT
µA
From VANA and VIN_Bx pins: NRST = 1.8
V, VANA = VIN_Bx = 3.7 V, IOUT = 0 mA, not
switching
Active current
consumption during
PWM operation, per
phase
PLL and clock detector
current consumption
MAX
Additional current consumption when
internal RC oscillator, clock detector and
PLL are enabled
57
µA
19
mA
2
mA
DIGITAL INPUT SIGNALS NRST, EN1, EN2, EN3, EN4, SCL, SDA, GPIO1, GPIO2, GPIO3, CLKIN
VIL
Input low level
VIH
Input high level
1.2
0.4
VHYS
Hysteresis of Schmitt
Trigger inputs
10
ENx pulldown
resistance
ENx_PD = 1
NRST pulldown
resistance
Always present
77
200
V
mV
500
kΩ
650
1150
1700
DIGITAL OUTPUT SIGNALS nINT
VOL
Output low level
ISOURCE = 2 mA
RP
External pullup resistor
To VIO supply
0.4
10
V
kΩ
DIGITAL OUTPUT SIGNALS SDA
VOL
Output low level
ISOURCE = 10 mA
0.4
V
0.4
V
VVANA
V
VVANA
V
DIGITAL OUTPUT SIGNALS PGOOD, GPIO1, GPIO2, GPIO3
VOL
Output low level
ISOURCE = 2 mA
VOH
Output high level,
configured to push-pull
ISINK = 2 mA
VPU
Supply voltage for
external pull-up
resistor, configured to
open-drain
RPU
External pullup resistor,
configured to opendrain
VVANA – 0.4
10
kΩ
ALL DIGITAL INPUTS
ILEAK
Input current
All logic inputs over pin voltage range
(except NRST)
−1
1
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6.6 I2C Serial Bus Timing Requirements
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V.
MIN
ƒSCL
Serial clock frequency
Standard mode
100
Fast mode
400
Fast mode+
3.4
High-speed mode, Cb = 400 pF
SCL low time
tSU;DAT
tHD;DAT
tSU;STA
tHD;STA
tBUF
SCL high time
Data setup time
Data hold time
Setup time for a start or a
repeated start condition
Hold time for a start or a
repeated start condition
4.7
Fast mode
1.3
Fast mode+
0.5
High-speed mode, Cb = 100 pF
160
High-speed mode, Cb = 400 pF
320
0.6
Fast mode+
0.26
10
µs
High-speed mode, Cb = 400 pF
120
Standard mode
250
Fast mode
100
Fast mode+
50
High-speed mode
10
Standard mode
10
3450
Fast mode
10
900
Fast mode+
10
High-speed mode, Cb = 100 pF
10
70
High-speed mode, Cb = 400 pF
10
150
Standard mode
4.7
Fast mode
0.6
Fast mode+
0.26
High-speed mode
160
Standard mode
4.0
Fast mode
0.6
Fast mode+
0.26
High-speed mode
160
Standard mode
4.7
ns
ns
ns
ns
µs
ns
µs
ns
1.3
µs
0.5
4
Fast mode
0.6
Fast mode+
0.26
High-speed mode
160
µs
ns
1000
Fast mode
Rise time of SDA signal
ns
60
Standard mode
trDA
µs
High-speed mode, Cb = 100 pF
Bus free time between a stop
Fast mode
and start condition
Fast mode+
Setup time for a stop
condition
MHz
4
Fast mode
Standard mode
tSU;STO
kHz
1.7
Standard mode
Standard mode
tHIGH
UNIT
1
High-speed mode, Cb = 100 pF
tLOW
MAX
20
Fast mode+
300
120
High-speed mode, Cb = 100 pF
10
80
High-speed mode, Cb = 400 pF
20
160
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I2C Serial Bus Timing Requirements (continued)
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V.
MIN
MAX
Standard mode
tfDA
Fall time of SDA signal
300
Fast mode
20 × (VDD /
5.5 V)
300
Fast mode+
20 × (VDD /
5.5 V)
120
High-speed mode, Cb = 100 pF
10
80
High-speed mode, Cb = 400 pF
30
160
Standard mode
trCL1
Rise time of SCL signal
20
300
Fast mode+
120
High-speed mode, Cb = 100 pF
10
40
High-speed mode, Cb = 400 pF
20
80
Rise time of SCL signal after High-speed mode, Cb = 100 pF
a repeated start condition
and after an acknowledge bit High-speed mode, Cb = 400 pF
10
80
20
160
Standard mode
tfCL
Fall time of a SCL signal
Cb
Capacitive load for each bus
line (SCL and SDA)
tSP
Pulse width of spike
suppressed (SCL and SDA
spikes that are less than the
indicated width are
suppressed)
ns
1000
Fast mode
trCL
UNIT
ns
ns
300
Fast mode
20 × (VDD /
5.5 V)
300
Fast mode+
20 × (VDD /
5.5 V)
120
High-speed mode, Cb = 100 pF
10
40
High-speed mode, Cb = 400 pF
20
80
400
Standard mode, fast mode and fast mode+
50
High-speed mode
10
ns
pF
ns
tBUF
SDA
tfDA
tLOW
tHD;STA
trCL
tfCL
trDA
tSP
SCL
tHD;STA
tSU;STA
tHIGH
tSU;STO
tHD;DAT
tSU;DAT
START
REPEATED
START
STOP
START
Figure 1. I2C Timing
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6.7 Typical Characteristics
Unless otherwise specified: TA = 25°C, VIN = 3.7 V, VOUT = 1 V, V(NRST) = 1.8 V, ƒSW = 4 MHz, L = 0.47 µH (TOKO
DFE252012PD-R47M), COUT = 22 µF / phase, CPOL = 22 µF / phase.
4
10
3.5
9
8
7
Input Current (PA)
Input Current (PA)
3
2.5
2
1.5
6
5
4
3
1
2
0.5
0
2.5
1
3
3.5
4
4.5
Input Voltage (V)
5
0
2.5
5.5
3
3.5
D045
V(NRST) = 0 V
V(NRST) = 1.8 V
Figure 2. Shutdown Current Consumption vs Input Voltage
4
4.5
Input Voltage (V)
5
5.5
D046
Regulators disabled
Figure 3. Standby Current Consumption vs Input Voltage
90
85
Input Current (PA)
80
75
70
65
60
55
50
45
40
2.5
3
3.5
4
4.5
Input Voltage (V)
V(NRST) = 1.8 V
5
5.5
D051
Load = 0 mA
Figure 4. PFM Mode Current Consumption vs Input Voltage, One Regulator Enabled
12
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7 Detailed Description
7.1 Overview
The LP87524B/J-Q1 is a high-efficiency, high-performance power supply device with four step-down DC-DC
converter cores for automotive applications. Table 1 lists the output characteristics of the regulators.
Table 1. Supply Specification
OUTPUT
SUPPLY
VOUT RANGE (V)
RESOLUTION (mV)
IMAX MAXIMUM OUTPUT CURRENT (A)
Buck0, Buck1
0.6 to 3.36 (VIN = 2.8 V - 4 V)
1.0 to 3.36 (VIN = 2.8 V - 5.5 V)
10 (0.6 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
1.5 A
Buck2
0.6 to 3.36 (VIN = 2.8 V - 4 V)
1.0 to 3.36 (VIN = 2.8 V - 5.5 V)
10 (0.6 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
4A
Buck3
0.6 to 3.36 (VIN = 2.8 V - 4 V)
1.0 to 3.36 (VIN = 2.8 V - 5.5 V)
10 (0.6 V to 0.73 V)
5 (0.73 V to 1.4 V)
20 (1.4 V to 3.36 V)
2.5 A
The LP87524B/J-Q1 also supports switching clock synchronization to an external clock. The nominal frequency
of the external clock can be from 1 MHz to 24 MHz with 1-MHz steps.
Additional features include:
• Soft start
• Input voltage protection:
– Undervoltage lockout
– Overvoltage protection
• Output voltage monitoring and protection:
– Overvoltage monitoring
– Undervoltage monitoring
– Overload protection
• Thermal warning
• Thermal shutdown
Three enable signals can be multiplexed to general purpose I/O (GPIO) signals. The direction and output type
(open-drain or push-pull) are programmable for the GPIOs.
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7.2 Functional Block Diagram
VANA
Buck0
nINT
Interrupts
ILIM Det
Pwrgood Det
Overload
and SC Det
Iload ADC
Enable,
Roof/Floor,
Slew-Rate
Control
EN1 (GPIO1)
EN2 (GPIO2)
EN3 (GPIO3)
Buck1
ILIM Det
SDA
SCL
Pwrgood Det
Overload
and SC Det
Iload ADC
I2C
PGOOD
OTP
EPROM
Registers
Buck2
ILIM Det
UVLO
Pwrgood Det
Digital
Logic
Thermal
Monitor
NRST
Overload
and SC Det
Iload ADC
Buck3
ILIM Det
SW
Reset
Ref &
Bias
Oscillator
Pwrgood Det
Overload
and SC Det
Iload ADC
CLKIN
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7.3 Feature Descriptions
7.3.1 DC-DC Converters
7.3.1.1 Overview
The LP87524B/J-Q1 includes four step-down DC-DC converter cores configured for four single-phase outputs.
The cores are designed for flexibility; most of the functions are programmable, thus giving a possibility to
optimize the regulator operation for each application.
The LP87524B/J-Q1 has the following features:
• DVS support
• Automatic mode control based on the loading (PFM or PWM mode)
• Forced-PWM mode operation
• Optional external clock input to minimize crosstalk
• Optional spread spectrum technique to reduce EMI
• Phase control for optimized EMI
• Synchronous rectification
• Current mode loop with PI compensator
• Soft start
• Power Good flag with maskable interrupt
• Power Good signal (PGOOD) with selectable sources
• Average output current sensing (for PFM entry and load current measurement)
The following parameters can be programmed via registers:
• Output voltage
• Forced-PWM operation
14
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Feature Descriptions (continued)
•
Enable and disable delays for regulators and GPIOs controlled by ENx pins
There are two modes of operation for the converter, depending on the output current required: pulse-width
modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load
currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically
switch into PFM mode for reduced current consumption when forced-PWM mode is disabled.
A multi-phase synchronous buck converter offers several advantages over a single power stage converter. For
application processor power delivery, lower ripple on the input and output currents and faster transient response
to load steps are the most significant advantages. Also, because the load current is evenly shared among
multiple channels in multi-phase output configuration, the heat generated is greatly reduced for each channel due
to the fact that power loss is proportional to square of current. The physical size of the output inductor shrinks
significantly due to this heat reduction. A block diagram of a single core is shown in Figure 5.
+
FBN
-
Slave
Phase
Control
±
+
Voltage
Setting
Slew Rate
Control
PMOS
Current
Sense
Differential to SingleEnded
Ramp
Generator
Programmable
Parameters
+
-
±
VOUT
Gate
Control
Error
Amp
Loop
Comp
VDAC
VIN
POS
Current
Limit
+
FBP
NEG
Current
Limit
Power
Good
Control
Block
SW
NMOS
Current
Sense
Master
Interface
Slave
Interface
Zero
Cross
Detect
IADC
GND
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Figure 5. Detailed Block Diagram Showing One Core
7.3.1.2 Transition Between PWM and PFM Modes
The LP87524B/J-Q1 converter operates in PWM mode at load current of about 600 mA or higher. At lighter loadcurrent levels the device automatically switches into PFM mode for reduced current consumption when forcedPWM mode is disabled (AUTO-mode operation). By combining the PFM and the PWM modes a high efficiency is
achieved over a wide output-load-current range.
7.3.1.3 Buck Converter Load-Current Measurement
Buck load current can be monitored via I2C registers. The monitored buck converter is selected with the
LOAD_CURRENT_BUCK_SELECT[1:0] bits in SEL_I_LOAD register. A write to this selection register starts a
current measurement sequence. The regulator is forced to PWM mode during the measurement. The
measurement sequence is 50 µs long, maximum. LP87524B/J-Q1 can be configured to give out an interrupt
(I_LOAD_READY bit in INT_TOP1 register) after the load current measurement sequence is finished. Load
current measurement interrupt can be masked with I_LOAD_READY_MASK bit (TOP_MASK1 register). The
measurement result can be read from registers I_LOAD_1 and I_LOAD_2. Register I_LOAD_1 bits
BUCK_LOAD_CURRENT[7:0] give out the LSB bits and register I_LOAD_2 bits BUCK_LOAD_CURRENT[9:8]
the MSB bits. The measurement result BUCK_LOAD_CURRENT[9:0] LSB is 20 mA, and maximum value of the
measurement corresponds to 20.46 A.
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Feature Descriptions (continued)
7.3.1.4 Spread-Spectrum Mode
POWER SPECTRUM IS
SPREAD AND LOWERED
RADIADED ENERGY
Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband
frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add
EMI filters and shields to the boards. The LP87524B/J-Q1 device has register selectable spread-spectrum mode
which minimizes the need for output filters, ferrite beads, or chokes. In spread-spectrum mode, the switching
frequency varies around the center frequency, reducing the EMI emissions radiated by the converter and
associated passive components and PCB traces (see Figure 6). This feature is available only when internal RC
oscillator is used (PLL_MODE[1:0] = 00 in PLL_CTRL register), and it is enabled with the EN_SPREAD_SPEC
bit (PIN_FUNCTION register), and it affects all the buck cores.
FREQUENCY
Where a fixed-frequency converter exhibits large amounts of spectral energy at the switching frequency, the spreadspectrum architecture of the LP87524B/J-Q1 spreads that energy over a large bandwidth.
Figure 6. Spread-Spectrum Modulation
7.3.2 Sync Clock Functionality
The LP87524B/J-Q1 device contains a CLKIN input to synchronize switching clock of the buck regulator with the
external clock. The block diagram of the clocking and PLL module is shown in Figure 7. Depending on the
PLL_MODE[1:0] bits (in PLL_CTRL register) and the external clock availability, the external clock is selected and
interrupt is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK bit in
TOP_MASK1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0] bits (in
PLL_CTRL register) and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be inside
accuracy limits (–30%/+10%) for valid clock detection.
The NO_SYNC_CLK interrupt (in INT_TOP1 register) is also generated in cases the external clock is expected
but it is not available. These cases are start-up (read OTP-to-STANDBY transition) when PLL_MODE[1:0] = 01
and regulator enable (STANDBY-to-ACTIVE transition) when PLL_MODE[1:0] = 10.
16
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Feature Descriptions (continued)
24-MHz
RC
Oscillator
Internal
24-MHz
clock
CLKIN
Detector
Divider
´(;7_CLK_
)5(4´
CLKIN
1MHz
24MHz
Clock Select
Logic
PLL
´3//_02'(´
1MHz
Divider
24
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Figure 7. Clock and PLL Module
Table 2. PLL Operation
DEVICE
OPERATION MODE
PLL_MODE[1:0]
PLL AND CLOCK
DETECTOR STATE
INTERRUPT FOR
EXTERNAL CLOCK
CLOCK
STANDBY
00
Disabled
No
Internal RC
ACTIVE
00
Disabled
No
Internal RC
STANDBY
01
Enabled
When external clock
appears or disappears
Automatic change to external
clock when available
ACTIVE
01
Enabled
When external clock
appears or disappears
Automatic change to external
clock when available
STANDBY
10
Disabled
No
Internal RC
Enabled
When external clock
appears or disappears
Automatic change to external
clock when available
ACTIVE
10
STANDBY
11
Reserved
ACTIVE
11
Reserved
7.3.3 Power-Up
The power-up sequence for the LP87524B/J-Q1 is as follows:
• VANA (and VIN_Bx) reach minimum recommended level (VVANA > VANAUVLO).
• NRST is set to high level (or shorted to VANA). This initiates power-on-reset (POR), OTP reading and
enables the system I/O interface. The I2C host must allow at least 1.2 ms before writing or reading data to the
LP87524B/J-Q1.
• Device enters STANDBY-mode.
• The host can change the default register setting by I2C if needed.
• The regulator(s) can be enabled/disabled by ENx pin(s) and by I2C interface.
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7.3.4 Regulator Control
7.3.4.1 Enabling and Disabling Regulators
The regulator(s) can be enabled when the device is in STANDBY or ACTIVE state. There are two ways for
enable and disable the regulators:
• Using EN_BUCKx bit in BUCKx_CTRL1 register (EN_PIN_CTRLx register bit is 0)
• Using EN1/2/3 control pins (EN_BUCKx bit is 1 AND EN_PIN_CTRLx register bit is 1 in BUCKx_CTRL1
register)
If the EN1/2/3 control pins are used for enable and disable then the control pin is selected with
BUCKx_EN_PIN_SELECT[1:0] bits (in BUCKx_CTRL1 register). The delay from the control signal rising edge to
enabling of the regulator is set by BUCKx_STARTUP_DELAY[3:0] bits and the delay from control signal falling
edge to disabling of the regulator is set by BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register.
The delays are valid only for EN1/2/3 signal control. The control with EN_BUCKx bit is immediate without the
delays.
The control of the regulator (with 0-ms delays) is shown in Table 3.
NOTE
The control of the regulator cannot be changed from one ENx pin to a different ENx pin
because the control is ENx signal edge sensitive. The control from ENx pin to register bit
and back to the original ENx pin can be done during operation.
Table 3. Regulator Control
CONTROL
METHOD
EN_BUCKx
EN_PIN_CTRLx
BUCKx_EN_PI
N_SELECT[1:0]
EN_ROOF_FLOOR
x
EN1 PIN
EN2 PIN
EN3 PIN
BUCKx
OUTPUT VOLTAGE
Enable/disable
control with
EN_BUCKx bit
0
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Disabled
1
0
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
BUCKx_VSET[7:0]
Enable/disable
control with EN1
pin
1
1
00
0
Low
Don't Care
Don't Care
Disabled
1
1
00
0
High
Don't Care
Don't Care
BUCKx_VSET[7:0]
Enable/disable
control with EN2
pin
1
1
01
0
Don't Care
Low
Don't Care
Disabled
1
1
01
0
Don't Care
High
Don't Care
BUCKx_VSET[7:0]
Enable/disable
control with EN3
pin
1
1
10
0
Don't Care
Don't Care
Low
Disabled
1
1
10
0
Don't Care
Don't Care
High
BUCKx_VSET[7:0]
Roof/floor control
with EN1 pin
1
1
00
1
Low
Don't Care
Don't Care
BUCKx_FLOOR_VSET[7:0]
1
1
00
1
High
Don't Care
Don't Care
BUCKx_VSET[7:0]
Roof/floor control
with EN2 pin
1
1
01
1
Don't Care
Low
Don't Care
BUCKx_FLOOR_VSET[7:0]
1
1
01
1
Don't Care
High
Don't Care
BUCKx_VSET[7:0]
Roof/floor control
with EN3 pin
1
1
10
1
Don't Care
Don't Care
Low
BUCKx_FLOOR_VSET[7:0]
1
1
10
1
Don't Care
Don't Care
High
BUCKx_VSET[7:0]
The regulator is enabled by the ENx pin or by I2C writing as shown in Figure 8. The soft-start circuit limits the inrush current during start-up. When the output voltage rises to 0.35-V level, the output voltage becomes slew-rate
controlled. If there is a short circuit at the output and the output voltage does not increase above 0.35-V level in 1
ms, the regulator is disabled, and interrupt is set. When the output voltage reaches the Power-Good threshold
level the BUCKx_PG_INT interrupt flag (in INT_BUCK_x register) is set. The Power-Good interrupt flag can be
masked using BUCKx_PG_MASK bit (in BUCKx_MASK register).
The ENx input pins have integrated pulldown resistors. The pulldown resistors are enabled by default, and the
host can disable those with ENx_PD bits (in CONFIG register).
18
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Voltage decrease because of load
No new Powergood interrupt
Voltage
BUCKx_VSET[7:0]
Powergood
Ramp 3.8 mV/Ps
0.6V
0.35V
Resistive pull-down
(if enabled)
Soft start
Time
Enable
BUCK_x_STAT(BUCKx_STAT)
0
BUCK_x_STAT(BUCKx_PG_STAT)
0
1
INT_BUCK_x(BUCKx_PG_INT)
0
1
1
0
0
1
0
0
nINT
Powergood
interrupt
Host clears
interrupt
Figure 8. Regulator Enable and Disable
7.3.4.2 Changing Output Voltage
The output voltage of the regulator can be changed by the ENx pin (voltage levels defined by the BUCKx_VOUT
and BUCKx_FLOOR_VOUT registers) or by writing to the BUCKx_VOUT and BUCKx_FLOOR_VOUT registers.
The voltage change is always slew-rate controlled, 3.8 mV/µs. During voltage change the forced-PWM mode is
used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by
the load current and the BUCKx_FPWM bit in BUCKx_CTRL1 register.
The Power-Good interrupt is generated when the output voltage reaches the programmed voltage level, as
shown in Figure 9.
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Voltage
BUCKx_VSET
Powergood
Ramp 3.8 mV/Ps
Powergood
BUCKx_FLOOR_VSET
Time
ENx
BUCKx_STAT(BUCKx_STAT)
1
BUCKx_STAT(BUCKx_PG_STAT)
1
INT_BUCKx(BUCKx_PG_INT)
0
0
1
0
1
0
1
1
nINT
Powergood
interrupt
Host clears
interrupt
Powergood
interrupt
Host clears
interrupt
Figure 9. Regulator Output Voltage Change With ENx pin
7.3.5 Enable and Disable Sequences
The LP87524B/J-Q1 device supports start-up and shutdown sequencing with programmable delays for different
regulator outputs using single EN1/2/3 control signal. The regulator is selected for delayed control with:
• EN_BUCKx = 1 (in BUCKx_CTRL1 register)
• EN_PIN_CTRLx = 1 (in BUCKx_CTRL1 register)
• EN_ROOF_FLOORx = 0 (in BUCKx_CTRL1 register)
• BUCKx_VSET[7:0] = Required voltage when ENx is high (in BUCKx_VOUT register)
• The ENABLE pin for control is selected with BUCKx_EN_PIN_SELECT[1:0] (in BUCKx_CTRL1 register)
• The delay from rising edge of ENx signal to the regulator enable is set by BUCKx_STARTUP_DELAY[3:0]
bits (in BUCKx_DELAY register) and
• The delay from falling edge of ENx signal to the regulator disable is set by BUCKx_SHUTDOWN_DELAY[3:0]
bits (in BUCKx_DELAY register)
There are four time steps available for start-up and shutdown sequences. The delay times are selected with
DOUBLE_DELAY bit in CONFIG register and HALF_DELAY bit in PGOOD_CTRL2 register as shown in Table 4.
20
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Table 4. Start-up and Shutdown Delays
X_STARTUP_DELAY /
X_SHUTDOWN_DELAY
DOUBLE_DELAY = 0
HALF_DELAY = 1
DOUBLE_DELAY = 1
HALF_DELAY = 1
DOUBLE_DELAY = 0
HALF_DELAY = 0
DOUBLE_DELAY = 1
HALF_DELAY = 0
0000
0 ms
0 ms
0 ms
0 ms
0001
0.32 ms
0.64 ms
1 ms
2 ms
0010
0.64 ms
1.28 ms
2 ms
4 ms
0011
0.96 ms
1.92 ms
3 ms
6 ms
0100
1.28 ms
2.56 ms
4 ms
8 ms
0101
1.6 ms
3.2 ms
5 ms
10 ms
0110
1.92 ms
3.84 ms
6 ms
12 ms
0111
2.24 ms
4.48 ms
7 ms
14 ms
1000
2.56 ms
5.12 ms
8 ms
16 ms
1001
2.88 ms
5.76 ms
9 ms
18 ms
1010
3.2 ms
6.4 ms
10 ms
20 ms
1011
3.52 ms
7.04 ms
11 ms
22 ms
1100
3.84 ms
7.68 ms
12 ms
24 ms
1101
4.16 ms
8.32 ms
13 ms
26 ms
1110
4.48 ms
8.96 ms
14 ms
28 ms
1111
4.8 ms
9.6 ms
15 ms
30 ms
An example of start-up and shutdown sequences is shown in Figure 10. The start-up and shutdown delays for
the Buck0/1 regulators are 1 ms and 4 ms and for the Buck2/3 regulators 3 ms and 1 ms. The delay settings are
used only for enable/disable control with EN1/2/3 signals, not for Roof/Floor control.
Typical sequence
ENx
EN_BUCK01
1ms
EN_BUCK23
4ms
3ms
1ms
Sequence with short ENx low and high periods
ENx
Startup cntr
0
Shutdown cntr
0
0
1
0
0
EN_BUCK01
1
2
3
4
1
5
6
0
0
1
2 0
1ms
EN_BUCK23
1
2
3
4
5
4ms
3ms
1ms
Figure 10. Start-Up and Shutdown Sequencing
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7.3.6 Device Reset Scenarios
There are three reset methods implemented on the LP87524B/J-Q1:
• Software reset with SW_RESET register bit (in RESET register)
• POR from rising edge of NRST signal
• Undervoltage lockout (UVLO) reset from VANA supply
A SW-reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event
disables all the regulators immediately, resets all the register bits to the default values and OTP bits are loaded
(see Figure 14). I2C interface is not reset during software reset. The host must wait at least 1.2 ms after writing
SW reset until making a new I2C read or write to the device.
If VANA supply voltage falls below UVLO threshold level or NRST signal is set low then all the regulators are
disabled immediately, and all the register bits are reset to the default values. When the VANA supply voltage
rises above UVLO threshold level AND NRST signal rises above threshold level an internal power-on reset
(POR) occurs. OTP bits are loaded to the registers and a start-up is initiated according to the register settings.
The host must wait at least 1.2 ms after POR until reading or writing to I2C interface.
7.3.7 Diagnosis and Protection Features
The LP87524B/J-Q1 is capable of providing four levels of protection features:
• Information of valid regulator output voltage which sets interrupt or PGOOD signal;
• Warnings for diagnosis which sets interrupt;
• Protection events which are disabling the regulators affected; and
• Faults which are causing the device to shutdown.
The LP87524B/J-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the
nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all
the pending interrupts are cleared.
When a fault is detected, it is indicated by a RESET_REG interrupt flag (in INT2_TOP register) after next startup.
Table 5. Summary of Interrupt Signals
EVENT
RESULT
INTERRUPT REGISTER AND
BIT
INTERRUPT MASK
STATUS BIT
RECOVERY/INTERRUPT
CLEAR
Current limit triggered
(20-µs debounce)
Interrupt
INT_BUCKx = 1
BUCKx_ILIM_INT = 1
BUCKx_ILIM_MASK
BUCKx_ILIM_STAT
Write 1 to BUCKx_ILIM_INT bit
Interrupt is not cleared if
current limit is active
Short circuit (VVOUT <
0.35 V at 1 ms after
enable) or overload
(VVOUT decreasing
below 0.35 V during
operation, 1 ms
debounce)
Regulator disable and
interrupt
INT_BUCKx = 1
BUCKx_SC_INT = 1
N/A
N/A
Write 1 to BUCKx_SC_INT bit
Thermal warning
Interrupt
TDIE_WARN = 1
TDIE_WARN_MASK
TDIE_WARN_STAT
Write 1 to TDIE_WARN bit
Interrupt is not cleared if
temperature is above thermal
warning level
Thermal whutdown
All regulators disabled
and Output GPIOx set to
low and interrupt
TDIE_SD = 1
N/A
TDIE_SD_STAT
Write 1 to TDIE_SD bit
Interrupt is not cleared if
temperature is above thermal
shutdown level
VANA overvoltage
(VANAOVP)
All regulators disabled
and Output GPIOx set to
low and interrupt
INT_OVP
N/A
OVP_STAT
Write 1 to INT_OVP bit
Interrupt is not cleared if VANA
voltage is above VANA OVP
level
Power Good, output
voltage reaches the
programmed value
Interrupt
INT_BUCKx = 1
BUCKx_PG_INT = 1
BUCKx_PG_MASK
BUCKx_PG_STAT
Write 1 to BUCKx_PG_INT bit
GPIO
Interrupt
INT_GPIO
GPIO_MASK
GPIO_IN register
Write 1 to INT_GPIO bit
External clock appears
or disappears
Interrupt
NO_SYNC_CLK (1)
SYNC_CLK_MASK
SYNC_CLK_STAT
Write 1 to NO_SYNC_CLK bit
Load current
measurement ready
Interrupt
I_LOAD_READY = 1
I_LOAD_READY_MASK
N/A
Write 1 to I_LOAD_READY bit
(1)
22
Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled.
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Table 5. Summary of Interrupt Signals (continued)
EVENT
RESULT
INTERRUPT REGISTER AND
BIT
INTERRUPT MASK
STATUS BIT
RECOVERY/INTERRUPT
CLEAR
Start-up (NRST rising
edge)
Device ready for
operation, registers reset
to default values and
interrupt
RESET_REG = 1
RESET_REG_MASK
N/A
Write 1 to RESET_REG bit
Glitch on supply voltage
and UVLO triggered
(VANA falling and
rising)
Immediate shutdown
followed by power up,
registers reset to default
values and interrupt
RESET_REG = 1
RESET_REG_MASK
N/A
Write 1 to RESET_REG bit
Software requested
reset
Immediate shutdown
followed by power up,
registers reset to default
values and interrupt
RESET_REG = 1
RESET_REG_MASK
N/A
Write 1 to RESET_REG bit
7.3.7.1 Power-Good Information (PGOOD pin)
In addition to the interrupt based indication of current limit and Power-Good level the LP87524B/J-Q1 device
supports the indication with PGOOD signal. Either voltage and current monitoring or a voltage monitoring only
can be selected for PGOOD indication. This selection is individual for all buck regulators and is set by
PGx_SEL[1:0] bits (in PGOOD_CTRL1 register). When both voltage and current are monitored, PGOOD signal
active indicates that regulator output is inside the Power-Good voltage window and that load current is below ILIM
FWD. If only voltage is monitored, then the current monitoring is ignored for the PGOOD signal. When a regulator
is disabled, the monitoring is automatically masked to prevent it forcing PGOOD inactive. This allows connecting
PGOOD signals from various devices together when open-drain outputs are used. When regulator voltage is
transitioning from one target voltage to another, the voltage monitoring PGOOD signal is set inactive. The
monitoring from all the output rails are combined, and PGOOD is active only if all the sources shows active
status. The status from all the voltage rails are summarized in Table 6.
If the PGOOD signal is inactive or it changes the state to inactive, the source for the state can be read from
PGOOD_FLT register. During reading all the PGx_FLT bit are cleared that are not driving the PGOOD inactive.
When PGOOD signal goes active, the host must read the PGOOD_FLT register to clear all the bits. The PGOOD
signal follows the status of all the monitored outputs.
The PGOOD signal can be also configured so that it maintains inactive state even when the monitored outputs
are valid but there are PGx_FLT bits pending clearance in PGOOD_FLT register. This mode of operation is
selected by setting EN_PGFLT_STAT bit to 1 (in PGOOD_CTRL2 register).
The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit (in
PGOOD_CTRL2 register). If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and
overvoltage are monitored.
The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and PGOOD_OD bits in
PGOOD_CTRL2 register.
The filtering time for invalid output voltage is always typically 7 µs and for valid output voltage the filtering time is
selected with PGOOD_SET_DELAY bit (in PGOOD_CTRL2 register). The Power-Good waveforms are shown in
Figure 12.
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ILIM
Buck0
Power Good
MUX
PG0_SEL[1:0]
ILIM
Buck1
Power Good
MUX
PG1_SEL[1:0]
PGOOD
ILIM
Buck2
Power Good
MUX
PG2_SEL[1:0]
ILIM
Buck3
Power Good
MUX
PG3_SEL[1:0]
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Figure 11. PGOOD Block Diagram
Table 6. PGOOD Operation
STATUS / USE CASE
CONDITION
INPUT TO PGOOD SIGNAL
Buck not selected for PGOOD monitoring
PGx_SEL = 00 (in PGOOD_CTRL1
register)
Active
Buck disabled
Active
BUCK SELECTED FOR PGOOD MONITORING
Buck start-up delay
Buck soft start
Buck voltage ramp-up
Output voltage within window limits after
start-up
Output voltage inside voltage window and
current limit active
Output voltage spikes (overvoltage or
undervoltage)
Inactive
VOUT < 0.35 V
Inactive
0.35 V < VOUT < VSET
Inactive
Must be inside limits longer than debounce
time
Active
Current limit active longer than debounce
time
Active (if only voltage monitoring selected)
Inactive (if also current monitoring selected)
If spikes are outside voltage window longer
than debounce time
Inactive
Voltage setting change, output voltage
ramp
Output voltage within window limits after
voltage change
Inactive
Must be inside limits longer than debounce
time
Active
Buck shutdown delay
Active
Buck output voltage ramp down
Active
24
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Table 6. PGOOD Operation (continued)
STATUS / USE CASE
CONDITION
INPUT TO PGOOD SIGNAL
Buck disabled by thermal shutdown and
interrupt pending
Inactive
Buck disabled by overvoltage and
interrupt pending
Inactive
Buck disabled by short-circuit detection
and interrupt pending
Inactive
Voltage
Powergood window
BUCKx_VSET (1)
Powergood
window
BUCKx_VSET (2)
Time
ENx
7us/11ms
PGOOD_SET_DELAY
PGOOD
BUCKx_VSET
BUCKx_VSET (1)
BUCKx_VSET (2)
Figure 12. PGOOD Waveforms (PGOOD_POL=0)
7.3.7.2 Warnings for Diagnosis (Interrupt)
7.3.7.2.1 Output Power Limit
The regulators have output peak current limits. The peak current limits are described in Specifications. If the load
current is increased so that the current limit is triggered, the regulator continues to regulate to the limit current
level (current peak regulation, peak on every switching cycle). The voltage may decrease if the load current is
higher than the average output current. If the current regulation continues for 20 µs, the LP87524B/J-Q1 device
sets the BUCKx_ILIM_INT bit (in INT_BUCKx register) and pulls the nINT pin low. The host processor can read
BUCKx_ILIM_STAT bits (in BUCKx_STAT register) to see if the regulator is still in peak current regulation mode.
If the load is so high that the output voltage decreases below a 350-mV level, the LP87524B/J-Q1 device
disables the regulator and sets the BUCKx_SC_INT bit (in INT_BUCKx register). In addition the BUCKx_STAT
bit (in BUCKx_STAT register) is set to 0. The interrupt is cleared when the host processor writes 1 to
BUCKx_SC_INT bit. The overload situation is shown in Figure 13.
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New startup if
enable is valid
Regulator disabled
by digital
Voltage
VOUTx
350mV
Resistive
pull-down
1ms
Time
Current
ILIMx
Time
20Ps
INT_BUCKx(BUCKx_ILIM_INT)
0
1
0
INT_BUCKx(BUCKx_SC_INT)
0
1
0
BUCKx_STAT(BUCKx_STAT)
1
0
1
nINT
Host clearing the interrupt by writing to flags
Figure 13. Overload Situation
7.3.7.2.2 Thermal Warning
The LP87524B/J-Q1 device includes a monitoring feature against overtemperature by setting an interrupt for host
processor. The threshold level of the thermal warning is selected with TDIE_WARN_LEVEL bit (in CONFIG
register).
If the LP87524B/J-Q1 device temperature increases above thermal warning level the device sets TDIE_WARN
bit (in INT_TOP1 register) and pulls nINT pin low. The status of the thermal warning can be read from
TDIE_WARN_STAT bit (in TOP_STAT register), and the interrupt is cleared by writing 1 to TDIE_WARN bit.
7.3.7.3 Protection (Regulator Disable)
If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal
shutdown, overvoltage protection, or UVLO), the output power FETs are set to high-impedance mode, and the
output pulldown resistor is enabled (if enabled with EN_RDISx bits in BUCKx_CTRL1 register). The turnoff time
of the output voltage is defined by the output capacitance, load current, and the resistance of the integrated
pulldown resistor. The pulldown resistors are active as long as VANA voltage is above approximately a 1.2-V
level.
26
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Short-Circuit and Overload Protection
A short-circuit protection feature allows the LP87524B/J-Q1 to protect itself and external components against
short circuit at the output or against overload during start-up. The fault threshold is 350 mV, the protection is
triggered, and the regulator is disabled if the output voltage is below the threshold level 1 ms after the regulator
is enabled.
In a similar way the overload situation is protected during normal operation. If the voltage on the feedback pin of
the regulator falls below 0.35 V and remains below the threshold level for 1 ms, the regulator is disabled.
In the short-circuit and overload situations the BUCKx_SC_INT (in INT_BUCKx register) and the INT_BUCKx bits
(in INT_TOP1 register) are set to 1, the BUCKx_STAT bit (in BUCKx_STAT register) is set to 0, and the nINT
signal is pulled low. The host processor clears the interrupt by writing 1 to the BUCKx_SC_INT bit. Upon clearing
the interrupt the regulator makes a new start-up attempt if the regulator is in enabled state.
7.3.7.3.2 Overvoltage Protection
The LP87524B/J-Q1 device monitors the input voltage from the VANA pin in standby and active operation
modes. If the input voltage rises above VANAOVP voltage level, all the regulators are disabled, pulldown resistors
discharge the output voltages (if EN_RDISx = 1 in BUCKx_CTRL1 register), GPIOs that are configured to
outputs are set to logic low level, nINT signal is pulled low, INT_OVP bit (in INT_TOP1 register) is set to 1, and
BUCKx_STAT bits (in BUCK_x_STAT register) are set to 0. The host processor clears the interrupt by writing 1
to the INT_OVP bit. If the input voltage is above the overvoltage detection level the interrupt is not cleared. The
host can read the status of the overvoltage from the OVP_STAT bit (in TOP_STAT register). Regulators cannot
be enabled as long as the input voltage is above overvoltage detection level or the overvoltage interrupt is
pending.
7.3.7.3.3 Thermal Shutdown
The LP87524B/J-Q1 has an overtemperature protection function that operates to protect the device from shortterm misuse and overload conditions. When the junction temperature exceeds around 150°C, the regulators are
disabled, the TDIE_SD bit (in INT_TOP1 register) is set to 1, the nINT signal is pulled low, and the device enters
STANDBY. nINT is cleared by writing 1 to the TDIE_SD bit. If the temperature is above thermal shutdown level
the interrupt is not cleared. The host can read the status of the thermal shutdown from the TDIE_SD_STAT bit
(in TOP_STAT register). Regulators cannot be enabled as long as the junction temperature is above thermal
shutdown level or the thermal shutdown interrupt is pending.
7.3.7.4 Fault (Power Down)
7.3.7.4.1 Undervoltage Lockout
When the input voltage falls below VANAUVLO at the VANA pin, the buck converters are disabled immediately,
and the output capacitors are discharged using the pulldown resistor, and the LP87524B/J-Q1 device enters
SHUTDOWN. When VANA voltage is above UVLO threshold level and NRST signal is high, the device powers
up to STANDBY state.
If the reset interrupt is unmasked by default (RESET_REG_MASK = 0 in TOP_MASK2 register) the
RESET_REG interrupt (in INT_TOP2 register) indicates that the device has been in SHUTDOWN. The host
processor must clear the interrupt by writing 1 to the RESET_REG bit. If the host processor reads the
RESET_REG flag after detecting an nINT low signal, it knows that the input supply voltage has been below
UVLO level (or the host has requested reset), and the registers are reset to default values.
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7.3.8 GPIO Signal Operation
The LP87524B/J-Q1 device supports up to 3 GPIO signals. The GPIO signals are multiplexed with enable
signals. The selection between enable and GPIO function is set with GPIOx_SEL bits in PIN_FUNCTION
register. The GPIOs are mapped to EN signals so that:
• EN1 is multiplexed with GPIO1
• EN2 is multiplexed with GPIO2
• EN3 is multiplexed with GPIO3
When the pin is selected for GPIO function, additional bits defines how the GPIO operates:
• GPIOx_DIR defines the direction of the GPIO, input or output (GPIO_CONFIG register)
• GPIOx_OD defines the type of the output when the GPIO is set to output, either push-pull with VANA level or
open-drain (GPIO_CONFIG register)
When the GPIOx is defined as output, the logic level of the pin is set by GPIOx_OUT bit (in GPIO_OUT register).
When the GPIOx is defined as input, the logic level of the pin can be read from GPIOx_IN bit (in GPIO_IN
register).
The control of the GPIOs configured to outputs can be included to start-up and shutdown sequences. The GPIO
control for a sequence with ENx signal is selected by EN_PIN_CTRL_GPIOx and EN_PIN_SELECT_GPIOx bits
(in
PIN_FUNCTION
register).
The
delays
during
start-up
and
shutdown
are
set
by
GPIOx_STARTUP_DELAY[3:0] and GPIOx_SHUTDOWN_DELAY[3:0] bits (in GPIOx_DELAY register) in the
same way as control of the regulators.
The GPIOx signals have a selectable pulldown resistor. The pulldown resistors are selected by ENx_PD bits (in
CONFIG register).
NOTE
The control of the GPIOx pin cannot be changed from one ENx pin to a different ENx pin
because the control is ENx signal edge sensitive. The control from ENx pin to register bit
and back to the original ENx pin can be done during operation.
7.3.9 Digital Signal Filtering
The digital signals have a debounce filtering. The signal/supply is sampled with a clock signal and a counter.
This results as an accuracy of one clock period for the debounce window.
28
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Table 7. Digital Signal Filtering
EVENT
SIGNAL/SUPPLY
RISING EDGE DEBOUNCE TIME
FALLING EDGE DEBOUNCE
TIME
Enable/disable/voltage select
for Buckx
EN1
3 µs
(1)
3 µs
(1)
Enable/disable/voltage select
for Buckx
EN2
3 µs
(1)
3 µs
(1)
Enable/disable/voltage select
for Buckx
EN3
3 µs
(1)
3 µs
(1)
VANA UVLO
VANA
20 µs (VANA voltage rising)
Immediate (VANA voltage falling)
VANA overvoltage
VANA
20 µs (VANA voltage rising)
20 µs (VANA voltage falling)
TDIE_WARN
20 µs
20 µs
TDIE_SD
20 µs
20 µs
VOUTx_ILIM
20 µs
20 µs
Overload
FB_B0, FB_B1, FB_B2,
FB_F3
1 ms
20 µs
Power-Good interrupt
FB_B0, FB_B1, FB_B2,
FB_F3
20 µs
20 µs
PGOOD pin (voltage
monitoring)
PGOOD / FB_B0, FB_B1,
FB_B2, FB_F3
4-8 µs (start-up debounce time during
start-up)
4 to 8 µs
PGOOD pin (current
monitoring)
PGOOD
20 µs
20 µs
Thermal warning
Thermal shutdown
Current limit
(1)
No glitch filtering, only synchronization.
7.4 Device Functional Modes
7.4.1 Modes of Operation
SHUTDOWN: The NRST voltage is below threshold level. All switch, reference, control, and bias circuitry of the
LP87524B/J-Q1 device are turned off.
READ OTP: The main supply voltage VANA is above VANAUVLO level and NRST voltage is above threshold
level. The regulators are disabled and the reference and bias circuitry of the LP87524B/J-Q1 are
enabled. The OTP bits are loaded to registers.
STANDBY: The main supply voltage VANA is above VANAUVLO level and NRST voltage is above threshold
level. The regulators are disabled and the reference, control and bias circuitry of the LP87524B/JQ1 are enabled. All registers can be read or written by the host processor via the system serial
interface. The regulators can be enabled if needed.
ACTIVE:
The main supply voltage VANA is above VANAUVLO level and NRST voltage is above threshold
level. At least one regulated DC-DC converter is enabled. All registers can be read or written by the
host processor via the system serial interface.
The operating modes and transitions between the modes are shown in Figure 14.
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Device Functional Modes (continued)
SHUTDOWN
NRST low
OR
VVANA < VANAUVLO
NRST high
AND
FROM ANY STATE
EXCEPT SHUTDOWN
VVANA > VANAUVLO
READ
OTP
REG
RESET
STANDBY
2
I C RESET
REGULATOR
ENABLED
REGULATOR(S)
DISABLED
ACTIVE
Figure 14. Device Operation Modes
30
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7.5 Programming
7.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the devices
connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL). Every
device on the bus is assigned a unique address and acts as either a master or a slave depending on whether it
generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor placed
somewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus data
transfer. The LP87524B/J-Q1 supports standard mode (100 kHz), fast mode (400 kHz), fast mode+ (1 MHz), and
high-speed mode (3.4 MHz).
7.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
SCL
SDA
data
change
allowed
data
valid
data
change
allowed
data
valid
data
change
allowed
Figure 15. Data Validity Diagram
7.5.1.2 Start and Stop Conditions
The LP87524B/J-Q1 is controlled via an I2C-compatible interface. START and STOP conditions classify the
beginning and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while
SCL is HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C
master always generates the START and STOP conditions.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 16. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 17 shows the
SDA and SCL signal timing for the I2C-compatible bus. See the Figure 1 for timing values.
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Programming (continued)
tBUF
SDA
tfDA
tHD;STA
trCL
tLOW
tfCL
trDA
tSP
SCL
tHD;STA
tSU;STA
tHIGH
tSU;STO
tHD;DAT
tSU;DAT
START
STOP
REPEATED
START
START
Figure 17. I2C-Compatible Timing
7.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP87524B/JQ1 pulls down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP87524B/J-Q1
generates an acknowledge after each byte has been received.
There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
NOTE
If the NRST signal is low during I2C communication the LP87524B/J-Q1 device does not
drive SDA line. The ACK signal and data transfer to the master is disabled at that time.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ack from slave
ack from slave
ack from slave
start
MSB Chip Addr LSB
w
ack
MSB Register Addr LSB
ack
MSB
Data LSB
ack
stop
start
id = 60h
w
ack
addr = 40h
ack
address 40h data
ack
stop
SCL
SDA
Figure 18. Write Cycle (w = write; SDA = 0), id = Device Address = 0x60 for LP87524B/J-Q1
32
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Programming (continued)
ack from slave
start
MSB Chip Addr LSB
w
ack from slave
MSB Register Addr LSB
repeated start
ack from slave data from slave nack from master
rs
MSB Chip Address LSB
rs
id = 60h
r
MSB
Data
LSB
stop
address 3Fh data
nack stop
SCL
SDA
start
id =60h
w ack
address = 3Fh
ack
r ack
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 19. Read Cycle ( r = read; SDA = 1), id = Device Address = 0x60 for LP87524B/J-Q1
7.5.1.4 I2C-Compatible Chip Address
NOTE
The device address for the LP87524B/J-Q1 is 0x60
After the START condition, the I2C master sends the 7-bit address followed by an eighth bit, read or write (R/W).
R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The second byte following the device address
selects the register address to which the data will be written. The third byte contains the data for the selected
register.
MSB
1
Bit 7
LSB
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
2
I C Slave Address (chip address)
A.
Here device address is 1100000Bin = 60Hex.
Figure 20. Example Device Address
7.5.1.5 Auto-Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8bit word is sent to the device, the internal address index counter is incremented by one and the next register is
written. Table 8 below shows writing sequence to two consecutive registers. Note that auto increment feature
does not work for read.
Table 8. Auto-Increment Example
MASTER
ACTION
START
DEVICE
ADDRESS
= 0x60
LP87524B/J-Q1
REGISTER
ADDRESS
WRITE
ACK
DATA
ACK
DATA
ACK
STOP
ACK
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7.6 Register Maps
7.6.1 Register Descriptions
The LP87524B/J-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers,
their addresses, and their abbreviations are listed in Table 9. A more detailed description is given in the
OTP_REV to GPIO_OUT sections.
The asterisk (*) marking indicates register bits which are updated from OTP memory during READ OTP state.
NOTE
This register map describes the default values read from OTP memory for a device with
orderable code of LP87524BRNFRQ1 and LP87524JRNFRQ1. For other LP8752x
versions the default values read from OTP memory can be different.
Table 9. Summary of LP87524B/J-Q1 Control Registers
34
Addr
Register
Read /
Write
D7
D6
0x01
OTP_REV
R
0x02
BUCK0_
CTRL1
0x04
D5
D4
D3
D2
D1
D0
R/W
EN_BUCK0
EN_PIN_
CTRL0
BUCK0_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR0
EN_RDIS0
BUCK0_
FPWM
Reserved
BUCK1_
CTRL1
R/W
EN_BUCK1
EN_PIN_
CTRL1
BUCK1_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR1
EN_RDIS1
BUCK1_
FPWM
Reserved
0x06
BUCK2_
CTRL1
R/W
EN_BUCK2
EN_PIN_
CTRL2
BUCK2_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR2
EN_RDIS2
BUCK2_
FPWM
Reserved
0x08
BUCK3_
CTRL1
R/W
EN_BUCK3
EN_PIN_
CTRL3
BUCK3_EN_PIN
SELECT[1:0]
EN_ROOF
_FLOOR3
EN_RDIS3
BUCK3_
FPWM
Reserved
0x0A
BUCK0_
VOUT
R/W
BUCK0_VSET[7:0]
0x0B
BUCK0_
FLOOR_
VOUT
R/W
BUCK0_FLOOR_VSET[7:0]
0x0C
BUCK1_
VOUT
R/W
BUCK1_VSET[7:0]
0x0D
BUCK1_
FLOOR_
VOUT
R/W
BUCK1_FLOOR_VSET[7:0]
0x0E
BUCK2_
VOUT
R/W
BUCK2_VSET[7:0]
0x0F
BUCK2_
FLOOR_
VOUT
R/W
BUCK2_FLOOR_VSET[7:0]
0x10
BUCK3_
VOUT
R/W
BUCK3_VSET[7:0]
0x11
BUCK3_
FLOOR_
VOUT
R/W
BUCK3_FLOOR_VSET[7:0]
0x12
BUCK0_
DELAY
R/W
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
0x13
BUCK1_
DELAY
R/W
BUCK1_SHUTDOWN_DELAY[3:0]
BUCK1_STARTUP_DELAY[3:0]
0x14
BUCK2_
DELAY
R/W
BUCK2_SHUTDOWN_DELAY[3:0]
BUCK2_STARTUP_DELAY[3:0]
0x15
BUCK3_
DELAY
R/W
BUCK3_SHUTDOWN_DELAY[3:0]
BUCK3_STARTUP_DELAY[3:0]
0x16
GPIO2_
DELAY
R/W
GPIO2_SHUTDOWN_DELAY[3:0]
GPIO2_STARTUP_DELAY[3:0]
0x17
GPIO3_
DELAY
R/W
GPIO3_SHUTDOWN_DELAY[3:0]
GPIO3_STARTUP_DELAY[3:0]
0x18
RESET
R/W
OTP_ID[7:0]
Reserved
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Register Maps (continued)
Table 9. Summary of LP87524B/J-Q1 Control Registers (continued)
Addr
Register
Read /
Write
D7
D6
D5
D4
D3
D2
D1
D0
0x19
CONFIG
R/W
DOUBLE_D
ELAY
CLKIN_PD
Reserved
EN3_PD
TDIE
_WARN
_LEVEL
EN2_PD
EN1_PD
Reserved
0x1A
INT_TOP1
R/W
Reserved
INT_
BUCK23
INT_
BUCK01
NO_SYNC
_CLK
TDIE_SD
TDIE_
WARN
INT_
OVP
I_LOAD_
READY
0x1B
INT_TOP2
R/W
0x1C
INT_BUCK_
0_1
R/W
Reserved
BUCK1_
PG_INT
BUCK1_
SC_INT
BUCK1_
ILIM_INT
Reserved
BUCK0_
PG_INT
BUCK0_
SC_INT
BUCK0_
ILIM_INT
0x1D
INT_BUCK_
2_3
R/W
Reserved
BUCK3_
PG_INT
BUCK3_
SC_INT
BUCK3_
ILIM_INT
Reserved
BUCK2_
PG_INT
BUCK2_
SC_INT
BUCK2_
ILIM_INT
0x1E
TOP_
STAT
R
SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_
WARN_
STAT
OVP_
STAT
Reserved
0x1F
BUCK_0_1_
STAT
R
BUCK1_
STAT
BUCK1_
PG_STAT
Reserved
BUCK1_
ILIM_
STAT
BUCK0_
STAT
BUCK0_
PG_STAT
Reserved
BUCK0_
ILIM_
STAT
0x20
BUCK_2_3_
STAT
R
BUCK3_
STAT
BUCK3_
PG_STAT
Reserved
BUCK3_
ILIM_STAT
BUCK2_
STAT
BUCK2_
PG_STAT
Reserved
BUCK2_
ILIM_STAT
0x21
TOP_
MASK1
R/W
Reserved
SYNC_CLK
_MASK
Reserved
TDIE_WAR
N_MASK
Reserved
I_LOAD_
READY_
MASK
0x22
TOP_
MASK2
R/W
0x23
BUCK_0_1_
MASK
R/W
Reserved
BUCK1_
PG_MASK
Reserved
BUCK1_
ILIM_
MASK
Reserved
BUCK0_
PG_MASK
Reserved
BUCK0_
ILIM_
MASK
0x24
BUCK_2_3_
MASK
R/W
Reserved
BUCK3_
PG_MASK
Reserved
BUCK3_
ILIM_
MASK
Reserved
BUCK2_
PG_MASK
Reserved
BUCK2_
ILIM_
MASK
0x25
SEL_I_
LOAD
R/W
Reserved
LOAD_CURRENT_
BUCK_SELECT[1:0]
0x26
I_LOAD_2
R
Reserved
BUCK_LOAD_CURRENT[
9:8]
0x27
I_LOAD_1
R
0x28
PGOOD
_CTRL1
R/W
0x29
PGOOD
_CTRL2
R/W
0x2A
PGOOD_FL
T
R
0x2B
PLL_CTRL
R/W
Reserved
RESET_
REG_MASK
BUCK_LOAD_CURRENT[7:0]
PG3_SEL[1:0]
HALF_DEL
AY
EN_PG0_
NINT
PLL_MODE[1:0]
0x2C
PIN_
FUNCTION
R/W
0x2D
GPIO_
CONFIG
R/W
Reserved
0x2E
GPIO_IN
R
GPIO_OUT
Reserved
Reserved
EN_
SPREAD
_SPEC
0x2F
RESET_
REG
Reserved
R/W
PG2_SEL[1:0]
PGOOD_SE
T_
DELAY
EN_PGFLT
_STAT
Reserved
PG1_SEL[1:0]
PG0_SEL[1:0]
Reserved
PGOOD_WI
NDOW
PGOOD_O
D
PGOOD_P
OL
PG3_FLT
PG2_FLT
PG1_FLT
PG0_FLT
EXT_CLK_FREQ[4:0]
EN_PIN_CT
RL
_GPIO3
EN_PIN_SE
LECT
_GPIO3
EN_PIN_CT
RL
_GPIO2
EN_PIN_SE
LECT
_GPIO2
GPIO3_SEL
GPIO2_SEL
GPIO1_SEL
GPIO3_OD
GPIO2_OD
GPIO1_OD
Reserved
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
Reserved
GPIO3_IN
GPIO2_IN
GPIO1_IN
Reserved
GPIO3_OU
T
GPIO2_OU
T
GPIO1_OU
T
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7.6.1.1 OTP_REV
Address: 0x01
D7
D6
D5
D4
D3
D2
D1
D0
OTP_ID[7:0]
Bits
Field
Type
7:0
OTP_ID[7:0]
R
Default
Description
0x71* for
LP87524B
Identification code of the OTP EPROM version
0x72* for
LP87524J
7.6.1.2 BUCK0_CTRL1
Address: 0x02
D7
D6
EN_BUCK0
EN_PIN_CTRL
0
D5
D4
BUCK0_EN_PIN_SELECT[1:0]
D3
D2
D1
D0
EN_ROOF_
FLOOR0
EN_RDIS0
BUCK0_FPWM
Reserved
Bits
Field
Type
Default
7
EN_BUCK0
R/W
1*
Enable Buck0 regulator:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled
6
EN_PIN_CTRL0
R/W
1*
Enable EN1/2/3 pin control for Buck0:
0 - Only the EN_BUCK0 bit controls Buck0
1 - EN_BUCK0 bit AND ENx pin control Buck0
5:4
BUCK0_EN_PIN
_SELECT[1:0]
R/W
0x0*
3
EN_ROOF_
FLOOR0
R/W
0
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL0 = 1:
0 - Enable/disable (1/0) control
1 - Roof/floor (1/0) control
2
EN_RDIS0
R/W
1
Enable output discharge resistor when Buck0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1
BUCK0_FPWM
R/W
0*
0
Reserved
R/W
0*
36
Description
Enable EN1/2/3 pin control for Buck0:
0x0 - EN_BUCK0 bit AND EN1 pin control Buck0
0x1 - EN_BUCK0 bit AND EN2 pin control Buck0
0x2 - EN_BUCK0 bit AND EN3 pin control Buck0
0x3 - Reserved
Forces the Buck0 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode).
1 - Forced to PWM operation
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7.6.1.3 BUCK1_CTRL1
Address: 0x04
D7
D6
EN_BUCK1
EN_PIN_CTRL
1
D5
D4
BUCK1_EN_PIN_SELECT[1:0]
D3
D2
D1
D0
EN_ROOF_
FLOOR1
EN_RDIS1
BUCK1_FPWM
Reserved
Bits
Field
Type
Default
Description
7
EN_BUCK1
R/W
1*
Enable Buck1 regulator:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled
6
EN_PIN_CTRL1
R/W
1*
Enable EN1/2/3 pin control for Buck1:
0 - Only EN_BUCK1 bit controls Buck1
1 - EN_BUCK1 bit AND ENx pin control Buck1
5:4
BUCK1_EN_PIN
_SELECT[1:0]
R/W
0x0*
3
EN_ROOF_
FLOOR1
R/W
0
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL1 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control
2
EN_RDIS1
R/W
1
Enable output discharge resistor when Buck1 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1
BUCK1_FPWM
R/W
0*
0
Reserved
R/W
0
Enable EN1/2/3 pin control for Buck1:
0x0 - EN_BUCK1 bit AND EN1 pin control Buck1
0x1 - EN_BUCK1 bit AND EN2 pin control Buck1
0x2 - EN_BUCK1 bit AND EN3 pin control Buck1
0x3 - Reserved
Forces the Buck1 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode).
1 - Forced to PWM operation
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7.6.1.4 BUCK2_CTRL1
Address: 0x06
D7
D6
EN_BUCK2
EN_PIN_CTRL
2
D5
D4
BUCK2_EN_PIN_SELECT[1:0]
D3
D2
D1
D0
EN_ROOF_
FLOOR2
EN_RDIS2
BUCK2_FPWM
Reserved
Bits
Field
Type
Default
7
EN_BUCK2
R/W
1*
Enable Buck2 regulator:
0 - Buck2 regulator is disabled
1 - Buck2 regulator is enabled
6
EN_PIN_CTRL2
R/W
1*
Enable EN1/2/3 pin control for Buck2:
0 - Only EN_BUCK2 bit controls Buck2
1 - EN_BUCK2 bit AND ENx pin control Buck2
5:4
BUCK2_EN_PIN
_SELECT[1:0]
R/W
0x0*
3
EN_ROOF_
FLOOR2
R/W
0
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL2 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control
2
EN_RDIS2
R/W
1
Enable output discharge resistor when Buck2 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1
BUCK2_FPWM
R/W
1*
0
Reserved
R/W
0*
38
Description
Enable EN1/2/3 pin control for Buck2:
0x0 - EN_BUCK2 bit AND EN1 pin control Buck2
0x1 - EN_BUCK2 bit AND EN2 pin control Buck2
0x2 - EN_BUCK2 bit AND EN3 pin control Buck2
0x3 - Reserved
Forces the Buck2 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation
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7.6.1.5 BUCK3_CTRL1
Address: 0x08
D7
D6
EN_BUCK3
EN_PIN_CTRL
3
D5
D4
BUCK3_EN_PIN_SELECT[1:0]
D3
D2
D1
D0
EN_ROOF_
FLOOR3
EN_RDIS3
BUCK3_FPWM
Reserved
Bits
Field
Type
Default
Description
7
EN_BUCK3
R/W
1*
Enable Buck3 regulator:
0 - Buck3 regulator is disabled
1 - Buck3 regulator is enabled
6
EN_PIN_CTRL3
R/W
1*
Enable EN1/2/3 pin control for Buck3:
0 - Only EN_BUCK3 bit controls Buck3
1 - EN_BUCK3 bit AND ENx pin control Buck3
5:4
BUCK3_EN_PIN
_SELECT[1:0]
R/W
0x0*
3
EN_ROOF_
FLOOR3
R/W
0
Enable Roof/Floor control of EN1/2/3 pin if EN_PIN_CTRL3 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control
2
EN_RDIS3
R/W
1
Enable output discharge resistor when Buck3 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled
1
BUCK3_FPWM
R/W
1*
0
Reserved
R/W
0
Enable EN1/2/3 pin control for Buck3:
0x0 - EN_BUCK3 bit AND EN1 pin control Buck3
0x1 - EN_BUCK3 bit AND EN2 pin control Buck3
0x2 - EN_BUCK3 bit AND EN3 pin control Buck3
0x3 - Reserved
Forces the Buck3 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode)
1 - Forced to PWM operation
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7.6.1.6 BUCK0_VOUT
Address: 0x0A
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_VSET[7:0]
Bits
Field
Type
Default
7:0
BUCK0_VSET[7:0]
R/W
0xFC*
Description
Sets the output voltage of Buck0 regulator
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.7 BUCK0_FLOOR_VOUT
Address: 0x0B
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_FLOOR_VSET[7:0]
Bits
Field
Type
Default
7:0
BUCK0_FLOOR
_VSET[7:0]
R/W
0x00
Description
Sets the output voltage of Buck0 regulator when floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.8 BUCK1_VOUT
Address: 0x0C
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_VSET[7:0]
40
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Bits
Field
Type
Default
7:0
BUCK1_VSET[7:0]
R/W
0x75*
Description
Sets the output voltage of Buck1 regulator:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.9 BUCK1_FLOOR_VOUT
Address: 0x0D
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_FLOOR_VSET[7:0]
Bits
Field
Type
Default
7:0
BUCK1_FLOOR
_VSET[7:0]
R/W
0x00
Description
Sets the output voltage of Buck1 regulator when floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.10 BUCK2_VOUT
Address: 0x0E
D7
D6
D5
D4
D3
D2
D1
D0
BUCK2_VSET[7:0]
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Bits
Field
Type
Default
7:0
BUCK2_VSET[7:0]
R/W
0xB1* for
LP87524B
0x4D* for
LP87524J
www.ti.com
Description
Sets the output voltage of Buck2 regulator:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.11 BUCK2_FLOOR_VOUT
Address: 0x0F
D7
D6
D5
D4
D3
D2
D1
D0
BUCK2_FLOOR_VSET[7:0]
Bits
Field
Type
Default
7:0
BUCK2_FLOOR
_VSET[7:0]
R/W
0x00
Description
Sets the output voltage of Buck2 regulator when floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.12 BUCK3_VOUT
Address: 0x10
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_VSET[7:0]
42
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Bits
Field
Type
Default
7:0
BUCK3_VSET[7:0]
R/W
0xCA* for
LP87524B
0xB1* for
LP87524J
Description
Sets the output voltage of Buck3 regulator:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.13 BUCK3_FLOOR_VOUT
Address: 0x11
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_FLOOR_VSET[7:0]
Bits
Field
Type
Default
7:0
BUCK3_FLOOR
_VSET[7:0]
R/W
0x00
Description
Sets the output voltage of Buck3 regulator when Floor state is used:
Reserved, DO NOT USE
0x00...0x09
0.6 V - 0.73 V, 10 mV steps
0x0A - 0.6 V
...
0x17 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0x18 - 0.735 V
...
0x9D - 1.4 V
1.4 V - 3.36 V, 20 mV steps
0x9E - 1.42 V
...
0xFF - 3.36 V
If the input voltage is above 4 V, do not use output voltages below 1.0 V.
7.6.1.14 BUCK0_DELAY
Address: 0x12
D7
D6
D5
D4
D3
BUCK0_SHUTDOWN_DELAY[3:0]
D2
D1
D0
BUCK0_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
BUCK0_
SHUTDOWN_
DELAY[3:0]
R/W
0x0*
Shutdown delay of Buck0 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
Description
3:0
BUCK0_
STARTUP_
DELAY[3:0]
R/W
0x5*
Start-up delay of Buck0 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
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7.6.1.15 BUCK1_DELAY
Address: 0x13
D7
D6
D5
D4
D3
BUCK1_SHUTDOWN_DELAY[3:0]
D2
D1
D0
BUCK1_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
BUCK1_
SHUTDOWN_
DELAY[3:0]
R/W
0x0*
Shutdown delay of Buck1 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
Description
3:0
BUCK1_
STARTUP_
DELAY[3:0]
R/W
0x5*
start-up delay of Buck1 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.16 BUCK2_DELAY
Address: 0x14
D7
D6
D5
D4
D3
BUCK2_SHUTDOWN_DELAY[3:0]
D2
D1
D0
BUCK2_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
7:4
BUCK2_
SHUTDOWN_
DELAY[3:0]
R/W
0x0*
Shutdown delay of Buck2 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
3:0
BUCK2_
STARTUP_
DELAY[3:0]
R/W
0x2*
start-up delay of Buck2 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
44
Description
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7.6.1.17 BUCK3_DELAY
Address: 0x15
D7
D6
D5
D4
D3
BUCK3_SHUTDOWN_DELAY[3:0]
D2
D1
D0
BUCK3_start-up_DELAY[3:0]
Bits
Field
Type
Default
7:4
BUCK3_
SHUTDOWN_
DELAY[3:0]
R/W
0x1*
Shutdown delay of Buck3 from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
Description
3:0
BUCK3_
STARTUP_
DELAY[3:0]
R/W
0x0*
Startup delay of Buck3 from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.18 GPIO2_DELAY
Address: 0x16
D7
D6
D5
D4
D3
GPIO2_SHUTDOWN_DELAY[3:0]
D2
D1
D0
GPIO2_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
GPIO2_
SHUTDOWN_
DELAY[3:0]
R/W
0x0*
Delay for GPIO2 falling edge from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
3:0
GPIO2_
STARTUP_
DELAY[3:0]
R/W
0x5*
Delay for GPIO2 rising edge from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.19 GPIO3_DELAY
Address: 0x17
D7
D6
D5
D4
D3
GPIO3_SHUTDOWN_DELAY[3:0]
D2
D1
D0
GPIO3_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
GPIO3_
SHUTDOWN_
DELAY[3:0]
R/W
0x0*
Delay for GPIO3 falling edge from falling edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
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Bits
Field
Type
Default
3:0
GPIO3_
STARTUP_
DELAY[3:0]
R/W
0x3*
www.ti.com
Description
Delay for GPIO3 rising edge from rising edge of ENx signal (DOUBLE_DELAY = 0 in
CONTROL register and HALF_DELAY = 0 in PGOOD_CTRL2 register. See other
delay options in Table 4):
0x0 - 0 ms
0x1 - 1 ms
...
0xF - 15 ms
7.6.1.20 RESET
Address: 0x18
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
0x00
0
SW_RESET
R/W
0
D0
SW_RESET
Description
Software commanded reset. When written to 1, the registers are reset to default
values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared.
7.6.1.21 CONFIG
Address: 0x19
D7
D6
D5
D4
D3
D2
D1
D0
DOUBLE_DEL
AY
CLKIN_PD
EN4_PD
EN3_PD
TDIE_WARN_
LEVEL
EN2_PD
EN1_PD
Reserved
Bits
Field
Type
Default
7
DOUBLE_DELAY
R/W
0*
Start-up and shutdown delays from ENx signals:
0 - 0 ms - 15 ms with 1-ms steps
1 - 0 ms - 30 ms with 2-ms steps
Description
6
CLKIN_PD
R/W
1*
Selects the pulldown resistor on the CLKIN input pin:
0 - Pulldown resistor is disabled.
1 - Pulldown resistor is enabled.
5
Reserved
R/W
0*
4
EN3_PD
R/W
0*
Selects the pulldown resistor on the EN3 (GPIO3) input pin:
0 - Pulldown resistor is disabled.
1 - Pulldown resistor is enabled.
3
TDIE_WARN_
LEVEL
R/W
1*
Thermal warning threshold level:
0 - 125°C
1 - 137°C.
2
EN2_PD
R/W
0*
Selects the pull down resistor on the EN2 (GPIO2) input pin:
0 - Pulldown resistor is disabled.
1 - Pull-down resistor is enabled.
1
EN1_PD
R/W
1*
Selects the pull down resistor on the EN1 (GPIO1) input pin:
0 - Pulldown resistor is disabled.
1 - Pulldown resistor is enabled.
0
Reserved
R/W
0
7.6.1.22 INT_TOP1
Address: 0x1A
46
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
INT_BUCK23
INT_BUCK01
NO_SYNC_CL
K
TDIE_SD
TDIE_WARN
INT_OVP
I_LOAD_
READY
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Bits
Field
Type
Default
7
Reserved
R/W
0
Description
6
INT_BUCK23
R
0
Interrupt indicating that output Buck3 and/or Buck2 have a pending interrupt. The
reason for the interrupt is indicated in INT_BUCK_2_3 register.
This bit is cleared automatically when INT_BUCK_2_3 register is cleared to 0x00.
5
INT_BUCK01
R
0
Interrupt indicating that output Buck1 and/or Buck0 have a pending interrupt. The
reason for the interrupt is indicated in INT_BUCK_0_1 register.
This bit is cleared automatically when INT_BUCK_0_1 register is cleared to 0x00.
4
NO_SYNC_CLK
R/W
0
Latched status bit indicating that the external clock is not valid.
Write 1 to clear interrupt.
3
TDIE_SD
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal shutdown level. The regulators have been disabled if they were enabled. The
regulators cannot be enabled if this bit is active. The actual status of the thermal
warning is indicated by TDIE_SD_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
2
TDIE_WARN
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal warning level. The actual status of the thermal warning is indicated by
TDIE_WARN_STAT bit in TOP_STAT register.
Write 1 to clear interrupt.
1
INT_OVP
R/W
0
Latched status bit indicating that the input voltage has exceeded the overvoltage
detection level. The actual status of the overvoltage is indicated by OVP_STAT bit in
TOP_STAT register.
Write 1 to clear interrupt.
0
I_LOAD_READY
R/W
0
Latched status bit indicating that the load current measurement result is available in
I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.
7.6.1.23 INT_TOP2
Address: 0x1B
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
0x00
0
RESET_REG
R/W
0
D0
RESET_REG
Description
Latched status bit indicating that either start-up (NRST rising edge) is done, VANA
supply voltage has been below undervoltage threshold level, or the host has requested
a reset (SW_RESET bit in RESET register). The regulators have been disabled, and
registers are reset to default values and the normal start-up procedure is done.
Write 1 to clear interrupt.
7.6.1.24 INT_BUCK_0_1
Address: 0x1C
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_PG
_INT
BUCK1_SC
_INT
BUCK1_ILIM
_INT
Reserved
BUCK0_PG
_INT
BUCK0_SC
_INT
BUCK0_ILIM
_INT
Bits
Field
Type
Default
Description
7
Reserved
R/W
0
6
BUCK1_PG_INT
R/W
0
Latched status bit indicating that Buck1 output voltage has reached Power-Goodthreshold level.
Write 1 to clear.
5
BUCK1_SC_INT
R/W
0
Latched status bit indicating that the Buck1 output voltage has fallen below 0.35-V
level during operation or Buck1 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
4
BUCK1_ILIM_INT
R/W
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
3
Reserved
R/W
0
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Bits
Field
Type
Default
2
BUCK0_PG_INT
R/W
0
Latched status bit indicating that Buck0 output voltage has reached Power-Goodthreshold level.
Write 1 to clear.
Description
1
BUCK0_SC_INT
R/W
0
Latched status bit indicating that the Buck0 output voltage has fallen below 0.35-V
level during operation or Buck0 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
0
BUCK0_ILIM_INT
R/W
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
7.6.1.25 INT_BUCK_2_3
Address: 0x1D
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_PG
_INT
BUCK3_SC
_INT
BUCK3_ILIM
_INT
Reserved
BUCK2_PG
_INT
BUCK2_SC
_INT
BUCK2_ILIM
_INT
Bits
Field
Type
Default
7
Reserved
R/W
0
Description
6
BUCK3_PG_INT
R/W
0
Latched status bit indicating that Buck3 output voltage has reached Power-Goodthreshold level.
Write 1 to clear.
5
BUCK3_SC_INT
R/W
0
Latched status bit indicating that the Buck3 output voltage has fallen below 0.35-V
level during operation or Buck3 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
4
BUCK3_ILIM_INT
R/W
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
3
Reserved
R/W
0
2
BUCK2_PG_INT
R/W
0
Latched status bit indicating that Buck2 output voltage has reached Power-Goodthreshold level.
Write 1 to clear.
1
BUCK2_SC_INT
R/W
0
Latched status bit indicating that the Buck2 output voltage has fallen below 0.35-V
level during operation or Buck2 output did not reach 0.35-V level in 1 ms from enable.
Write 1 to clear.
0
BUCK2_ILIM_INT
R/W
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
7.6.1.26 TOP_STAT
Address: 0x1E
D7
D6
D5
Reserved
D4
D3
D2
D1
D0
SYNC_CLK
_STAT
TDIE_SD
_STAT
TDIE_WARN
_STAT
OVP_STAT
Reserved
Bits
Field
Type
Default
7:5
Reserved
R
0x0
4
SYNC_CLK_STAT
R
0
Status bit indicating the status of external clock (CLKIN):
0 - External clock frequency is valid
1 - External clock frequency is not valid
3
TDIE_SD_STAT
R
0
Status bit indicating the status of thermal shutdown:
0 - Die temperature below thermal shutdown level
1 - Die temperature above thermal shutdown level
2
TDIE_WARN
_STAT
R
0
Status bit indicating the status of thermal warning:
0 - Die temperature below thermal warning level
1 - Die temperature above thermal warning level
1
OVP_STAT
R
0
Status bit indicating the status of input overvoltage monitoring:
0 - Input voltage below overvoltage threshold level
1 - Input voltage above overvoltage threshold level
0
Reserved
R
0
48
Description
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7.6.1.27 BUCK_0_1_STAT
Address: 0x1F
D7
D6
D5
D4
D3
D2
D1
D0
BUCK1_STAT
BUCK1_PG
_STAT
Reserved
BUCK1_ILIM
_STAT
BUCK0_STAT
BUCK0_PG
_STAT
Reserved
BUCK0_ILIM
_STAT
Bits
Field
Type
Default
Description
7
BUCK1_STAT
R
0
Status bit indicating the enable/disable status of Buck1:
0 - Buck1 regulator is disabled
1 - Buck1 regulator is enabled
6
BUCK1_PG_STAT
R
0
Status bit indicating Buck1 output voltage validity (raw status)
0 - Buck1 output is below Power-Good-threshold level
1 - Buck1 output is above Power-Good-threshold level
5
Reserved
R
0
4
BUCK1_ILIM
_STAT
R
0
Status bit indicating Buck1 current limit status (raw status)
0 - Buck1 output current is below current limit level
1 - Buck1 output current limit is active
3
BUCK0_STAT
R
0
Status bit indicating the enable/disable status of Buck0:
0 - Buck0 regulator is disabled
1 - Buck0 regulator is enabled
2
BUCK0_PG_STAT
R
0
Status bit indicating Buck0 output voltage validity (raw status):
0 - Buck0 output is below Power-Good-threshold level
1 - Buck0 output is above Power-Good-threshold level
1
Reserved
R
0
0
BUCK0_ILIM
_STAT
R
0
Status bit indicating Buck0 current limit status (raw status):
0 - Buck0 output current is below current limit level
1 - Buck0 output current limit is active
7.6.1.28 BUCK_2_3_STAT
Address: 0x20
D7
D6
D5
D4
D3
D2
D1
D0
BUCK3_STAT
BUCK3_PG
_STAT
Reserved
BUCK3_ILIM
_STAT
BUCK2_STAT
BUCK2_PG
_STAT
Reserved
BUCK2_ILIM
_STAT
Bits
Field
Type
Default
Description
7
BUCK3_STAT
R
0
Status bit indicating the enable/disable status of Buck3:
0 - Buck3 regulator is disabled
1 - Buck3 regulator is enabled
6
BUCK3_PG_STAT
R
0
Status bit indicating Buck3 output voltage validity (raw status):
0 - Buck3 output is below Power-Good-threshold level
1 - Buck3 output is above Power-Good-threshold level
5
Reserved
R
0
4
BUCK3_ILIM
_STAT
R
0
Status bit indicating Buck3 current limit status (raw status):
0 - Buck3 output current is below current limit level
1 - Buck3 output current limit is active
3
BUCK2_STAT
R
0
Status bit indicating the enable/disable status of Buck2:
0 - Buck2 regulator is disabled
1 - Buck2 regulator is enabled
2
BUCK2_PG_STAT
R
0
Status bit indicating Buck2 output voltage validity (raw status):
0 - Buck2 output is below Power-Good-threshold level
1 - Buck2 output is above Power-Good-threshold level
1
Reserved
R
0
0
BUCK2_ILIM
_STAT
R
0
Status bit indicating Buck2 current limit status (raw status):
0 - Buck2 output current is below current limit level
1 - Buck2 output current limit is active
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7.6.1.29 TOP_MASK1
Address: 0x21
D7
D6
Reserved
D5
Reserved
Bits
Field
Type
D4
D3
D2
D1
D0
SYNC_CLK
_MASK
Reserved
TDIE_WARN
_MASK
Reserved
I_LOAD_
READY_MASK
Default
7
Reserved
R/W
1*
6:5
Reserved
R/W
0x0
4
SYNC_CLK
_MASK
R/W
0*
3
Reserved
R/W
0
2
TDIE_WARN
_MASK
R/W
0*
1
Reserved
R/W
0
0
I_LOAD_
READY_MASK
R/W
1*
Description
Masking for external clock detection interrupt (NO_SYNC_CLK in INT_TOP1 register):
0 - Interrupt generated
1 - Interrupt not generated
Masking for thermal warning interrupt (TDIE_WARN in INT_TOP1 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect TDIE_WARN_STAT status bit in TOP_STAT register.
Masking for load current measurement ready interrupt (I_LOAD_READY in INT_TOP
register).
0 - Interrupt generated
1 - Interrupt not generated
7.6.1.30 TOP_MASK2
Address: 0x22
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:1
Reserved
R/W
0x00
0
RESET_REG
_MASK
R/W
1*
D0
RESET_REG
_MASK
Description
Masking for register reset interrupt (RESET_REG in INT_TOP2 register):
0 - Interrupt generated
1 - Interrupt not generated
7.6.1.31 BUCK_0_1_MASK
Address: 0x23
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_PG
_MASK
Reserved
BUCK1_ILIM
_MASK
Reserved
BUCK0_PG
_MASK
Reserved
BUCK0_ILIM
_MASK
Bits
Field
Type
Default
7
Reserved
R/W
0
6
BUCK1_PG_MASK
R/W
1*
50
5
Reserved
R
0
4
BUCK1_ILIM
_MASK
R/W
1*
3
Reserved
R/W
0
Description
Masking for Buck1 Power-Good interrupt (BUCK1_PG_INT in INT_BUCK_0_1
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK1_PG_STAT status bit in BUCK_0_1_STAT register.
Masking for Buck1 current-limit-detection interrupt (BUCK1_ILIM_INT in
INT_BUCK_0_1 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK1_ILIM_STAT status bit in BUCK_0_1_STAT register.
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Bits
Field
Type
Default
2
BUCK0_PG_MASK
R/W
1*
1
Reserved
R
0
0
BUCK0_ILIM
_MASK
R/W
1*
Description
Masking for Buck0 Power-Good interrupt (BUCK0_PG_INT in INT_BUCK_0_1
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK0_PG_STAT status bit in BUCK_0_1_STAT register.
Masking for Buck0 current-limit-detection interrupt (BUCK0_ILIM_INT in
INT_BUCK_0_1 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK0_ILIM_STAT status bit in BUCK_0_1_STAT register.
7.6.1.32 BUCK_2_3_MASK
Address: 0x24
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_PG
_MASK
Reserved
BUCK3_ILIM
_MASK
Reserved
BUCK2_PG
_MASK
Reserved
BUCK2_ILIM
_MASK
Bits
Field
Type
Default
7
Reserved
R/W
0
6
BUCK3_PG_MASK
R/W
1*
5
Reserved
R
0
4
BUCK3_ILIM
_MASK
R/W
1*
3
Reserved
R/W
0
2
BUCK2_PG_MASK
R/W
1*
1
Reserved
R
0
0
BUCK2_ILIM
_MASK
R/W
1*
Description
Masking for Buck3 Power-Good interrupt (BUCK3_PG_INT in INT_BUCK_2_3
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK3_PG_STAT status bit in BUCK_2_3_STAT register.
Masking for Buck3 current-limit-detection interrupt (BUCK3_ILIM_INT in
INT_BUCK_2_3 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK3_ILIM_STAT status bit in BUCK_2_3_STAT register.
Masking for Buck2 Power-Good interrupt (BUCK2_PG_INT in INT_BUCK_2_3
register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK2_PG_STAT status bit in BUCK_2_3_STAT register.
Masking for Buck2 current limit-detection interrupt (BUCK2_ILIM_INT in
INT_BUCK_2_3 register):
0 - Interrupt generated
1 - Interrupt not generated
This bit does not affect BUCK2_ILIM_STAT status bit in BUCK_2_3_STAT register.
7.6.1.33 SEL_I_LOAD
Address: 0x25
D7
D6
D5
D4
D3
D2
D1
Reserved
Bits
Field
Type
Default
7:2
Reserved
R/W
0x00
1:0
LOAD_CURRENT_
BUCK_SELECT
[1:0]
R/W
0x0
D0
LOAD_CURRENT_BUCK
_SELECT[1:0]
Description
Start the current measurement on the selected regulator:
0x0 - Buck0
0x1 - Buck1
0x2 - Buck2
0x3 - Buck3
A single measurement is started when register is written.
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7.6.1.34 I_LOAD_2
Address: 0x26
D7
D6
D5
D4
D3
D2
Reserved
Bits
Field
Type
Default
7:2
Reserved
R
0x00
1:0
BUCK_LOAD_
CURRENT[9:8]
R
0x0
D1
D0
BUCK_LOAD_CURRENT[9:8]
Description
This register describes 3 MSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and max code corresponding to 20.47-A current.
7.6.1.35 I_LOAD_1
Address: 0x27
D7
D6
D5
D4
D3
D2
D1
D0
BUCK_LOAD_CURRENT[7:0]
Bits
Field
Type
Default
Description
7:0
BUCK_LOAD_
CURRENT[7:0]
R
0x00
This register describes 8 LSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and max code corresponding to a 20.47-A current.
7.6.1.36 PGOOD_CTRL1
Address: 0x28
D7
D6
D5
PG3_SEL[1:0]
D4
D3
PG2_SEL[1:0]
D2
D1
PG1_SEL[1:0]
D0
PG0_SEL[1:0]
Bits
Field
Type
Default
Description
7:6
PG3_SEL[1:0]
R/W
0x1*
PGOOD signal source control from Buck3
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good-threshold voltage AND current limit
5:4
PG2_SEL[1:0]
R/W
0x1*
PGOOD signal source control from Buck2
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good threshold voltage AND current limit
3:2
PG1_SEL[1:0]
R/W
0x1*
PGOOD signal source control from Buck1
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good-threshold voltage AND current limit
1:0
PG0_SEL[1:0]
R/W
0x1*
PGOOD signal source control from Buck0
0x0 - Masked
0x1 - Power-Good-threshold voltage
0x2 - Reserved, do not use
0x3 - Power-Good-threshold voltage AND current limit
7.6.1.37 PGOOD_CTRL2
Address: 0x29
D7
D6
D5
D4
D3
D2
D1
D0
HALF_DELAY
EN_PG0
_NINT
PGOOD_SET
_DELAY
EN_PGFLT
_STAT
Reserved
PGOOD_
WINDOW
PGOOD_OD
PGOOD_POL
52
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Bits
Field
Type
Default
7
HALF_DELAY
R/W
0*
Select the time step for start-up and shutdown delays:
0 - Start-up and shutdown delays have 0.5-ms or 1-ms time steps, based on
DOUBLE_DELAY bit in CONFIG register.
1 - Start-up and shutdown delays have 0.32-ms or 0.64-ms time steps, based on
DOUBLE_DELAY bit in CONFIG register.
Description
6
EN_PG0_NINT
R/W
0*
Combine Buck0 PGOOD signal to nINT signal:
0 - Buck0 PGOOD signal not included to nINT signal
1 - Buck0 PGOOD signal included to nINT signal. If nINT OR Buck0 PGOOD is low
then nINT signal is low.
5
PGOOD_SET_DEL
AY
R/W
1*
Debounce time of output voltage monitoring for PGOOD signal (only when PGOOD
signal goes valid):
0 - 4-10 µs
1 - 11 ms
4
EN_PGFLT_STAT
R/W
0*
Operation mode for PGOOD signal:
0 - Indicates live status of monitored voltage outputs.
1 - Indicates status of PGOOD_FLT register, inactive if at least one of PGx_FLT bit is
inactive.
3
Reserved
R/W
0
2
PGOOD_WINDOW
R/W
1*
Voltage monitoring method for PGOOD signal:
0 - Only undervoltage monitoring
1 - Overvoltage and undervoltage monitoring
1
PGOOD_OD
R/W
1*
PGOOD signal type:
0 - Push-pull output (VANA level)
1 - Open-drain output
0
PGOOD_POL
R/W
0*
PGOOD signal polarity:
0 - PGOOD signal high when monitored outputs are valid
1 - PGOOD signal low when monitored outputs are valid
7.6.1.38 PGOOD_FLT
Address: 0x2A
D7
D6
D5
D4
Reserved
Bits
D3
D2
D1
D0
PG3_FLT
PG2_FLT
PG1_FLT
PG0_FLT
Field
Type
Default
Description
7:4
Reserved
R/W
0x0
3
PG3_FLT
R
0
Source for PGOOD inactive signal:
0 - Buck3 has not set PGOOD signal inactive.
1 - Buck3 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck3 output is valid.
2
PG2_FLT
R
0
Source for PGOOD inactive signal:
0 - Buck2 has not set PGOOD signal inactive.
1 - Buck2 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck2 output is valid.
1
PG1_FLT
R
0
Source for PGOOD inactive signal:
0 - Buck1 has not set PGOOD signal inactive.
1 - Buck1 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck1 output is valid.
0
PG0_FLT
R
0
Source for PGOOD inactive signal:
0 - Buck0 has not set PGOOD signal inactive.
1 - Buck0 has set PGOOD signal inactive. This bit can be cleared by reading this
register when Buck0 output is valid.
7.6.1.39 PLL_CTRL
Address: 0x2B
D7
D6
PLL_MODE[1:0]
D5
D4
D3
Reserved
D2
D1
D0
EXT_CLK_FREQ[4:0]
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Bits
Field
Type
Default
7:6
PLL_MODE[1:0]
R/W
0x2*
5
Reserved
R/W
0
4:0
EXT_CLK_FREQ[4
:0]
R/W
0x01*
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Description
Selection of external clock and PLL operation:
0x0 - Forced to internal RC oscillator — PLL disabled.
0x1 - PLL is enabled in STANDBY and ACTIVE modes. Automatic external clock use
when available, interrupt generated if external clock appears or disappears.
0x2 - PLL is enabled only in ACTIVE mode. Automatic external clock use when
available, interrupt generated if external clock appears or disappears.
0x3 - Reserved
Frequency of the external clock (CLKIN):
0x00 - 1 MHz
0x01 - 2 MHz
0x02 - 3 MHz
...
0x16 - 23 MHz
0x17 - 24 MHz
0x18...0x1F - Reserved
See Specifications for input clock frequency tolerance.
7.6.1.40 PIN_FUNCTION
Address: 0x2C
D7
D6
D5
D4
D3
D2
D1
D0
EN_SPREAD_
SPEC
EN_PIN_CTRL
_GPIO3
EN_PIN_SELE
CT_GPIO3
EN_PIN_CTRL
_GPIO2
EN_PIN_SELE
CT_GPIO2
GPIO3_SEL
GPIO2_SEL
GPIO1_SEL
Bits
Field
Type
Default
7
EN_SPREAD
_SPEC
R/W
0*
Enable spread-spectrum feature:
0 - Disabled
1 - Enabled
Description
6
EN_PIN_CTRL_GP
IO3
R/W
1*
Enable EN1/2 pin control for GPIO3 (GPIO3_SEL=1 AND GPIO3_DIR=1):
0 - Only GPIO3_OUT bit controls GPIO3.
1 - GPIO3_OUT bit AND ENx pin control GPIO3
5
EN_PIN_SELECT_
GPIO3
R/W
0*
Enable EN1/2 pin control for GPIO3:
0 - GPIO3_SEL bit AND EN1 pin control GPIO3
1 - GPIO3_SEL bit AND EN2 pin control GPIO3
4
EN_PIN_CTRL_GP
IO2
R/W
1*
Enable EN1/3 pin control for GPIO2 (GPIO2_SEL=1 AND GPIO2_DIR=1):
0 - Only GPIO2_OUT bit controls GPIO2.
1 - GPIO2_OUT bit AND ENx pin control GPIO2
3
EN_PIN_SELECT_
GPIO2
R/W
0*
Enable EN1/3 pin control for GPIO2:
0 - GPIO2_SEL bit AND EN1 pin control GPIO2
1 - GPIO2_SEL bit AND EN3 pin control GPIO2
2
GPIO3_SEL
R/W
1*
EN3 pin function:
0 - EN3
1 - GPIO3
1
GPIO2_SEL
R/W
1*
EN2 pin function:
0 - EN2
1 - GPIO2
0
GPIO1_SEL
R/W
0*
EN1 pin function:
0 - EN1
1 - GPIO1
7.6.1.41 GPIO_CONFIG
Address: 0x2D
54
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GPIO3_OD
GPIO2_OD
GPIO1_OD
Reserved
GPIO3_DIR
GPIO2_DIR
GPIO1_DIR
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Bits
Field
Type
Default
7
Reserved
R
0
Description
6
GPIO3_OD
R/W
1*
GPIO3 signal type when configured to output:
0 - Push-pull output (VANA level)
1 - Open-drain output
5
GPIO2_OD
R/W
1*
GPIO2 signal type when configured to output:
0 - Push-pull output (VANA level)
1 - Open-drain output
4
GPIO1_OD
R/W
0*
GPIO1 signal type when configured to output:
0 - Push-pull output (VANA level)
1 - Open-drain output
3
Reserved
R
0
2
GPIO3_DIR
R/W
1*
GPIO3 signal direction:
0 - Input
1 - Output
1
GPIO2_DIR
R/W
1*
GPIO2 signal direction:
0 - Input
1 - Output
0
GPIO1_DIR
R/W
0*
GPIO1 signal direction:
0 - Input
1 - Output
7.6.1.42 GPIO_IN
Address: 0x2E
D7
D6
D5
D4
D3
Reserved
Bits
Field
Type
Default
7:3
Reserved
R
0x00
2
GPIO3_IN
R
0
State of GPIO3 signal:
0 - Logic low level
1 - Logic high level
1
GPIO2_IN
R
0
State of GPIO2 signal:
0 - Logic low level
1 - Logic high level
0
GPIO1_IN
R
0
State of GPIO1 signal:
0 - Logic low level
1 - Logic high level
D2
D1
D0
GPIO3_IN
GPIO2_IN
GPIO1_IN
Description
7.6.1.43 GPIO_OUT
Address: 0x2F
D7
D6
D5
D4
D3
Reserved
D2
D1
D0
GPIO3_OUT
GPIO2_OUT
GPIO1_OUT
Bits
Field
Type
Default
7:3
Reserved
R/W
0x00
Description
2
GPIO3_OUT
R/W
1*
Control for GPIO3 signal when configured to GPIO Output:
0 - Logic low level
1 - Logic high level
1
GPIO2_OUT
R/W
1*
Control for GPIO2 signal when configured to GPIO Output:
0 - Logic low level
1 - Logic high level
0
GPIO1_OUT
R/W
0
Control for GPIO1 signal when configured to GPIO Output:
0 - Logic low level
1 - Logic high level
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LP87524B/J-Q1 is a multi-phase step-down converter with four switcher cores, which are configured to four
one-phase regulators configuration.
8.2 Typical Application
R0
VIN
VIN_B0
CIN0 CIN1 CIN2 CIN3
VIN_B1
SW_B0
FB_B0
C0
COUT0
VIN_B2
CVANA
CPOL0
LOAD
R1
VIN_B3
VANA
VOUT0
L0
C1
SW_B1
FB_B1
L1
VOUT1
COUT1
CPOL1
LOAD
R2
NRST
SDA
SCL
nINT
CLKIN
PGOOD
EN1 (GPIO1)
EN2 (GPIO2)
EN3 (GPIO3)
SW_B2
FB_B2
L2
C2
VOUT2
COUT2
CPOL2
LOAD
R3
SW_B3
FB_B3
C3
L3
VOUT3
COUT3
CPOL3
LOAD
GNDs
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Figure 21. Four 1-Phase Configuration
8.2.1 Design Requirements
8.2.1.1 Inductor Selection
The inductors are L0, L1, L2, and L3 are shown in the Typical Application. The inductance and DCR of the
inductor affects the control loop of the buck regulator. TI recommends using inductors similar to those listed in
Table 10. Pay attention to the saturation current and temperature rise current of the inductor. Check that the
saturation current is higher than the peak current limit and the temperature rise current is higher than the
maximum expected rms output current. Minimum effective inductance to ensure good performance is 0.22 μH at
maximum peak output current over the operating temperature range. DC resistance of the inductor must be less
than 0.05 Ω for good efficiency at high-current condition. The inductor AC loss (resistance) also affects
conversion efficiency. Higher Q factor at switching frequency usually gives better efficiency at light load to middle
load. Shielded inductors are preferred as they radiate less noise.
56
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Typical Application (continued)
Table 10. Recommended Inductors
MANUFACTURER
PART NUMBER
VALUE
DIMENSIONS
L × W × H (mm)
RATED DC CURRENT,
ISAT maximum (typical) / ITEMP
maximum (typical) (A)
DCR typical /
maximum
(mΩ)
TOKO
DFE252012PD-R47M
0.47 µH (20%)
2.5 × 2 × 1.2
5.2 (–) / 4 (–) (1)
- / 27
Vishay
(1)
IHLP1616AB-1A
0.47 µH (20%)
4.1 × 4.5 × 1.2
– (6 ) / – (6 )
(1)
19 / 21
Operating temperature range is up to 125°C including self temperature rise.
8.2.1.2 Input Capacitor Selection
The input capacitors CIN0, CIN1, CIN2, and CIN3 are shown in the Typical Application. A ceramic input bypass
capacitor of 10 μF is required for each phase of the regulator. Place the input capacitor as close as possible to
the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating improves the input
voltage filtering. Use X7R type of capacitors, not Y5V or F. DC bias characteristics capacitors must be
considered, minimum effective input capacitance to ensure good performance is 1.9 μF per buck input at
maximum input voltage including tolerances and ambient temperature range, assuming that there are at least 22
μF of additional capacitance common for all the power input pins on the system power rail. See Table 11.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces
voltage ripple imposed on the input power source. A ceramic capacitor's low ESR provides the best noise filtering
of the input voltage spikes due to this rapidly changing current. Select an input filter capacitor with sufficient
ripple current rating. In addition ferrite can be used in front of the input capacitor to reduce the EMI.
Table 11. Recommended Input Capacitors (X7R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
(mm)
VOLTAGE
RATING (V)
Murata
GCM21BR71A106KE22
10 µF (10%)
0805
2 × 1.25 × 1.25
10 V
8.2.1.3 Output Capacitor Selection
The output capacitors COUT0, COUT1, COUT2, and COUT3 are shown in Typical Application. A ceramic local output
capacitor of 22 μF is required per phase. Use ceramic capacitors, X7R or X7T types; do not use Y5V or F. DC
bias voltage characteristics of ceramic capacitors must be considered. The output filter capacitor smooths out
current flow from the inductor to the load, helps maintain a steady output voltage during transient load changes
and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance and sufficiently
low ESR and ESL to perform these functions. Minimum effective output capacitance to ensure good performance
is 10 μF per phase including the DC voltage roll-off, tolerances, aging and temperature effects.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part. See Table 12.
POL capacitors (CPOL0, CPOL1, CPOL2, CPOL3) can be used to improve load transient performance and to decrease
the ripple voltage. A higher output capacitance improves the load step behavior and reduces the output voltage
ripple as well as decreases the PFM switching frequency. However, output capacitance higher than 100 µF per
phase is not necessarily of any benefit. Note that the output capacitor may be the limiting factor in the output
voltage ramp and the maximum total output capacitance listed in electrical characteristics must not be exceeded.
At shutdown the output voltage is discharged to 0.6 V level using forced-PWM operation. This can increase the
input voltage if the load current is small and the output capacitor is large. Below 0.6 V level the output capacitor
is discharged by the internal discharge resistor and with large capacitor more time is required to settle VOUT down
as a consequence of the increased time constant.
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Table 12. Recommended Output Capacitors (X7R or X7T Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W × H
(mm)
VOLTAGE
RATING (V)
Murata
GCM31CR71A226KE02
22 µF (10%)
1206
3.2 × 1.6 × 1.6
10
8.2.1.4 Snubber Components
If the input voltage for the regulators is above 4 V, snubber components are needed at the switching nodes to
decrease voltage spiking in the switching node and to improve EMI. The snubber capacitors C0, C1, C2, and C3
and the snubber resistors R0, R1, R2, and R3 are shown in Figure 21. The recommended components are shown
in Table 13 and these component values give good performance on LP87524B/J-Q1 EVM. The optimal
resistance and capacitance values finally depend on the PCB layout.
Table 13. Recommended Snubber Components
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W x
H (mm)
VOLTAGE /
POWER RATING
Vishay-Dale
CRCW04023R90JNED
3.9 Ω (5%)
0402
1 × 0.5 × 0.4
62 mW
Murata
GCM1555C1H391JA16
390 pF (5%)
0402
1 × 0.5 × 0.5
50 V
8.2.1.5 Supply Filtering Components
The VANA input is used to supply analog and digital circuits in the device. See Table 14 for recommended
components for VANA input supply filtering.
Table 14. Recommended Supply Filtering Components
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L × W ×
H (mm)
VOLTAGE RATING
(V)
Murata
GCM155R71C104KA55
100 nF (10%)
0402
1.0 × 0.5 × 0.5
16
Murata
GCM188R71C104KA37
100 nF (10%)
0603
1.6 × 0.8 × 0.8
16
8.2.2 Detailed Design Procedure
The performance of the LP87524B/J-Q1 device depends greatly on the care taken in designing the printed circuit
board (PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended,
while proper grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling
capacitors must be connected close to the device and between the power and ground pins to support high peak
currents being drawn from system power rail during turnon of the switching MOSFETs. Keep input and output
traces as short as possible, because trace inductance, resistance, and capacitance can easily become the
performance limiting items. The separate power pins VIN_Bx are not connected together internally. Connect the
VIN_Bx power connections together outside the package using power plane construction.
58
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8.2.3 Application Curves
Measurements are done using typical application set up with connections shown in Figure 21 (snubber
components included when VIN > 4 V). Graphs may not reflect the OTP default settings. Unless otherwise
specified: VIN = 3.7 V, VOUT = 1 V, V(NRST) = 1.8 V, TA = 25°C, ƒSW = 4 MHz, L = 0.47 µH (TOKO DFE252012PDR47M), COUT = 22 µF / phase, and CPOL = 22 µF / phase. Measurements are done using connections in the
Typical Application.
100
100
90
80
Efficiency (%)
Efficiency (%)
90
70
60
1PH, VIN=3.3V, AUTO
1PH, VIN=3.3V, FPWM
1PH, VIN=5.0V, AUTO
1PH, VIN=5.0V, FPWM
50
40
0.001
0.01
0.1
Output Current (A)
1
80
70
60
1PH, VOUT=1.0V, FPWM
1PH, VOUT=1.8V, FPWM
1PH, VOUT=2.5V, FPWM
50
0.01
5
0.1
Output Current (A)
D923
VOUT = 1.8 V
1
5
D924
VIN = 3.3 V
Figure 22. Efficiency in PFM/PWM Mode
Figure 23. Efficiency in Forced-PWM Mode
100
1.02
1.016
1.012
1.008
Output Voltage (V)
Efficiency (%)
90
80
70
60
1.004
1
0.996
0.992
0.988
1PH, VOUT=1.0V, FPWM
1PH, VOUT=1.8V, FPWM
1PH, VOUT=2.5V, FPWM
50
40
0.01
0.1
Output Current (A)
1
1PH, Vin=3.3V, FPWM
1PH, Vin=5.0V, FPWM
0.984
0.98
5
0
0.5
D925
1
1.5
2
2.5
Output Current (A)
3
3.5
D026
VIN = 5 V
Figure 25. Output Voltage vs Load Current in Forced-PWM
Mode
1.02
1.02
1.016
1.016
1.012
1.012
1.008
1.008
Output Voltage (V)
Output Voltage (V)
Figure 24. Efficiency in Forced-PWM Mode
1.004
1
0.996
0.992
1.004
1
0.996
0.992
1PH, BUCK0
1PH, BUCK1
1PH, BUCK2
1PH, BUCK3
0.988
0.988
0.984
1PH, Vin=3.3V, AUTO
1PH, Vin=5.0V, AUTO
0.984
0.98
2.8 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6
Input Voltage (V)
D028
0.98
0
0.2
0.4
0.6
Output Current (A)
0.8
4
1
D027
Figure 26. Output Voltage vs Load Current in PFM/PWM
Mode
VOUT = 1 V
Load = 1 A
Figure 27. Output Voltage vs Input Voltage in PWM Mode
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1.02
1.016
Output Voltage (V)
1.012
1.008
VOUT(200mV/div)
V(EN1)(500mV/div)
1.004
1
0.996
0.992
0.988
1PH, PWM
1PH, PFM
0.984
0.98
-40
-20
0
20
40
60
80
Temperature (°C)
100
120
V(SW)(2V/div)
140
D036
Load = 1 A (PWM) and 0.1 A (PFM)
Time (100 µs/div)
IOUT = 0 A
Figure 28. Output Voltage vs Temperature
Figure 29. Start-Up With EN1, Forced PWM
VOUT(200mV/div)
V(EN1)(500mV/div)
VOUT(200mV/div)
V(EN1)(500m/div)
ILOAD(500mA/div)
ILOAD(500mA/div)
V(SW)(2V/div)
V(SW)(2V/div)
Time (100 µs/div)
Time (100 µs/div)
RLOAD = 1 Ω
RLOAD = 1 Ω
Figure 30. Start-Up With EN1, Forced PWM
(1-Phase Output)
Figure 31. Shutdown With EN1, Forced PWM
(1-Phase Output)
VOUT(10mV/div)
VOUT(10mV/div)
V(SW_B0)(1V/div)
V(SW_B0)(2V/div)
Time (100 ns/div)
Time (40 µs/div)
IOUT = 10 mA
IOUT = 200 mA
Figure 32. Output Voltage Ripple, PFM Mode
(1-Phase Output)
60
Figure 33. Output Voltage Ripple, Forced-PWM Mode
(1-Phase Output)
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VOUT(10mV/div)
VOUT(10mV/div)
V(SW_B0)(1V/div)
V(SW_B0)(1V/div)
Time (2 µs/div)
Time (2 µs/div)
Figure 34. Transient from PFM-to-PWM Mode
(1-Phase Output)
Figure 35. Transient from PWM-to-PFM Mode
(1-Phase Output)
VOUT(20mV/div)
VOUT(20mV/div)
I(LOAD(1A/div)
I(LOAD(1A/div)
Time (40 µs/div)
IOUT = 0.1 A → 2 A → 0.1 A
Time (40 µs/div)
TR = TF = 1 µs
IOUT = 0.1 A → 2 A → 0.1
A
Figure 36. Transient Load Step Response, AUTO Mode
(1-Phase Output)
TR = TF = 1 µs
Figure 37. Transient Load Step Response, Forced-PWM
Mode (1-Phase Output)
VOUT(200mV/div)
VOUT(200mV/div)
Time (20 µs/div)
Time (20 µs/div)
Figure 38. VOUT Transition from 0.6 V to 1.4 V
Figure 39. VOUT Transition from 1.4 V to 0.6 V
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V(EN1)(1V/div)
V(nINT)(1V/div)
VOUT(50mV/div)
IOUT(2A/div)
Time (200 µs/div)
Figure 40. Start-up With Short on Output (1-Phase Output)
9 Power Supply Recommendations
The device is designed to operate from an input voltage supply range from 2.8 V and 5.5 V. This input supply
must be well regulated and able to withstand maximum input current and maintain stable voltage without voltage
drop even at load transition condition. The resistance of the input supply rail must be low enough that the input
current transient does not cause too high drop in the LP87524B/J-Q1 supply voltage that can cause false UVLO
fault triggering. If the input supply is located more than a few inches from the LP87524B/J-Q1 additional bulk
capacitance may be required in addition to the ceramic bypass capacitors.
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10 Layout
10.1 Layout Guidelines
The high frequency and large switching currents of the LP87524B/J-Q1 make the choice of layout important.
Good power supply results only occur when care is given to proper design and layout. Layout affects noise
pickup and generation and can cause a good design to perform with less-than-expected results. With a range of
output currents from milliamps to 10 A, good power supply layout is much more difficult than most general PCB
design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage and
current regulation across its intended operating voltage and current range.
1. Place CIN as close as possible to the VIN_Bx pin and the PGND_Bxx pin. Route the VIN trace wide and thick
to avoid IR drops. The trace between the positive node of the input capacitor and the VIN_Bx pin(s) of
LP87524B/J-Q1, as well as the trace between the negative node of the input capacitor and power
PGND_Bxx pin(s), must be kept as short as possible. The input capacitance provides a low-impedance
voltage source for the switching converter. The inductance of the connection is the most important parameter
of a local decoupling capacitor — parasitic inductance on these traces must be kept as small as possible for
proper device operation. The parasitic inductance can be reduced by using a ground plane as close as
possible to top layer by using thin dielectric layer between top layer and ground plane.
2. The output filter, consisting of COUT and L, converts the switching signal at SW_Bx to the noiseless output
voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI
behavior. Route the traces between the LP87524B/J-Q1 output capacitors and the load direct and wide to
avoid losses due to the IR drop.
3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a
quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling
capacitor as close as possible to the VANA pin.
4. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the LP87524B/JQ1 device to the respective sense pins on the processor. The sense lines are susceptible to noise. They
must be kept away from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high bandwidth
signals such as the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short, direct,
and close to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground
plane if possible. If series resistors are used for load current measurement, place them after connection of
the voltage feedback.
5. PGND_Bxx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers,
which are not able to withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx.
6. If the input voltage is above 4 V, place snubber components (capacitor and resistor) between SW_Bx and
ground on all four phases. The components can be also placed to the other side of the board if there are
area limitations and the routing traces can be kept short.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent parameters such as thermal coupling, airflow, added heat
sinks and convection surfaces, and the presence of other heat-generating components affect the power
dissipation limits of a given component. Proper PCB layout, focusing on thermal performance, results in lower die
temperatures. Wide and thick power traces come with the ability to sink dissipated heat. This can be improved
further on multi-layer PCB designs with vias to different planes. This results in reduced junction-to-ambient (RθJA)
and junction-to-board (RθJB) thermal resistances and thereby reduces the device junction temperature, TJ. TI
strongly recommends to perform of a careful system-level 2D or full 3D dynamic thermal analysis at the
beginning product design process, by using a thermal modeling analysis software.
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10.2 Layout Example
Via to GND plane
Via to VIN plane
VOUT1
VOUT0
L1
CIN1
VIN
L0
COUT0
COUT1
CIN0
GND
VIN
VIN
CVANA
VIN
SDA 6
SCL 5
AGND 4
19 nINT
CLKIN 3
20 NRST
CIN5
FB_B0 8
EN1 7
18 VANA GND
21 FB_B3
AGND
VIN_B3
SW_B3
PGND_B23
SW_B2
VIN_B2
GND
14 FB_B1
GND 15 EN2
16 PGOOD
17 AGND
VIN_B1
SW_B1
PGND_B01
SW_B0
VIN_B0
13 12 11 10 9
CIN4
GND
EN3 2
FB_B2 1
22 23 24 25 26
VIN
VIN
VIN
CIN3
CIN2
GND
L3
COUT3
COUT2
L2
VOUT3
VOUT2
Figure 41. LP87524B/J-Q1 Board Layout
The output voltage rails are shorted together based on the configuration as shown in Typical Application.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RNF0026C
VQFN-HR - 0.9 mm max height
SCALE 2.800
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
A-A 25.000
TYPICAL
C
0.9 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 2
10X
0.3
0.2
8X 0.5
4X (0.35)
4X (0.575)
4X (0.625)
14
8
10X
7
A
2X
2.5
SYMM
10X 0.5
0.66 0.1
12X
21
1
26
SYMM
1.72
1.52
A
27
PIN 1 ID
(0.2) TYP
4X (0.4)
13
9
22
THERMAL PAD
12X
2.24 0.1
0.3
0.2
0.1
0.05
C A B
C
0.5
0.3
4223207/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RNF0026C
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
8X (0.5)
10X (0.25)
12X (0.6)
22
26
1
21
10X (1.82)
12X (0.25)
SYMM
(3.08)
27
(0.66)
2X (3.65)
10X (0.5)
( 0.2) TYP
VIA
4X (0.4)
8
14
4X (0.825)
13
9
(R0.05)
TYP
4X (0.35)
(0.87)
4X (0.775)
(2.24)
2X (3.2)
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
SOLDER MASK DETAIL
NOT TO SCALE
4223207/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RNF0026C
VQFN-HR - 0.9 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.575) TYP
10X
EXPOSED METAL
12X (0.6)
SYMM
(0.5)
TYP
26
22
21
1
12X (0.25)
(1.01) TYP
(1.775)
TYP
(1.035) TYP
10X (0.5)
27
2X (0.98)
SYMM
2X (0.66)
(0.59)
(R0.05) TYP
EXPOSED METAL
4X (0.3)
4X (0.825)
8
14
20X (0.81)
13
9
4X (0.3)
20X (0.25)
4X (0.775)
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 8, 14 & 21: 87% - PADS 9-13 & 22-26: 88% - THERMAL PAD 27: 87%
SCALE:25X
4223207/A 08/2016
NOTES: (continued)
6. For alternate stencil design recommendations, see IPC-7525 or board assembly site preference.
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PACKAGE OPTION ADDENDUM
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19-Dec-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP87524BRNFRQ1
ACTIVE
VQFN-HR
RNF
26
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4B-Q1
LP87524BRNFTQ1
ACTIVE
VQFN-HR
RNF
26
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4B-Q1
LP87524JRNFRQ1
ACTIVE
VQFN-HR
RNF
26
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4J-Q1
LP87524JRNFTQ1
ACTIVE
VQFN-HR
RNF
26
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LP8752
4J-Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Dec-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LP87524BRNFRQ1
VQFNHR
RNF
26
3000
330.0
12.4
4.25
4.75
1.2
8.0
12.0
Q1
LP87524BRNFTQ1
VQFNHR
RNF
26
250
180.0
12.4
4.25
4.75
1.2
8.0
12.0
Q1
LP87524JRNFRQ1
VQFNHR
RNF
26
3000
330.0
12.4
4.25
4.75
1.2
8.0
12.0
Q1
LP87524JRNFTQ1
VQFNHR
RNF
26
250
180.0
12.4
4.25
4.75
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Dec-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP87524BRNFRQ1
VQFN-HR
RNF
26
3000
346.0
346.0
35.0
LP87524BRNFTQ1
VQFN-HR
RNF
26
250
203.0
203.0
35.0
LP87524JRNFRQ1
VQFN-HR
RNF
26
3000
346.0
346.0
35.0
LP87524JRNFTQ1
VQFN-HR
RNF
26
250
203.0
203.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
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circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
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respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
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TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
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INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
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and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
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TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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