Rohm BD9040FV Step-down,high-efficiency switching regulators (controller type) Datasheet

Large Current External FET Controller Type Switching Regulators
Step-down,High-efficiency
Switching Regulators (Controller type)
BD9040FV,BD9045FV
No.09028EAT03
●Over View
BD9040FV(output type of 1ch) and BD9045FV(output type of 2ch) are switching controllers that can be used within the wide
range of the input.Highly effective can be achieved by the synchronous rectification method and it is possible to contribute to
the eco-design of all electronic equipment (energy-saving).
●Feature(BD9040FV，BD 9045FV)
1) Wide input voltage range：4.5V～18V
2) Reference voltage 0.9V±1%
3) The overcurrent of timer latch type, excess voltage, short, and RTO/S protection are built-in
4) The switching frequency is changeable.(200kHz～750kHz)
5) A ceramic capacitor can be used for the output.
●Applications
For thin television, DVD･HDD recorder , STB, amusement and others.
●Absolute maximum rating (Ta=25℃)
Parameter
Power-supply voltage
Symbol
Rating
Unit
Vcc
20
V
EN input voltage
VEN
20
V
SW voltage
VSW
Vcc
V
Voltage between BOOT-SW
VBOOT
6
V
Permissible loss 1
Pd1
0.81** (BD9040FV)
W
Permissible loss 2
Pd2
0.94*** (BD9045FV)
W
Range of operating temperature
Topr
-40～+85
℃
Storage temperature range
Tstg
-55～+150
℃
Tjmax
150
℃
Junction temperature
**
***
Ta=25℃ or more is reduced with 6.5mW/℃.
Ta=25℃ or more is reduced with 7.5mW/℃.
●Operation condition (Ta=-40℃～+85℃)
Parameter
Power supply voltage***
Timing resistance
Frequency of oscillator
***
○
Min
4.5
Limit
Typ
12
Max
18
RT
39
－
130
kΩ
Fosc
200
－
750
kHz
Symbol
Vcc
Unit
V
Please be short-circuited to use VREG5 and VCC when the Vcc is 6V or less.
The radiation design is not done.
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1/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Electric characteristics (Unless otherwise specified Ta=25℃ VCC=12V EN=5V) (BD9040FV)
Parameter
Symbol
Limit
Min
Typ
Max
Unit
VCC Current of bias
ICC
-
3
6
mA
Standby current
ISTB
-
430
860
µA
VREG5
5
5.5
6
V
VREG5_L
-
20
50
mV
VREG3
2.85
3.0
3.15
V
VREG3_L
-
10
20
mV
Condition
VEN=0V
［VREG5］
Standard voltage output voltage
Load stability level
IVREG5=0 to 6mA
［VREG3 part]
Standard voltage
Load stability level
IVREG3=0 to 1mA
［prevention part for mis-operation of low input］
VREG5 Threshold voltage
VREG5_UVLO
3.4
3.8
4.2
V
VREG5:Sweep down
VREG3 Threshold voltage
VREG3_UVLO
2.4
2.5
2.6
V
VREG3:Sweep down
FOSC
240
300
360
kHz
Ivo+
-
-
1
µA
Isource
-12
-6.5
-2
mA
VFB=1.1V
Sink current
Isink
0.75
1.5
5
mA
VFB=0.7V
Return standard voltage
VOB
0.891
0.900
0.909
V
FB-COMP Short
Output short detection voltage
Vosh
0.37
0.45
0.53
V
VFB:Sweep down
ΔVosh
22
45
90
mV
VFB:Sweep up
Charge current
ISS
-14
-10
-6
µA
Vss=1V
Discharge current 1
IDIS
0.6
1.7
5
mA
Vss=1V
Discharge current 2
IDIS2
2.35
3.3
4.62
Maximum voltage
Vss_MAX
1.75
1.95
2.15
V
Standby current
Vss_STB
-
-
0.3
V
Iswin
9
10
11
µA
Vovp
1.06
1.1
1.14
V
ITM
-14
-10
-6
µA
Threshold voltage
Vth_TM
0.9
1
1.1
V
OFF Sink current
IOFFS
0.6
1.7
5
mA
REN
150
300
450
kΩ
REN_SS
150
300
450
kΩ
［Oscillator］
Oscillation frequency
RT=91 kΩ
［Error amplifier］
VO input bias current
Source current
Hysteresis voltage
［Soft start part］
Vss=1V, VEN_SS=0V
［overcurrent protection Division］
CL inflow current
VCL=Vcc-0.2V
［Overvoltage protection Division］
Detection voltage
［Timer latch circuit Division］
Source current
VTM=1V
VTM=0.5V
［Each ch control part］
EN
pull-up resistor
EN_SS pull-up resistor
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2/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Reference data (Unless otherwise specified Ta=25℃)
4.0
90
3.5
80
80
70
1.8V
60
2.6V
3.3V
EFFICIENCY[%]
1.2V
50
40
30
3.3V
60
50
40
30
20
20
VIN =12V
10
Io=2A
10
0
1
2
OUTPUT CURRENT：Io[A]
6
3
9
12
15
INPUT VOLTAGE ： VIN [V]
Fig.1 Efficiency 1
BD9045FV
0.5
0.4
0.3
BD9040FV
0.1
4
6
8
930
920
910
900
890
880
870
860
-40
10 12 14 16 18 20
-15
10
35
60
OUTPUT VOLTAGE ： Vo[V]
3
2
1
40
60
280
270
-40
80
10
35
60
85
Fig.6 Frequency
temperature characteristic
RCL=10kΩ
3.0
2.5
2.0
1.5
Latch OFF
1.0
BD9040FV
RCL=10kΩ
Use SP8K2
0.5
0
1
2
3
4
3.0
2.5
2.0
85℃
1.5
25℃
1.0
-40℃
0.5
0.0
0
1
OUTPUT CURRENT ： Io[A]
AMBIENT TEMPERATURE ： Ta[℃]
Fig.7 Overcurrent protection
temperature characteristic
-15
3.5
0.0
20
290
AMBIENT TEMPERATURE ： Ta[℃]
3.5
4
0
300
85
4.0
BD9045FV
RCL=12kΩ
Use SP8K2
4 6 8 10 12 14 16 18 20
OUTPUT VOLTAGE ： Vo[V]
310
Fig.5 Reference voltage
temperature characteristic
7
0
-20
2
320
AMBIENT TEMPERATURE ： Ta[℃]
Fig.4 Standby current
5
0.5
330
940
INPUT VOLTAGE ： VIN [V]
6
1.0
Fig.3 Circuit current
850
0.0
2
1.5
0
OSILATING FREQUENCY ： FOSC[kHz]
REFERENCE VOLTAGE ： VOB[V]
STANDBY CURRENT ： ISTB[uA]
0.7
0
BD9040FV
2.0
18
950
0.8
0.2
2.5
Fig.2 Efficiency 2
0.9
0.6
BD9045FV
3.0
0.0
0
0
OUTPUT CURRENT ： Io[A]
5.0V
70
OUTPUT VOLTAGE ： Vo[V]
EFFICIENCY[%]
5.0V
INPUT CURRENT ： IIN[mA]
100
90
100
Fig.8 Load regulation
2
3
4
5
INPUT VOLTAGE：VEN[V]
Fig9. EN Threshold voltage
OUTPUT VOLTAGE ： Vo[V]
3.5
20mV/div
3.0
VOUT
2.5
2.0
20mV/div
VOUT
85℃
1.5
25℃
1.0
-40℃
IOUT
0.5
1A/div
1A/div
0.0
0
1
2
3
4
IOUT
5
INPUT VOLTAGE：VEN_SS[V]
Fig.10 EN_SS Threshold voltage
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Fig.11 Load response 1
3/18
Fig.12 Load response 2
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Pin configuration
(BD9040FV)
EN_SS
1
20
CL
RT
2
19
BOOT
TM
3
18
OUTH
SS
4
17
SW
COMP
5
16
DGND
FB
6
15
OUTL
EN
7
14
VREG5
N.C.
8
13
N.C.
VREG3
9
12
N.C.
GND
10
11
VCC
●Pin function table (BD9040FV)
Terminal number
terminal name
1
EN_SS
SS discharge Delay ON/OFF terminal
2
RT
Oscillation frequency setting terminal
3
TM
Output OCP and OVP timer latch setting terminal
4
SS
5
COMP
Function
Soft start time setting terminal
Error amplifier output
6
FB
Error amplifier input
7
EN
Output ON/OFF terminal
8
N.C
Unconnected terminal
9
VREG3
10
GND
REG output for standard power supply
GND
11
VCC
Input power supply terminal
12
N.C
Unconnected terminal
13
N.C
Unconnected terminal
14
VREG5
15
OUTL
16
DGND
17
SW
18
OUTH
Terminal of drive at high side in FET gate
19
BOOT
OUTH driver power supply terminal
20
CL
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REG output for FET drive
drive terminal at low side of FET gate
Source terminal at low side of FET
High side FET source terminal
Overcurrent detection setting terminal
4/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Block diagram
(BD9040FV)
VCC
RT
5.5V Reg
VREG5
3.0V Reg
UVLO
3.8V
TSD
B.G
O/S Check
TSD
OSC
UVLO
VREG3
2.5V
TM
OCP
CL
Set
DRV
Reset
DRV
BOOT
OUTH
SW
VREG5
TSD
UVLO
Q
Slope
Set
OUTL
Reset
PWM
UVLO
DGND
FB
SS
OVP
ErrAmp
COMP
0.9V
Q
EN_SS
COMP
Set
Sequence DET
Reset
0.45V
EN
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GND
5/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Pin configuration
(BD9045FV)
GND
14
15
14 OUTL1
TM1
13
16
13 DGND1
SS1
12
17
12 SW1
COMP1
18
11
11
FB1
10
19
10 BOOT1
OUTH1
EN1
20
9
9
CL1
VCC
21
8
8
VREG5
EN2
22
7
7
N.C.
VREG3
23
6
6
CL2
RT
24
5
5
BOOT2
FB2
25
4
4
OUTH2
COMP2
26
3
3
SW2
SS2
27
2
2
DGND2
TM2
28
1
1
OUTL2
●Pin function table (BD9045FV)
Terminal number
terminal name
Functions
1
OUTL2
Terminal 2 of drive at low side FET gate
2
DGND2
Low side FET source terminal2
3
SW2
4
OUTH2
Terminal 2of drive at high side of FET gate
High side FET source terminal2
5
BOOT2
OUTH2 driver power supply terminal
6
CL2
Overcurrent detection setting terminal
7
N.C.
Unconnected terminal
2
8
VREG5
9
CL1
Overcurrent detection setting terminal
10
BOOT1
OUTH1 driver power supply terminal
Terminal 1of drive at high side of FET gate
REG output for FET drive
1
11
OUTH1
12
SW1
13
DGND1
Low side FET source terminal 1
14
OUTL1
Terminal 1of drive at low side of FET gate
15
GND
16
TM1
Output 1 OCP and OVP timer latch setting terminal
17
SS1
Soft start time setting terminal 1
18
COMP1
19
FB1
Error amplifier input1
20
EN1
Outpt1ON/OFF terminal
21
VCC
Input power supply terminal
22
EN2
Output2ON/OFFterminal
23
VREG3
24
RT
Oscillation frequency setting terminal
25
FB2
Error amplifier input 2
26
COMP2
27
SS2
Soft start time setting terminal 2
28
TM2
Output 2 OCP and OVP timer latch setting terminal
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© 2009 ROHM Co., Ltd. All rights reserved.
High side FET source terminal 1
GND terminal
Error amplifier output 1
REG output for standard power supply
Error amplifier output 2
6/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Block diagram
(BD9045FV)
VCC
5V Reg
VREG5
RT
3V Reg
O/S Check
UVLO
B.G
VREG3
OSC
UVLO
3.8V
TSD
TSD
TM1
TM2
OCP
OCP
CL1
CL2
BOOT1
BOOT2
DRV
OUTH2
DRV
SW2
DRV
Set
Set
DRV
Reset
Reset
OUTH1
SW1
TSD
UVLO
TSD
UVLO
VREG5
VREG5
Q
OUTL2
Reset Set
DGND2
FB2
SS2
PWM
COMP
Slope
Slope
PWM
COMP
Q
Set
－
＋
＋
OUTL1
Reset
OVP
ErrAmp
ErrAmp
UVLO
0.9V
0.9V
COMP
DGND1
FB1
SS1
OVP
COMP1
Set
Q
Q
Reset
Sequence DET
Sequence DET
0.45V
0.45V
EN2
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Set
Reset
EN1
7/18
GND
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Block functional descriptions
・Error amplifier(ErrAmp)
It is a circuit to compare the 0.9V reference voltage and the output voltage’s feedback voltage. Switching Duty is
determined by the COMP voltage that is the result of the comparison. In addition, due to the SS terminal voltage on
start-up, the Soft Start begins operating, and so the COMP voltage is limited by the SS voltage.
・Oscillator(OSC)
It is a block, the oscillating frequency of which is decided by RT and can be set up to 200kHz～750kHz.
・SLOPE
It is a block in which triangular wave is created from the clock generated by the OSC. And the generated triangular wave is
transmitted to the PWM comparator.
・PWM Comparator(PWM COMP)
The error amplifier’s output COMP voltage and the SLOPE block’s triangular wave are compared, and the switching Duty
is determined. The switching duty is limited by the maximum Duty ratio internally decided and can not become 100%.
・Reference voltage(5V Reg, 3V Reg)
It is a block to generate 5.5V and 3V internal reference voltage.
・Overcurrent protection circuit(OCP)
At the time of OUTH=H, if SW voltage becomes not more than CL voltage, the overcurrent protection circuit operates.
When the overcurrent protection operates, the Duty is limited, and so the output voltage is lowered. Moreover, when an
overcurrent is detected by the overcurrent protection circuit, the charging of the external capacitor on TM terminal is
started. When the voltage on TM terminal exceeds 1V, the output becomes OFF state and then is latched. Once EN is
made to be L, the latch is released.
・Overvoltage protection circuit(OVP)
When FB voltage becomes more than 1.1 V, the overvoltage protection operates. When the overvoltage protection
operates, the charging of the external capacitor on TM terminal is started. When the voltage on TM terminal exceeds 1V,
the output becomes OFF state and then is latched. Once EN is made to be L, the latch is released.
・Output short circuit protection circuit
If FB voltage becomes not more than 0.4V, the output short circuit protection circuit operates. When the output short circuit
protection operates, the charging of the external capacitor on TM terminal is started. When the voltage on TM terminal
exceeds 1V, the output becomes OFF state and then is latched. Once EN is made to be L, the latch is released.
・O/S Check
When RT terminals become open or short circuit states, RT OPEN and SHORT circuit protections operate respectively.
When RT terminals’ open or short circuit state is detected, the charging of the external capacitor on TM terminal is started.
When the voltage on TM terminal exceeds 1V, the output becomes OFF state and then is latched. Once EN is made to be
L, the latch is released.
・Under Voltage Lockout (UVLO) / Thermal Shutdown(TSD)
When VREG5 becomes no more than around 3.8V or VREG3 no more than around 2.5, the output of the under voltage
lockout is turned off.
Then, When VREG5 becomes more than around 4.2V or VREG3 more than around 2.6, the output of the under voltage
lockout is reset.
Moreover, when the temperature of chip becomes more than around 150℃, the output of the thermal shutdown (TSD) is
turned off, and when it is returned to a certain temperature, the output is reset.
When UVLO and TSD operate, the capacitors of TM and SS are discharged.
・Function of EN
EN is pulled down in regard to GND and pulled up in regard to VCC, and normally EN=H.
At the time of EN=L, the capacitors of OFF, TM and SS of output are discharged, and become the standby state.
(As for BD9045, due to EN1 and EN2, the capacitors of OFF, TM and SS of each ch output are discharged. In addition it
becomes the standby state when both EN1 and EN2 are made to be L).
・Function of EN_SS(BD9040 alone)
EN_SS is pulled down in regard to GND and pulled up in regard to VCC, and normally EN_SS=H. At the time of EN_SS=L,
the capacitors of OFF, TM and SS of output are discharged.At the time of EN_SS=L, the capacitor of SS is
constant-current discharged, so it can be made delayed during output’s OFF.
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8/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Application circuit example
BD9040FV
VIN 12V
30uF
EN_SS
0.1uF
4.7nF
CL
RT
82kΩ
0.1uF
3kΩ
47pF
0.1uF
0.1uF
10kΩ
BOOT
TM
OUTH
SS
SW
COMP
DGND
FB
OUTL
EN
VREG5
N.C.
N.C.
VREG3
N.C.
GND
VCC
0.1uF
10uH
30uF
Vo 3.3V
2.2nF
150Ω
27kΩ
10kΩ
1uF
※ There are many factors (The PCB board layout, output current, etc.) that can affect the DCDC characteristics, please
Verify and confirm using practical applications.
BD9045FV
VIN 12V
30uF
0.1uF
0.1uF
10nF
3.3kΩ
GND
OUTL1
TM1
DGND1
SS1
SW1
COMP1
0.1uF
10kΩ
OUTH1
22pF
BOOT1
EN1
CL1
VCC
VREG5
EN2
N.C.
VREG3
CL2
RT
BOOT2
FB2
OUTH2
2.2nF
120Ω
30uF
0.1uF
FB1
Vo 1.8V
10uH
0.1uF
10kΩ
12kΩ
1uF
0.1uF
12kΩ
82kΩ
10nF
100pF
0.1uF
COMP2
2kΩ
0.1uF
Vo 1.2V
10uH
SW2
SS2
DGND2
TM2
OUTL2
0.1uF
3.3nF
100Ω
15kΩ
30uF
39kΩ
※There are many factors (The PCB board layout, output current, etc.) that can affect the DCDC characteristics, please
Verify and confirm using practical applications.
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9/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Application components selection
(1) Setting of output L constant value
The coil value significantly influences the output ripple current. Thus, as seen
in equation (1), the bigger the coil, and the higher the switching frequency, the
lower the drop in ripple current.
ΔIL
ΔIL =
(VCC-VOUT)×VOUT
IL
VOUT
[A]・・・
（1）
L×VCC×f
VCC
The optimal output ripple current setting is 30% of maximum current.
ΔIL = 0.3×IOUTmax.[A]・・・(2)
L
Co
(VCC-VOUT)×VOUT
L=
[H]・・・
（3）
ΔIL×VCC×f
(ΔIL：output ripple current, f：switching frequency)
Output ripple current
※
Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease efficiency.
Please establish sufficient margin to ensure that peak current does not exceed the coil current rating.
※
Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency.
(2) Setting of output constant Co
Select the output capacitor with the highest value for ripple voltage (VPP) tolerance and maximum drop voltage
(at rapid load change). The following equation is used to determine the output ripple voltage.
Step down
ΔVPP = ΔIL × RESR +
ΔIL
Co
×
Vo
Vcc
×
1
f
[V]･･･(4)
provided that f： switching frequency
Be sure to keep the output Co setting within the allowable ripple voltage range.
※Please allow sufficient output voltage margin in establishing the capacitor rating.
Note that low-ESR capacitors enable lower output ripple voltage.
Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor in
the conditions described in the capacitance equation (5) for output capacitors, below.
Tss：soft start time
Tss × (ILimit – IOUT)
IOUT：load current
・・・ （5）
Co ≦
VOUT：output voltage
VOUT
ILimit：over current detection value reference
Note: less than optimal capacitance values may cause problems at startup.
(3) Input capacitor(Cin)selection
VIN
Cin
VOUT
L
Co
Input capacitor
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The input capacitor serves to lower the output impedance of the power
source connected to the input pin (VCC). Increased power supply
output impedance can cause input voltage (VCC) instability, and may
negatively impact oscillation and ripple rejection characteristics.
Therefore, be certain to establish an input capacitor in close proximity
to the VCC and GND pins. Select a low-ESR capacitor with the required
ripple current capacity and the capability to withstand temperature
changes without wide tolerance fluctuations. The ripple current IRMS is
determined using equation (6).
IRMS = IOUT ×
VOUT（VCC - VOUT）
VCC
[A]・・・(6)
Also, be certain to ascertain the operating temperature, load range and
MOSFET conditions for the application in which the capacitor will be
used, since capacitor performance is heavily dependent on the
application’s input power characteristics, substrate wiring and MOSFET
gate drain capacity.
10/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
(4) Feedback resistor design
Please refer to the following equation in determining the proper feedback resistance.
The recommended setting is in a range between 1kΩ and 330kΩ. Resistance less than 1kΩ risks decreased power
efficiency, while setting the resistance value higher than 330kΩ will result in an internal error amp input bias current of
0.4uA increasing the offset voltage.
Vo
Internal reference
0.9V
R1
FB
R2
R1 +R2
Vo =
× 0.9 [V] ・・・(7)
R2
f [kHz]
(5) Setting switching frequency
The triangular wave switching frequency can be set by connecting a resistor to the RT pin. The RT sets the frequency by
adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper
RT resistance. Settings outside this range may render the switching function inoperable, and proper operation of the
controller overall cannot be guaranteed when unsupported resistance values are used.
750
700
650
600
550
500
450
400
350
300
250
200
0
20
40
60
80
100
120
140
160
R T [ kΩ]
(6) Setting the soft start delay
The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup.
The figure below shows the relation between soft start delay time and capacitance, which can be calculated using
equation (8) at right.
TSL = 0.8 ×
Vo
Css
TSH = 0.7 ×
Css
[sec]・・・（8）
Iss（10µA typ）
Vcc
If the capacitance value is reduced (to no more than 0.01 uF or so), the overshoot in output may be caused.
Please use high accuracy components (such as X5R) when implementing sequential startups involving other power
sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on input
voltage, output voltage, load, coil, output capacitance and phase compensation constant etc.
Iss（10µA typ）
[sec]
×
(7) Setting the EN_SS (output delay function)(in the case of BD9040FV)
If EN_SS is made to be L, the output voltage’s OFF time can be made delayed. The calculating formula for delay time is
shown in the following equation.
TDIS=
Vss_MAX(1.95VTyp)-(0.8+0.7×
Vo
Vcc
) ×
Css
Idis(3.3uA,Typ)
[sec]・・・(9)
VCC
EN_SS
VO
Tdis
TSL TSH
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11/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
(8) Overcurrent protection
Current limit value (ILimit) is determined by the resistance RCL established between VCC and CL. (refer to the following
diagram)The current limit is self-feedback type, when overcurrent is detected, the output Duty is reduced, and the current
is limited. When load returns to normal state, the output voltage returns to its former state.
overcurrent protection
6
6
5
5
4
4
Io [A]
Io [A]
overcurrent protection
3
In case of SP8K2
2
3
2
In case of SP8K2
1
1
0
0
12
13
14
15
16
R CL [kΩ]
17
12
18
BD9040FV measurement value of our company’s substrate
13
BD9045FV
14
15
16
R CL [kΩ]
17
18
measurement value of our company’s substrate
※There are many factors (the layout and service condition) that can affect the characteristics, please verify and confirm
using practical applications.Overcurrent protection detection value is dependent on the ON resistance of external FET
and so varies with temperature. (Refer to Fig.7 on page 3)
Please determine it in such a way that a good margin is left while setting it. Moreover, in case of different layout of
substrate or large gate capacitance of external FET, sufficient voltage between gate and source of external FET can not
be provided, the ON resistance becomes high, and so the overcurrent protection value may be greatly changed.
Please use a FET, the gate capacitance of which is no more than1500pF, as external FET. (the recommended: SP8K2，
SP8K1)However, There are many factors (the layout and service condition) that can affect the characteristics, please
verify and confirm using practical applications.
Compare the VCL that is set by RCL and the ΔVsw that is generated by ON resistance of loxFET.
VCC
RCL
CL
VCL
10uA
OUTH
Io
Overcurrent
protection
ΔVsw
SW
OUTL
(9) Setting of OFF latch timer time
・OFF latch timer is charged if one of the following conditions is met.
・Current limit is operating.
・Overvoltage protection(FB≧1.1V)is operating.
・Output short circuit protection(FB≦0.45V)is operating.
・Resistor connected on RT terminal becomes open.
・RT terminal is shorted with GND.
・Resistor connected on CL terminal becomes open.
If the charging is started and continued until the fully-charged, the output is OFF latched. The time from start-up of
charging till output OFF is determined by the following formula.
CTM
TTM =
[sec] ・・・(10)
ITM(10uA typ)
This OFF latch is released once EN is made to be「L」or if VCC is once lowered and then rises again.
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12/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
(10) Method for determining phase compensation
Conditions for application stability
Feedback stability conditions are as follows:
・When gain is 1 (0dB) and phase shift is 150° or less (i.e., phase margin is at least 30°):
a dual-output high-frequency step-down switching regulator is required
Additionally, in DC/DC applications, sampling is based on the switching frequency; therefore, overall GBW may be set at
no more than 1/10 the switching frequency. In summary, target characteristics for application stability are:
・Phase shift of 150° or less (i.e., phase margin of 30° or more) with gain of 1 (0dB)
・GBW (i.e., gain 0dB frequency) no more than 1/10 the switching frequency.
Stability conditions mandate a relatively higher switching frequency, in order to limit GBW enough to increase response.
The key to achieving successful stabilization using phase compensation is to cancel the secondary phase margin/delay
(-180°) generated by LC resonance, by employing a dual phase lead. In short, adding two phase leads stabilizes the
application.GBW (the frequency at gain 1) is determined by the phase compensation capacitor connected to the error amp.
Thus, a larger capacitor will serve to lower GBW if desired.
① General use integrator (low-pass filter)
Feedback
COMP
A
R
Integrator open loop characteristics
②
Gain
[dB]
-20dB/decade
GBW(b)
90
0
Phase 0
[deg] -90
-90
FB
(a)
A
180
Point(a) fa =
1
1.25[Hz]・・・
（11）
2πRCA
0
C
-180
-180
-90°
Point(b) fa = GBW
-180°
Phase margin
1
2πRC
[Hz] ・・・
（12）
The error amp is provided with phase compensation similar to that depicted in figures ① and ② above and thus serves
as the system’s low-pass filter.In DC/DC converter applications, R is established parallel to the feedback resistance.
When electrolytic or other high-ESR output capacitors are used
Phase compensation is relatively simple for applications employing high-ESR output capacitors (on the order of several
Ω). In DC/DC converter applications, where LC resonance circuits are always incorporated, the phase margin at these
locations is -180°. However, wherever ESR is present, a 90° phase lead is generated, limiting the net phase margin to -90°
in the presence of ESR. Since the desired phase margin is in a range less than 150°, this is a highly advantageous
approach in terms of the phase margin. However, it also has the drawback of increasing output voltage ripple components.
③ LC resonance circuit
④ ESR connected
Vcc
1
[Hz]:
2π√LC
fr =
1
fr =
2π√LC
Vo
[Hz]・・・
（13）
fESR =
resonance point
・・
（14）
1
[Hz]: Zero （15）
2πRESRC
Resonance point phase margin -180º
L
C
-90°:Pole
Since ESR changes the phase characteristics, only one phase lead need be provided for high-ESR applications. Please
choose one of the following methods to add the phase lead.
⑤ Add C to feedback resistance
⑥ Add R3 to aggregator
Vo
Vo
C2
C1
R3
FB
FB
A
COMP
1
2πC1R1
[Hz]・・・(16)
R2
Phase lead fz =
C2
R1
R1
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© 2009 ROHM Co., Ltd. All rights reserved.
R2
Phase lead fz =
13/18
A
COMP
1
[Hz]・・・(17)
2πC2R3
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
Set the phase lead frequency close to the LC resonance frequency in order to cancel the LC resonance.
・When using ceramic, OS-CON, or other low-ESR capacitors for the output capacitor:
Where low-ESR (on the order of tens of mΩ) output capacitors are employed, a two phase-lead insertion scheme is
required, but this is different from the approach described in figure ③～⑥, since in this case the LC resonance gives
rise to a 180° phase margin/delay. Here, a phase compensation method such as that shown in figure ⑦ below can
be implemented.
⑦Phase compensation provided by secondary (dual) phase lead
Vo
R3
C1
R1
Phase lead
fz1 =
1
2πR1C1
[Hz]・・・(18)
Phase lead
fz2 =
1
2πR3C2
[Hz] ・・・(19)
C2
FB
A
COMP
R2
LC resonance frequency fr =
1
2π√LC
[Hz] ・・・(20)
Once the phase-lead frequency is determined, it should be set close to the LC resonance frequency.
This technique simplifies the phase topology of the DCDC Converter. Therefore,it might need a certain amount
of trial-and-error process. There are many factors(The PCB board layout, Output Current, etc.)that can affect
the DCDC characteristics. Please verify and confirm using practical applications.
(9)MOS FET selection
VCC
VDS
IL
VGSM1
VGSM2
Vo
FET uses Nch MOS
・VDS＞Vcc
・VGSM1＞BOOT-SW interval voltage
・VGSM2＞VREG5
・allowable current＞output current + ripple current
※Should be at least the over current protection value
※Select a low ON-resistance MOSFET for highest efficiency
※Attention
If the input capacitance of FET is extremely large or it is used with
Duty no more than 10%, it is possible that output FETs on both upper
side and under side are simultaneously turned on and so the
efficiency deteriorates. The input capacitance of output FET is
recommended to be no more than 1000pF. But these characteristics
vary with substrates’ layouts or varieties of parts etc, so please
confirm them thoroughly with actual devices when it is put into mass
production.
VDS
(10)Schottky barrier diode selection
・Reverse voltage VR＞Vcc
・Allowable current ＞ output current + ripple current
※Should be at least the over current protection value
※Select a low forward voltage, fast recovery diode for highest efficiency
VCC
Vo
VR
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14/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Timing chart
EN=L
EN=L
EN=L
UVLO
VCC
SS
EN1
Vreg3
Vreg5
3.8V
TM
1V
4.2V
1V
1.1V
FB
検出
OVP
OVP
detection
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15/18
0.45V
SCP detection
SCP 検出
on
latch condition
ラッチ状態で
output
OFF
出力 OFF
on
latch condition
ラッチ状態で
出力 OFF
output
OFF
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
● Input & output equivalent circuits
2(24)PIN
[RT]
７PIN
[EN]
(20,22)PIN
[EN1, EN2]
VREG3
VCC VCC
VCC VCC
300kΩ
VREG3
20kΩ
EN
EN
RT
150Ω
20PIN
(9,6)PIN
367kΩ 20kΩ
315kΩ 20kΩ
200kΩ
184kΩ
15PIN
[OUTL]
(14, 1)PIN [OUTL1, OUTL2]
[CL]
[CL1, CL2]
20kΩ
377kΩ
5PIN
[COMP]
(18,26)PIN [COMP1, COMP2]
VCC
VREG5
2kΩ
VCC
VREG3
VREG5
CL
3kΩ
20kΩ
VREG3
COMP
OUTL
5kΩ
6PIN
[FB]
(19, 25)IN [FB1, FB2]
1PIN
3PIN
[TM]
(6，28)PIN [TM1, TM2]
[EN_SS]
VREG3
VCC
VCC
VCC
VREG3
VREG3
VREG3
300kΩ
1kΩ
EN_SS
2kΩ
200kΩ
FB
20kΩ
TM
1kΩ
55Ω
100kΩ
4PIN
(7, 27)PIN
9PIN
(23)PIN
[SS]
[SS1, SS2]
VCC
VCC
VREG3
9,17,18PIN
(10, 5)PIN
(12, 3)PIN
(11, 4)PIN
[VREG3]
[VREG3]
VCC
[BOOT, SW, OUTH]
[BOOT1, BOOT2]
[SW1, SW2]
[OUTH1, OUTH2]
BOOT
VCC
OUTH
2kΩ
SS
150kΩ
50Ω
VREG3
100kΩ
100kΩ
SW
300kΩ
※ The inside of ( ) is of BD9045FV
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16/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Notes for use
1. Absolute maximum ratings
Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may
result in IC deterioration or damage. Assumptions should not be made regarding the state of the IC (short mode or open
mode) when such damage is suffered.
A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the
absolute maximum ratings may be exceeded is anticipated.
2. GND potential
Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND pin
carry a voltage lower than or equal to the GND pin, including during actual transient phenomena. if there is a terminal,
electric potential of which is lower than that of GND, please take such measures as provide a bypass route etc.
3. Permissible dissipation Pd
If by any chance you use it in such a way that the permissible dissipation is exceeded, occurs the deterioration of original
performances of IC such as reduction of current capacity caused by an increase in temperature of chip, which will lead to a
decline in reliability, therefore please use it in such a way that its dissipation is within the permissible one and allows for a
sufficient margin.
4. Input power supply
Please wire and arrange in such a way that, in the wiring pattern and pattern layout, the wiring to the input pin VIN is
sufficiently short and furthermore electrical interference is not caused.
The electrical characteristics included in this specification may vary with such conditions as temperature, power supply
voltage and external circuits etc., so please confirm them thoroughly including transient characteristic.
6. Thermal shutdown circuit
Thermal shutdown circuit is built-in in order to prevent the thermal destruction of IC. Please use it within its permissible
dissipation range, but if by any chance the state of exceeding the permissible dissipation continues, the temperature of
chip rises, as a result the thermal shutdown circuit operates and so the output is turned off.
If after that the temperature Tj of chip falls, the circuit resets automatically. Furthermore, the thermal shutdown circuit leads
to the state of exceeding the absolute maximum rating, so please absolutely avoid such set design as uses the thermal
shutdown circuit.
7. nter-pin shorts and mounting errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply and GND pin caused by the
presence of a foreign object may result in damage to the IC.
8. Applications with modes that reverse VCC and pin potentials may cause damage to internal IC circuits. For example, such
damage might occur when VCC is shorted with the GND pin while an external capacitor is charged. Please use 1μF and
0.1μF respectively as the capacitor of VREG5’s output terminal and the capacitor of VREG3’s output terminal. Moreover, it
is recommended to insert a diode for preventing back current flow in series with VCC or bypass diodes between VCC and
each pin.
9.Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
10. Please insert the protective diode when it is conceivable that the back electromotive force is produced at the time of
start-up or output OFF because a load that has a large inductance component is connected on output terminal.
11. Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure,
and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process.
12. GND wiring pattern
If there are both small-signal GND and large-current GND, then large-current GND pattern and small-signal GND pattern
are separated, and in order that the pattern wiring and the voltage change caused by large current do not change the
voltage of small-signal GND, it is recommended to carry out the one-point grounding at the reference point of set.
Please be careful of not changing the GND wiring pattern of external parts.
13. SW terminal
In case of connecting of application, SW terminal may become a negative electric potential due to the back electromotive
force of coil. Please take such measures as provide a bypas route between SW terminal and GND at the time of setting of
application.
14. Output
At the time of EN=L，UVLO, and timer latch, the current flows out from SW terminal. If the service condition is such that the
output load becomes no more than 1mA, then please insert a 1kΩ resistor between output and GND.
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17/18
2009.05 - Rev.A
Technical Note
BD9040FV, BD9045FV
●Ordering part number
B
D
9
Part No.
0
4
0
F
Part No.
9040
9045
V
-
Package
FV : SSOP-B20
SSOP-B28
E
2
Packaging and forming specification
E2: Embossed tape and reel
(SSOP-B20, SSOP-B28)
SSOP-B20
<Tape and Reel information>
6.5 ± 0.2
11
0.3Min.
4.4 ± 0.2
6.4 ± 0.3
20
1
Tape
Embossed carrier tape
Quantity
2500pcs
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
10
1.15 ± 0.1
0.1± 0.1
0.15 ± 0.1
0.1
0.65
0.22 ± 0.1
1pin
Reel
(Unit : mm)
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
SSOP-B28
<Tape and Reel information>
10 ± 0.2
(MAX 10.35 include BURR)
15
0.3Min.
1
Embossed carrier tape
Quantity
2000pcs
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
14
0.15 ± 0.1
0.1
1.15 ± 0.1
Tape
Direction
of feed
5.6 ± 0.2
7.6 ± 0.3
28
0.1
0.65
0.22 ± 0.1
1pin
(Unit : mm)
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© 2009 ROHM Co., Ltd. All rights reserved.
Reel
18/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
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R0039A