ICSI IS41C44004 4mx4 bit dynamic ram with edo page mode Datasheet

IC41C4400x and IC41LV4400x Series
Document Title
4Mx4 bit Dynamic RAM with EDO Page Mode
Revision History
Revision No
History
Draft Date
Remark
0A
0B
Initial Draft
add Industrial grade parts
May 20,2001
October 17,2002
Preliminary
The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and
products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices.
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
1
IC41C4400x and IC41LV4400x Series
4M x 4 (16-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
DESCRIPTION
• Extended Data-Out (EDO) Page Mode
access cycle
• TTL compatible inputs and outputs
• Refresh Interval:
-- 2,048 cycles/32 ms
-- 4,096 cycles/64 ms
• Refresh Mode: RAS-Only,
CAS-before-RAS (CBR), and Hidden
• JEDEC standard pinout
• Single power supply:
5V ± 10% or 3.3V ± 10%
• Byte Write and Byte Read operation via
two CAS
PRODUCT SERIES OVERVIEW
Part No.
IS41C44002
These features make the 4400 Series ideally suited for highbandwidth graphics, digital signal processing, high-performance
computing systems, and peripheral applications.
The 4400 Series is packaged in a 24-pin 300mil SOJ and a 24
pin TSOP-2
KEY TIMING PARAMETERS
Parameter
Refresh
Voltage
2K
5V ± 10%
IS41C44004
4K
5V ± 10%
IS41LV44002
2K
3.3V ± 10%
IS41LV44004
4K
3.3V ± 10%
PIN CONFIGURATION
24 Pin SOJ, TSOP-2
The ICSI 4400 Series is a 4,194,304 x 4-bit high-performance
CMOS Dynamic Random Access Memory. These devices
offer an accelerated cycle access called EDO Page Mode.
EDO Page Mode allows 2,048 or 4096 random accesses within
a single row with access cycle time as short as 20 ns per 4-bit
word.
-50
-60
Unit
RAS Access Time (tRAC)
50
60
ns
CAS Access Time (tCAC)
13
15
ns
Column Address Access Time (tAA)
25
30
ns
EDO Page Mode Cycle Time (tPC)
20
25
ns
Read/Write Cycle Time (tRC)
84
104
ns
PIN DESCRIPTIONS
VCC
1
24
GND
I/O0
2
23
I/O3
I/O1
3
22
I/O2
WE
4
21
CAS
RAS
5
20
*A11(NC)
6
A10
A0-A11
Address Inputs (4K Refresh)
A0-A10
Address Inputs (2K Refresh)
I/O0-3
Data Inputs/Outputs
OE
WE
Write Enable
19
A9
OE
Output Enable
RAS
Row Address Strobe
7
18
A8
CAS
Column Address Strobe
A0
8
17
A7
Vcc
Power
A1
9
16
A6
A2
10
15
A5
GND
Ground
A3
11
14
A4
NC
No Connection
VCC
12
13
GND
* A11 is NC for 2K Refresh devices.
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
IC41C4400x and IC41LV4400x Series
FUNCTIONAL BLOCK DIAGRAM
OE
WE
CAS
CAS
CONTROL
LOGIC
WE
CONTROL
LOGICS
CAS
OE
CONTROL
LOGIC
WE
OE
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
ROW DECODER
REFRESH
COUNTER
ADDRESS
BUFFERS
A0-A10(A11)
MEMORY ARRAY
4,194,304 x 4
DATA I/O BUFFERS
RAS
CLOCK
GENERATOR
RAS
RAS
I/O0-I/O3
TRUTH TABLE
Function
Standby
Read
Write: Word (Early Write)
Read-Write
EDO Page-Mode Read 1st Cycle:
2nd Cycle:
EDO Page-Mode Write 1st Cycle:
2nd Cycle:
EDO Page-Mode
1st Cycle:
Read-Write
2nd Cycle:
Hidden Refresh
Read
Write(1)
RAS-Only Refresh
CBR Refresh
RAS
H
L
L
L
L
L
L
L
L
L
L→H→L
L→H→L
L
H→L
CAS
H
L
L
L
H→L
H→L
H→L
H→L
H→L
H→L
L
L
H
L
WE
X
H
L
H→L
H
H
L
L
H→L
H→L
H
L
X
X
OE
X
L
X
L→H
L
L
X
X
L→H
L→H
L
X
X
X
Address tR/tC
X
ROW/COL
ROW/COL
ROW/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
I/O
High-Z
DOUT
DIN
DOUT, DIN
DOUT
DOUT
DIN
DIN
DOUT, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
Note:
1. EARLY WRITE only.
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
3
IC41C4400x and IC41LV4400x Series
Functional Description
Refresh Cycle
The IC41C4400x and IC41LV4400x are CMOS DRAMs
optimized for high-speed bandwidth, low power
applications. During READ or WRITE cycles, each bit is
uniquely addressed through the 11 or 12 address bits.
These are entered 11 bits (A0-A10) at a time for the 2K
refresh device or 12 bits (A0-A11) at a time for the 4K
refresh device. The row address is latched by the Row
Address Strobe (RAS). The column address is latched by
the Column Address Strobe (CAS). RAS is used to latch
the first nine bits and CAS is used the latter ten bits.
To retain data, 2,048 refresh cycles are required in each
32 ms period, or 4,096 refresh cycles are required in each
64ms period. There are two ways to refresh the memory:
1. By clocking each of the 2,048 row addresses (A0
through A10) or 4096 row addresses (A0 through A11)
with RAS at least once every 32 ms or 64ms respectively.
Any read, write, read-modify-write or RAS-only cycle
refreshes the addressed row.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time specified
by tAR. Data Out becomes valid only when tRAC, tAA, tCAC
and tOEA are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS,
while holding CAS LOW. In CAS-before-RAS refresh
cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a
RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Write Cycle
A write cycle is initiated by the falling edge of CAS and WE,
whichever occurs last. The input data must be valid at or
before the falling edge of CAS or WE, whichever occurs
last.
4
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
IC41C4400x and IC41LV4400x Series
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameters
VT
Voltage on Any Pin Relative to GND
VCC
Supply Voltage
IOUT
PD
TA
Output Current
Power Dissipation
Commercial Operation Temperature
Industrial Operation Temperature
Storage Temperature
TSTG
5V
3.3V
5V
3.3V
Rating
Unit
−1.0 to +7.0
−0.5 to +4.6
−1.0 to +7.0
−0.5 to +4.6
50
1
0 to +70
−40 to +85
−55 to +125
V
V
mA
W
o
C
o
C
o
C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
Parameter
VCC
Supply Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
TA
Commercial Ambient Temperature
Industrial Ambient Temperature
5V
3.3V
5V
3.3V
5V
3.3V
Min.
Typ.
Max.
Unit
4.5
3.0
2.4
2.0
−1.0
−0.3
0
−40
5.0
3.3
−
−
−
−
−
−
5.5
3.6
VCC + 1.0
VCC + 0.3
0.8
0.8
70
85
V
V
V
o
o
C
C
CAPACITANCE(1,2)
Symbol
Parameter
CIN1
CIN2
CIO
Input Capacitance: A0-A10(A11)
Input Capacitance: RAS, CAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O3
Max.
Unit
5
7
7
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25oC, f = 1 MHz.
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
5
IC41C4400x and IC41LV4400x Series
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
IIL
Input Leakage Current
IIO
Speed
Min.
Max.
Unit
Any input 0V < VIN < Vcc
Other inputs not under test = 0V
−5
5
µA
Output Leakage Current
Output is disabled (Hi-Z)
0V < VOUT < Vcc
−5
5
µA
VOH
Output High Voltage Level
IOH = −5.0 mA with VCC=5V
IOH = −2.0 mA with VCC=3.3V
2.4
−
V
VOL
Output Low Voltage Level
IOL = 4.2 mA with VCC=5V
IOL = 2 mA with VCC=3.3V
−
0.4
V
ICC1
Standby Current: TTL
RAS, CAS − VIH
5V
3.3V
−
−
2
0.5
mA
ICC2
Standby Current: CMOS
RAS, CAS > VCC − 0.2V
5V
3.3V
−
−
1
0.5
mA
ICC3
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
RAS, CAS,
Address Cycling, tRC = tRC (min.)
-50
-60
−
−
120
110
mA
ICC4
Operating Current:
EDO Page Mode(2,3,4)
Average Power Supply Current
RAS = VIL, CAS,
Cycling tPC = tPC (min.)
-50
-60
−
−
90
80
mA
ICC5
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
RAS Cycling, CAS > VIH
tRC = tRC (min.)
-50
-60
−
−
120
110
mA
ICC6
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
RAS, CAS Cycling
tRC = tRC (min.)
-50
-60
−
−
120
110
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
6
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
IC41C4400x and IC41LV4400x Series
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tRC
tRAC
tCAC
tAA
tRAS
tRP
tCAS
tCP
tCSH
tRCD
tASR
tRAH
tASC
tCAH
tAR
tRAD
tRAL
tRPC
tRSH
tRHCP
tCLZ
tCRP
tOD
tOE
tOED
tOEHC
tOEP
tOES
tRCS
tRRH
tRCH
tWCH
tWCR
tWP
tWPZ
tRWL
tCWL
tWCS
tDHR
Parameter
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
RAS Precharge Time
CAS Pulse Width(23)
CAS Precharge Time(9)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
Column-Address Hold Time
(referenced to RAS)
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 24)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 24)
Output Enable Time(15, 16)
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
Read Command Hold Time
(referenced to RAS)(12)
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17)
Write Command Hold Time
(referenced to RAS)(17)
Write Command Pulse Width(17)
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
-50
Max.
Min.
-60
Max.
84
−
−
−
50
30
8
9
38
12
0
8
0
8
30
−
50
13
25
10K
−
10K
−
−
37
−
−
−
−
−
104
−
−
−
60
40
10
9
40
14
0
10
0
10
40
−
60
15
30
10K
−
10K
−
−
45
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
25
5
8
30
0
5
3
−
12
5
10
5
0
0
25
−
−
−
−
−
−
15
12
−
−
−
−
−
−
12
30
5
10
35
0
5
3
−
15
5
10
5
0
0
30
−
−
−
−
−
−
15
15
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
−
0
−
ns
8
40
−
−
10
50
−
−
ns
ns
8
7
13
8
0
39
−
−
−
−
−
−
10
7
15
10
0
39
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
Min.
Units
7
IC41C4400x and IC41LV4400x Series
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
tACH
tOEH
tDS
tDH
tRWC
tRWD
tCWD
tAWD
tPC
tRASP
tCPA
tPRWC
tCOH
tOFF
tWHZ
tCSR
tCHR
tORD
tREF
tT
Parameter
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
EDO Page Mode READ-WRITE
Cycle Time
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 24)
Output Disable Delay from WE
CAS Setup Time (CBR REFRESH)(20, 25)
CAS Hold Time (CBR REFRESH)( 21, 25)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Auto Refresh Period
2,048 Cycles
4,096 Cycles
Transition Time (Rise or Fall)(2, 3)
Min.
-50
Max.
Min.
-60
Max.
Units
15
−
15
−
ns
8
−
10
−
ns
0
8
108
64
−
−
−
−
0
10
133
77
−
−
−
−
ns
ns
ns
ns
26
39
20
−
−
−
32
47
25
−
−
−
ns
ns
ns
50
−
56
100K
30
−
60
−
68
100K
35
−
ns
ns
ns
5
0
−
12
5
0
−
15
ns
ns
3
5
8
0
10
−
−
−
3
5
10
0
10
−
−
−
ns
ns
ns
ns
−
−
1
32
64
50
−
−
1
32
64
50
ms
ns
AC TEST CONDITIONS
Output load:
Two TTL Loads and 50 pF
Input timing reference levels: VIH = 2.4V, VIL = 0.8V
Output timing reference levels: VOH = 2.0V, VOL = 0.8V
8
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
IC41C4400x and IC41LV4400x Series
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH
and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase
by the amount that tRCD exceeds the value shown.
8. Assumes that tRCD > tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the
data output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD
is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD
is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS > tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD > tRWD
(MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from
the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back
to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a
LATE WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW
and OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. Determined by falling edge of CAS.
21. Determined by rising edge of CAS.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23. CAS must meet minimum pulse width.
24. The 3 ns minimum is a parameter guaranteed by design.
25. Enables on-chip refresh and address counters.
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
9
IC41C4400x and IC41LV4400x Series
READ CYCLE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
tRRH
CAS
tAR
tRAD
tRAH
tASR
ADDRESS
tRAL
tCAH
tASC
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLC
I/O
tOFF(1)
Open
Open
Valid Data
tOE
tOD
OE
tOES
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
10
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
IC41C4400x and IC41LV4400x Series
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
CAS
tAR
tRAD
tRAH
tASR
ADDRESS
tRAL
tCAH
tACH
tASC
Row
Column
Row
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
tDHR
tDS
I/O
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
tDH
Valid Data
11
IC41C4400x and IC41LV4400x Series
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
CAS
tAR
tRAD
tRAH
tASR
tRAL
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
tRWD
tCWL
tRWL
tCWD
tRCS
tAWD
tWP
WE
tAA
tRAC
tCAC
tCLZ
I/O
tDS
Open
Valid DOUT
tOE
tOD
tDH
Valid DIN
Open
tOEH
OE
12
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
IC41C4400x and IC41LV4400x Series
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tCAS,
tCLCH
tRCD
tCP
tPC(1)
tCAS,
tCLCH
tCP
tRSH
tCAS,
tCLCH
tCP
CAS
tAR
tRAD
tASR
ADDRESS
tASC
tCAH tASC
Row
Column
tRAL
tCAH
tCAH tASC
Column
Column
Row
tRAH
tRRH
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tCAC
tCOH
Valid Data
tOE
tOES
tAA
tCPA
tCAC
tCLZ
tOFF
Valid Data
tOEHC
Valid Data
Open
tOE
tOD
tOES
tOD
OE
tOEP
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
13
IC41C4400x and IC41LV4400x Series
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tPC
tCAS,
tCLCH
tRCD
tCP
tCAS,
tCLCH
tCP
tRSH
tCAS,
tCLCH
tCP
CAS
tAR
tACH
tCAH tASC
tRAD
tASR
ADDRESS
tASC
Row
Column
tRAH
tACH
tRAL
tCAH
tACH
tCAH tASC
Column
tCWL
tWCS
Column
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tWCH
tWP
tWP
Row
tWP
WE
tWCR
tDHR
tRWL
tDS
tDS
tDH
I/O
Valid Data
tDS
tDH
Valid Data
tDH
Valid Data
OE
14
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
IC41C4400x and IC41LV4400x Series
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
tRASP
tRP
RAS
tCSH
tCRP
tCAS, tCLCH
tRCD
tCP
tPC / tPRWC(1)
tCAS, tCLCH
tRSH
tCAS, tCLCH
tCP
tCP
CAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
tCAH
Row
tASC
tCAH
Column
tRWD
tRCS
tRAL
tCAH
tASC
Column
tCWL
tWP
Column
tRWL
tCWL
tWP
tCWL
tWP
tAWD
tCWD
Row
tAWD
tCWD
tAWD
tCWD
WE
tAA
tAA
tCPA
tDH
tDS
tRAC
tCAC
tCLZ
I/O
Open
tCAC
tCLZ
DOUT
DIN
DIN
DOUT
tOD
tOE
tDH
tDS
tCAC
tCLZ
DOUT
tOD
tOE
tAA
tCPA
tDH
tDS
Open
DIN
tOD
tOE
tOEH
OE
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
15
IC41C4400x and IC41LV4400x Series
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
tRASP
tRP
RAS
tCSH
tPC
tPC
tCRP
tCAS
tRCD
tCAS
tCP
tRSH
tCAS
tCP
tCP
CAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
Row
tCAH
tASC
tCAH
Column (A)
tASC
Column (B)
tRCS
tACH
tRAL
tCAH
Column (N)
Row
tRCH
tWCS
tWCH
WE
tAA
tRAC
tCAC
tCPA
tCAC
tAA
tWHZ
tCOH
I/O
Open
Valid Data (A)
tDS
Valid Data (B)
tDH
DIN
Open
tOE
OE
16
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
IC41C4400x and IC41LV4400x Series
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tCP
tCAS
CAS
tAR
tRAD
tASR
ADDRESS
tRAH
tCAH
tASC
Row
tASC
Column
Column
tRCS
tRCH
tRCS
WE
tAA
tRAC
tCAC
tCLZ
Open
I/O
tWHZ
tCLZ
Valid Data
Open
tOE
tOD
OE
RAS
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCRP
tRPC
CAS
tASR
ADDRESS
I/O
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
tRAH
Row
Row
Open
17
IC41C4400x and IC41LV4400x Series
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tRPC
tCP
tCHR
tCHR
tRPC
tCSR
tCSR
CAS
Open
I/O
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tRSH
tCHR
CAS
tAR
tRAD
tRAH tASC
tASR
ADDRESS
Row
tRAL
tCAH
Column
tAA
tRAC
tOFF(2)
tCAC
tCLZ
I/O
Open
Valid Data
tOE
Open
tOD
tORD
OE
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
18
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
IC41C4400x and IC41LV4400x Series
ORDERING INFORMATION
Commercial Range: 0°°C to 70°°C
Voltage: 5V
Speed (ns)
50
50
60
60
Speed (ns)
50
50
60
60
Order Part No.
IC41C44002-50J
IC41C44002-50T
IC41C44002-60J
IC41C44002-60T
Order Part No.
IC41C44004-50J
IC41C44004-50T
IC41C44004-60J
IC41C44004-60T
Refresh
Package
2K
2K
2K
2K
300mil SOJ
300mil TSOP-2
300-mil SOJ
300mil TSOP-2
Refresh
Package
4K
4K
4K
4K
300mil SOJ
300mil TSOP-2
300mil SOJ
300mil TSOP-2
Refresh
Package
2K
2K
2K
2K
300mil SOJ
300mil TSOP-2
300mil SOJ
300mil TSOP-2
Refresh
Package
4K
4K
4K
4K
300mil SOJ
300mil TSOP-2
300mil SOJ
300mil TSOP-2
Voltage: 3.3V
Speed (ns)
50
50
60
60
Speed (ns)
50
50
60
60
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002
Order Part No.
IC41LV44002-50J
IC41LV44002-50T
IC41LV44002-60J
IC41LV44002-60T
Order Part No.
IC41LV44004-50J
IC41LV44004-50T
IC41LV44004-60J
IC41LV44004-60T
19
IC41C4400x and IC41LV4400x Series
ORDERING INFORMATION
Industrial Range: -40°°C to 85°°C
Voltage: 5V
Speed (ns)
50
50
60
60
Order Part No.
IC41C44002-50JI
IC41C44002-50TI
IC41C44002-60JI
IC41C44002-60TI
Speed (ns)
50
50
60
60
Order Part No.
IC41C44004-50JI
IC41C44004-50TI
IC41C44004-60JI
IC41C44004-60TI
Refresh
Package
2K
2K
2K
2K
300mil SOJ
300mil TSOP-2
300-mil SOJ
300mil TSOP-2
Refresh
Package
4K
4K
4K
4K
300mil SOJ
300mil TSOP-2
300mil SOJ
300mil TSOP-2
Refresh
Package
2K
2K
2K
2K
300mil SOJ
300mil TSOP-2
300mil SOJ
300mil TSOP-2
Refresh
Package
4K
4K
4K
4K
300mil SOJ
300mil TSOP-2
300mil SOJ
300mil TSOP-2
Voltage: 3.3V
Speed (ns)
50
50
60
60
IC41LV44002-50JI
IC41LV44002-50TI
IC41LV44002-60JI
IC41LV44002-60TI
Speed (ns)
50
50
60
60
Order Part No.
Order Part No.
IC41LV44004-50JI
IC41LV44004-50TI
IC41LV44004-60JI
IC41LV44004-60TI
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
20
Integrated Circuit Solution Inc.
DR007-0B 10/17/2002