3.75 kV, 7-Channel, SPIsolator Digital Isolators for SPI ADuM3151/ADuM3152/ADuM3153 Data Sheet FUNCTIONAL BLOCK DIAGRAMS Industrial programmable logic controllers (PLCs) Sensor isolation ADuM3151 20 VDD2 ENCODE DECODE 19 GND2 MCLK 3 ENCODE DECODE 18 SCLK ENCODE 17 SI DECODE 16 SO MSS 6 15 SSS VIA 7 14 VOA MO 4 MI 5 VIB 8 The ADuM3151/ADuM3152/ADuM3153 are 7-channel, SPIsolator™ digital isolators optimized for isolated serial peripheral interfaces (SPIs). Based on the Analog Devices, Inc., iCoupler® chip scale transformer technology, the low propagation delay in the CLK, MO/SI, MI/SO, and SS SPI bus signals supports SPI clock rates of up to 17 MHz. These channels operate with 14 ns propagation delay and 1 ns jitter to optimize timing for SPI. The ADuM3151/ADuM3152/ADuM3153 isolators also provide three additional independent low data rate isolation channels in three different channel direction combinations. Data in the slow channels is sampled and serialized for a 250 kbps data rate with up to 2.5 μs of jitter in the low speed channels. ENCODE CONTROL BLOCK CONTROL BLOCK 13 VOB VOC 9 12 VIC GND1 10 11 GND2 Figure 1. ADuM3151 Functional Block Diagram VDD1 1 ADuM3152 GND1 2 ENCODE 20 VDD2 DECODE 19 GND2 SCLK MCLK 3 ENCODE DECODE 18 MO 4 DECODE ENCODE 17 SI MI 5 ENCODE DECODE 16 SO 15 SSS 14 VOA 13 VIB VOC 9 12 VIC GND1 10 11 GND2 GENERAL DESCRIPTION 1 DECODE MSS 6 VIA 7 VOB 8 CONTROL BLOCK CONTROL BLOCK 12368-002 APPLICATIONS VDD1 1 GND1 2 Figure 2. ADuM3152 Functional Block Diagram VDD1 1 20 VDD2 ADuM3153 GND1 2 ENCODE DECODE MCLK 3 ENCODE DECODE MO 4 DECODE ENCODE MI 5 ENCODE DECODE VOA 7 VOC 9 GND1 10 18 SCLK 17 SI 16 SO 15 SSS MSS 6 VOB 8 19 GND2 14 VIA CONTROL BLOCK CONTROL BLOCK 13 VIB 12 VIC 11 GND2 12368-003 Supports up to 17 MHz SPI clock speed 4 high speed, low propagation delay, SPI signal isolation channels Three 250 kbps data channels 20-lead SSOP package with 5.1 mm creepage High temperature operation: 125°C High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals UL recognition per UL 1577 3750 V rms for 1 minute CSA Component Acceptance Notice 5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 565 V peak 12368-001 FEATURES Figure 3. ADuM3153 Functional Block Diagram 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending. Rev. 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Technical Support www.analog.com ADuM3151/ADuM3152/ADuM3153 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Recommended Operating Conditions .................................... 12 Applications ....................................................................................... 1 Absolute Maximum Ratings ......................................................... 13 General Description ......................................................................... 1 ESD Caution................................................................................ 13 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ......................... 14 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 17 Specifications..................................................................................... 3 Applications Information .............................................................. 18 Electrical Characteristics—5 V Operation................................ 3 Introduction ................................................................................ 18 Electrical Characteristics—3.3 V Operation ............................ 5 Printed Circuit Board (PCB) Layout ....................................... 19 Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 7 Propagation Delay Related Parameters ................................... 19 Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 9 DC Correctness and Magnetic Field Immunity ..................... 19 Package Characteristics ............................................................. 10 Power Consumption .................................................................. 20 Regulatory Information ............................................................. 11 Insulation Lifetime ..................................................................... 20 Insulation and Safety Related Specifications .......................... 11 Outline Dimensions ....................................................................... 22 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Insulation Characteristics.......................................................... 12 Ordering Guide .......................................................................... 22 REVISION HISTORY 3/15—Rev. 0 to Rev. A Changes to Features Section............................................................ 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 4 Changes to Table 5 ............................................................................ 5 Changes to Table 6 ............................................................................ 6 Changes to Table 8 ............................................................................ 7 Changes to Table 9 ............................................................................ 8 Changes to Table 11 .......................................................................... 9 Changes to Table 12 ........................................................................ 10 Changes to Regulatory Information Section and Table 14 ....... 11 Changes to Table 16 and Figure 4 ................................................. 12 Changes to Figure 8, Figure 9, Figure 11, and Figure 12 ........... 17 Changes to High Speed Channels Section .................................. 18 Changes to Power Consumption Section .................................... 20 6/14—Revision 0: Initial Version Rev. A | Page 2 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V. Minimum and maximum specifications apply over the entire recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 1. Switching Specifications Parameter MCLK, MO, SO SPI Clock Rate Data Rate Fast (MO, SO) Propagation Delay Pulse Width Pulse Width Distortion Codirectional Channel Matching 1 Jitter, High Speed MSS Data Rate Fast Propagation Delay Pulse Width Pulse Width Distortion Setup Time 2 Jitter, High Speed VIA, VIB, VIC Data Rate Slow Propagation Delay Pulse Width Jitter, Low Speed VIx 3 Minimum Input Skew 4 Symbol SPIMCLK DRFAST tPHL, tPLH PW PWD tPSKCD JHS DRFAST tPHL, tPLH PW PWD MSSSETUP JHS DRSLOW tPHL, tPLH PW JLS tVIx SKEW3 Min A Grade Typ Max Min 1 2 25 100 B Grade Typ Max 12 12.5 3 3 2 2 1 21 1 2 25 100 21 1.5 3 10 1 1 250 2.6 0.1 4 2.5 10 34 25 12.5 3 0.1 4 17 34 14 250 2.6 2.5 10 Unit MHz Mbps ns ns ns ns ns Test Conditions/Comments Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Mbps ns ns ns ns ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| kbps µs µs µs ns Within PWD limit 50% input to 50% output Within PWD limit Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade. 3 VIx = VIA, VIB, or VIC. 4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. 1 2 Table 2. Supply Current Device Number ADuM3151 ADuM3152 ADuM3153 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 1 MHz, A Grade Min Typ Max 4.0 8.5 6.0 10.5 4.8 8 6.5 10.5 4.0 6.5 6.0 12 17 MHz, B Grade Min Typ Max 14.0 22 13.5 23 14.0 21.5 14.0 22.5 14.0 21.5 13.3 21 Rev. A | Page 3 of 22 Unit mA mA mA mA mA mA Test Conditions/Comments CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels ADuM3151/ADuM3152/ADuM3153 Data Sheet Table 3. For All Models 1, 2, 3 Parameter DC SPECIFICATIONS MCLK, MSS, MO, SO, VIA, VIB, VIC Logic High Input Threshold Logic Low Input Threshold Input Hysteresis Input Current per Channel SCLK, SSS, MI, SI, VOA, VOB, VOC Logic High Output Voltages VOH Logic Low Output Voltages VOL VDD1, VDD2 Undervoltage Lockout Supply Current for High Speed Channel Dynamic Input Supply Current Dynamic Output Supply Current Supply Current for All Low Speed Channels Quiescent Side 1 Current Quiescent Side 2 Current AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 4 Symbol Min VIH VIL VIHYST II 0.7 × VDDx Typ Max 0.3 × VDDx −1 +1 Test Conditions/Comments V V mV µA 0 V ≤ VINPUT ≤ VDDx UVLO 5.0 4.8 0.0 0.2 2.6 IDDI(D) IDDO(D) 0.080 0.046 mA/Mbps mA/Mbps IDD1(Q) IDD2(Q) 4.3 6.1 mA mA 2.5 35 ns kV/µs tR/tF |CM| VDDx − 0.1 VDDx − 0.4 500 +0.01 Unit 25 0.1 0.4 V V V V V IOUTPUT = −20 µA, VINPUT = VIH IOUTPUT = −4 mA, VINPUT = VIH IOUTPUT = 20 µA, VINPUT = VIL IOUTPUT = 4 mA, VINPUT = VIL 10% to 90% VINPUT = VDDx, VCM = 1000 V, transient magnitude = 800 V VDDx = VDD1 or VDD2. VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, VIB, or VIC pins. 3 IOUTPUT is the output current of any of the SCLK, SSS, MI, SI, VOA, VOB, or VOC pins. 4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 Rev. A | Page 4 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted. Table 4. Switching Specifications Parameter MCLK, MO, SO SPI Clock Rate Data Rate Fast (MO, SO) Propagation Delay Pulse Width Pulse Width Distortion Codirectional Channel Matching1 Jitter, High Speed MSS Data Rate Fast Propagation Delay Pulse Width Pulse Width Distortion Setup Time 2 Jitter, Low Speed VIA, VIB, VIC Data Rate Slow Propagation Delay Pulse Width Jitter, Low Speed VIx 3 Minimum Input Skew 4 Symbol SPIMCLK DRFAST tPHL, tPLH PW PWD tPSKCD Min DRSLOW tPHL, tPLH PW JLS tVIx SKEW3 Min B Grade Typ Max 1 2 30 100 12.5 34 20 12.5 3 4 JHS DRFAST tPHL, tPLH PW PWD MSSSETUP JLS A Grade Typ Max 3 2 1 1 2 30 100 12.5 1.5 3 10 2.5 2.5 250 2.6 0.1 4 0.1 4 2.5 10 Test Conditions/Comments MHz Mbps ns ns ns ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| ns 34 30 3 Unit 250 2.6 2.5 10 Mbps ns ns ns ns ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| kbps µs µs µs ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade. 3 VIx = VIA, VIB, or VIC. 4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. 1 2 Table 5. Supply Current Device Number ADuM3151 ADuM3152 ADuM3153 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 1 MHz, A Grade/B Grade Min Typ Max 2.8 6.5 4.6 8 3.4 6 5.0 8 2.8 5.5 3.5 9 17 MHz, B Grade Min Typ Max 10.5 18 9.0 17 11.7 18 10.0 16 11.7 18 10.0 15 Rev. A | Page 5 of 22 Unit mA mA mA mA mA mA Test Conditions/Comments CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels ADuM3151/ADuM3152/ADuM3153 Data Sheet Table 6. For All Models 1, 2, 3 Parameter DC SPECIFICATIONS MCLK, MSS, MO, SO, VIA, VIB, VIC Logic High Input Threshold Logic Low Input Threshold Input Hysteresis Input Current per Channel SCLK, SSS, MI, SI, VOA, VOB, VOC Logic High Output Voltages VOH Logic Low Output Voltages VOL VDD1, VDD2 Undervoltage Lockout Supply Current for High Speed Channel Dynamic Input Supply Current Dynamic Output Supply Current Supply Current for All Low Speed Channels Quiescent Side 1 Current Quiescent Side 2 Current AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 4 Symbol Min VIH VIL VIHYST II 0.7 × VDDx Typ Max 0.3 × VDDx −1 +1 Test Conditions/Comments V V mV µA 0 V ≤ VINPUT ≤ VDDx UVLO 5.0 4.8 0.0 0.2 2.6 IDDI(D) IDDO(D) 0.086 0.019 mA/Mbps mA/Mbps IDD1(Q) IDD2(Q) 2.9 4.7 mA mA 2.5 35 ns kV/µs tR/tF |CM| VDDx − 0.1 VDDx − 0.4 500 +0.01 Unit 25 0.1 0.4 V V V V V IOUTPUT = −20 µA, VINPUT = VIH IOUTPUT = −4 mA, VINPUT = VIH IOUTPUT = 20 µA, VINPUT = VIL IOUTPUT = 4 mA, VINPUT = VIL 10% to 90% VINPUT = VDDx, VCM = 1000 V, transient magnitude = 800 V VDDx = VDD1 or VDD2. VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, VIB, or VIC pins. 3 IOUTPUT is the output current of any of the SCLK, SSS, MI, SI, VOA, VOB, or VOC pins. 4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 Rev. A | Page 6 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION All typical specifications are at TA = 25°C, VDD1 = 5 V, and VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted. Table 7. Switching Specifications Parameter MCLK, MO, SO SPI Clock Rate Data Rate Fast (MO, SO) Propagation Delay Pulse Width Pulse Width Distortion Codirectional Channel Matching1 Jitter, High Speed MSS Data Rate Fast Propagation Delay Pulse Width Pulse Width Distortion Setup Time 2 Jitter, High Speed VIA, VIB, VIC Data Rate Slow Propagation Delay Pulse Width Jitter, Low Speed VIx 3 Minimum Input Skew 4 Symbol SPIMCLK DRFAST tPHL, tPLH PW PWD tPSKCD Min DRSLOW tPHL, tPLH PW JLS tVIx SKEW3 Min B Grade Typ Max 1 2 27 100 15.6 34 16 12.5 3 3 JHS DRFAST tPHL, tPLH PW PWD MSSSETUP JHS A Grade Typ Max 3 2 1 1 2 27 100 12.5 1.5 3 10 1 1 250 2.6 0.1 4 0.1 4 2.5 10 Test Conditions/Comments MHz Mbps ns ns ns ns 1/(4 × tPHL) Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| ns 34 26 3 Unit 250 2.6 2.5 10 Mbps ns ns ns ns ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| kbps µs µs µs ns Within PWD limit 50% input to 50% output Within PWD limit Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade. 3 VIx = VIA, VIB, or VIC. 4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. 1 2 Table 8. Supply Current Device Number ADuM3151 ADuM3152 ADuM3153 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 1 MHz, A Grade/B Grade Min Typ Max 4.0 8.5 4.6 8 4.8 8 5.0 8 4.0 6.5 4.7 9 17 MHz, B Grade Min Typ Max 13.9 22 9.0 17 14.0 21.5 10.0 16 14.0 21.5 10.0 15 Rev. A | Page 7 of 22 Unit mA mA mA mA mA mA Test Conditions/Comments CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels ADuM3151/ADuM3152/ADuM3153 Data Sheet Table 9. For All Models 1, 2, 3 Parameter DC SPECIFICATIONS MCLK, MSS, MO, SO, VIA, VIB, VIC Logic High Input Threshold Logic Low Input Threshold Input Hysteresis Input Current per Channel SCLK, SSS, MI, SI, VOA, VOB, VOC Logic High Output Voltages Logic Low Output Voltages VDD1, VDD2 Undervoltage Lockout Supply Current for All Low Speed Channels Quiescent Side 1 Current Quiescent Side 2 Current AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 4 Symbol Min VIH VIL VIHYST II 0.7 × VDDx VOH VDDX − 0.1 VDDX − 0.4 Typ Max 0.3 × VDDx 500 +0.01 −1 +1 Unit Test Conditions/Comments V V mV µA 0 V ≤ VINPUT ≤ VDDx UVLO 5.0 4.8 0.0 0.2 2.6 IDD1(Q) IDD2(Q) 4.3 4.7 mA mA 2.5 35 ns kV/µs VOL tR/tF |CM| 25 0.1 0.4 V V V V V IOUTPUT = −20 µA, VINPUT = VIH IOUTPUT = −4 mA, VINPUT = VIH IOUTPUT = 20 µA, VINPUT = VIL IOUTPUT = 4 mA, VINPUT = VIL 10% to 90% VINPUT = VDDX, VCM = 1000 V, transient magnitude = 800 V VDDx = VDD1 or VDD2. VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, VIB, or VIC pins. 3 IOUTPUT is the output current of any of the SCLK, SSS, MI, SI, VOA, VOB, VOC pins. 4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 Rev. A | Page 8 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION All typical specifications are at TA = 25°C, VDD1 = 3.3 V, and VDD2 = 5 V. Minimum and maximum specifications apply over the entire recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching specifications are tested with CL =15 pF and CMOS signal levels, unless otherwise noted. Table 10. Switching Specifications Parameter MCLK, MO, SO SPI Clock Rate Data Rate Fast (MO, SO) Propagation Delay Pulse Width Pulse Width Distortion Codirectional Channel Matching 1 Jitter, High Speed MSS Data Rate Fast Propagation Delay Pulse Width Pulse Width Distortion Setup Time 2 Jitter, High Speed VIA, VIB, VIC Data Rate Propagation Delay Pulse Width Jitter, Low Speed VIx 3 Minimum Input Skew 4 Symbol SPIMCLK DRFAST tPHL, tPLH PW PWD tPSKCD JHS DRFAST tPHL, tPLH PW PWD MSSSETUP JHS DRSLOW tPHL, tPLH PW JLS tVIx SKEW3 Min A Grade Typ Max Min B Grade Typ Max 1 2 27 100 15.6 34 16 12.5 3 5 3 2 1 1 2 27 100 34 27 12.5 2 3 1.5 10 1 1 250 2.6 0.1 4 0.1 4 2.5 10 250 2.6 2.5 10 Unit Test Conditions/Comments MHz Mbps ns ns ns ns ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Mbps ns ns ns ns ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| kbps µs µs µs ns Within PWD limit 50% input to 50% output Within PWD limit |tPLH − tPHL| Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output ahead of another fast signal, it must be set up prior to the competing signal by different times depending on speed grade. 3 VIx = VIA, VIB, or VIC. 4 An internal asynchronous clock not available to users samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output. 1 2 Table 11. Supply Current Device Number ADuM3151 ADuM3152 ADuM3153 Symbol IDD1 IDD2 IDD1 IDD2 IDD1 IDD2 1 MHz, A Grade/B Grade Min Typ Max 2.8 6.5 6.0 10.5 3.5 6 6.5 10.5 2.8 5.5 6.0 12 17 MHz, B Grade Min Typ Max 10.5 18 13.0 23 11.7 18 13.4 22.5 11.7 18 13.4 21 Rev. A | Page 9 of 22 Unit mA mA mA mA mA mA Test Conditions/Comments CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels CL = 0 pF, low speed channels ADuM3151/ADuM3152/ADuM3153 Data Sheet Table 12. For All Models 1, 2, 3 Parameter DC SPECIFICATIONS MCLK, MSS, MO, SO, VIA, VIB, VIC Logic High Input Threshold Logic Low Input Threshold Input Hysteresis Input Current per Channel SCLK, SSS, MI, SI, VOA, VOB, VOC Logic High Output Voltages Symbol Min VIH VIL VIHYST II 0.7 × VDDx 500 +0.01 −1 VDDx − 0.1 VDDx − 0.4 +1 Unit Test Conditions/Comments V V mV µA 0 V ≤ VINPUT ≤ VDDx UVLO 5.0 4.8 0.0 0.2 2.6 IDD1(Q) IDD2(Q) 2.9 6.1 mA mA 2.5 35 ns kV/µs VOL VDD1, VDD2 Undervoltage Lockout Supply Current for All Low Speed Channels Quiescent Side 1 Current Quiescent Side 2 Current AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 4 Max 0.3 × VDDx VOH Logic Low Output Voltages Typ tR/tF |CM| 25 0.1 0.4 V V V V V IOUTPUT = −20 µA, VINPUT = VIH IOUTPUT = −4 mA, VINPUT = VIH IOUTPUT = 20 µA, VINPUT = VIL IOUTPUT = 4 mA, VINPUT = VIL 10% to 90% VINPUT = VDDX, VCM = 1000 V, transient magnitude = 800 V VDDx = VDD1 or VDD2. VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, VIB, VIC pins. 3 IOUTPUT is the output current of any of the SCLK, SSS, MI, SI, VOA, VOB, VOC pins. 4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 1 2 PACKAGE CHARACTERISTICS Table 13. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 IC Junction to Case Thermal Resistance 1 2 Symbol RI-O CI-O CI θJC Min Typ 1012 1.0 4.0 75 Max Unit Ω pF pF °C/W Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground. Rev. A | Page 10 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 REGULATORY INFORMATION The ADuM3151/ADuM3152/ADuM3153 are approved by the organizations listed in Table 14. See Table 19 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross isolation waveforms and insulation levels. Table 14. UL Recognized under 1577 Component Recognition Program1 3750 V rms Single Protection File E214100 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2, 510 V rms (721 V peak) maximum working voltage3 File 205078 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-122 Reinforced insulation, 565 V peak File 2471900-4880-0001 1 In accordance with UL 1577, each model is proof tested by applying an insulation test voltage ≥4500 V rms for 1 second (current leakage detection limit = 10 μA). In accordance with DIN V VDE V 0884-10, each model is proof tested by applying an insulation test voltage ≥ 525 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval. 3 See Table 19 for recommended maximum working voltages under various operating conditions. 2 INSULATION AND SAFETY RELATED SPECIFICATIONS Table 15. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 3750 5.1 Unit V rms mm min Minimum External Tracking (Creepage) L(I02) 5.1 mm min Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Material Group CTI 0.017 >400 II mm min V Rev. A | Page 11 of 22 Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303, Part 1 Material group (DIN VDE 0110, 1/89, Table 1) ADuM3151/ADuM3152/ADuM3153 Data Sheet DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval. Table 16. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 Test Conditions/Comments VIORM × 1.875 = Vpd(m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup 1 VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety Limiting Values VIOSM(TEST) = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 4) Case Temperature Safety Total Dissipated Power Insulation Resistance at TS VIO = 500 V Symbol Characteristic Unit VIORM Vpd(m) I to IV I to III I to II 40/105/21 2 565 1059 V peak V peak Vpd(m) 848 V peak Vpd(m) 678 V peak VIOTM VIOSM 5000 6250 V peak V peak TS IS1 RS 150 1.4 >109 °C W Ω RECOMMENDED OPERATING CONDITIONS 2.0 SAFE LIMITING POWER (W) 1.8 Table 17. 1.6 Parameter Operating Temperature Range Supply Voltage Range 1 1.4 1.2 1.0 0.8 Input Signal Rise and Fall Times 0.6 1 0.4 50 100 150 AMBIENT TEMPERATURE (°C) 200 12368-004 0 Min −40°C 3.0 Max +125 5.5 Unit °C V 1.0 ms See the DC Correctness and Magnetic Field Immunity section for information on the immunity to the external magnetic fields. 0.2 0 Symbol TA VDD1, VDD2 Figure 4. Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per DIN V VDE V 0884-10 Rev. A | Page 12 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 19. Maximum Continuous Working Voltage1 Table 18. Parameter AC 60 Hz RMS Voltage Max 400 Unit V rms DC Voltage 722 V peak Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Range Supply Voltages (VDD1, VDD2) Input Voltages (VIA, VIB, VIC, MCLK, MO, MSS) Output Voltages (SCLK, SSS, MI, SI, VOA, VOB, VOC) Average Current per Output Pin1 Common-Mode Transients2 1 2 Rating −65°C to +150°C −40°C to +125°C −0.5 V to +7.0 V −0.5 V to VDDx + 0.5 V 1 −0.5 V to VDDx + 0.5 V 2 3 −10 mA to +10 mA −100 kV/µs to +100 kV/µs See Figure 4 for maximum safety rated current values across temperature. Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Constraint 20-year lifetime at 0.1% failure rate, zero average voltage Limited by the creepage of the package, Pollution Degree 2, Material Group II2, 3 See the Insulation Lifetime section for more details. Other pollution degree and material group requirements yield a different limit. Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards. ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 13 of 22 ADuM3151/ADuM3152/ADuM3153 Data Sheet 1 20 VDD2 GND1 2 19 GND2 MCLK 3 18 SCLK MO 4 ADuM3151 17 SI TOP VIEW (Not to Scale) 16 SO VDD1 MI 5 15 SSS VIA 7 14 VOA MSS 6 VIB 8 13 VOB VOC 9 12 VIC GND1 10 11 GND2 12368-005 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5. ADuM3151 Pin Configuration Table 20. ADuM3151 Pin Function Descriptions Pin No. 1 2, 10 3 4 5 6 Mnemonic VDD1 GND1 MCLK MO MI MSS Direction Power Return Clock Input Output Input 7 8 9 11, 19 12 13 14 15 16 17 18 20 VIA VIB VOC GND2 VIC VOB VOA SSS SO SI SCLK VDD2 Input Input Output Return Input Output Output Output Input Output Output Power Description Input Power Supply for Side 1. A bypass capacitor from VDD1 to GND1 to local ground is required. Ground 1. Ground reference for Isolator Side 1. SPI Clock from the Master Controller. SPI Data from the Master MO/SI Line. SPI Data from the Slave to the Master MI/SO Line. Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns setup time from the next clock or data edge. Low Speed Data Input A. Low Speed Data Input B. Low Speed Data Output C. Ground 2. Ground reference for Isolator Side 2. Low Speed Data Input C. Low Speed Data Output B. Low Speed Data Output A. Slave Select to the Slave. This signal uses an active low logic. SPI Data from the Slave to the Master MI/SO Line. SPI Data from the Master to the Slave MO/SI Line. SPI Clock from the Master Controller. Input Power Supply for Side 2. A bypass capacitor from VDD2 to GND2 to local ground is required. Rev. A | Page 14 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 VDD2 1 20 19 GND2 MCLK 3 18 SCLK ADuM3152 17 SI TOP VIEW (Not to Scale) 16 SO MO 4 MI 5 MSS 6 VIA 7 15 SSS 14 VOA VOB 8 13 VIB VOC 9 12 VIC GND1 10 11 GND2 12368-006 VDD1 GND1 2 Figure 6. ADuM3152 Pin Configuration Table 21. ADuM3152 Pin Function Descriptions Pin No. 1 2, 10 3 4 5 6 Mnemonic VDD1 GND1 MCLK MO MI MSS Direction Power Return Clock Input Output Input 7 8 9 11, 19 12 13 14 15 16 17 18 20 VIA VOB VOC GND2 VIC VIB VOA SSS SO SI SCLK VDD2 Input Output Output Return Input Input Output Output Input Output Output Power Description Input Power Supply for Side 1. A bypass capacitor from VDD1 to GND1 to local ground is required. Ground 1. Ground reference for Isolator Side 1. SPI Clock from the Master Controller. SPI Data from the Master MO/SI Line. SPI Data from the Slave to the Master MI/SO Line. Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns setup time from the next clock or data edge. Low Speed Data Input A. Low Speed Data Output B. Low Speed Data Output C. Ground 2. Ground reference for Isolator Side 2. Low Speed Data Input C. Low Speed Data Input B. Low Speed Data Output A. Slave Select to the Slave. This signal uses an active low logic. SPI Data from the Slave to the Master MI/SO Line. SPI Data from the Master to the Slave MO/SI Line. SPI Clock from the Master Controller. Input Power Supply for Side 2. A bypass capacitor from VDD2 to GND2 to local ground is required. Rev. A | Page 15 of 22 ADuM3151/ADuM3152/ADuM3153 Data Sheet VDD2 1 20 19 GND2 MCLK 3 18 SCLK ADuM3153 17 SI TOP VIEW (Not to Scale) 16 SO MO 4 MI 5 15 SSS 14 VIA VOB 8 13 VIB VOC 9 12 VIC GND1 10 11 GND2 MSS 6 VOA 7 12368-007 VDD1 GND1 2 Figure 7. ADuM3153 Pin Configuration Table 22. ADuM3153 Pin Function Descriptions Pin No. 1 2, 10 3 4 5 6 Mnemonic VDD1 GND1 MCLK MO MI MSS Direction Power Return Clock Input Output Input 7 8 9 11, 19 12 13 14 15 16 17 18 20 VOA VOB VOC GND2 VIC VIB VIA SSS SO SI SCLK VDD2 Output Output Output Return Input Input Input Output Input Output Output Power Description Input Power Supply for Side 1. A bypass capacitor from VDD1 to GND1 to local ground is required. Ground 1. Ground reference for Isolator Side 1. SPI Clock from the Master Controller. SPI Data from the Master MOSI Line SPI Data from the Slave to the Master MI/SO Line. Slave Select from the Master. This signal uses an active low logic. The slave select pin requires a 10 ns setup time from the next clock or data edge. Low Speed Data Output A. Low Speed Data Output B. Low Speed Data Output C. Ground 1. Ground reference for Isolator Side 2. Low Speed Data Input C. Low Speed Data Input B. Low Speed Data Input A. Slave Select to the Slave. This signal uses an active low logic. SPI Data from the Slave to the Master MI/SO Line. SPI Data from the Master to the Slave MO/SI Line. SPI Clock from the Master Controller. Input Power Supply for Side 2. A bypass capacitor from VDD2 to GND2 to local ground is required. Table 23. ADuM3151/ADuM3152/ADuM3153 Power-Off Default State Truth Table (Positive Logic) 1 VDD1 State VDD2 State Side 1 Outputs Side 2 Outputs SSS Comments Unpowered Powered Z Z Z Powered Unpowered Z Z Z Outputs on an unpowered side are high impedance within one diode drop of ground Outputs on an unpowered side are high impedance within one diode drop of ground 1 Z is high impedance. Rev. A | Page 16 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 TYPICAL PERFORMANCE CHARACTERISTICS 4.0 7 3.5 DYNAMIC SUPPLY CURRENT PER OUTPUT CHANNEL (mA) 5 5.0V 3.3V 4 3 2 1 5.0V 2.5 2.0 3.3V 1.5 1.0 40 DATA RATE (Mbps) 20 80 60 0 12368-100 0 Figure 8. Typical Dynamic Supply Current per Input Channel vs. Data Rate for 5.0 V and 3.3 V Operation 0 40 DATA RATE (Mbps) 80 60 Figure 11. Typical Dynamic Supply Current per Output Channel vs. Data Rate for 5.0 V and 3.3 V Operation 25 30 IDD2 SUPPLY CURRENT (mA) 25 20 5.0V 3.3V 15 10 5 0 20 40 DATA RATE (Mbps) 60 80 20 5.0V 15 3.3V 10 5 0 12368-102 0 0 40 DATA RATE (Mbps) 60 80 25 16 3.3V 14 3.3V PROPAGATION DELAY (ns) 20 12 10 20 Figure 12. Typical IDD2 Supply Current vs. Data Rate for 5.0 V and 3.3 V Operation Figure 9. Typical IDD1 Supply Current vs. Data Rate for 5.0 V and 3.3 V Operation PROPAGATION DELAY (ns) 20 12368-101 0.5 0 IDD1 SUPPLY CURRENT (mA) 3.0 12368-103 DYNAMIC SUPPLY CURRENT PER INPUT CHANNEL (mA) 6 5.0V 8 6 4 5.0V 15 10 5 10 60 AMBIENT TEMPERATURE (°C) 110 0 –40 12368-012 0 –40 10 60 AMBIENT TEMPERATURE (°C) Figure 10. Typical Propagation Delay vs. Ambient Temperature for High Speed Channels Without Glitch Filter (See the High Speed Channels Section) 110 12368-013 2 Figure 13. Typical Propagation Delay vs. Ambient Temperature for High Speed Channels with Glitch Filter (See the High Speed Channels Section) Rev. A | Page 17 of 22 ADuM3151/ADuM3152/ADuM3153 Data Sheet APPLICATIONS INFORMATION The ADuM3151/ADuM3152/ADuM3153 are a family of devices created to optimize isolation of SPI for speed and provide additional low speed channels for control and status monitoring functions. The isolators are based on differential signaling iCoupler technology for enhanced speed and noise immunity. High Speed Channels The ADuM3151/ADuM3152/ADuM3153 have four high speed channels. The first three channels, CLK, MI/SO, and MO/SI (the slash indicates the connection of the particular input and output channel across the isolator), are optimized for either low propagation delay in the B grade or high noise immunity in the A grade. The difference between the grades is the addition of a glitch filter to these three channels in the A grade version, which increases the propagation delay. The B grade version, with a maximum propagation delay of 14 ns, supports a maximum clock rate of 17 MHz in the standard 4-wire SPI. However, because the glitch filter is not present in the B grade version, ensure that spurious glitches of less than 10 ns are not present. Glitches of less than 10 ns in the B grade devices can cause the missing of the second edge of the glitch. This pulse condition is then seen as a spurious data transition on the output that is corrected by a refresh or the next valid data edge. It is recommended to use the A grade devices in noisy environments. The relationship between the SPI signal paths and the pin mnemonics of the ADuM3151/ADuM3152/ADuM3153 and the data directions is detailed in Table 24. Table 24. Pin Mnemonics Correspondence to the SPI Signal Path Names SPI Signal Path CLK MO/SI MI/SO SS Master Side 1 MCLK MO MI MSS Data Direction → → ← → Slave Side 2 SCLK SI SO SSS prevents short pulses from propagating to the output or causing other errors in operation. The MSS signal requires a 10 ns setup time in the B grade devices prior to the first active clock edge to allow the added propagation time of the glitch filter. Low Speed Data Channels The low speed data channels are provided as economical isolated datapaths where timing is not critical. The dc value of all high and low speed inputs on a given side of the devices are sampled simultaneously, packetized and shifted across an isolation coil. The high speed channels are compared for dc accuracy, and the low speed data is transferred to the appropriate low speed outputs. The process is then reversed by reading the inputs on the opposite side of the devices, packetizing them and sending them back for similar processing. The dc correctness data for the high speed channels is handled internally, and the low speed data is clocked to the outputs simultaneously. A free running internal clock regulates this bidirectional data shuttling. Because data is sampled at discrete times based on this clock, the propagation delay for a low speed channel is between 0.1 µs and 2.6 µs, depending on where the input data edge changes with respect to the internal sample clock. Figure 14 illustrates the behavior of the low speed channels and the relationship between the codirectional channels. • • • SAMPLE CLOCK The datapaths are SPI mode agnostic. The CLK and MOSI, SPI data paths are optimized for propagation delay and channel to channel matching. The MISO SPI datapath is optimized for propagation delay. The devices do not synchronize to the clock channels so there are no constraints on the clock polarity or the timing with respect to the data lines. To allow compatibility with nonstandard SPI interfaces, the MI pin is always active, and does not tristate when the slave select is not asserted. This precludes tying several MI lines together without adding a tristate buffer or multiplexor. The SS (slave select bar) is typically an active low signal. It can have many different functions in SPI and SPI-like busses. Many of these functions are edge triggered, so the SS path contains a glitch filter in both the A grade and the B grade. The glitch filter Point A: When data is sampled between the input edges of two low speed data inputs, a very narrow gap between edges is increased to the width of the output clock. Point B: Data edges that occur on codirectional channels between samples are sampled and simultaneously sent to the outputs, which synchronizes the data edges between the two channels at the outputs. Point C: Data pulses that are less than the minimum low speed pulse width may not be transmitted because they may not be sampled. INPUT A A INPUT B B A C B OUTPUT A OUTPUT B A C OUTPUT CLOCK 12368-014 INTRODUCTION Figure 14. Slow Channel Timing A low speed data system that is carefully designed so that staggered data transitions at the inputs become either Rev. A | Page 18 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 synchronized or pushed apart when they are presented at the output. Edge order is always preserved for as long as the edges are separated by at least VIx SKEW. In other words, if one edge is leading another at the input, the order of the edges is not reversed by the isolator. PRINTED CIRCUIT BOARD (PCB) LAYOUT The ADuM3151/ADuM3152/ADuM3153 digital isolators require no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at both input and output supply pins: VDD1 and VDD2 (see Figure 15). The capacitor value must be between 0.01 µF and 0.1 µF. The total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm. SCLK ADuM3151/ ADuM3152/ ADuM3153 MO MI SI SO MSS SSS VIA/VOA VOA/VIB VIC VOC GND2 GND1 12368-015 VIB/VOB VIB/VOB Figure 15. Recommended PCB Layout In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, design the board layout so that any coupling that does occur affects all pins equally on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. PROPAGATION DELAY RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input to output propagation delay time for a high to low transition may differ from the propagation delay time of a low to high transition. INPUT 50% OUTPUT tPHL 12368-016 tPLH 50% Figure 16. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved. The pulses at the transformer output have an amplitude greater than 1.5 V. The decoder has a sensing threshold of about 1.0 V; thereby, establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)∑πrn2; n = 1, 2, …, N where: β is the magnetic flux density. rn is the radius of the nth turn in the receiving coil. N is the number of turns in the receiving coil. Given the geometry of the receiving coil in the ADuM3151/ ADuM3152/ADuM3153 and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 17. 100 Channel to channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM3151/ADuM3152/ADuM3153 component. Rev. A | Page 19 of 22 10 1 0.1 0.01 0.001 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 17. Maximum Allowable External Magnetic Flux Density 12368-017 GND1 If the low speed decoder receives no pulses for more than about 5 µs, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a high-Z state by the watchdog timer circuit. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) VDD2 GND2 MCLK Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and is, therefore, either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than ~1.2 µs, a periodic set of refresh pulses indicative of the correct input state are sent via the low speed channel to ensure dc correctness at the output. The limitation on the magnetic field immunity of the device is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines such conditions. The ADuM3151/ADuM3152/ADuM3153 were examined in a 3 V operating condition because it represents the most susceptible mode of operation for this product. BYPASS < 2mm VDD1 DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY ADuM3151/ADuM3152/ADuM3153 Data Sheet For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.5 kgauss, induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. If such an event occurs, with the worst-case polarity, during a transmitted pulse, it reduces the received pulse from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM3151/ADuM3152/ADuM3153 transformers. Figure 18 expresses these allowable current magnitudes as a function of frequency for selected distances. The ADuM3151/ADuM3152/ ADuM3153 are insensitive to external fields. Only extremely large, high frequency currents, very close to the component are a concern. For the 1 MHz example noted, a user would have to place a 1.2 kA current 5mm away from the ADuM3151/ ADuM3152/ADuM3153 to affect component operation. DISTANCE = 1m 100 For Side 1, the supply current is given by IDD1 = IDDI(D) × (fMCLK + fMO + fMSS) + fMI × (IDDO(D) + ((0.5 × 10−3) × CL(MI) × VDD1)) + IDD1(Q) For Side 2, the supply current is given by IDD2 = IDDI(D) × fSO + fSCLK × (IDDO(D) + ((0.5 × 10−3) × CL(SCLK) × VDD2)) + fSI × (IDDO(D) + ((0.5 × 10−3) × CL(SI) × VDD2)) + fSSS × (IDDO(D) + ((0.5 × 10−3) × CL(SSS) × VDD2)) + IDD2(Q) where: IDDI(D), IDDO(D) are the input and output dynamic supply currents per channel (mA/Mbps). fx is the logic signal data rate for the specified channel (Mbps). CL(x) is the load capacitance of the specified output (pF). VDDx is the supply voltage of the side being evaluated (V). IDD1(Q), IDD2(Q) are the specified Side 1 and Side 2 quiescent supply currents (mA). Figure 8 and Figure 11 show the supply current per channel as a function of data rate for an input and unloaded output. Figure 9 and Figure 12 show the total IDD1 and IDD2 supply currents as a function of data rate for the ADuM3151/ADuM3152/ADuM3153 channel configurations with all high speed channels running at the same speed and the low speed channels at idle. 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 INSULATION LIFETIME 0.01 1k 10k 100k 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) 12368-018 MAXIMUM ALLOWABLE CURRENT (kA) 1000 These quiescent currents add to the high speed current as is shown in the following equations for the total current for each side of the isolator. Dynamic currents are taken from Table 3 and Table 6 for the respective voltages. Figure 18. Maximum Allowable Current for Various Current to ADuM3151/ADuM3152/ADuM3153 Spacings At combinations of strong magnetic field and high frequency, any loops formed by the PCB traces may induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Take care to avoid PCB structures that form loops. POWER CONSUMPTION The supply current at a given channel of the ADuM3151/ ADuM3152/ADuM3153 isolators is a function of the supply voltage, the data rate of the channel, and the output load of the channel and whether it is a high or low speed channel. The low speed channels draw a constant quiescent current caused by the internal ping-pong datapath. The operating frequency is low enough that the capacitive losses caused by the recommended capacitive load are negligible compared to the quiescent current. The explicit calculation for the data rate is eliminated for simplicity, and the quiescent current for each side of the isolator due to the low speed channels can be found in Table 3, Table 6, Table 9, and Table 12 for the particular operating voltages. All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation as well as the materials and material interfaces. There are two types of insulation degradation of primary interest: breakdown along surfaces exposed to the air and insulation wear out. Surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. Insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-term insulation degradation. Surface Tracking Surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. Safety agencies perform characterization testing on the surface insulation of components that allow the components to be categorized into different material groups. Lower material group ratings are more resistant to surface tracking and, therefore, can provide adequate lifetime with smaller creepage. The minimum creepage for a given working voltage and material group is in each system level standard and Rev. A | Page 20 of 22 Data Sheet ADuM3151/ADuM3152/ADuM3153 The lifetime of insulation due to wear out is determined by its thickness, the material properties, and the voltage stress applied. It is important to verify that the product lifetime is adequate at the application working voltage. The working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. It is the working voltage applicable to tracking that is specified in most standards. Testing and modeling have shown that the primary driver of long-term degradation is displacement current in the polyimide insulation causing incremental damage. The stress on the insulation can be broken down into broad categories, such as dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. The ratings in certification documents are usually based on 60 Hz sinusoidal stress because this reflects isolation from line voltage. However, many practical applications have combinations of 60 Hz ac and dc across the barrier, as shown in Equation 1. Because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as shown in Equation 2. For insulation wear out with the polyimide materials used in this product, the ac rms voltage determines the product lifetime. VRMS = VAC RMS + VDC 2 2 where: VAC RMS is the time varying portion of the working voltage. VDC is the dc offset of the working voltage. VRMS is the total rms working voltage. Calculation and Use of Parameters Example The following is an example that frequently arises in power conversion applications. Assume that the line voltage on one side of the isolation is 240 V ac rms, and a 400 V dc bus voltage is present on the other side of the isolation barrier. The isolator material is polyimide. To establish the critical voltages in VDC TIME The working voltage across the barrier from Equation 1 is VRMS = VAC RMS 2 + VDC 2 VRMS = 2402 + 4002 VRMS = 466 V This is the working voltage used together with the material group and pollution degree when looking up the creepage required by a system standard. To determine if the lifetime is adequate, obtain the time varying portion of the working voltage. The ac rms voltage can be obtained from Equation 2. VAC RMS = VRMS2 − VDC 2 (1) (2) VRMS VPEAK Figure 19. Critical Voltage Example VAC RMS = 4662 − 4002 or VAC RMS = VRMS 2 − VDC 2 VAC RMS 12368-019 Insulation Wear Out determining the creepage clearance and lifetime of a device, see Figure 19 and the following equations. ISOLATION VOLTAGE is based on the total rms voltage across the isolation, pollution degree, and material group. The material group and creepage for the ADuM3151/ADuM3152/ADuM3153 isolators are detailed in Table 15. VAC RMS = 240 V rms In this case, the ac rms voltage is simply the line voltage of 240 V rms. This calculation is more relevant when the waveform is not sinusoidal. The value is compared to the limits for the working voltage listed in Table 19 for the expected lifetime, under a 60 Hz sine wave, and it is well within the limit for a 50-year service life. Note that the dc working voltage limit in Table 19 is set by the creepage of the package as specified in IEC 60664-1. This value may differ for specific system level standards. Rev. A | Page 21 of 22 ADuM3151/ADuM3152/ADuM3153 Data Sheet OUTLINE DIMENSIONS 7.50 7.20 6.90 11 20 5.60 5.30 5.00 1 8.20 7.80 7.40 10 0.65 BSC SEATING PLANE 8° 4° 0° 0.95 0.75 0.55 060106-A 0.38 0.22 0.05 MIN COPLANARITY 0.10 0.25 0.09 1.85 1.75 1.65 2.00 MAX COMPLIANT TO JEDEC STANDARDS MO-150-AE Figure 20. 20-Lead Shrink Small Outline Package [SSOP] (RS-20) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADuM3151ARSZ ADuM3151ARSZ-RL7 No. of Inputs, VDD1 Side 5 5 No. of Inputs, VDD2 Side 2 2 Maximum Data Rate (MHz) 1 1 Maximum Propagation Delay, 5 V (ns) 25 25 Isolation Rating (V ac) 3750 3750 Temperature Range −40°C to +125°C −40°C to +125°C ADuM3151BRSZ ADuM3151BRSZ-RL7 5 5 2 2 17 17 14 14 3750 3750 −40°C to +125°C −40°C to +125°C EVAL-ADuM3151Z ADuM3152ARSZ ADuM3152ARSZ-RL7 4 4 3 3 1 1 25 25 3750 3750 −40°C to +125°C −40°C to +125°C ADuM3152BRSZ ADuM3152BRSZ-RL7 4 4 3 3 17 17 14 14 3750 3750 −40°C to +125°C −40°C to +125°C ADuM3153ARSZ ADuM3153ARSZ-RL7 3 3 4 4 1 1 25 25 3750 3750 −40°C to +125°C −40°C to +125°C ADuM3153BRSZ ADuM3153BRSZ-RL7 3 3 4 4 17 17 14 14 3750 3750 −40°C to +125°C −40°C to +125°C 1 Z = RoHS Compliant Part. ©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12368-0-3/15(A) Rev. A | Page 22 of 22 Package Description 20-Lead SSOP 20-Lead SSOP, 7” Tape and Reel 20-Lead SSOP 20-Lead SSOP, 7” Tape and Reel Evaluation Board 20-Lead SSOP 20-Lead SSOP, 7” Tape and Reel 20-Lead SSOP 20-Lead SSOP, 7” Tape and Reel 20-Lead SSOP 20-Lead SSOP, 7” Tape and Reel 20-Lead SSOP 20-Lead SSOP, 7” Tape and Reel Package Option RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20 RS-20