Cypress CY7C1302DV25-167BZC 9-mbit burst of two pipelined srams with qdr architecture jtag interface Datasheet

CY7C1302DV25
9-Mbit Burst of Two Pipelined SRAMs
with QDR™ Architecture
9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture
Features
Functional Description
■
Separate independent Read and Write data ports
❐ Supports concurrent transactions
■
167-MHz clock for high bandwidth
❐ 2.5 ns Clock-to-Valid access time
■
2-word burst on all accesses
■
Double Data Rate (DDR) interfaces on both Read and Write
ports (data transferred at 333 MHz) @ 167 MHz
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize
clock-skew and flight-time mismatches.
■
Single multiplexed address input bus latches address inputs
for both Read and Write ports
■
Separate Port Selects for depth expansion
■
Synchronous internally self-timed writes
■
2.5 V core power supply with HSTL Inputs and Outputs
■
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■
Variable drive HSTL output buffers
■
Expanded HSTL output voltage (1.4 V–1.9 V)
■
JTAG Interface
Configurations
CY7C1302DV25 – 512 K × 18
Cypress Semiconductor Corporation
Document Number: 38-05625 Rev. *D
•
The CY7C1302DV25 is a 2.5 V Synchronous Pipelined SRAM
equipped with QDR™ architecture. QDR architecture consists of
two separate ports to access the memory array. The Read port
has dedicated data outputs to support Read operations and the
Write Port has dedicated data inputs to support Write operations.
Access to each port is accomplished through a common address
bus. The Read address is latched on the rising edge of the
K clock and the Write address is latched on the rising edge of
K clock. QDR has separate data inputs and data outputs to
completely eliminate the need to “turn-around” the data bus
required with common I/O devices. Accesses to the
CY7C1302DV25 Read and Write ports are completely
independent of one another. All accesses are initiated
synchronously on the rising edge of the positive input clock (K).
In order to maximize data throughput, both Read and Write ports
are equipped with DDR interfaces. Therefore, data can be
transferred into the device on every rising edge of both input
clocks (K and K) and out of the device on every rising edge of
the output clock (C and C, or K and K in a single clock domain)
thereby maximizing performance while simplifying system
design. Each address location is associated with two 18-bit
words that burst sequentially into or out of the device.
Depth expansion is accomplished with a Port Select input for
each port. Each Port Select allows each port to operate
independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 9, 2011
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CY7C1302DV25
Logic Block Diagram - CY7C1302DV25
Address
Register
18
K
K
CLK
Gen.
Write
Data Reg
256Kx18
Memory
Array
Write
Data Reg
256Kx18
Memory
Array
Read Add. Decode
A(17:0)
18
Write Add. Decode
D[17:0]
Address
Register
Control
Logic
Read Data Reg.
36
Vref
WPS
BWS0
Control
Logic
BWS1
Document Number: 38-05625 Rev. *D
18
Reg.
18
Reg. 18
Reg.
18
A(17:0)
18
RPS
C
C
18
Q[17:0]
Page 2 of 25
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CY7C1302DV25
Contents
Selection Guide ................................................................ 4
Pin Configuration ............................................................. 4
165-ball FBGA (13 × 15 × 1.4 mm) Pinout .................. 4
Pin Definitions .................................................................. 4
Introduction ....................................................................... 5
Functional Overview .................................................... 5
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 6
Single Clock Mode ...................................................... 6
Concurrent Transactions ............................................. 6
Depth Expansion ......................................................... 6
Programmable Impedance .......................................... 6
Application Example ........................................................ 7
Truth Table ........................................................................ 8
Write Cycle Descriptions ................................................. 8
IEEE 1149.1 Serial Boundary Scan (JTAG) .................... 9
Disabling the JTAG Feature ........................................ 9
Test Access Port—Test Clock ..................................... 9
Test Mode Select ........................................................ 9
Test Data-In (TDI) ....................................................... 9
Test Data-Out (TDO) ................................................... 9
Performing a TAP Reset ............................................. 9
TAP Registers ............................................................. 9
TAP Instruction Set ..................................................... 9
TAP Controller State Diagram ....................................... 11
TAP Controller Block Diagram ...................................... 12
TAP Electrical Characteristics ...................................... 12
Document Number: 38-05625 Rev. *D
TAP AC Switching Characteristics ............................... 13
TAP Timing and Test Conditions .................................. 14
Identification Register Definitions ................................ 14
Scan Register Sizes ....................................................... 15
Instruction Codes ........................................................... 15
Boundary Scan Order .................................................... 16
Maximum Ratings ........................................................... 17
Operating Range ............................................................. 17
Electrical Characteristics ............................................... 17
DC Electrical Characteristics ..................................... 17
AC Input Requirements ............................................. 17
Thermal Resistance ........................................................ 18
Capacitance .................................................................... 18
AC Test Loads and Waveforms ..................................... 18
Switching Characteristics .............................................. 18
Switching Waveforms .................................................... 20
Ordering Information ...................................................... 21
Ordering Code Definitions ......................................... 21
Package Diagram ............................................................ 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC Solutions ......................................................... 25
Page 3 of 25
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CY7C1302DV25
Selection Guide
CY7C1302DV25-167
Unit
Maximum Operating Frequency
167
MHz
Maximum Operating Current
500
mA
Pin Configuration
165-ball FBGA (13 × 15 × 1.4 mm) Pinout
CY7C1302DV25 (512 K × 18)
1
2
3
4
5
6
7
8
9
WPS
BWS1
K
NC
RPS
D9
A
NC
K
BWS0
A
NC
D10
VSS
A
A
A
VSS
D11
Q10
VSS
VSS
VSS
VSS
VSS
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
A
NC
B
NC
Gnd/144M NC/36M
C
NC
D
NC
E
NC
NC
Q9
10
NC/18M Gnd/72M
NC
11
NC
NC
Q8
NC
Q7
D8
NC
NC
D7
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
NC
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Pin Definitions
Name
I/O
Description
D[17:0]
InputData input signals, sampled on the rising edge of K and K clocks during valid Write
Synchronous operations.
WPS
InputWrite Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active,
Synchronous a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port
will cause D[17:0] to be ignored.
BWS0,
BWS1
InputByte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous Write operations. Used to select which byte is written into the device during the current portion of
the Write operations. Bytes not written remain unaltered.
BWS0 controls D[8:0] and BWS1 controls D[17:9].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks
Synchronous for active Read and Write operations. These address inputs are multiplexed for both Read and
Write operations. Internally, the device is organized as 512 K × 18 (2 arrays each of 256 K × 18).
These inputs are ignored when the appropriate port is deselected.
Q[17:0]
OutputsData Output signals. These pins drive out the requested data during a Read operation. Valid data
Synchronous is driven out on the rising edge of both the C and C clocks during Read operations or K and K
when in single clock mode. When the Read port is deselected, Q[17:0] are automatically
three-stated.
Document Number: 38-05625 Rev. *D
Page 4 of 25
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CY7C1302DV25
Pin Definitions (continued)
Name
RPS
I/O
Description
InputRead Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When
Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When
deselected, the pending access is allowed to complete and the output drivers are automatically
three-stated following the next rising edge of the C clock. Each read access consists of a burst of
two sequential transfers.
C
Input-Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various devices on
the board back to the controller. See application example for further details.
C
Input-Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data
from the device. C and C can be used together to deskew the flight times of various devices on
the board cack to the controller. See application example for further details.
K
Input-Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[17:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the
device and to drive out data through Q[17:0] when in single clock mode.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. Q[17:0] output impedance is set to 0.2 × RQ, where RQ is a resistor connected
between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables
the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
ZQ
TDO
Output
TCK
Input
TDO for JTAG.
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC/18M
N/A
Address expansion for 18M. This is not connected to the die and so can be tied to any voltage
level.
NC/36M
N/A
Address expansion for 36M. This is not connected to the die and so can be tied to any voltage
level.
GND/72M
Input
Address expansion for 72M. This must be tied LOW.
GND/144M
Input
Address expansion for 144M. This must be tied LOW.
N/A
Not connected to the die. Can be tied to any voltage level.
NC
VREF
VDD
VSS
VDDQ
InputReference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
Power Supply Power supply inputs to the core of the device.
Ground
Ground for the device.
Power Supply Power supply inputs for the outputs of the device.
Introduction
Functional Overview
The CY7C1302DV25 is a synchronous pipelined Burst SRAM
equipped with both a Read port and a Write port. The Read port
is dedicated to Read operations and the Write port is dedicated
to Write operations. Data flows into the SRAM through the Write
port and out through the Read port. These devices multiplex the
address inputs in order to minimize the number of address pins
required. By having separate Read and Write ports, the QDR-I
completely eliminates the need to “turn-around” the data bus and
avoids any possible data contention, thereby simplifying system
design.
Document Number: 38-05625 Rev. *D
Accesses for both ports are initiated on the rising edge of the
Positive Input Clock (K). All synchronous input timing is
referenced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the output clocks (C and C, or
K and K when in single clock mode).
All synchronous data inputs (D[17:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[17:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C, or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS[1:0]) inputs pass
through input registers controlled by the rising edge of input
clocks (K and K).
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CY7C1302DV25
Read Operations
The CY7C1302DV25 is organized internally as 2 arrays of
256 K × 18. Accesses are completed in a burst of two sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. Following
the next K clock rise the corresponding lower order 18-bit word
of data is driven onto the Q[17:0] using C as the output timing
reference. On the subsequent rising edge of C the higher order
data word is driven onto the Q[17:0]. The requested data will be
valid 2.5 ns from the rising edge of the output clock (C and C, or
K and K when in single clock mode, 167-MHz device).
Synchronous internal circuitry will automatically three-state the
outputs following the next rising edge of the positive output clock
(C). This will allow for a seamless transition between devices
without the insertion of wait states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D[17:0] is latched into the lower 18-bit
Write Data register provided BWS[1:0] are both asserted active.
On the subsequent rising edge of the negative input clock (K),
the address is latched and the information presented to D[17:0] is
stored into the Write Data register provided BWS[1:0] are both
asserted active. The 36 bits of data are then written into the
memory array at the specified location.
When deselected, the Write port will ignore all inputs after the
pending Write operations have been completed.
Byte Write Operations
Byte Write operations are supported by the CY7C1302DV25. A
Write operation is initiated as described in the Write Operation
section above. The bytes that are written are determined by
BWS0 and BWS1 which are sampled with each set of 18-bit data
word. Asserting the appropriate Byte Write Select input during
the data portion of a write will allow the data being presented to
be latched and written into the device. Deasserting the Byte
Write Select input during the data portion of a write will allow the
data stored in the device for that byte to remain unaltered. This
Document Number: 38-05625 Rev. *D
feature can be used to simplify Read/Modify/Write operations to
a Byte Write operation.
Single Clock Mode
The CY7C1302DV25 can be used with a single clock mode. In
this mode the device will recognize only the pair of input clocks
(K and K) that control both the input and output registers. This
operation is identical to the operation if the device had zero skew
between the K/K and C/C clocks. All timing parameters remain
the same in this mode. To use this mode of operation, the user
must tie C and C HIGH at power-up.This function is a strap option
and not alterable during device operation.
Concurrent Transactions
The Read and Write ports on the CY7C1302DV25 operate
completely independently of one another. Since each port
latches the address inputs on different clock edges, the user can
Read or Write to any location, regardless of the transaction on
the other port. Also, reads and writes can be started in the same
clock cycle. If the ports access the same location at the same
time, the SRAM will deliver the most recent information
associated with the specified address location. This includes
forwarding data from a Write cycle that was initiated on the
previous K clock rise.
Depth Expansion
The CY7C1302DV25 has a Port Select input for each port. This
allows for easy depth expansion. Both Port Selects are sampled
on the rising edge of the Positive Input Clock only (K). Each port
select input can deselect the specified port. Deselecting a port
will not affect the other port. All pending transactions (Read and
Write) will be completed prior to the device being deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM, The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175  and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles to account for
drifts in supply voltage and temperature.
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CY7C1302DV25
Application Example[1]
Note
1. The above application shows 4 QDR-I being used.
Document Number: 38-05625 Rev. *D
Page 7 of 25
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CY7C1302DV25
Truth Table[2, 3, 4, 5, 6, 7]
Operation
K
RPS
WPS
DQ
DQ
Write Cycle:
Load address on the rising edge of K
clock; input write data on K and K rising
edges.
L–H
X
L
D(A+0) at K(t) 
D(A+1) at K(t) 
Read Cycle:
Load address on the rising edge of K
clock; wait one cycle; read data on 2
consecutive C and C rising edges.
L–H
L
X
Q(A+0) at C(t+1)
Q(A+1) at C(t+1) 
NOP: No Operation
L–H
H
H
D=X
Q = High Z
D=X
Q = High Z
Stopped
X
X
Previous State
Previous State
Standby: Clock Stopped
Write Cycle Descriptions[2, 8]
BWS0
BWS1
K
K
Comments
L
L
L–H
–
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L
L
–
L–H
During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.
L
H
L–H
–
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
L
H
–
L–H
During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the
device. D[17:9] remains unaltered.
H
L
L–H
–
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
D[8:0] remains unaltered.
H
L
–
L–H
During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device.
D[8:0] remains unaltered.
H
H
L–H
–
No data is written into the device during this portion of a Write operation.
H
H
–
L–H
No data is written into the device during this portion of a Write operation.
Notes
2. ,X = Don't Care, H = Logic HIGH, L = Logic LOW represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 can be altered on different portions of a Write cycle, as
long as the set-up and hold requirements are achieved.
Document Number: 38-05625 Rev. *D
Page 8 of 25
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CY7C1302DV25
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access
port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-1900. The TAP operates using JEDEC
standard 2.5 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this pin unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction codes). The output
changes on the falling edge of TCK. TDO is connected to the
least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating. At
power-up, the TAP is reset internally to ensure that TDO comes
up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction registers. Data is serially loaded into the TDI pin on
the rising edge of TCK. Data is output on the TDO pin on the
falling edge of TCK.
Document Number: 38-05625 Rev. *D
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins as shown in TAP Controller Block Diagram. Upon
power-up, the instruction register is loaded with the IDCODE
instruction. It is also loaded with the IDCODE instruction if the
controller is placed in a reset state as described in the previous
section.
When the TAP controller is in the Capture IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several no connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can
be used to capture the contents of the Input and Output ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions
table.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the Instruction
Code table. Three of these instructions are listed as RESERVED
and should not be used. The other five instructions are described
in detail below.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
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CY7C1302DV25
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction is
loaded into the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK captured in the boundary scan
register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Document Number: 38-05625 Rev. *D
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required—that is, while data captured
is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
EXTEST Output Bus Three-state
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a three-state mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus three-state”, is
latched into the preload register during the “Update-DR” state in
the TAP controller, it will directly control the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it will enable the output buffers to drive
the output bus. When LOW, this bit will place the output bus into
a high Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the “Shift-DR” state. During “Update-DR”, the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is pre-set
HIGH to enable the output when the device is powered-up, and
also when the TAP controller is in the “Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 10 of 25
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CY7C1302DV25
TAP Controller State Diagram[9]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
SHIFT-IR
1
0
1
0
UPDATE-IR
1
0
Note
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 38-05625 Rev. *D
Page 11 of 25
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CY7C1302DV25
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
TDI
2
1
0
1
0
Selection
Circuitry
Instruction Register
31 30 29
.
.
2
TDO
Identification Register
106 .
.
.
.
2
1
0
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics
Over the Operating Range [10, 11, 12]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH =2.0 mA
1.7
–
V
VOH2
Output HIGH Voltage
IOH =100 A
2.1
–
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
–
0.7
V
VOL2
Output LOW Voltage
IOL = 100 A
–
0.2
V
VIH
Input HIGH Voltage
1.7
VDD + 0.3
V
VIL
Input LOW Voltage
–0.3
0.7
V
IX
Input and Output Load Current
–5
5
A
GND  VI  VDDQ
Notes
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
11. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5 V (Pulse width less than tCYC/2).
12. All voltage referenced to Ground.
Document Number: 38-05625 Rev. *D
Page 12 of 25
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CY7C1302DV25
TAP AC Switching Characteristics
Over the Operating Range[13, 14]
Parameter
Description
Min
Max
Unit
50
–
ns
TCK Clock Frequency
–
20
MHz
TCK Clock HIGH
20
–
ns
TCK Clock LOW
20
–
ns
tTMSS
TMS Set-up to TCK Clock Rise
10
–
ns
tTDIS
TDI Set-up to TCK Clock Rise
10
–
ns
tCS
Capture Set-up to TCK Rise
10
–
ns
tTCYC
TCK Clock Cycle Time
tTF
tTH
tTL
Set-up Times
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
10
–
ns
tTDIH
TDI Hold after Clock Rise
10
–
ns
tCH
Capture Hold after Clock Rise
10
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
20
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
Output Times
Notes
13. TCS and TCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.
Document Number: 38-05625 Rev. *D
Page 13 of 25
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CY7C1302DV25
TAP Timing and Test Conditions[15]
1.25 V
50 
ALL INPUT PULSES
2.5 V
1.25 V
TDO
Z0 = 50 
(a)
CL = 20 pF
0V
GND
tTH
tTL
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOX
tTDOV
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Value
Description
CY7C1302DV25
000
Cypress Device ID (28:12)
01011010010010110
Cypress JEDEC ID (11:1)
00000110100
ID Register Presence (0)
1
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Note
15. Test conditions are specified using the load in TAP AC test conditions. Tr/Tf = 1 ns.
Document Number: 38-05625 Rev. *D
Page 14 of 25
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CY7C1302DV25
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
107
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the Input/Output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a high Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the Input/Output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 38-05625 Rev. *D
Page 15 of 25
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CY7C1302DV25
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
27
11H
54
7B
81
3G
1
6P
28
10G
55
6B
82
2G
2
6N
29
9G
56
6A
83
1J
3
7P
30
11F
57
5B
84
2J
4
7N
31
11G
58
5A
85
3K
5
7R
32
9F
59
4A
86
3J
6
8R
33
10F
60
5C
87
2K
7
8P
34
11E
61
4B
88
1K
8
9R
35
10E
62
3A
89
2L
9
11P
36
10D
63
1H
90
3L
10
10P
37
9E
64
1A
91
1M
11
10N
38
10C
65
2B
92
1L
12
9P
39
11D
66
3B
93
3N
13
10M
40
9C
67
1C
94
3M
14
11N
41
9D
68
1B
95
1N
15
9M
42
11B
69
3D
96
2M
16
9N
43
11C
70
3C
97
3P
17
11L
44
9B
71
1D
98
2N
18
11M
45
10B
72
2C
99
2P
19
9L
46
11A
73
3E
100
1P
20
10L
47
Internal
74
2D
101
3R
21
11K
48
9A
75
2E
102
4R
22
10K
49
8B
76
1E
103
4P
23
9J
50
7C
77
2F
104
5P
24
9K
51
6C
78
3F
105
5N
25
10J
52
8A
79
1G
106
5R
26
11J
53
7A
80
1F
Document Number: 38-05625 Rev. *D
Page 16 of 25
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CY7C1302DV25
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature .............................. –65 °C to + 150 °C
Ambient Temperature with
Power Applied ........................................ –55 °C to + 125 °C
Static Discharge Voltage ........................................ > 2001 V
(per MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Ambient
Temperature (TA)
Supply Voltage on VDD Relative to GND .....–0.5 V to +3.6 V
Range
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
Commercial
DC Applied to Outputs in high Z .......–0.5 V to VDDQ + 0.5 V
Industrial
0 °C to +70 °C
VDD[17]
VDDQ[17]
2.5 ± 0.1 V 1.4 V to 1.9 V
–40 °C to +85 °C
DC Input Voltage[16] ............................. –0.5 V to VDD + 0.5 V
Electrical Characteristics
Over the Operating Range[18]
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VOH
Output HIGH Voltage
Note 19
VOL
Output LOW Voltage
Note 20
VOH(LOW)
Output HIGH Voltage
IOH = –0.1 mA, Nominal Impedance
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VIH
Input HIGH Voltage[16]
Voltage[16, 21]
VIL
Input LOW
IX
Input Load Current
GND  VI  VDDQ
IOZ
Output Leakage Current
GND  VI  VDDQ, Output Disabled
VREF
Input Reference Voltage[22]
Typical value = 0.75 V
IDD
VDD Operating Supply
ISB1
Automatic Power-Down
Current
Min
Typ
Max
Unit
2.4
2.5
2.6
V
1.4
1.5
1.9
V
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VDDQ – 0.2
–
VDDQ
V
VSS
–
0.2
V
VREF + 0.1
–
VDDQ + 0.3
V
–0.3
–
VREF – 0.1
V
–5
–
5
A
–5
–
5
A
0.68
0.75
0.95
V
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
–
–
500
mA
Max. VDD, Both Ports Deselected,
VIN  VIH or VIN  VIL,
f = fMAX = 1/tCYC, Inputs Static
–
–
240
mA
AC Input Requirements
Over the Operating Range
Min
Typ
Max
Unit
VIH
Parameter
Input HIGH Voltage
Description
Test Conditions
VREF + 0.2
–
–
V
VIL
Input LOW Voltage
–
–
VREF – 0.2
V
Notes
16. Overshoot: VIH(AC) < VDDQ + 0.85 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5 V (Pulse width less than tCYC/2).
17. Power-up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
18. All voltage referenced to Ground.
19. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175   RQ  350 .
20. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175   RQ  350 .
21. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max) = VREF – 0.2 V.
22. VREF (Min.) = 0.68 V or 0.46 VDDQ, whichever is larger, VREF (Max) = 0.95 V or 0.54 VDDQ, whichever is smaller.
Document Number: 38-05625 Rev. *D
Page 17 of 25
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CY7C1302DV25
Thermal Resistance[23]
Parameter
Test Conditions
165-ball FBGA
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
16.7
C/W
2.5
C/W
Test Conditions
Max
Unit
Description
JA
Thermal Resistance
(Junction to Ambient)
JC
Thermal Resistance
(Junction to Case)
Capacitance[23]
Parameter
Description
TA = 25 C, f = 1 MHz, VDD = 2.5 V, VDDQ = 1.5 V
CIN
Input Capacitance
5
pF
CCLK
Clock Input Capacitance
6
pF
CO
Output Capacitance
7
pF
AC Test Loads and Waveforms
VREF = 0.75 V
0.75 V
VREF
VREF
OUTPUT
Z0 = 50 
Device
Under
Test
RL = 50 
RQ =
250 
R = 50 
ALL INPUT PULSES
1.25 V
0.75 V
OUTPUT
Device
Under
VREF = 0.75 V Test ZQ
ZQ
0.75 V
5 pF
[24]
0.25 V
Slew Rate = 2 V/ns
RQ =
250 
(a)
(b)
Switching Characteristics
Over the Operating Range[24]
Cypress
Parameter
Consortium
Parameter
tPower[25]
Description
VCC (typical) to the First Access Read or Write
167 MHz
Unit
Min
Max
10
–
s
Cycle Time
tCYC
tKHKH
K Clock and C Clock Cycle Time
6.0
–
ns
tKH
tKHKL
Input Clock (K/K and C/C) HIGH
2.4
–
ns
tKL
tKLKH
Input Clock (K/K and C/C) LOW
2.4
–
ns
tKHKH
tKHKH
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge
to rising edge)
2.7
3.3
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
0.0
2.0
ns
Set-up Times
tSA
tSA
Address Set-up to Clock (K and K) Rise
0.7
–
ns
tSC
tSC
Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS0, BWS1)
0.7
–
ns
tSD
tSD
D[17:0] Set-up to Clock (K and K) Rise
0.7
–
ns
Notes
23. Tested initially and after any design or process change that may affect these parameters.
24. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75 V,Vref = 0.75 V, RQ = 250 W, VDDQ = 1.5V ,
input pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC test loads.
25. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a
read or write operation can be initiated.
Document Number: 38-05625 Rev. *D
Page 18 of 25
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CY7C1302DV25
Switching Characteristics (continued)
Over the Operating Range[24]
Cypress
Parameter
Consortium
Parameter
Description
167 MHz
Min
Max
Unit
Hold Times
tHA
tHA
Address Hold after Clock (K and K) Rise
0.7
–
ns
tHC
tHC
Control Signals Hold after Clock (K and K) Rise
(RPS, WPS, BWS0, BWS1)
0.7
–
ns
tHD
tHD
D[17:0] Hold after Clock (K and K) Rise
0.7
–
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in single clock mode) to Data Valid
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise (Active to Active)
tCHZ
tCHZ
Clock (C and C) Rise to high Z (Active to high Z)[26, 27]
tCLZ
tCLZ
Clock (C and C) Rise to low Z[26, 27]
–
2.5
ns
1.2
–
ns
–
2.5
ns
1.2
–
ns
Notes
26. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
27. At any given voltage and temperature tCHZ is less than tCLZ and, tCHZ less than tCO.
Document Number: 38-05625 Rev. *D
Page 19 of 25
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CY7C1302DV25
Switching Waveforms[28, 29, 30]
READ
WRITE
READ
WRITE
READ
WRITE
NOP
WRITE
NOP
1
2
3
4
5
6
7
8
9
10
K
tKH
tKL
tKHKH
tCYC
K
RPS
tSC
tHC
WPS
A A0
D
D10
A1
A2
tSA tHA
tSA tHA
D11
D30
A3
A4
A5
D31
D50
D51
Q
Q00
tKHCH
tKHCH
tCO
Q01
tDOH
tCLZ
D60
tSD
tHD
tSD
A6
Q20
D61
tHD
Q21
Q40
Q41
tCHZ
tDOH
tCO
C
tKH
tKL
tKHKH
tCYC
C
DON’T CARE
UNDEFINED
Notes
28. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0 i.e., A0 + 1.
29. Outputs are disabled (High Z) one clock cycle after a NOP.
30. In this example, if address A2 = A1 then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole
diagram.
Document Number: 38-05625 Rev. *D
Page 20 of 25
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CY7C1302DV25
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only
the list of parts that are currently available. For a complete listing of all options, visit the Cypress website at www.cypress.com
and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. Cypress
maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at t http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
167
Package
Diagram
Ordering Code
CY7C1302DV25-167BZC
Package Type
51-85180 165-ball Fine-Pitch Ball Grid Array (13 × 15 × 1.4 mm)
Operating
Range
Commercial
Ordering Code Definitions
CY 7C 1302 D V25 - 167
BZ X
C
Temperature Range:
C = Commercial = 0 °C to +70 °C
X = Pb-free; X Absent = Leaded
Package Type:
BZ = 165-ball FBGA
Speed: 167 MHz
V25 = 2.5 V
Process Technology:  90 nm
Part Identifier
Marketing Code: 7C = SRAM
Company ID: CY = Cypress
Document Number: 38-05625 Rev. *D
Page 21 of 25
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Package Diagram
51-85180 *C
Document Number: 38-05625 Rev. *D
Page 22 of 25
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CY7C1302DV25
Acronyms
Document Conventions
Acronym
Description
BWS
byte write select
DDR
double data rate
FBGA
fine-pitch ball grid array
HSTL
high-speed transceiver logic
I/O
Input/output
JTAG
joint test action group
LSB
least significant bit
MSB
Units of Measure
Symbol
Unit of Measure
°C
degree Celcius
µA
micro Amperes
µs
micro seconds
mA
milli Amperes
mm
milli meter
most significant bit
mV
milli Volts
NC
no connect
mW
milli Watts
QDR
quad data rate
MHz
Mega Hertz
SRAM
static random access memory
ns
nano seconds
TAP
test access port

ohms
TCK
test clock
%
percent
TDI
test data-in
pF
pico Farad
TDO
test data-out
V
Volts
TMS
test mode select
W
Watts
Document Number: 38-05625 Rev. *D
Page 23 of 25
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CY7C1302DV25
Document History Page
Document Title: CY7C1302DV25, 9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture
Document Number: 38-05625
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
**
253010
See ECN
SYT
New Data Sheet
*A
436864
See ECN
NXR
Converted from Preliminary to Final
Removed 133 MHz & 100 MHz from product offering
Included the Industrial Operating Range.
Changed C/C Description in the Features Section & Pin Description Table
Changed tTCYC from 100 ns to 50 ns, changed tTF from 10 MHz to 20 MHz and
changed tTH and tTL from 40 ns to 20 ns in TAP AC Switching Characteristics
table
Modified the ZQ pin definition as follows:
Alternately, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode
Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND
Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD
Modified the Description of IX from Input Load current to Input Leakage
Current on page # 13
Modified test condition in note# 14 from VDDQ < VDD to VDDQ  VDD
Updated the Ordering Information table and replaced the Package Name
Column with Package Diagram
*B
2896202
03/19/2010
NJY
Removed inactive parts from the Ordering Information table; Updated
package diagram.
*C
3122015
12/28/2010
NJY
Updated Ordering Information and added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*D
3249352
05/05/2011
NJY
Updated Ordering Information.
Minor edits across the document.
Document Number: 38-05625 Rev. *D
Page 24 of 25
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CY7C1302DV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05625 Rev. *D
Revised May 9, 2011
Page 25 of 25
Quad Data Rate SRAM and QDR SRAM comprise a new family of products developed by Cypress, IDT, NEC, Renesas and Samsung. All products and company names mentioned in this document
may be the trademarks of their respective holders.
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