IXYS IXDN430YI 30 amp low-side ultrafast mosfet / igbt driver Datasheet

IXDN430 / IXDI430 / IXDD430 / IXDS430
30 Amp Low-Side Ultrafast MOSFET / IGBT Driver
Features
General Description
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected
• High Peak Output Current: 30A Peak
• Wide Operating Range: 8.5V to 35V
• Under Voltage Lockout Protection
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 5600 pF in <25ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
The IXDN430/IXDI430/IXDD430/IXDS430 are high speed high
current gate drivers specifically designed to drive MOSFETs
and IGBTs to their minimum switching time and maximum
practical frequency limits. The IXD_430 can source and sink
30A of peak current while producing voltage rise and fall times
of less than 30ns. The input of the drivers are compatible with
TTL or CMOS and are fully immune to latch up over the entire
operating range. Designed with small internal delays, cross
conduction/current shoot-through is virtually eliminated in all
configurations. Their features and wide safety margin in
operating voltage and power make the drivers unmatched in
performance and value.
Applications
• Driving MOSFETs and IGBTs
• Motor Controls
• Line Drivers
• Pulse Generators
• Local Power ON / OFF Switch
• Switch Mode Power Supplies (SMPS)
• DC to DC Converters
• Pulse Transformer Driver
• Limiting di/dt Under Short Circuit
• Class D Switching Amplifiers
The IXD_430 incorporates a unique ability to disable the output
under fault conditions. The standard undervoltage lockout is at
12.5V which can also be set to 8.5V in the IXDS430SI. When a
logical low is forced into the Enable inputs, both final output
stage MOSFETs (NMOS and PMOS) are turned off. As a
result, the output of the IXDD430 enters a tristate mode and
enables a Soft Turn-Off of the MOSFET when a short circuit is
detected. This helps prevent damage that could occur to the
MOSFET if it were to be switched off abruptly due to a dv/dt
over-voltage transient.
The IXDN430 is configured as a noninverting gate driver, and the
IXDI430 is an inverting gate driver. The IXDS430 can be configured
either as a noninverting or inverting driver. The IXD_430 are available
in the standard 28-pin SIOC (SI-CT), 5-pin TO-220 (CI), and in the
TO-263 (YI) surface mount packages. CT or 'Cool Tab' for the 28pin SOIC package refers to the backside metal heatsink tab.
Ordering Information
P a rt N u m b e r
P a c k a g e T yp e
IX D D 4 3 0 Y I
5 -p in T O -2 6 3
IX D D 4 3 0 C I
5 -p in T O -2 2 0
IX D I4 3 0 Y I
5 -p in T O -2 6 3
IX D I4 3 0 C I
5 -p in T O -2 2 0
IX D N 4 3 0 Y I
5 -p in T O -2 6 3
IX D N 4 3 0 C I
5 -p in T O -2 2 0
IX D S 4 3 0 S I
2 8 -p in S O IC
Tem p. Range
C o n fig u ra tio n
-5 5 °C to + 1 2 5 °
N o n In ve rtin g w ith
E n a b le
-5 5 °C to + 1 2 5 °
In ve rtin g
-5 5 °C to + 1 2 5 °
N o n In ve rtin g
-5 5 °C to + 1 2 5 °
In ve rtin g / N o n
In ve rtin g w ith E n a b le
and UVSEL
Copyright © IXYS CORPORATION 2004
DS99045B(8/04)
First Release
IXDN430 / IXDI430 / IXDD430 / IXDS430
Figure 1A - IXDD430 (Non Inverting With Enable) Diagram
Vcc
Vcc
400k
OUT P
1K
IN
OUT N
EN
GND
GND
Figure 1B - IXDN430 (Non-Inverting) Diagram
Vcc
Vcc
OUT P
1K
IN
OUT N
GND
GND
Figure 1C - IXDI430 (Inverting) Diagram
Vcc
Vcc
OUT P
1K
IN
OUT N
GND
GND
Figure 1D - IXDS430 (Inverting and Non Inverting with Enable) Diagram
Vcc
IN
Vcc
OUT P
1K
400K
OUT N
EN
400K
INV
GND
GND
Note: Out P and Out N are connected together in the 5 lead TO-220 and TO-263 packages.
2
IXDN430 / IXDI430 / IXDD430 / IXDS430
Operating Ratings
Absolute Maximum Ratings (Note 1)
Parameter
Value
P a ra m e te r
Supply Voltage
All Other Pins
40 V
-0.3 V to VCC + 0.3 V
O pera ting T em perature R ange
Power Dissipation, TAMBIENT ≤25 oC
TO220 (CI), TO263 (YI)
Derating Factors (to Ambient)
TO220 (CI), TO263 (YI)
2W
Storage Temperature
0.016W/oC
-65 oC to 150 oC
Lead Temperature (10 sec)
300 oC
V a lu e
M a xim um Junction T em perature
150 o C
-55 o C to 125 o C
T herm al Im pedance T O 220 (C I), TO 263 (Y I)
θ JC (Ju nction T o C ase)
0.95 o C /W
θ JA (Ju nction T o A m bien t)
62.5 o C /W
T herm al Im pedance 28 pin S O IC w ith H eat S lug (S I)
θ JC (Ju nction T o C ase)
3 o C /W
Electrical Characteristics
Unless otherwise noted, TA = 25 oC, 8.5V ≤ VCC ≤ 35V .
All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions.
S ym bol
Param eter
T est C onditio n s
M in
V IH
High input v oltage
4.5V ≤ V C C ≤ 18V
3.5
V IL
Low input v oltage
4.5V ≤ V C C ≤ 18V
V IN
Input v oltage range
I IN
Input current
V OH
High output v oltage
V OL
Low output v oltage
R OH
O utput resistance
@ O utput high
O utput resistance
@ O utput Low
Peak output current
V C C = 18V
V EN
Continuous output
current
Enable v oltage range
Lim ited by package power
dissipation
IXD D430 O nly
V EN H
High E n Input V oltage
IXD D430 O nly
V EN L
Low En Input V oltage
IXD D430 O nly
R EN
EN Input R esistance
IXD S430 O nly
V INV
INV Voltage Range
IXD S430 O nly
- 0.3
V INVH
High IN V Input Voltage
IXD S430 O nly
2/3 V cc
V INVL
Low IN V Input V oltage
IXD S430 O nly
R IN V
INV Input R esistance
IXD S430 O nly
tR
Rise tim e
C L = 5600pF V cc= 18V
18
20
ns
tF
Fall tim e
C L = 5600pF V cc= 18V
16
18
ns
t O ND LY
C L = 5600pF V cc= 18V
41
45
ns
C L = 5600pF V cc= 18V
35
39
ns
IXD D430 O nly, Vcc=18V
47
ns
IXD D430 O nly, Vcc=18V
120
ns
V CC
O n-tim e propagation
delay
Off-tim e propagation
delay
Enable to output high
delay tim e
Disable to output low
delay tim e
Power supply v oltage
IC C
Power supply current
V IN = 3.5V
V IN = 0V
V IN = + V C C
R OL
I PEA K
ID C
t O F FD LY
t E NO H
t D O LD
T yp
M ax
U nits
V
0.8
V
-5
V C C + 0.3
V
-10
10
µA
0.025
V
0.3
0.4
Ω
V C C = 18V
0.2
0.3
Ω
V C C = 18V
30
0V ≤ V IN ≤ V C C
V C C - 0.025
V
- 0.3
A
8
A
Vcc + 0.3
V
2/3 V cc
V
1/3 V cc
400
Vcc + 0.3
V
V
1/3 V cc
400
8.5
V
K ohm
V
K ohm
18
35
V
1
0
3
10
10
mA
µA
µA
Specifications Subject To Change Without Notice
Note 1: Operating the device beyond parameters with listed “absolute maximum ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
3
IXDN430 / IXDI430 / IXDD430 / IXDS430
Electrical Characteristics
Unless otherwise noted, temperature over -55 oC to +125 oC, 4.5 ≤ VCC ≤ 35V .
All voltage measurements with respect to GND. IXDD430 configured as described in Test Conditions.
Symbol
Parameter
Test Conditions
Min
VIH
High input voltage
4.5V ≤ VCC ≤ 18V
3.2
VIL
Low input voltage
4.5V ≤ VCC ≤ 18V
VIN
Input voltage range
ROH
tR
Output resistance
@ Output high
Output resistance
@ Output Low
Rise time
tF
tONDLY
ROL
tOFFDLY
VCC
Typ
Max
Units
V
1.1
V
VCC + 0.3
V
VCC = 18V
0.46
Ω
VCC = 18V
0.4
Ω
CL=5600pF Vcc=18V
20
ns
Fall time
CL=5600pF Vcc=18V
18
ns
On-time propagation
delay
Off-time propagation
delay
Power supply voltage
CL=5600pF Vcc=18V
58
ns
CL=5600pF Vcc=18V
51
ns
35
V
5-lead TO-220 Outline (IXD_430CI)
-5
8.5
18
5-lead TO-263 Outline (IXD_430YI)
28-pin SOIC Outline (IXD_430SI)
NOTE: Mounting tabs, solder tabs, or heat sink metalization on all packages are connected to ground.
4
IXDN430 / IXDI430 / IXDD430 / IXDS430
Pin Configurations
Vcc 1
28 Vcc
Vcc 2
27 Vcc
Vcc 3
26 Vcc
Vcc 4
25 Vcc
N/C 5
28 Pin SOIC
24 OUT P
(SI-CT)
23 OUT P
UVSEL 6
1
2
N/C 7
22 OUT P
IN 8
21 OUT N
3
4
5
EN 9
20 OUT N
INV 10
19 OUT N
GND 11
18 GND
GND 12
17 GND
GND 13
16 GND
GND 14
15 GND
Vcc
OUT
GND
IN
EN *
TO220 (CI)
TO263 (YI)
Pin Description
SYMBOL
FUNCTION
VCC
Supply Voltage
IN
Input
EN *
Enable
INV
Invert
OUT P
OUT N
Output
GND
Ground
UVSEL
Select Under
Voltage Level
DESCRIPTION
Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 8.5V to 35V.
Input signal-TTL or CMOS compatible.
The system enable pin. This pin, when driven low, disables the chip,
forcing high impedance state to the output (IXDD430 Only).
Forcing INV low causes the IXDS430 to become non-inverted, while
forcing INV high causes the IXDS430 to become inverted.
Respective P and N driver outputs. For application purposes this pin
is connected, through a resistor, to Gate of a MOSFET/IGBT. The P
and N output pins are connected together in the TO-263 and TO-220
packages.
The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.
W ith UVSEL connected to Vcc, IXDS430 outputs go low at Vcc <
8.5V; W ith UVSEL open, under voltage level is set at Vcc < 12.5V
* This pin is used only on the IXDD430, and is N/C (not connected) on the IXDI430 and IXDN430.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when
handling and assembling this component.
Figure 2 - Characteristics Test Diagram
.
C
BYPASS/
FILTER
+
-
.
Vcc
Vcc
OUT
GND IXDD430
CLOAD
IN
EN
+
Vin
5
IXDN430 / IXDI430 / IXDD430 / IXDS430
Typical Performance Characteristics
Fig. 3
Fig. 4
Rise Tim es vs. Supply Voltage
Fall Tim es vs. Supply Voltage
30
35
30
25
15000 pF
15000 pF
10000 pF
Fall Time (ns)
Rise Time (ns)
25
20
5600 pF
15
20
10000 pF
5600 pF
15
10
10
1000 pF
1000 pF
5
5
0
0
10
15
20
25
30
10
35
15
20
Fig. 5
Fig. 6
Output Rise Times vs. Load Capacitance
30
35
Output Fall Times vs. Load Capacitance
30
13V
18V
35V
30
25
Fall Time (ns)
25
Rise Time (ns)
25
Supply Voltage (V )
Supply Voltage (V)
20
15
35V
18V
13V
20
15
10
10
5
5
1000
3000
5000
7000
9000
11000
13000
0
1000
15000
3000
5000
Load Capacitance (pF)
Fig. 7
25
7000
Rise and Fall Times vs. Temperature
CL = 5600 pF, Vcc = 18V
11000
13000
15000
Fig. 8
Max / Min Input vs. Temperature
CL = 5600pF, Vcc = 18V
4
3.5
20
tR
15
Max / Min Input Voltage
Time (ns)
9000
Load Capacitance (pF)
tF
10
5
Min Input High
3
Max Input Low
2.5
2
1.5
1
0.5
0
0
-60
-10
40
90
140
190
-60
Temperature (C)
-10
40
90
Temperature (C)
6
140
190
IXDN430 / IXDI430 / IXDD430 / IXDS430
Fig. 9
Supply Current vs. Load Capacitance
Vcc = 13V
300
Fig. 10
1000
Supply Current vs. Frequency
Vcc = 13V
15000
10000
5600
1000
2 MHz
1 MHz
200
100
Supply Current (mA)
Supply Current (mA)
250
150
500 kHz
100
pF
pF
pF
pF
10
1
50
100 kHz
50 kHz
10 kHz
0
1000
10000
0.1
1
100000
10
Load Capacitance (pF)
Supply Current vs. Load Capacitance
Vcc = 18V
Fig. 11
100
1000
Fig. 12
300
Supply Current vs. Frequency
Vcc = 18V
1000
2 MHz
1 MHz
Supply Current (mA)
Supply Current (mA)
250
200
500 kHz
150
100
50
100
10
1
50 kHz
10 kHz
10000
0.1
1
100000
10
Fig. 14
Supply Current vs. Load Capacitance
Vcc = 25V
Fig. 13
400
100
1000
Supply Current vs. Frequency
Vcc = 25V
1000
350
2 MHz
10000
Frequency (kHz)
Load Capacitance (pF)
15000 pF
10000 pF
5600 pF
1000 pF
1 MHz
300
Supply Current (mA)
Supply Current (mA)
15000 pF
10000 pF
5600 pF
1000 pF
100 kHz
0
1000
250
200
500 kHz
150
100
100
10
1
100 kHz
50
0
1000
10000
Frequency (kHz)
50 kHz
10 kHz
10000
0.1
1
100000
10
100
Frequency (kHz)
Load Capacitance (pF)
7
1000
10000
IXDN430 / IXDI430 / IXDD430 / IXDS430
Fig. 15
Supply Current vs. Load Capacitance
Vcc = 35V
Fig. 16
400
1000
Supply Current vs. Frequency
Vcc = 35V
350
Supply Current (mA)
Supply Current (mA)
1 MHz
300
500 kHz
250
200
150
100
100 kHz
15000 pF
10000 pF
5600 pF
1000 pF
100
10
50 kHz
50
10 kHz
1
0
1000
10000
1
100000
10
50
Fig. 18
Propagation Delay vs. Supply Voltage
CL = 5600 pF Vin = 15V@1kHz
Propagation Delay vs. Input Voltage
CL = 5600 pF Vcc = 18V
45
tONDLY
tONDLY
40
40
Propagation Delay (ns)
Propagation Delay (ns)
10000
50
45
35
tOFFDLY
30
25
20
15
35
tOFFDLY
30
25
20
15
10
10
5
5
0
0
10
15
20
25
30
5
35
10
70
Fig. 20
Propagation Delay Times vs. Temperature
CL = 5600pF, Vcc = 18V
20
25
Quiescent Supply Current vs. Temperature
Vcc = 18V, Vin = 15V@1kHz, CL = 5600pF
0.6
Quiescent Vcc Input Current (mA)
Fig. 19
15
Input Voltage (V)
Supply Voltage (V)
60
50
tONDLY
Time (ns)
1000
Frequency (kHz)
Load Capacitance (pF)
Fig. 17
100
40
tOFFDLY
30
20
10
0
0.5
0.4
0.3
0.2
0.1
0
-60
-10
40
90
140
190
-60
Temperature (C)
-10
40
90
Temperature (C)
8
140
190
IXDN430 / IXDI430 / IXDD430 / IXDS430
Fig. 21 High State Output Resistance vs. Supply Voltage
Fig. 22
Low State Output Resistance (Ohms)
High State Output Resistance (Ohms)
Low State Output Resistance vs. Supply Voltage
0.25
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0.2
0.15
0.1
0.05
0
0
10
15
20
25
30
35
40
10
15
20
Supply Voltage (V)
Fig. 23
P Channel O utput Current vs. Vcc
Fig. 24
0
N Channel Output Current (A)
P Channel Output Current (A)
30
35
40
N Channel O utput Current vs. Vcc
70
-10
-20
-30
-40
-50
-60
-70
60
50
40
30
20
10
-80
0
10
15
20
25
30
35
40
10
15
20
V cc (V)
25
30
35
40
Vcc (V)
Fig. 25 P Channel Output Current vs. Temperature
Fig. 26
Vcc = 18V
N Channel Output Current vs. Temperature
Vcc = 18V
45
40
40
35
N Channel Output Current (A)
P Channel Output Current (A)
25
Supply Voltage (V)
30
25
20
15
10
35
30
25
20
15
10
5
5
0
0
-60
-10
40
90
140
-60
190
-10
40
90
Temperature (C)
Temperature (C)
9
140
190
IXDN430 / IXDI430 / IXDD430 / IXDS430
Figure 27 - Typical circuit to decrease di/dt during turn-off
Figure 28 - IXDD430 Application Test Diagram
+
Ld
10uH
-
VB
Rd
IXDD430
0.1ohm
VCC
VCCA
Rg
OUT
IN
EN
+
-
VCC
+
-
VIN
High_Power
VMO580-02F
1ohm
Rsh
1.5k ohm
GND
SUB
Rs
Low_Power
2N7002/PLP
Ls
R+
10kohm
One ShotCircuit
Rcomp
5kohm
NAND
CD4011A
NOT1
CD4049A
NOT2
CD4049A
Ccomp
1pF
Ros
0
Comp
LM339
V+
V-
+
C+
100pF
+
R
1Mohm
Cos
1pF
REF
Q
NOT3
CD4049A
NOR1
CD4001A
EN
NOR2
CD4001A
SR Flip-Flop
10
S
20nH
-
IXDN430 / IXDI430 / IXDD430 / IXDS430
APPLICATIONS INFORMATION
Short Circuit di/dt Limit
A short circuit in a high-power MOSFET module such as the
VM0580-02F, (580A, 200V), as shown in Figure 27, can cause
the current through the module to flow in excess of 1500A for
10µs or more prior to self-destruction due to thermal runaway.
For this reason, some protection circuitry is needed to turn off
the MOSFET module. However, if the module is switched off
too fast, there is a danger of voltage transients occuring on the
drain due to Ldi/dt, (where L represents total inductance in
series with drain). If these voltage transients exceed the
MOSFET's voltage rating, this can cause an avalanche breakdown.
In this way, the high-power MOSFET module is softly turned off
by the IXDD430, preventing its destruction.
Supply Bypassing and Grounding Practices,
Output Lead inductance
When designing a circuit to drive a high speed MOSFET
utilizing the IXDD430/IXDI430/IXDN430, it is very important to
keep certain design criteria in mind, in order to optimize
performance of the driver. Particular attention needs to be paid
to Supply Bypassing, Grounding, and minimizing the Output
Lead Inductance.
The IXDD430 has the unique capability to softly switch off the
high-power MOSFET module, significantly reducing these
Ldi/dt transients.
Say, for example, we are using the IXDD430 to charge a 15nF
capacitive load from 0 to 25 volts in 25ns.
Thus, the IXDD430 helps to prevent device destruction from
both dangers; over-current, and avalanche breakdown due to
di/dt induced over-voltage transients.
Using the formula: I= C ∆V / ∆t, where ∆V=25V C=15nF &
∆t=25ns we can determine that to charge 15nF to 25 volts in
25ns will take a constant current of 15A. (In reality, the charging
current won’t be constant, and will peak somewhere around
30A).
The IXDD430 is designed to not only provide ±30A under
normal conditions, but also to allow it's output to go into a high
impedance state. This permits the IXDD430 output to control
a separate weak pull-down circuit during detected overcurrent
shutdown conditions to limit and separately control dVGS/dt gate
turnoff. This circuit is shown in Figure 28.
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD430
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is a magnitude
larger than the load capacitance. Usually, this would be
achieved by placing two different types of bypassing capacitors,
with complementary impedance curves, very close to the driver
itself. (These capacitors should be carefully selected, low
inductance, low resistance, high-pulse current-service
capacitors). Lead lengths may radiate at high frequency due
to inductance, so care should be taken to keep the lengths of
the leads between these bypass capacitors and the IXDD430
to an absolute minimum.
Referring to Figure 28, the protection circuitry should include
a comparator, whose positive input is connected to the source
of the VM0580-02. A low pass filter should be added to the input
of the comparator to eliminate any glitches in voltage caused
by the inductance of the wire connecting the source resistor to
ground. (Those glitches might cause false triggering of the
comparator).
The comparator's output should be connected to a SRFF(Set
Reset Flip Flop). The flip-flop controls both the Enable signal,
and the low power MOSFET gate. Please note that CMOS
4000-series devices operate with a VCC range from 3 to 15 VDC,
(with 18 VDC being the maximum allowable limit).
GROUNDING
In order for the design to turn the load off properly, the IXDD430
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD430
and it’s load. Path #2 is between the IXDD430 and it’s power
supply. Path #3 is between the IXDD430 and whatever logic is
driving it. All three of these paths should be as low in resistance
and inductance as possible, and thus as short as practical. In
addition, every effort should be made to keep these three
ground paths distinctly separate. Otherwise, (for instance), the
returning ground current from the load may develop a voltage
that would have a detrimental effect on the logic line driving the
IXDD430.
A low power MOSFET, such as the 2N7000, in series with a
resistor, will enable the VMO580-02F gate voltage to drop
gradually. The resistor should be chosen so that the RC time
constant will be 100us, where "C" is the Miller capacitance of
the VMO580-02F.
For resuming normal operation, a Reset signal is needed at
the SRFF's input to enable the IXDD430 again. This Reset can
be generated by connecting a One Shot circuit between the
IXDD430 Input signal and the SRFF restart input. The One Shot
will create a pulse on the rise of the IXDD430 input, and this
pulse will reset the SRFF outputs to normal operation.
When a short circuit occurs, the voltage drop across the lowvalue, current-sensing resistor, (Rs=0.005 Ohm), connected
between the MOSFET Source and ground, increases. This
triggers the comparator at a preset level. The SRFF drives a
low input into the Enable pin disabling the IXDD430 output. The
SRFF also turns on the low power MOSFET, (2N7000).
11
IXDN430 / IXDI430 / IXDD430 / IXDS430
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.
TTL to High Voltage CMOS Level Translation
(IXDD430 Only)
The enable (EN) input to the IXDD430 is a high voltage
CMOS logic level input where the EN input threshold is ½
VCC, and may not be compatible with 5V CMOS or TTL input
levels. The IXDD430 EN input was intentionally designed
for enhanced noise immunity with the high voltage CMOS
logic levels. In a typical gate driver application, VCC =15V
and the EN input threshold at 7.5V, a 5V CMOS logical high
input applied to this typical IXDD430 application’s EN input
will be misinterpreted as a logical low, and may cause
undesirable or unexpected results. The note below is for
optional adaptation of TTL or 5V CMOS levels.
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to the
Q1 emitter will drive it on. This causes the level translator
output, the Q1 collector output to settle to VCESATQ1 +
VTTLLOW=<~2V, which is sufficiently low to be correctly interpreted
as a high voltage CMOS logic low (<1/3VCC=5V for VCC =15V given
in the IXDD430 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 29 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD430 EN input will enable
it, allowing the gate driver to fully function as an 30 Amp
output driver.
The total component cost of the circuit in Figure 29 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
The circuit in Figure 29 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic
input to high voltage CMOS logic levels needed by the
IXDD430 EN input. From the figure, VCC is the gate driver
power supply, typically set between 8V to 20V, and VDD is
the logic power supply, typically between 3.3V to 5.5V.
Resistors R1 and R2 form a voltage divider network so
that the Q1 base is positioned at the midpoint of the
expected TTL logic transition levels.
Figure 29 - TTL to High Voltage CMOS Level Translator
Vcc
(From gate driver
power supply)
(From logic Vdd
power supply)
R3
10K
R1
10K
Q1
2N3904
High Voltage
CMOS EN output
(To IXDD430 EN input)
R2
10K
5V CMOS or TTL input
EN
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
www.ixys.com
e-mail: [email protected]
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: [email protected]
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