LMH6502 Wideband, Low Power, Linear-in-dB Variable Gain Amplifier General Description Features The LMH™6502 is a wideband DC coupled differential input VS = ± 5V, TA = 25˚C, RF = 1kΩ, RG = 174Ω, RL = 100Ω, AV = AV(MAX) = 10 Typical values unless specified. n -3dB BW 130MHz n Gain control BW 100MHz n Adjustment range (typical over temp) 70dB ± 0.6dB n Gain matching (limit) n Slew rate 1800V/µs n Supply current (no load) 27mA ± 75mA n Linear output current ± 3.2V n Output voltage (RL = 100Ω) n Input voltage noise 7.7nV/ n Input current noise 2.4pA/ n THD (20MHz, RL = 100Ω, VO = 2VPP) −53dBc n Replacement for CLC520 voltage controlled gain stage followed by a high-speed current feedback Op Amp which can directly drive a low impedance load. Gain adjustment range is more than 70dB for up to 10MHz. Maximum gain is set by external components and the gain can be reduced all the way to cut-off. Power consumption is 300mW with a speed of 130MHz. Output referred DC offset voltage is less than 350mV over the entire gain control voltage range. Device-to-device Gain matching is within ± 0.6dB at maximum gain. Furthermore, gain at any VG is tested and the tolerance is guaranteed. The output current feedback Op Amp allows high frequency large signals (Slew Rate = 1800V/µs) and can also drive heavy load current (75mA). Differential inputs allow common mode rejection in low level amplification or in applications where signals are carried over relatively long wires. For single ended operation, the unused input can easily be tied to ground (or to a virtual half-supply in single supply application). Inverting or non-inverting gains could be obtained by choosing one input polarity or the other. To provide ease of use when working with a single supply, VG range is set to be from 0V to +2V relative to pin 11 potential (ground pin). In single supply operation, this ground pin is tied to a "virtual" half supply. LMH6502 gain control is linear in dB for a large portion of the total gain control range. This makes the device suitable for AGC circuits among other applications. For linear gain control applications, see the LMH6503 datasheet. The LMH6502 is available in the SOIC-14 and TSSOP-14 package. Gain vs. VG for Various Temperature Applications n n n n Variable attenuator AGC Voltage controller filter Video imaging processing Typical Application 20067737 20067706 AVMAX = 10V/V LMH™ is a trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation DS200677 www.national.com LMH6502 Wideband, Low Power, Linear-in-dB Variable Gain Amplifier June 2004 LMH6502 Absolute Maximum Ratings (Note 1) Junction Temperature If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Soldering Information: +150˚C Infrared or Convection (20 sec) 235˚C Wave Soldering (10 sec) 260˚C ESD Tolerance (Note 4): Human Body 2KV Machine Model Operating Ratings (Note 1) 200V Supply Voltages (V+ - V−) ± 10mA Input Current VIN Differential ± (V -V ) Temperature Range Output Current 120mA (Note 3) Thermal Resistance: + Supply Voltages (V+ - V−) − 12.6V + − Voltage at Input/ Output pins V +0.8V,V - 0.8V Storage Temperature Range −65˚C to +150˚C 5V to 12V −40˚C to +85˚C (θJC) (θJA) 14-Pin SOIC 45˚C/W 138˚C/W 14-Pin TSSOP 51˚C/W 160˚C/W Electrical Characteristics(Note 2) Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VS = ± 5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF = ± 0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 6) Typ (Note 6) Max (Note 6) Units Frequency Domain Response BW GF -3dB Bandwidth Gain Flatness VOUT < 0.5PP 130 VOUT < 0.5PP, AV(MAX) = 100 50 VOUT < 0.5VPP 0.6V ≤ VG ≤ 2V, ± 0.3dB 30 MHz MHz Att Range Flat Band (Relative to Max Gain) Attenuation Range (Note 14) ± 0.2dB, f < 30MHz ± 0.1dB, f < 30MHz 7.5 BW Control Gain control Bandwidth VG = 1V (Note 13) 100 MHz PL Linear Phase Deviation DC to 60MHz 1.5 deg G Delay Group Delay DC to 130MHz 2.5 ns CT (dB) Feed-through VG = 0V, 30MHz (Output Referred) −47 dB GR Gain Adjustment Range f < 10MHz 72 f < 30MHz 67 16 dB dB Time Domain Response tr, tf Rise and Fall Time 0.5V Step 2.2 ns OS % Overshoot 0.5V Step 10 % SR Slew Rate 4V Step 1800 V/µs ∆ G Rate Gain Change Rate VIN = 0.3V, 10%-90% of Final Output 4.8 dB/ns Distortion & Noise Performance HD2 2nd Harmonic Distortion 2VPP, 20MHz −55 dBc HD3 3rd Harmonic Distortion 2VPP, 20MHz −57 dBc THD Total Harmonic Distortion 2VPP, 20MHz −53 En tot Total Equivalent Input Noise 1MHz to 150MHz 7.7 nV/ IN Input Noise Current 1MHz to 150MHz 2.4 pA/ DG Differential Gain f = 4.43MHz, RL = 150Ω, Neg. Sync 0.34 % DP Differential Phase f = 4.43MHz, RL = 150Ω, Neg. Sync 0.10 deg www.national.com 2 dBc (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VS = ± 5V, AV(MAX) = 10, VCM = 0V, RF = 1kΩ, RG = 174Ω, VIN_DIFF = ± 0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 6) Typ (Note 6) Max (Note 6) Units DC & Miscellaneous Performance GACCU G Match Gain Accuracy (See Application Note) Gain Matching (See Application Note) VG = 2.0V 0.0 1V < VG < 2V +0.6/−0.3 VG = 2.0V – ± 0.6 1 < VG < 2V – +2.8/−3.9 1.61 1.58 1.72 1.84 1.91 ± 2.0 ± 1.70 ± 0.3 ± 0.12 ± 1.70 ± 1.56 ± 2.2 K Gain Multiplier (See Application Notes) VCM Input Voltage Range Pin 3 & 6 Common Mode, |CMRR| > 55dB (Note 9) VIN_DIFF Differential Input Voltage Between pins 3 & 6 I RG Current Pins 4 & 5 Bias Current Pins 3 & 6(Note 7) RG_MAX IBIAS Pins 3 & 6 (Note 7), VS = ± 2.5V 18 20 2.5 5 6 Pin 3 & 6(Note 8) 100 Offset Current Pin 3 & 6 0.01 V/V mA 9 Bias Current Drift dB V ± 2.22 I dB V ± 0.39 TC IBIAS OFF +0.6 +3.1/−3.6 µA nA/˚C 2.0 3.6 µA TC IOFF Offset Current Drift (Note 8) 5 nA/˚C RIN Input Resistance Pin 3 & 6 750 kΩ CIN Input Capacitance Pin 3 & 6 IVG VG Bias Current Pin 2, VG = 0V(Note 7) TC IVG VG Bias Drift Pin 2(Note 8) R VG VG Input Resistance C VG VG Input Capacitance Output Voltage Range RL = 100Ω VOUT 5 pF −300 µA 20 nA/˚C Pin 2 10 kΩ Pin 2 1.3 pF RL = Open ± 3.00 ± 2.95 ± 3.95 ± 3.82 ± 3.20 0.1 Ω ± 80 ± 75 ± 90 mA V ± 4.00 ROUT Output Impedance DC IOUT Output Current VOUT = ± 4V from Rails VO Output Offset Voltage 0V < VG < 2V ± 80 ± 300 ± 380 mV +PSRR +Power Supply Rejection Ratio (Note 10) Input Referred, 1V change, VG = 2.2V −69 −47 −45 dB −PSRR −Power Supply Rejection Ratio (Note 10) Input Referred, 1V change, VG = 2.2V −58 −41 −40 CMRR Common Mode Rejection Ratio (Note 9) Input Referred,VG = 2V −1.8V < VCM < 1.8V −72 IS Supply Current No Load 27 38 41 VS = ± 2.5V, RL = Open 9.3 16 19 OFFSET 3 dB dB mA www.national.com LMH6502 Electrical Characteristics(Note 2) LMH6502 Electrical Characteristics(Note 2) (Continued) Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations or value specified, whichever is lower. Note 4: Human body model: 1.5kΩ in series with 100pF. Machine model: 0Ω in series with 200pF. Note 5: Slew Rate is the average of the rising and falling rates. Note 6: Typical values represent the most likely parametric norm. Bold numbers refer to over temperature limits. Note 7: Positive current corresponds to current flowing in the device. Note 8: Drift determined by dividing the change in parameter distribution average at temperature extremes by the total temperature change. Note 9: CMRR definition: [|∆VOUT/∆VCM| / AV] with 0.1V differential input voltage. Note 10: +PSRR definition: [|∆VOUT/∆V+| / AV], −PSRR definition: [|∆VOUT/∆V−| / AV] with 0.1V differential input voltage. Note 11: Gain/Phase normalized to low frequency value at 25˚C. Note 12: Gain/Phase normalized to low frequency value at each AV. Note 13: Gain Control Frequency Response Schematic: 20067738 Note 14: Flat Band Attenuation (Relative to Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain flatness specified (either ± 0.2dB or ± 0.1dB) relative to AVMAX gain. For example, for f < 30MHz, here are the Flat Band Attenuation ranges: ± 0.2dB ± 0.1dB 20dB down to 4dB = 16dB range 20dB down to 12.5 dB = 7.5dB range Connection Diagram 14-Pin SOIC/TSSOP 20067736 Top View Ordering Information Package 14-pin SOIC Part Number Package Marking LMH6502MA LMH6502MA LMH6502MAX 14-Pin TSSOP www.national.com LMH6502MT LMH6502MTX Transport Media NSC Drawing 55 Units/Rail M14A 2.5k Units Tape and Reel 94 Units/Rail LMH6502MT 2.5k Units Tape and Reel 4 MTC14 Large Signal Frequency for Various VG Small Signal Frequency for Various VG 20067732 20067731 Frequency Response Over Temperature (AV = 10) Frequency Response for Various VG (AVMAX = 10) 20067707 20067708 Frequency Response for Various VG (AVMAX = 10) ( ± 2.5V) Small Signal Frequency Response for Various AVMAX 20067723 20067714 5 www.national.com LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. (Continued) Frequency Response for Various VG (AVMAX = 100) (Small Signal) Large Signal Frequency Response for Various AVMAX 20067724 20067729 Frequency Response for Various VG (AVMAX = 100) (Large Signal) IS vs. VS 20067730 20067750 IS vs. VS Input Bias Current vs. VS 20067751 www.national.com 20067752 6 = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. (Continued) AVMAX vs. VCM AVMAX vs. VCM 20067766 20067767 PSRR ± 5V PSRR ± 2.5V 20067704 20067703 CMRR ± 5V CMRR ± 2.5V 20067701 20067702 7 www.national.com LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. (Continued) AVMAX vs. Supply Voltage Supply Current vs. VCM 20067768 20067756 Output Offset Voltage vs. VCM (Typical Unit #1) Supply Current vs. VCM 20067758 20067757 Output Offset Voltage vs. VCM (Typical Unit #2) Output Offset Voltage vs. VCM (Typical Unit #3) 20067759 www.national.com 20067760 8 = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. (Continued) Feed through Isolation Gain Flatness and Linear Phase Deviation vs. VG 20067709 20067721 Gain Flatness Frequency vs. Gain (Note 14) Group Delay vs. Frequency 20067711 20067712 K Factor vs. RG Gain vs. VG Including Limits 20067739 20067705 9 www.national.com LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. (Continued) Gain vs. VG ( ± 5V) BW vs. RF 20067706 20067740 Gain vs. VG ( ± 2.5V) Output Offset Voltage vs. VG (Typical Unit #1) 20067753 20067713 Output Offset Voltage vs. VG (Typical Unit #2) Output Offset Voltage vs. VG (Typical Unit #3) 20067755 20067754 www.national.com 10 = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. (Continued) Output Offset Voltage vs. ± VS for various VG (Typical Unit# 1) Output Offset Voltage vs. ± VS for various VG (Typical Unit# 2) 20067762 20067761 Output Offset Voltage vs. ± VS for various VG (Typical Unit# 3) Noise vs. Frequency (AVMAX = 2) 20067763 20067725 Noise vs. Frequency (AVMAX = 10) Noise vs. Frequency (AVMAX = 100) 20067717 20067710 11 www.national.com LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. (Continued) −1dB Compression Output Voltage vs. Output Current 20067722 20067726 HD2 & HD3 vs. POUT THD vs. POUT 20067718 20067733 THD vs. POUT HD2 & HD3 vs. VG 20067728 20067719 www.national.com 12 = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. (Continued) THD vs. VG THD vs. VG 20067720 20067715 VG Bias Current vs. VG Step Response Plot 20067734 20067727 Step Response Plot Gain vs. VG Step 20067735 20067764 13 www.national.com LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM LMH6502 Typical Performance Characteristics Unless otherwise specified: VS = ±5V, 25˚C, VG = VGMAX, VCM = 0V, RF = 1kΩ, RG = 174Ω, both inputs terminated in 50Ω, RL = 100Ω, Typical values, results referred to device output. (Continued) Feedthrough from VG 20067765 CHOOSING RF & RG Maximum input amplitude and maximum gain are the two key specifications that determine component values in a LMH6502 application. The output stage op amp is a current-feedback type amplifier optimized for RF = 1kΩ. RG can then be computed as: Application Information THEORY OF OPERATION A simplified schematic is shown in Figure 1. +VIN and −VIN are buffered with closed loop voltage followers inducing a signal current in Rg proportional to (+VIN) - (−VIN), the differential input voltage. This current controls a current source which supplies two well-matched transistor, Q1 and Q2. The current flowing through Q2 is converted to the final output voltage using RF and the output amplifier, U1. By changing the fraction of the signal current "I" which flows through Q2, the gain is changed. This is done by changing the voltage applied differentially to the bases of Q1 and Q2. For example, with VG = 0V, Q1 conducts heavily and Q2 is off. With none of "I" flowing through RF, the LMH6502’s input to output gain is strongly attenuated. With VG = +2V, Q1 is off and the entire signal current flows through Q2 to RF producing maximum gain. With VG set to 1V, the bases of Q1 and Q2 are set to approximately the same voltage, Q1 and Q2 have the same collector currents - equal to one half of the signal current "I", thus the gain is approximately one half the maximum gain. (1) To determine whether the maximum input amplitude will overdrive the LMH6502, compute: (2) VDMAX = (RG + 3.0Ω) x 1.70mA the maximum differential input voltage for linear operation. If the maximum input amplitude exceeds the above VDMAX limit, then LMH6502 should either be moved to a location in the signal chain where input amplitudes are reduced, or the LMH6502 gain AVMAX should be reduced or the values for RG and RF should be increased. The overall system performance impact is different based on the choice made. If the input amplitude is reduced, re-compute the impact on signalto-noise ratio. If AVMAX is reduced, post LMH6502 amplifier gain, should be increased, or another gain stage added to make up for reduced system gain. To increase RG and RF, compute the lowest acceptable value for RG: (3) RG > 590 x VDMAX - 3Ω Operating with RG larger than this value insures linear operation of the input buffers. RF may be computed from selected RG and AVMAX: RF should be > = 1kΩ for overall best performance, however RF < 1kΩ can be implemented if necessary using a loop gain reducing resistor to ground on the inverting summing node of the output amplifier (see application note QA-13 for details). 20067741 ADJUSTING OFFSET Offset can be broken into two parts; an input-referred term and an output-referred term. The input-referred offset shows up as a variation in output voltage as VG is changed. This can be trimmed using the circuit in Figure 2 by placing a low frequency square wave (VLOW = 0V, VHIGH = 2V into VG with FIGURE 1. LMH6502 Block Diagram www.national.com 14 NOISE (Continued) Figure 3 describes the LMH6502’s output-referred spot noise density as a function of frequency with AVMAX = 10V/V. The plot includes all the noise contributing terms. However, with both inputs terminated in 50Ω, the input noise contribution is minimal. At AVMAX = 10V/V, the LMH6502 has a typical flatinput-referred spot noise density (ein) of 7.7nV/ band. For applications extending well into the flat-band region, the input RMS voltage noise can be determined from the following single-pole model: VIN = 0V, the input referred VOS term shows up as a small square wave riding a DC value. Adjust R10 to null the VOS square wave term to zero. After adjusting the input-referred offset, adjust R14 (with VIN = 0, VG = 0) until VOUT is zero. Finally, for inverting applications VIN may be applied to pin 6 and the offset adjustment to pin 3. These steps will minimize the output offset voltage. However, since the offset term itself varies with the gain setting, the correction is not perfect and some residual output offset will remain at in-between VG’s. Also, this offset trim does not improve output offset temperature coefficient. (5) 20067743 20067710 FIGURE 2. Nulling the output offset voltage FIGURE 3. Output Referred Voltage Noise vs. Frequency GAIN ACCURACY Defined as the actual gain compared against the theoretical gain at a certain VG (results expressed in dB). Theoretical gain is given by: CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION BOARD A good high frequency PCB layout including ground plane construction and power supply bypassing close to the package are critical to achieving full performance. The amplifier is sensitive to stray capacitance to ground at the I− input (pin 12); keep node trace area small. Shunt capacitance across the feedback resistor should not be used to compensate for this effect. For best performance at low maximum gains (AVMAX < 10) +RG and -RG connections should be treated in a similar fashion. Capacitance to ground should be minimized by removing the ground plane from under the body of RG.. Parasitic or load capacitance directly on the output (pin 10) degrades phase margin leading to frequency response peaking. The LMH6502 is fully stable when driving a 100Ω load. With reduced load (e.g. 1kΩ) there is a possibility of instability at very high frequencies beyond 400MHz especially with a capacitive load. When the LMH6502 is connected to a light load as such, it is recommended to add a snubber network to the output (e.g. 100Ω and 39pF in series tied between the LMH6502 output and ground). CL can also be isolated from the output by placing a small resistor in series with the output (pin 10). Component parasitics also influence high frequency results. Therefore it is recommended to use metal film resistors such as RN55D or leadless components such as surface mount devices. High profile sockets are not recommended. (4) Where K = 1.72 (nominal) & VC = 90mV @ room temperature. For a VG range, the value specified in the tables represents the worst case accuracy over the entire range. The "Typical" value would be the worst case difference between the "Typical Gain" and the "Theoretical gain". The "Max" value would be the worst case difference between the max/min gain limit and the "Theoretical gain". GAIN MATCHING Defined as the limit on gain variation at a certain VG (expressed in dB). Specified as "Max" only (no "Typical"). For a VG range, the value specified represents the worst case matching over the entire range. The "Max" value would be the worst case difference between the max/min gain limit and the typical gain. 15 www.national.com LMH6502 Application Information LMH6502 Application Information (Continued) OPERATING AT LOWER SUPPLY VOLTAGES National Semiconductor suggests the following evaluation boards as a guide for high frequency layout and as an aid in device testing and characterization: Device Package Evaluation Board Part Number LMH6502MA SOIC-14 CLC730033 LMH6502MT TSSOP-14 CLC730146 The LMH6502 is rated for operation down to 5V supplies (V+ -V−). There are some specifications shown for operation at ± 2.5V within the data sheet (i.e. Frequency Response, CMRR, PSRR, Gain vs. VG, etc.). Compared to ± 5V operation, at lower supplies: a) VG range shifts lower. Here are the approximate expressions for various VG voltages as a function of V+: The evaluation board is shipped when a device sample request is placed with National Semiconductor TABLE 1. VG Definition Based on V+ SINGLE SUPPLY OPERATION It is possible to operate the LMH6502 with a single supply. To do so, tie pin 11 (GND) to a potential about mid point between V+ and V−. Two examples are shown in Figure 4 & Figure 5. VG Definition Expression (V) VG_MIN Gain Cut-off 0.2 x V+ −1 VG_MID AVMAX/2 0.2 x V+ VG_MAX AVMAX 0.2 x V+ +1 b) VG_LIMIT (maximum permissible voltage on VG) is reduced. This is due to limitations within the device arising from transistor headroom. Beyond this limit, device performance will be affected (non-destructive). This could reveal itself as premature high frequency response rolloff. With ± 2.5V supplies, VG_LIMIT is below 1.1V whereas VG = 1.5V is needed to get maximum gain. This means that operating under these conditions has reduced the maximum permissible voltage on VG to a level below what is needed to get Max gain. If supply voltages are asymmetrical with V+ being lower, further "pinching" of VG range could result; for example, with V+ = 2V, and V− = −3V, VG_LIMIT = 0.40V which results in maximum gain being 2.5dB less than what would be expected when VS is higher. c) "Max_gain" reduces. There is an intrinsic reduction in max gain when the total supply voltage is reduced (see Typical Performance Characteristics plots for Gain vs. VG (VS = ± 2.5V). In addition, there is the more drastic mechanism described in "b" above. Beyond VG_LIMIT, high frequency response is also effected. 20067746 FIGURE 4. AC Coupled Single Supply VGA Application Circuits AGC LOOP Figure 6 shows a typical AGC circuit. The LMH6502 is followed up with a LMH6714 for higher overall gain. The output of the LMH6714 is rectified and fed to an inverting integrator using a LMH6657 (wideband voltage feedback op amp). When the output voltage, VOUT, is too large the integrator output voltage ramps down reducing the net gain of the LMH6502 and VOUT. If the output voltage is too small, the integrator ramps up increasing the net gain and the output voltage. Actual output level is set with R1. To prevent shifts in DC output voltage with DC changes in input signal level, trim pot R2 is provided. AGC circuits are always limited in the range of input signals over which constant output level can be maintained. In this circuit, we would expect that reasonable AGC action could be maintained for at least 40dB. In practice, rectifier dynamic range limits reduce this slightly. 20067747 FIGURE 5. Transformer Coupled Single Supply VGA www.national.com 16 LMH6502 Application Circuits (Continued) 20067748 FIGURE 6. Automatic Gain Control (AGC) Loop FREQUENCY SHAPING Frequency Shaping Frequency shaping and bandwidth extension of the LMH6502 can be accomplished using parallel networks connected across the RG ports. The network shown in the Figure 7 schematic will effectively extend the LMH6502’s bandwidth. 20067749 FIGURE 7. Frequency Shaping 17 www.national.com LMH6502 Physical Dimensions inches (millimeters) unless otherwise noted 14-Pin SOIC NS Package Number M14A 14-Pin TSSOP NS Package Number MTC14 www.national.com 18 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. National Semiconductor Americas Customer Support Center Email: [email protected] Tel: 1-800-272-9959 www.national.com National Semiconductor Europe Customer Support Center Fax: +49 (0) 180-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 National Semiconductor Asia Pacific Customer Support Center Email: [email protected] National Semiconductor Japan Customer Support Center Fax: 81-3-5639-7507 Email: [email protected] Tel: 81-3-5639-7560 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. LMH6502 Wideband, Low Power, Linear-in-dB Variable Gain Amplifier Notes