HS-82C12RH TM Data Sheet August 2000 Radiation Hardened 8-Bit Input/Output Port The Intersil HS-82C12RH is a radiation hardened 8-bit input/output port designed for use with the HS-80C85RH radiation hardened microprocessor. It is manufactured using a self-aligned, junction-isolated EPI-CMOS process and features three-state output buffers and device selection and control logic. A service request flip-flop is included for the generation and control of interrupts to the microprocessor. The device can be used in implement many of the peripheral and input/output functions of a microcomputer system. The HS-82C12RH is pinout- and function- compatible with industry-standard 8212 devices. File Number 3041.3 Features • Electrically Screened to SMD # 5962-95818 • QML Qualified per MIL-PRF-38535 Requirements • Radiation Performance - Hardened EPI-CMOS Process - Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max) - Transient Upset . . . . . . . . . . . . . . . . . > 1 x 108 rad(Si)/s - Latch-Up Immune • Low Power Dissipation • High Noise Immunity • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. • Low Input Load Current Detailed Electrical Specifications for these devices are contained in SMD 5962-95818. A “hot-link” is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp • Asynchronous Register Clear • 8-Bit Data Register and Buffer • Service Request Flip-Flop for Interrupt Generation • Three-State Outputs • Bus-Compatible with HS-80C85RH CPU Ordering Information ORDERING NUMBER • Electrically Equivalent to Sandia SA3026 INTERNAL MKT. NUMBER TEMP. RANGE (oC) • Military Temperature Range . . . . . . . . . . . -55oC to 125oC Functional Diagram 5962R9581801QJC HS1-82C12RH-8 -55 to 125 5962R9581801QXC HS9-82C12RH-8 -55 to 125 DS1 5962R9581801V9A HS0-82C12RH-Q 25 DS2 5962R9581801VJC HS1-82C12RH-Q -55 to 125 5962R9581801VXC HS9-82C12RH-Q -55 to 125 CONTROL AND DEVICE SELECT LOGIC STB CLR SERVICE REQUEST F.F. 2 INT 3 MD DI0-7 DATA LATCH AND BUFFER (8) DO0-7 Pin Description PIN DI0-DI7 1 DESCRIPTION Data In DO0-DO7 Data Out DS1, DS2 Device Select MD Mode STB Strobe INT Interrupt CLR Clear CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HS-82C12RH Pinouts 24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T24 TOP VIEW DS1 1 24 VDD MD 2 23 INT DI0 3 22 DI7 DO0 4 21 DO7 DI1 5 20 DI6 DO1 6 19 DO6 DI2 7 18 DI5 DO2 8 17 DO5 DI3 9 16 DI4 DO3 10 15 DO4 STB 11 14 CLR GND 12 13 DS2 24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP4-F24 TOP VIEW 2 DS1 1 MD 2 DI0 3 DO0 4 DI1 5 DO1 DI2 6 DO2 8 DI3 DO3 9 STB GND 11 7 10 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD INT DI7 DO7 DI6 DO6 DI5 DO5 DI4 DO4 CLR DS2 HS-82C12RH Timing Waveforms (DS, • DS2) tE 0.5VDD tD VOH OUTPUT VOL 0.5VDD FIGURE 1. READ TIMING DATA tPW MD OR (DS, • DS2) tH tWE OUTPUT FIGURE 2. WRITE TIMING DATA tSET tH STB OR (DS, • DS2) tPD OUTPUT FIGURE 3. DATA SETUP, HOLD, PROPAGATION DELAY TIMING tPW STB tPW (DS, • DS2) tR tS INT FIGURE 4. INTERRUPT TIMING tPW CLR tC DO FIGURE 5. CLEAR TIMING 3 HS-82C12RH Functional Description Data Latch Mode The data latch is comprised of eight “D” type flip-flops. The output of each flip-flop will follow the corresponding data input (DI0 - DI7) when the clock (C) is high. The clock input is level sensitive and the data becomes latched when the clock returns low. the mode input (MD) is used to control the state of the output buffer and to determine the source of the data latch clock (C). When MD is high, the output buffers are enabled and the source of the data latch clock (C) is the device select logic (DS1 • DS2). An asynchronous reset (CLR) is used to clear the latched data. Since the clock (C) overrides the reset (CLR), the data must be in the latched state in order to clear the flip-flops. If the data is not latched (i.e. clock is high) when CLR goes low, then the Q outputs of the data latch will continue to follow the data input, overriding the reset signal. When MD is low, the state of the output buffer is controlled by the device select logic (DS1 • DS2) and the source of the data latch clock is the strobe (STB) input. Output Buffer Three-state buffers are used to provide output drive for the data latch. A high level on the “output buffer enable” control line enables the buffer outputs. When “output buffer enable” is low the buffer outputs are forced to the high-impedance state. Device Select Logic The inputs DS1 and DS2 are used for device selection. When DS1 is low and DS2 is high, the device is selected. The output buffers are enabled and the service request flipflop is asynchronously cleared when the device is selected. 4 Strobe The strobe input (STB) is used as the data latch clock (C) when the mode input (MD) is low. The service request flipflop is synchronously set on the negative going edge of STB. Service Request Flip-Flop The service request flip-flop is to generate interrupts to microcomputer systems. It is negative edge triggered and asynchronously cleared (reset). The output of the service request flip-flop is AND-gated with the device select logic (DS1 • DS2). The output of the AND gate is the active low interrupt (INT) signal. HS-82C12RH Logic Diagram INT DEVICE DS1 23 DATA OUT ENABLE SELECT 13 LATCH RESET DI0 DS2 S STB D E 3 D Q C Q DO0 Q Q TSB Q Q TSB Q Q TSB Q Q TSB Q Q TSB Q Q TSB Q Q TSB Q Q TSB 4 R SERVICE REQUEST FLIP-FLOP 11 DI1 D E 5 CLR DO1 6 R 14 DI2 D E 7 DO2 8 R LATCH CLOCK DI3 D E MD 9 2 DO3 10 R DI4 D E 16 DO4 15 R DI5 D E 18 DO5 17 R DI6 D E 20 DO6 19 R DI7 D E 22 DO7 21 R TABLE 1. DATA OUT STB MD DS1 • DS2 TABLE 2. INT DATA OUT EQUALS 0 0 0 High Z State 1 0 0 High Z State 0 1 0 Data Latch 1 1 0 Data Latch 0 0 1 Data Latch 1 0 1 Data In 0 1 1 Data In 1 1 1 Data In 5 CLR DS1 • DS2 STB (NOTE) Q INT 0 RESET 0 0 0 1 1 0 0 0 1 1 0 1 0 1 1 RESET 0 0 0 1 0 0 0 1 NOTE: Internal Service Request Flip-Flop HS-82C12RH Die Characteristics DIE DIMENSIONS: Substrate: 90 mils x 76 mils x 14 mils ±1 mil Radiation Hardened Silicon Gate, Dielectric Isolation INTERFACE MATERIALS: Backside Finish: Glassivation: Silicon Type: SiO2 Thickness: 8kÅ ±1kÅ ASSEMBLY RELATED INFORMATION: Top Metallization: Substrate Potential: Type: AlSi Thickness: 11kÅ ±2kÅ Unbiased (DI) Metallization Mask Layout (23) INT (24) VDD (1) DS1 (2) MD (3) DI0 HS-82C12RH (22) DI7 DO0 (4) (21) DO7 DI1 (5) (20) DI6 DO1 (6) (19) DO6 DI2 (7) (18) DI5 DO2 (8) (17) DO5 DI3 (9) (16) DI4 CLR (14) DS2 (13) GND (12) STB (11) DO3 (10) (15) DO4 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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