ON MC14569BDT Programmable divide-by-n dual 4-bit binary/bcd down counter Datasheet

MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable divide–by–N dual 4–bit binary
or BCD down counter constructed with MOS P–channel and
N–channel enhancement mode devices (complementary MOS) in a
monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase–locked loops,
and other frequency division applications requiring low power
dissipation and/or high noise immunity.
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MARKING
DIAGRAMS
16
PDIP–16
P SUFFIX
CASE 648
• Speed–up Circuitry for Zero Detection
• Each 4–Bit Counter Can Divide Independently in BCD or Binary
•
•
•
MC14569BCP
AWLYYWW
1
Mode
Can be Cascaded With MC14526B for
Frequency Synthesizer Applications
All Outputs are Buffered
Schmitt Triggered Clock Conditioning
16
TSSOP–16
DT SUFFIX
CASE 948F
14
569B
ALYW
1
16
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Parameter
Symbol
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Value
Unit
– 0.5 to +18.0
V
– 0.5 to VDD + 0.5
V
±10
mA
PD
Power Dissipation,
per Package (Note 2.)
500
mW
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
1. Maximum Ratings are those values beyond which damage to the device
may occur.
2. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
v
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14569BCP
PDIP–16
2000/Box
MC14569BDT
TSSOP–16
96/Rail
MC14569BDW
SOIC–16
47/Rail
MC14569BDWR2
SOIC–16
1000/Tape & Reel
v
 Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
AWLYYWW
1
Input or Output Current
(DC or Transient) per Pin
Iin, Iout
14569B
SOIC–16
DW SUFFIX
CASE 751G
1
Publication Order Number:
MC14569B/D
MC14569B
PIN ASSIGNMENT
ZERO
DETECT
CTL1
1
16
VDD
2
15
Q
P0
3
14
P7
P1
4
13
P6
P2
5
12
P5
P3
CASCADE
FEEDBACK
VSS
6
11
P4
7
10
CTL2
8
9
CLOCK
BLOCK DIAGRAM
P0 P1 P2 P3
CTL = Low for Binary Count
3
CTL = High for BCD Count
CLOCK
9
CASCADE 7
FEEDBACK
4
5
CTL1 CTL2
6
2
10
P4 P5 P6 P7
11 12 13
CLOCK
LOAD
BINARY/BCD
COUNTER #1
ZERO DETECT ENCODER
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2
14
BINARY/BCD
COUNTER #2
VDD = PIN 16
VSS = PIN 8
15
Q
1 ZERO
DETECT
MC14569B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (3.)
Max
Min
Max
Unit
Output Voltage
Vin = VDD or 0
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
Vin = 0 or VDD
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
(VO = 0.5 or 4.5 Vdc) “1” Level
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
IOH
Source
Sink
Total Supply Current (4.) (5.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
Vdc
mAdc
IT = (0.58 µA/kHz) f + IDD
IT = (1.20 µA/kHz) f + IDD
IT = (1.95 µA/kHz) f + IDD
3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
4. The formulas given are for the typical characteristics only at 25_C.
5. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
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3
µAdc
MC14569B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
All Types
VDD
Vdc
Min
Typ (6.)
Max
Unit
Output Rise Time
tTLH
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Output Fall Time
tTHL
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Turn–On Delay Time
Zero Detect Output
tPLH
5.0
10
15
—
—
—
420
175
125
700
300
250
5.0
10
15
—
—
—
675
285
200
1200
500
400
5.0
10
15
—
—
—
380
150
100
600
300
200
5.0
10
15
—
—
—
530
225
155
1000
400
300
ns
tWH
5.0
10
15
300
150
115
100
45
30
—
—
—
ns
fcl
5.0
10
15
—
—
—
3.5
9.5
13.0
2.1
5.1
7.8
MHz
tTLH, tTHL
5.0
10
15
ns
Q Output
Turn–Off Delay Time
Zero Detect Output
ns
tPHL
Q Output
Clock Pulse Width
Clock Pulse Frequency
Clock Pulse Rise and Fall Time
ns
NO LIMIT
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
µs
MC14569B
SWITCHING WAVEFORMS
20 ns
20 ns
CLOCK
10%
90%
50%
fin = fmax
tWH
tPHL
tPLH
Q
10%
90%
50%
tTLH
tTHL
Figure 1.
20 ns
20 ns
CLOCK
10%
90%
50%
tWH
tPHL
tPLH
90%
ZERO DETECT
10%
tTLH
tTHL
Figure 2.
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5
MC14569B
PIN DESCRIPTIONS
INPUTS
CONTROLS
P0, P1, P2, P3 (Pins 3, 4, 5, 6) — Preset Inputs.
Programmable inputs for the least significant counter. May
be binary or BCD depending on the control input.
P4, P5, P6, P7 (Pins 11, 12, 13, 14) — Preset Inputs.
Programmable inputs for the most significant counter. May
be binary or BCD depending on the control input.
Clock (Pin 9) — Preset data is decremented by one on
each positive transition of this signal.
Cascade Feedback (Pin 7) — This pin is normally set
high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to
Table 1 for output characteristics.
CTL1 (Pin 2) — This pin controls the counting mode of
the least significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
CTL2 (Pin 10) — This pin controls the counting mode of
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
OUTPUTS
Zero Detect (Pin 1) — This output is normally low and
goes high for one clock cycle when the counter has
decremented to zero.
Q (Pin 15) — Output of the last stage of the most
significant counter. This output will be inactive unless the
preset input P7 has been set high.
SUPPLY PINS
VSS (Pin 18) — Negative Supply Voltage. This pin is
usually connected to ground.
VDD (Pin 16) — Positive Supply Voltage. This pin is
connected to a positive supply voltage ranging from 3.0
volts to 18.0 volts.
OPERATING CHARACTERISTICS
The MC14569B is a programmable divide–by–N dual
4–bit down counter. This counter may be programmed (i.e.,
preset) in BCD or binary code through inputs P0 to P7. For
each counter, the counting sequence may be chosen
independently by applying a high (for BCD count) or a low
(for binary count) to the control inputs CTL1 and CTL2.
The divide ratio N (N being the value programmed on the
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a
division ratio of one is not possible. After N clock cycles,
one pulse appears on the Zero Detect output. (See Timing
Diagram.) The Q output is the output of the last stage of the
most significant counter (See Tables 1 through 5, Mode
Controls.)
When cascading the MC14569B to the MC14526B, the
Cascade Feedback input, Q, and Zero Detect outputs must
be respectively connected to “0”, Clock, and Load of the
following counter. If the MC14569B is used alone, Cascade
Feedback must be connected to VDD.
18
CL = 50 pF
f, FREQUENCY (MHz), TYPICAL
16
14
12
VDD = 15 V
10
8.0
10 V
6.0
4.0
5.0 V
2.0
0
– 40
– 20
0
+ 20
+ 40
+ 60
TA, AMBIENT TEMPERATURE (°C)
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6
+ 80
+ 100
MC14569B
Table 1. Mode Controls (Cascade Feedback = Low)
Counter Control Values
Divide Ratio
CTL1
CTL2
Zero Detect
Q
0
0
1
1
0
1
0
1
256
160
160
100
256
160
160
100
NOTE: Data Preset Inputs (P0–P7) are “Don’t Cares” while Cascade Feedback is
Low.
Table 2. Mode Controls (CTL1 = Low, CTL2 = Low, Cascade Feedback = High)
Divide Ratio
Preset Inputs
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
256
X
2
3
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
15
16
0
0
1
0
0
0
0
0
32
0
1
0
0
0
0
0
0
64
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
1
1
27
128
26
64
Q
Comments
Max Count
Illegal State
Min Count
127
128
256
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
128
0
0
0
136
136
1
1
1
1
1
1
255
255
25
32
24
16
23
8
22
4
21
2
20
1
Counter #2
Binary
Counter #1
Binary
Q Output Active
Bit Value
Counting
Sequence
X = No Output (Always Low)
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7
MC14569B
Table 3. Mode Controls (CTL1 = High, CTL2 = Low, Cascade Feedback = High)
Preset Inputs
Divide Ratio
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
160
X
2
3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
9
10
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
19
20
0
0
1
1
0
0
0
0
30
0
1
0
0
0
0
0
0
40
0
1
0
1
0
0
0
0
50
0
1
1
0
0
0
0
0
60
0
1
1
1
0
0
0
0
70
1
0
0
0
0
0
0
0
1
0
0
1
0
1
1
Q
Comments
Max Count
Illegal State
Min Count
80
160
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
80
0
0
0
90
90
1
1
0
0
0
0
150
150
1
1
1
1
1
0
0
1
159
159
80
40
20
10
8
4
2
1
Counter #2
Binary
Counter #1
BCD
Q Output Active
Bit Value
Counting
Sequence
X = No Output (Always Low)
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8
MC14569B
Table 4. Mode Controls (CTL1 = Low, CTL2 = High, Cascade Feedback = High)
Preset Values
Divide Ratio
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
160
X
2
3
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
15
16
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
31
32
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
Q
Comments
Max Count
Illegal State
Min Count
48
160
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
64
X
0
1
0
0
0
0
80
X
0
1
1
1
0
0
0
0
112
X
1
0
0
0
0
0
0
0
128
128
1
0
0
1
0
0
0
0
144
144
1
0
0
1
1
1
1
1
159
159
27
128
26
64
25
32
24
16
23
8
22
4
21
2
20
1
Counter #2
BCD
Counter #1
Binary
Q Output Active
Bit Value
Counting
Sequence
X = No Output (Always Low)
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MC14569B
Table 5. Mode Controls (CTL1 = High, CTL2 = High, Cascade Feedback = High)
Preset Values
Divide Ratio
P7
P6
P5
P4
P3
P2
P1
P0
Zero
Detect
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
100
X
2
3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
9
10
0
0
1
1
0
0
0
0
30
0
1
0
0
0
0
0
0
40
0
1
0
1
0
0
0
0
50
0
1
1
1
0
0
0
0
70
1
0
0
0
0
0
0
0
1
0
0
1
0
1
0
80
40
Q
Comments
Max Count
illegal state
Min Count
80
100
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
80
0
0
0
90
90
0
1
1
0
0
1
99
99
20
10
8
4
2
1
Counter #2
BCD
Q Output Active
Bit Value
Counter #1
BCD
Counting
Sequence
X = No Output (Always Low)
TIMING DIAGRAM MC14569B
CLOCK
1
2
3
4
5
6
7
8
DIVIDE
BY 2
ZERO
DETECT
OUTPUT
DIVIDE
BY 3
DIVIDE
BY 4
DIVIDE
BY 12
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10
9
10
11
12
13
14
15
16
MC14569B
LOGIC DIAGRAM
CTL1
2
DP Q
D
DP Q
P0
P1
P2
3
D
DP Q
4
5
P3
PE
C
D
PE
C
DP Q
PE
D
C
DP Q
D
6
PE
C
DP Q
D
DP Q
D
DP Q
D
IU
PE
C
PE
C
PE
C
PE
C
VDD
CASCADE 7
FEEDBACK
CLOCK
VDD
9
1
ZERO
DETECT
P4
P5
P6
P7
CTL2
11
12
13
14
DP D
C
Q
PE
DP D
C
Q
PE
DP D
C
Q
PE
DP D
Q
PE
C
15
10
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11
MC14569B
TYPICAL APPLICATIONS
fin
C
CF
Q
C
MC14569B
ZERO DETECT
PE
CF
MC14522B
OR
MC14526B
Q4
C
“0”
PE
DP0 – – – – – – DP3
CF
MC14522B
OR
MC14526B
Q4
Q1/C2
“0”
PE
MC14568B
DP0 – – – – – – DP3
“0”
DP0 – – – – – – DP3
LSD
fout
MSD
Figure 3. Cascading MC14568B and MC14522B or MC14526B with MC14569B
(40 kHz)
PCin
C1
CT1
VSS
“0”
fout
VCO
PCout
G
VSS
F
VSS
(144 – 146 MHz)
Q1/C2
PE
VDD
DP0 – – – – DP3
MC14011
CF
Q
MC14569B
C
ZERO DETECT
MIXER
2k
2M
CRYSTAL
OSCILLATOR
Frequencies shown in parenthesis are given as an example
(143.5 MHz)
Figure 4. Frequency Synthesizer with MC14568B and MC14569B Using a Mixer
(Channel Spacing 10 kHz)
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12
MC14569B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
http://onsemi.com
13
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14569B
PACKAGE DIMENSIONS
TSSOP–16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F–01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
K
ÉÉ
ÇÇÇ
ÇÇÇ
ÉÉ
K1
2X
L/2
16
9
J1
B
–U–
L
SECTION N–N
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
0.15 (0.006) T U
S
A
–V–
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
F
DETAIL E
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
H
D
DETAIL E
G
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14
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MC14569B
PACKAGE DIMENSIONS
SOIC–16
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–03
ISSUE B
A
D
9
1
8
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
h X 45 _
E
0.25
16X
M
T A
S
B
S
14X
e
L
A
0.25
B
B
A1
H
8X
M
B
M
16
q
SEATING
PLANE
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
C
http://onsemi.com
15
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
10.15
10.45
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC14569B
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16
MC14569B/D