Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD19534Q5A SLPS483 – MAY 2014 CSD19534Q5A 100 V N-Channel NexFET™ Power MOSFETs 1 Features • • • • • • • Product Summary Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb-Free Terminal Plating RoHS Compliant Halogen Free SON 5 mm × 6 mm Plastic Package 1 TA = 25°C TYPICAL VALUE Drain-to-Source Voltage 100 V Qg Gate Charge Total (10 V) 17 nC Qgd Gate Charge Gate to Drain 3.2 RDS(on) Drain-to-Source On Resistance VGS(th) Threshold Voltage Primary Side Telecom Motor Control 3 Description This 100 V, 12.6 mΩ, SON 5 mm x 6mm NexFET™ power MOSFET is designed to minimize losses in power conversion applications. 14.1 mΩ VGS = 10 V 12.6 mΩ 2.8 Top View S Device Media Qty Package Ship 13-Inch Reel 2500 CSD19534Q5AT 7-Inch Reel 250 SON 5 x 6 mm Plastic Package Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings 8 1 7 2 D D VALUE UNIT VDS Drain-to-Source Voltage 100 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 50 Continuous Drain Current (Silicon limited), TC = 25°C 44 ID (1) S 6 3 D IDM D G V CSD19534Q5A TA = 25°C S nC VGS = 6 V . Ordering Information(1) 2 Applications • • UNIT VDS 5 4 D PD P0093-01 A Continuous Drain Current 10 Pulsed Drain Current(2) 137 Power Dissipation(1) 3.2 Power Dissipation, TC = 25°C 63 –55 to 150 °C 55 mJ . TJ, Tstg Operating Junction and Storage Temperature Range . EAS Avalanche Energy, single pulse ID = 33 A, L = 0.1 mH, RG = 25 Ω A W (1) Typical RθJA = 40°C/W on a 1-inch2, 2-oz. Cu pad on a 0.06inch thick FR4 PCB. (2) Max RθJC = 2.0°C/W, pulse duration ≤100 μs, duty cycle ≤1% RDS(on) vs VGS Gate Charge 10 TC = 25°C, I D = 10A TC = 125°C, I D = 10A 36 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 40 32 28 24 20 16 12 8 4 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 10A VDS = 50V 9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 Qg - Gate Charge (nC) 14 16 18 G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD19534Q5A SLPS483 – MAY 2014 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 1 1 1 2 3 7 7.1 7.2 7.3 7.4 5.1 Electrical Characteristics.......................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Mechanical, Packaging, and Orderable Information ............................................................. 8 Device and Documentation Support.................... 7 Q5A Package Dimensions ........................................ 9 Recommended PCB Pattern................................... 10 Recommended Stencil Opening ............................. 11 Q5A Tape and Reel Information ............................. 11 4 Revision History 2 DATE REVISION NOTES May 2014 * Initial release. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A CSD19534Q5A www.ti.com SLPS483 – MAY 2014 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 80 V 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On Resistance gfs Transconductance 100 2.4 V 2.8 3.4 V VGS = 6 V, ID = 10 A 14.1 17.6 mΩ VGS = 10 V, ID = 10 A 12.6 15.1 mΩ VDS = 10 V, ID = 10 A 47 S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance 1290 1680 pF 257 330 pF Crss RG Reverse Transfer Capacitance 5.7 7.4 pF Series Gate Resistance 1.1 2.2 Ω Qg Gate Charge Total (10 V) 17 22 nC Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0 V, VDS = 50 V, f = 1 MHz VDS = 50 V, ID = 10 A VDS = 50 V, VGS = 0 V VDS = 50 V, VGS = 10 V, IDS = 10 A, RG = 0 Ω 3.2 nC 5.1 nC 3.3 nC 44 nC 9 ns 14 ns 20 ns 6 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage ISD = 10 A, VGS = 0 V 0.8 1.0 V Qrr Reverse Recovery Charge nC Reverse Recovery Time VDS= 50 V, IF = 10 A, di/dt = 300 A/μs 134 trr 53 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) PARAMETER (1) RθJC Junction-to-Case Thermal Resistance RθJA Junction-to-Ambient Thermal Resistance (1) (2) (1) (2) MIN TYP MAX 2.0 50 UNIT °C/W RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A 3 CSD19534Q5A SLPS483 – MAY 2014 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick) Cu. Source Max RθJA = 115°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A CSD19534Q5A www.ti.com SLPS483 – MAY 2014 Typical MOSFET Characteristics (continued) 100 100 90 90 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) (TA = 25°C unless otherwise stated) 80 70 60 50 40 30 VGS =10V VGS =8V VGS =6V 20 10 0 0 0.4 0.8 1.2 1.6 2 VDS - Drain-to-Source Voltage (V) 2.4 80 70 60 50 40 30 10 0 2.8 TC = 125°C TC = 25°C TC = −55°C 20 0 1 2 3 4 VGS - Gate-to-Source Voltage (V) G001 5 6 G001 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 100000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 9 8 C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 10000 1000 100 2 10 1 0 0 2 4 ID = 10 A 6 8 10 12 Qg - Gate Charge (nC) 14 16 1 18 0 10 20 G001 90 100 G001 VDS = 50 V Figure 4. Gate Charge Figure 5. Capacitance 3.4 40 RDS(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) 30 40 50 60 70 80 VDS - Drain-to-Source Voltage (V) 3.2 3 2.8 2.6 2.4 2.2 2 1.8 1.6 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C, I D = 10A TC = 125°C, I D = 10A 36 32 28 24 20 16 12 8 4 0 0 2 G001 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A 5 CSD19534Q5A SLPS483 – MAY 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 2 100 VGS = 6V VGS = 10V ISD − Source-to-Drain Current (A) Normalized On-State Resistance 2.2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 1 G001 ID = 10 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 1000 100 10us 100us 1ms 10ms DC 100 10 1 0.1 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) Single Pulse TC = 25ºC TC = 125ºC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 5000 1000 10 0.01 0.1 TAV - Time in Avalanche (mS) G001 1 G001 Max RθJC = 2.0°C/W IDS - Drain- to- Source Current (A) Figure 10. Maximum Safe Operating Area 60 55 50 45 40 35 30 25 20 15 10 5 0 −50 −25 0 Figure 11. Single Pulse Unclamped Inductive Switching 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A CSD19534Q5A www.ti.com SLPS483 – MAY 2014 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A 7 CSD19534Q5A SLPS483 – MAY 2014 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A CSD19534Q5A www.ti.com SLPS483 – MAY 2014 2 3 4 5 4 5 6 3 6 7 2 7 1 8 1 8 7.1 Q5A Package Dimensions DIM MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 E3 3.03 3.13 3.23 e 1.17 1.27 1.37 e1 0.27 0.37 0.47 e2 0.15 0.25 0.35 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° 12° Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A 9 CSD19534Q5A SLPS483 – MAY 2014 www.ti.com 7.2 Recommended PCB Pattern F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 DIM MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 10 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A CSD19534Q5A www.ti.com SLPS483 – MAY 2014 7.3 Recommended Stencil Opening (0.020) 8x 0.500 (0.020) 0.500 5 4 0.500 (0.020) 8x 1.585 (0.062) 1.235 (0.049) (0.024) 0.620 (0.170) 4.310 0.385 (0.015) 1.270 (0.050) 1 8 1.570 (0.062) 4x 0.615 (0.024) 1.105 (0.044) 3.020 (0.119) K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.4 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD19534Q5A 11 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) CSD19534Q5A ACTIVE VSONP DQJ 8 2500 Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM CSD19534Q5AT ACTIVE VSONP DQJ 8 250 Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -55 to 150 CSD19534 CSD19534 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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