ON NCP2704FCCT1G Audio management integrated circuit Datasheet

NCP2704
Audio Management
Integrated Circuit with
2.8 W Class D and LongPlay
True Ground Headphone
Amplifier
The NCP2704 is a cost effective audio subsystem designed for
portable applications such as cellular phones and portable media
player. It has been designed to cover the power audio requirements in
portable equipment: including a high fidelity Class D speaker
amplifier and a Class G equivalent LongPlay true ground headphone
amplifier. This patented headphone amplifier circuitry allows the
removal of the bulky output capacitors and minimize audio playback
current consumption with minimum external components. In addition
the user can set the output swing to have enough output dynamic even
when a damping resistor is added.
Through a flexible I2C interface, NCP2704 can support both single
ended and differential types of analog input signal. In both cases, it
offers a zero pop noise signature. The same interface allows a user
defined architecture with an input control, highly accurate gain setting
capability from −60 dB to +12 dB and output control. In addition
NCP2704 offers the possibility to reduce the EMI perturbation by
lowering the rise and fall times of the Class D outputs (software
programmable). The Loudspeaker also amplifier includes an AGC
which performs two functions: limiter and non−clipping.
Features
• Flexible MUX Capability and Volume Control
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MARKING
DIAGRAM
NCP2704
AYWW
G
A1
20 PIN CSP
FC SUFFIX
CASE 499BH
NCP2704 = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
PINOUT
A1
A2
A3
A4
A5
IN2B
IN1B
HSR
HSL
PVM
B1
B2
B3
B4
B5
Separated Mixer Control Between Louspeaker and Headset
C1N
GND
I2CEN
IN2A
IN1A
♦ Support Either Differential or Single−ended Input
C1
C2
C3
C4
C5
High Sound Quality
SCL
NC
GND
SDA
GND
♦ −100 dB PSRR on Headphone Amplifier
D1
D2
D3
D4
D5
♦ −80 dB PSRR on Loudspeaker Amplifier
LPN
PVDD
LPP HSVDD C1P
♦ 0.02% THD+N at 1 kHz on Headset Amplifier
♦ 0.1% THD+N at 1 kHz on Loudspeaker Amplifier
Low EMI Filterless Class D Loudspeaker Amplifier, Programmable
High Efficiency or Low EMI Mode
Programmable AGC: Non−Clipping or Power Limit (Loudspeaker
ORDERING INFORMATION
See detailed ordering and shipping information in the package
Output)
section on page 27 of this data sheet.
Long Play True Ground Headphone Amplifier,
• 20−Bumpdimensions
Chip Scale Package (2.5 x 2.0 mm)
Programmable Output Swing (Up to 5 Vpp)
• This is a Pb−Free Device
I2C Control
Typical Applications
Software Shutdown
• Cellular Phones
No Pop and Click Noise
• Portable Media Player
TDMA Noise Free
Thermal and Short−Circuit Protection
♦
•
•
•
•
•
•
•
•
•
© Semiconductor Components Industries, LLC, 2010
November, 2010 − Rev. 0
1
Publication Order Number:
NCP2704/D
NCP2704
PVDD
IN2A
IN2B
INPUT1
PROCESSING
0 dB to 20 dB
Loudspeaker
Volume
− 60 dB to
+12 dB
IN1A
IN1B
INPUT2 PROCESSING
0 dB to 20 dB
GND
LPP
CLASS D
LOUDSPEAKER
AMPLIFIER with AGC
+12 dB
LPN
HSL
MIXER / MUX
Headset Left
Volume
− 60 dB to
+12dB
HSR
Headset Right
Volume
− 60 dB to
+12dB
I2CEN
POWER SUPPLY CONVERSION
SCL
SDA
VRP
I 2C
INTERFACE
VRM
PVM
GND
HSVDD
GND
Figure 1. Simplified Block Diagram
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C1N
C1P
8
NCP2704
PIN FUNCTION DESCRIPTION
Pin
Pin Name
Type
B2
IN1A
Input
First audio input. It is paired with IN1B. This pin is configured for single ended or differential
types of input, pending on the I2C programming.
Description
A2
IN1B
Input
First audio input. It is paired with IN1A. This pin is configured for single ended or differential
types of input, pending on the I2C programming.
B1
IN2A
Input
Second audio input. It is paired with IN2B. This pin is configured for single ended or differential
types of input, pending on the I2C programming.
A1
IN2B
Input
Second audio input. It is paired with IN2A. This pin is configured for single ended or differential
types of input, pending on the I2C programming.
C3
SCL
Input
Clock input for the I2C bus.
C4
SDA
Input /
Output
Data input for the I2C bus.
B3
GND
Power
Analog ground.
D4
HSVDD
Power
Power supply dedicated to the charge pump and the headset amplifier. A low ESR ceramic
capacitor to ground is required.
C5
GND
Power
Power ground dedicated to the charge pump and the headset amplifier.
C2
GND
Power
Power ground dedicated to the loudspeaker and the receiver.
A3
HSR
Output
Headset amplifier right output.
A4
HSL
Output
Headset amplifier left output.
D1
LPN
Output
Loudspeaker negative output.
D3
LPP
Output
Loudspeaker positive output.
D2
PVDD
Power
Power supply. A low ESR ceramic capacitor to ground is required.
B4
I2CEN
Input
D5
C1P
Output
Charge pump flying capacitor positive capacitor.
B5
C1N
Output
Charge pump flying capacitor negative capacitor.
A5
PVM
Output
Charge pump output. This is the symmetrical voltage of the power supply applied on the
HSVBAT. A low ESR ceramic capacitor to ground is required.
C1
NC
−
I2C enable pin
Not connected pin
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NCP2704
MAXIMUM RATINGS
Symbol
Value
Unit
PVDD : Power Supply Voltage (Note 1)
Rating
VIN
−0.3 to + 6.0
V
HSVDD (Note 1)
VIN
−0.3 to + 4.5
V
Other Pins (Note 1)
VYY
−0.3 to PVDD + 0.3
V
Human Body Model (HBM) ESD Rating are (Note 2)
ESD HBM
2000
V
Machine Model (MM) ESD Rating are (Note 2)
ESD MM
200
V
RqJC
Note 7
°C/W
TA
−40 to +85
°C
CSP 2.5 x 2 mm package (Notes 6 and 7)
Thermal Resistance Junction−to−Case
Operating Ambient Temperature Range
Operating Junction Temperature Range
TJ
−40 to +125
°C
Maximum Junction Temperature (Note 6)
TJMAX
+150
°C
Storage Temperature Range
TSTG
−65 to +150
°C
Moisture Sensitivity (Note 5)
MSL
Level 1
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = 25°C.
2. According to JEDEC standard JESD22−A108B.
3. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) $2.0 kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM) $200 V per JEDEC standard: JESD22−A115 for all pins.
4. Latch up Current Maximum Rating: $100 mA per JEDEC standard: JESD78 Class II.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
6. The thermal shutdown set to 160°C (typical) avoids irreversible damage on the device due to power dissipation.
7. The RqCA is dependent of the PCB heat dissipation. The maximum power dissipation (PD) is dependent by the min input voltage, the max
output current and external components selected.
R qCA +
125 * T A
PD
* R qJC
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NCP2704
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for PVDD
between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and PVDD = 3.6 V, HSVDD = 1.8 V.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
GENERAL
PVDD
Supply voltage range
2.5
5.5
V
HSVDD
Supply voltage range
1.6
3.6
V
ISD
IQ
RIN
CMRR
Shutdown current
Quiescent current
Soft shutdown
PVDD
HSVDD
Headset mode at Ta = 25°C,
PVDD = 3.6 V, HSVDD = 1.8 V
PVDD
HSVDD
Speaker mode at Ta = 25°C,
PVDD = 3.6 V, HSVDD = 1.8 V
PVDD
HSVDD
Headset + Speaker mode at Ta =
25°C, PVDD = 3.6 V, HSVDD = 1.8 V
PVDD
HSVDD
Input resistance
Common mode rejection ratio
0.1
mA
mA
18
F = 1 kHz, differential input mode
1
0.1
2
0.25
2.5
2.2
1.8
2.8
2.1
2.2
2.8
2.8
3.3
20
24
kW
−80
dB
TSD
Thermal shutdown temperature
160
°C
TSD_hyst
Thermal shutdown temperature
hysteresis
20
°C
UVLO1
Undervoltage lockout on PVDD
2.2
V
UVLO hysteresis on PVDD
150
mV
Undervoltage lockout on HSVDD
1.4
V
UVLO hysteresis on HSVDD
100
mV
UVLO1hys
UVLO2
UVLO2hys
VOLUME CONTROL
Digital volume range Loudspeaker
Minimum gain
Maximum gain
−60
12
dB
Digital volume range Headset
Minimum gain
Maximum gain
−60
12
dB
Preamp gain
Input 1 or 2
INxG = 00
INxG = 01
INxG = 10
INxG = 11
0
+6
+12
+20
Maximum gain setting Headset
INxG = 11 and gain control =
110100
+32
dB
Maximum gain setting Speaker
INxG = 11 and gain control = 100111
(speaker amplifier has a gain of
+12 dB)
+44
dB
8. Guaranteed by design and characterized.
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5
dB
NCP2704
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for PVDD
between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and PVDD = 3.6 V, HSVDD = 1.8 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
LOUDSPEAKER
|VOS|
RDS(ON)
Absolute Offset Voltage
Inputs AC Grounded
mV
$1
Static drain−source on−state resistance
for both P and NMOS (Note x)
200
ZSD
Output Impedance in Shutdown Mode
20
kW
IBR
Current Breaker Threshold
2
A
FLP
−3 dB Cut off Frequency of the Built in
Low Pass Filter
30
kHz
FSW1
Class D Switching Frequency
300
kHz
TON
Turn On Time
4
ms
TOFF
Turn Off Time
No audio signal and outputs tied to
GND
8
ms
PO
RMS Output Power
RL = 8 W, F = 1 kHz, THD+N < 1%
PVDD = 2.5 V
PVDD = 3.0 V
PVDD = 3.6 V
PVDD = 4.2 V
PVDD = 5.0 V
0.33
0.49
0.75
0.97
1.4
PO
RMS Output Power
RL = 8 W, F = 1 kHz, THD+N < 10%
PVDD = 2.5 V
PVDD = 3.0 V
PVDD = 3.6 V
PVDD = 4.2 V
PVDD = 5.0 V
0.41
0.60
0.87
1.20
1.7
Total Harmonic Distortion + Noise
PVDD = 5.0 V, POUT = 1 W, RL =
8W
PVDD = 3.6 V, POUT = 0.35 W, RL =
8W
0.1
Signal to Noise Ratio
PVDD = 3.6 V, POUT = 0.8 W, RL =
8W
94
dB
CMRR
Common Mode Rejection Ratio
Vic = 0.5 V to (VDD − 0.8 V)
RL = 8 W, Vripple_pk−pk
F = 20 Hz to 20 kHz
−80
dB
PSRR
Power Supply Rejection Ratio
VPripple_pk−pk = 200 mV, RL = 8 W
Inputs AC grounded
F = 217 Hz, Gain = 0 dB
−80
dB
Efficiency
RL = 8 W, F = 1 kHz
PVDD = 3.6 V, POUT = 0.6 W
87
%
THD+N
SNR
h
8. Guaranteed by design and characterized.
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6
300
mW
W
W
%
0.1
NCP2704
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for PVDD
between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and PVDD = 3.6 V, HSVDD = 1.8 V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
HEADSET
VOS
Output offset voltage
Input AC grounded
$1
mV
TWU
Turning On time
Slow = 1
Slow = 0
1
34
ms
VLP
Max Output Swing (peak value) (output
in phase)
(see LDO programming table, v
HSVDD − 200 mV)
HSVDD = 1.8 V, Headset = 16 W
HSVDD = 2.5 V, Headset = 16 W
1
1.65
Vpeak
HSVDD = 1.8 V, Headset = 32 W
HSVDD = 2.7 V, Headset = 32 W
1.3
2
HSVDD = 1.8 V, No load
HSVDD = 2.7 V, No load
1.6
2.5
PO
Max Output Power
HSVDD = 1.8V, THD+N = 1%
Headset = 16 W
Headset = 32 W
30
26
PO
Max Output Power
HSVDD = 2.5V, THD+N = 1%
Headset = 16 W
Headset = 32 W
86
62
Crosstalk
mW
mW
−75
dB
PSRR
Power Supply Rejection Ratio
Inputs Shorted to Ground
Gain = 0 dB
F = 217 Hz to 1 kHz
−100
dB
THD+N
Total Harmonic Distortion + Noise
Headset = 16 W
POUT = 15 mW, F = 1 kHz
0.015
%
THD+N
Total Harmonic Distortion + Noise
Headset = 32 W
VOUT = 400 mV, F = 1 kHz
−75
dB
COUT
Maximum Output Capacitance to
Ground
100
pF
Output Impedance in Shutdown Mode
25
kW
ZSD
Channel to channel gain tolerance
TA = +25 °C, volume at 0 dB
FSW2
Headset charge pump switching
frequency
PO > 500 mW
1.2
MHz
FSW3
Headset charge pump switching
frequency
PO < 500 mW
150
KHz
SNR
Signal to Noise Ratio
HSVDD = 1.8 V, POUT = 20 mW, RL
= 16 W
97
dB
8. Guaranteed by design and characterized.
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$0.3
$2.5
%
NCP2704
ELECTRICAL CHARACTERISTICS Min and Max Limits apply for TA between −40°C to +85°C and TJ up to + 125°C for PVDD
between 2.5 V to 5.5 V (Unless otherwise noted). Typical values are referenced to TA = + 25°C and PVDD = 3.6 V, HSVDD = 1.8 V.
Symbol
I2C
Parameter
Conditions
Min
Typ
Max
Unit
INTERFACE (Note 8)
VIL
Low input voltage level
−0.5
0.3 *
VBAT
V
VIH
High input voltage level
0.7 *
VBAT
VBAT
+ 0.5
V
VOL
Low level output voltage
0
0.2 *
VBAT
V
FCLK−MAX
Clock maximum speed
400
kHz
tHD−START
Hold time (repeated) start condition
0.6
ms
tLOW
Low period of SCL clock
1.3
ms
tHIGH
High period of SCL clock
0.6
ms
tSU−START
Setup time for a repeated start
condition
0.6
ms
tSU−STO
Setup time for STOP condition
0.6
ms
8. Guaranteed by design and characterized.
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8
NCP2704
TYPICAL OPERATING CHARACTERISTICS
Loudspeaker
Figure 2. THD+N vs Pout, 8 W load
Figure 3. Efficiency vs Pout
Figure 4. THD+N vs Frequency at PVDD = 3.6 V
Figure 5. THD+N vs Frequency at PVDD = 5 V
Figure 6. PSRR vs Frequency
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NCP2704
TYPICAL OPERATING CHARACTERISTICS
Headphone
Figure 7. THD+N vs Pout, 32 W Load in Phase
Figure 8. THD+N vs Pout, 16 W Load in Phase
Figure 9. THD+N vs Pout, 32 W Load Out of Phase
Figure 10. THD+N vs Pout, 16 W Load Out of Phase
Figure 11. THD+N vs Frequency, 32 W Load in
Phase, Left Channel
Figure 12. THD+N vs Frequency, 32 W Load in
Phase, Right Channel
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NCP2704
TYPICAL OPERATING CHARACTERISTICS
Headphone
Figure 13. PSRR vs Frequency
Figure 14. Crosstalk vs Frequency
Figure 15. SNR vs Frequency at Pout = 20 mW
Figure 16. Power Dissipation vs Pout with 16 W
Load
Figure 17. Power Dissipation vs Pout with 32 W Load
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NCP2704
DETAIL OPERATING DESCRIPTION
DETAILED DESCRIPTIONS
configuration defines the START condition (noted S).
Communication is terminated when a LOW to HIGH
transition occurs on SDA while SCL is high. This defines the
STOP condition (noted P).
I2C COMPATIBLE INTERFACE
Start and Stop Conditions
Communication is initiated by HIGH to LOW transition
on SDA line while SCL is still high. This signal
Figure 18. Start and Stop Bits Configuration on the I2C Bus
Data Validity
During normal data transmission, the SDA will not
transition during a SCL High.
Figure 19. Data Validity
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NCP2704
Data transfer on the I2C bus
Figure 20. Normal Transmission of Data on the I2C Bus
Note about “repeated Start” (Sr)
Data communication begins with a Start. The first
transmitted Byte is the Slave address (7 bits, MSB first)
followed by the Read/Write bit. A “zero” indicates a “write”
and a “one” indicates a “read” sequence. The byte is
followed by an acknowledgement (mandatory) where the
receiver pulls down the SDA line after the last received bit,
to indicate that the information was received correctly. The
receiver releases the SDA line after the 9th SCL pulse. Then
the second byte may be transmitted.
More details about Data transfer and Acknowledgement
may be found in chapter 7 of “the I2C bus specification”.
A Sr condition can happen any time during an I2C
transaction. The SDA line cannot transition while SCL line
is in High level state, except for START / STOP and Sr
conditions. A Sr condition is a equivalent to a START
condition (SDA line transitions from High to Low while
SCL is High level). However, a STOP condition is not
necessary before a Start. When there is no Stop, the Start is
called Sr:
Normal STOP Then START:
/ACK
ACK
Figure 21.
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STOP
START
NCP2704
Repeated Start (Sr):
First case: SDA transitions normally from 0 to 1 during
SCL low state. However, master generates a Start during
SCL high state. This is a Start without stop and is a Sr
condition
ACK
Normal 0 to 1
Transitioning During Low
SCL
SR = Start Without Stop
Figure 22.
Second case: SDA is already at High state (for example
after a /ACK. Then, master generates a Start during SCL
high state. This is a Start without stop and is a Sr condition
/NACK
SR = Start Without Stop
Figure 23.
Bus Timing
Figure 24.
NCP2704 I2C ADDRESS
I2C Address
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
1
X
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NCP2704
REGISTER MAP
12 different registers can be addressed through the “Register Address” byte.
I2C Address
Register
Number
Function
D7
D6
D5
D4
D3
D2
D1
D0
0
Input Control
−
−
0
0
0
0
0
0
1
Speaker Volume
Control
−
−
0
0
0
0
0
1
2
Left Volume Control
−
−
0
0
0
0
1
0
3
Right Volume Control
−
−
0
0
0
0
1
1
4
Output control
−
−
0
0
0
1
0
0
5
LDO Control
−
−
0
0
0
1
0
1
6
Status
−
−
0
0
0
1
1
0
7
ACNT
−
−
0
0
0
1
1
1
8
ACONFA
−
−
0
0
1
0
0
0
9
ACONFR
−
−
0
0
1
0
0
1
10
ACONFH
−
−
0
0
1
0
1
0
11
EMI control
−
−
0
0
1
0
1
1
59
Reserved*
−
−
1
1
1
0
1
1
60
Reserved*
−
−
1
1
1
1
0
0
61
Reserved*
−
−
1
1
1
1
0
1
62
Reserved*
−
−
1
1
1
1
1
0
63
Reserved*
−
−
1
1
1
1
1
1
*End user should never neither read nor write this register.
INPUT CONTROL
This register allows the setting of the input stage as follows:
INxC sets up the configuration on each input. NCP2704 brings the flexibility to set up each input pair for a differential input
signal or two single−ended ones.
− 1 = Inputs are set as differential input with InxA as the positive and InxB as the negative.
− 0 = Inputs are set as stereo single−ended input with InxA as left input and InxB as right input.
D7
D6
D5
D4
x
x
IN1C
IN2C
D3
D2
IN1G
IN1G configures the gain on the first input
D3
D2
IN1G
0
0
0 dB
0
1
+ 6 dB
1
0
+ 12 dB
1
1
+ 20 dB
IN2G configures the gain on the second input
D1
D0
IN2G
0
0
0 dB
0
1
+ 6 dB
1
0
+ 12 dB
1
1
+ 20 dB
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D1
D0
IN2G
NCP2704
When a single−ended configuration is required, for
example a stereo signal, the first internal stage is described
on Figure 25:
Figure 25. NCP2704 Input Stage for Single−Ended Type of Input
When a differential audio signal is used, the internal first
stage is described in Figure 26:
R1
POSITIVE
INPUT
R1
_
R1
+
R2=2R1 or R1
R1
NEGATIVE
_
INPUT
+
Figure 26. NCP2704 Input Stage for Differential Type of Input
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NCP2704
RIGHT, LEFT VOLUME CONTROL
As described in the register “REGISTER MAP” section, NCP2704 allows separated volume control for Headset Right,
Headset Left.
D7*
D6*
x
x
D5
D4
D3
D2
D1
D0
GAIN CONTROL
*D7 and D6 bits can be either 0 or 1. NCP2704 will only process D5 to D0 to address the targeted gain setting.
D5
D4
D3
D2
D1
D0
Gain (dB)
0
0
0
0
0
0
Mute
0
0
0
0
0
1
−60
0
0
0
0
1
0
−54
0
0
0
0
1
1
−48
0
0
0
1
0
0
−45
0
0
0
1
0
1
−42
0
0
0
1
1
0
−39
0
0
0
1
1
1
−36
0
0
1
0
0
0
−34
0
0
1
0
0
1
−32
0
0
1
0
1
0
−30
0
0
1
0
1
1
−28
0
0
1
1
0
0
−27
0
0
1
1
0
1
−26
0
0
1
1
1
0
−25
0
0
1
1
1
1
−24
0
1
0
0
0
0
−23
0
1
0
0
0
1
−22
0
1
0
0
1
0
−21
0
1
0
0
1
1
−20
0
1
0
1
0
0
−19
0
1
0
1
0
1
−18
0
1
0
1
1
0
−17
0
1
0
1
1
1
−16
0
1
1
0
0
0
−15
0
1
1
0
0
1
−14
0
1
1
0
1
0
−13
0
1
1
0
1
1
−12
0
1
1
1
0
0
−11
0
1
1
1
0
1
−10
0
1
1
1
1
0
−9
0
1
1
1
1
1
−8
1
0
0
0
0
0
−7
1
0
0
0
0
1
−6
1
0
0
0
1
0
−5
1
0
0
0
1
1
−4
1
0
0
1
0
0
−3
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NCP2704
D5
D4
D3
D2
D1
D0
Gain (dB)
1
0
0
1
0
1
−2
1
0
0
1
1
0
−1
1
0
0
1
1
1
0
1
0
1
0
0
0
+1
1
0
1
0
0
1
+2
1
0
1
0
1
0
+3
1
0
1
0
1
1
+4
1
0
1
1
0
0
+5
1
0
1
1
0
1
+6
1
0
1
1
1
0
+7
1
0
1
1
1
1
+8
1
1
0
0
0
0
+9
1
1
0
0
0
1
+10
1
1
0
0
1
0
+11
1
1
0
0
1
1
+12
As described above, an additional gain setting is possible in the “INPUT CONTROL” register. Thus, final gain setting can
go up to 32 dB for the signal applied on the IN1 and IN2 input.
SPEAKER VOLUME CONTROL
As described in the register “REGISTER MAP” section, NCP2704 allows separated volume control for Loudspeaker.
D7*
D6*
x
x
D5
D4
D3
D2
D1
D0
DIGITAL GAIN CONTROL
*D7 and D6 bits can be either 0 or 1. NCP2704 will only process D5 to D0 to address the targeted gain setting.
D5
D4
D3
D2
D1
D0
Gain (dB)
0
0
0
0
0
0
Mute
0
0
0
0
0
1
−60
0
0
0
0
1
0
−54
0
0
0
0
1
1
−48
0
0
0
1
0
0
−45
0
0
0
1
0
1
−42
0
0
0
1
1
0
−39
0
0
0
1
1
1
−36
0
0
1
0
0
0
−34
0
0
1
0
0
1
−32
0
0
1
0
1
0
−30
0
0
1
0
1
1
−28
0
0
1
1
0
0
−27
0
0
1
1
0
1
−26
0
0
1
1
1
0
−25
0
0
1
1
1
1
−24
0
1
0
0
0
0
−23
0
1
0
0
0
1
−22
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NCP2704
D5
D4
D3
D2
D1
D0
Gain (dB)
0
1
0
0
1
0
−21
0
1
0
0
1
1
−20
0
1
0
1
0
0
−19
0
1
0
1
0
1
−18
0
1
0
1
1
0
−17
0
1
0
1
1
1
−16
0
1
1
0
0
0
−15
0
1
1
0
0
1
−14
0
1
1
0
1
0
−13
0
1
1
0
1
1
−12
0
1
1
1
0
0
−11
0
1
1
1
0
1
−10
0
1
1
1
1
0
−9
0
1
1
1
1
1
−8
1
0
0
0
0
0
−7
1
0
0
0
0
1
−6
1
0
0
0
1
0
−5
1
0
0
0
1
1
−4
1
0
0
1
0
0
−3
1
0
0
1
0
1
−2
1
0
0
1
1
0
−1
1
0
0
1
1
1
0
1
0
1
0
0
0
+1
1
0
1
0
0
1
+2
1
0
1
0
1
0
+3
1
0
1
0
1
1
+4
1
0
1
1
0
0
+5
1
0
1
1
0
1
+6
1
0
1
1
1
0
+7
1
0
1
1
1
1
+8
1
1
0
0
0
0
+9
1
1
0
0
0
1
+10
1
1
0
0
1
0
+11
1
1
0
0
1
1
+12
As described above, an additional gain setting is possible in the “INPUT CONTROL” register. Thus, final gain setting can
go up to 44 dB for the signal applied on the IN1 and IN2 input.
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NCP2704
OUTPUT CONTROL
The NCP2704 embeds one class D loudspeaker amplifier and a true ground headset stereo amplifier (Left and Right). The
“INPUT CONTROL” register has defined the Input 1 and 2 configuration (single−ended or differential). The last stage of the
audio subsystem defines which between IN1A, IN1B, IN2A, IN2B or a combination is applied to each amplifier.
D7
D6
D5
D4
x
Reset
/SD
Slow
D3
D2
D1
D0
Output Mode
POWER ON RESET CONDITIONS
D6
RESET
0
No I2C Register Change
1
I2C Register in Reset Configuration
The RESET function can be set by driving D6 bit to high Level. In that case, all registers are set in the following
configuration.
Reset Configuration
Registers
D7
D6
D5
D4
D3
D2
D1
D0
Input control
0
0
0
0
0
0
0
0
Headset right volume control
0
0
0
0
0
0
0
0
Headset left volume control
0
0
0
0
0
0
0
0
Loudspeaker volume control
0
0
0
0
0
0
0
0
Output control
0
0
x
0
0
0
0
0
LDO control
0
0
0
0
0
0
0
0
Status
0
0
0
0
0
0
0
1
AGC control register
0
0
1
1
1
1
1
1
AGC configuration register Attack time
0
0
0
0
0
0
0
1
AGC configuration register Release time
0
0
0
0
0
0
0
1
AGC configuration register Hold time
0
0
0
0
0
0
0
0
EMI control
0
0
0
0
0
0
0
0
Reset Functionality and Default State
When HSVDD decreases and goes below UVLO
threshold (1.3 V), the amplifiers enter in shutdown
mode. When HSVDD goes over UVLO + Hysteresis
the amplifiers turn on with the previous
configuration.
♦ Shutdown functionality
NCP2704 has an internal software shutdown through bit
D5 of the Output control register.
• Software Shutdown: When a software shutdown occurs
through D5 bit in the “Output control” register (D5 =
0), the device enter in a low power shutdown mode. In
addition all the registers are set in their default state.
• Gain modifications setting
When bit D4 = 0 (default state), volume changes step by
step. In this case Ton and Toff = 32 ms and pop and click noise
is reduced. When bit D4 = 1, Ton and Toff = 1 ms.
♦
Reset configuration will be effective in three different
application cases:
• POR: As soon as power supply is detected by
NCP2704, all the registers are set in the default
configuration.
• RESET bit: It can be done in the Mode control register
by setting D6 bit (RESET) to 1. Then Mode Control
and Gain Control registers are set in their default state.
Once done, RESET bit goes back to 0.
• RESET Threshold:
♦ When PVDD decreases and goes below UVLO
threshold (2.2 V), the amplifiers enter in shutdown
mode. When PVDD goes over UVLO + Hysteresis
the amplifiers turn on with the previous
configuration.
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NCP2704
OUTPUT CONFIGURATION
OUTPUT MODE 0
OUTPUT CONFIGURATION with IN1C = IN2C = 0
Conf
N5
D3
D2
D1
D0
Loudspeaker
Left Headset
Right Headset
0
0
0
0
0
SD
SD
SD
1
0
0
0
1
IN1A + IN1B
SD
SD
2
0
0
1
0
SD
IN1A
IN1B
3
0
0
1
1
IN1A + IN1B
IN1A
IN1B
4
0
1
0
0
IN2A + IN2B
SD
SD
5
0
1
0
1
SD
IN2A
IN2B
6
0
1
1
0
IN2A + IN2B
IN2A
IN2B
7
0
1
1
1
IN1A + IN1B + IN2A +
IN2B
SD
SD
8
1
0
0
0
SD
IN1A + IN2A
IN1B + IN2B
9
1
0
0
1
IN1A + IN1B + IN2A +
IN2B
IN1A + IN2A
IN1B + IN2B
10
1
0
1
0
IN1A + IN1B
IN2A
IN2B
11
1
0
1
1
IN2A + IN2B
IN1A
IN1B
12
1
1
0
0
SD
SD
SD
13
1
1
0
1
SD
SD
SD
14
1
1
1
0
SD
SD
SD
15
1
1
1
1
SD
SD
SD
OUTPUT MODE 1
OUTPUT CONFIGURATION with IN1C = IN2C = 1
Conf
N5
D3
D2
D1
D0
Loudspeaker
Left Headset
Right Headset
0
0
0
0
0
SD
SD
SD
1
0
0
0
1
IN1_Diff
SD
SD
2
0
0
1
0
SD
IN1_Diff
IN1_Diff
3
0
0
1
1
IN1_Diff
IN1_Diff
IN1_Diff
4
0
1
0
0
IN2_Diff
SD
SD
5
0
1
0
1
SD
IN2_Diff
IN2_Diff
6
0
1
1
0
IN2_Diff
IN2_Diff
IN2_Diff
7
0
1
1
1
IN1_Diff + IN2_Diff
SD
SD
8
1
0
0
0
SD
IN1_Diff + IN2_Diff
IN1_Diff + IN2_Diff
9
1
0
0
1
IN1_Diff + IN2_Diff
IN1_Diff + IN2_Diff
IN1_Diff + IN2_Diff
10
1
0
1
0
IN1_Diff
IN2_Diff
IN2_Diff
11
1
0
1
1
IN2_Diff
IN1_Diff
IN1_Diff
12
1
1
0
0
SD
SD
SD
13
1
1
0
1
SD
SD
SD
14
1
1
1
0
SD
SD
SD
15
1
1
1
1
SD
SD
SD
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NCP2704
OUTPUT MODE 2
OUTPUT CONFIGURATION with IN1C = 1 and IN2C = 0
Conf
N5
D3
D2
D1
D0
Loudspeaker
Left Headset
Right Headset
0
0
0
0
0
SD
SD
SD
1
0
0
0
1
IN1_Diff
SD
SD
2
0
0
1
0
SD
IN1_Diff
IN1_Diff
3
0
0
1
1
IN1_Diff
IN1_Diff
IN1_Diff
4
0
1
0
0
IN2A + IN2B
SD
SD
5
0
1
0
1
SD
IN2A
IN2B
6
0
1
1
0
IN2A + IN2B
IN2A
IN2B
7
0
1
1
1
SD
SD
SD
8
1
0
0
0
SD
SD
SD
9
1
0
0
1
SD
SD
SD
10
1
0
1
0
IN1_Diff
IN2A
IN2B
11
1
0
1
1
IN2A + IN2B
IN1_Diff
IN1_Diff
12
1
1
0
0
SD
SD
SD
13
1
1
0
1
SD
SD
SD
14
1
1
1
0
SD
SD
SD
15
1
1
1
1
SD
SD
SD
OUTPUT MODE 3
OUTPUT CONFIGURATION with IN1C = 0 and IN2C = 1
Conf
N5
D3
D2
D1
D0
Loudspeaker
Left Headset
Right Headset
0
0
0
0
0
SD
SD
SD
1
0
0
0
1
IN1A + IN1B
SD
SD
2
0
0
1
0
SD
IN1A
IN1B
3
0
0
1
1
IN1A + IN1B
IN1A
IN1B
4
0
1
0
0
IN2_Diff
SD
SD
5
0
1
0
1
SD
IN2_Diff
IN2_Diff
6
0
1
1
0
IN2_Diff
IN2_Diff
IN2_Diff
7
0
1
1
1
SD
SD
SD
8
1
0
0
0
SD
SD
SD
9
1
0
0
1
SD
SD
SD
10
1
0
1
0
IN1A + IN1B
IN2_Diff
IN2_Diff
11
1
0
1
1
IN2_Diff
IN1A
IN1B
12
1
1
0
0
SD
SD
SD
13
1
1
0
1
SD
SD
SD
14
1
1
1
0
SD
SD
SD
15
1
1
1
1
SD
SD
SD
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NCP2704
AGC CONTROL
The AGC function is to protect the speaker from damage due to exceeded output power. The function limits the output power
without deteriorating the audio quality.
AGC CONTROL REGISTER (ACNT)
This register allows controlling the AGC setup.
D7
D6
D5
D4
D3
D2
D1
D0
AGCE
NC/L
PWR(2)
PWR(1)
PWR(0)
THD(2)
THD(1)
THD(0)
THD(2−0): Define the maximum distortion level acceptable in non−clipping mode.
THD Bit
Maximum THDN level
000
1%
001
2%
010
4%
011
6%
100
8%
101
10%
110
15%
111
20%
PWR(2−0): Define the maximum peak voltage in output of the amplifier in case of limiter mode.
PWR Bit
Vpeakmax (V)
000
0.5
001
1
010
1.5
011
2
100
2.5
101
3
110
3.5
111
4
NC/L: Non−clipping mode and limiter mode selection bit.
• 0 = Non−clipping mode.
• 1 = Limiter mode.
AGCE : Activate or disable the AGC function bit.
• 0 = AGC disable.
• 1 = AGC enable.
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ACNT
NCP2704
AGC CONFIGURATION REGISTER (ACONFA−ACONFR−ACONFH)
This register controls the AGC configuration.
D7*
D6*
D5
D4
D3
D2
D1
D0
x
x
A(5)
A(4)
A(3)
A(2)
A(1)
A(0)
ACONFA
x
x
R(5)
R(4)
R(3)
R(2)
R(1)
R(0)
ACONFR
x
x
H(5)
H(4)
H(3)
H(2)
H(1)
H(0)
ACONFH
A(5−0): Define the attack time.
A(5−0)
ms/0.5 dB
00000
Class D clock
ms/6 dB
00001
0.1067
1.28
00010
0.2134
2.56
00011
0.3201
3.84
−−−
0.1067ms/step
−−−
11111
6.722
80.66
Attack time is defined as the minimum time between two gain decrease.
R(5−0): Define the release time.
R(5−0)
s/0.5 dB
s/6 dB
00000
Class D clock
00001
0.0137
0.1644
00010
0.0274
0.3288
00011
0.0411
0.4932
−−−
0.0137s/step
−−−
11111
0.8631
10.36
Release time is defined as the minimum time between two gain increase.
H(5−0): Define the hold time.
H(5−0)
Timer Hold (s)
00000
Hold time off
00001
0.0137
00010
0.0274
00011
0.0411
−−−
0.0137s/step
11111
0.8631
Hold time is defined as the minimum time between a gain increase after a gain decrease.
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NCP2704
EMI CONTROL
The EMI control register sets the rising and falling edges of the Class D speaker outputs. This register gives the possibility
to the user to have the best efficiency by choosing the lowest value, or reduce the EMI perturbation by increasing it. By default
the programming value sets the fastest time to have the best efficiency.
D7
D6
D5
D4
x
x
x
x
D3
D2
D1
D0
EMI Control
D3
D2
D1
D0
Value tr and tf (ns)
0
0
0
0
20
0
0
0
1
15
0
0
1
0
10
0
0
1
1
5
0
1
0
0
1
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
Reserved
1
0
0
1
Reserved
1
0
1
0
Reserved
1
0
1
1
Reserved
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
HEADSET SUPPLY VOLTAGE AND LDO SETTING
Apply a supply voltage from 1.6 V to 3.6 V to the pin HPVDD. The internal signal VRP and VRM will be the output of an
internal converter set by the LDO control register.
D7
D6
D5
D4
x
x
x
x
D3
D2
D1
D0
Internal LDO Output
The LDO control register bits (D3 to D0) set VRP and VRM.
D3
D2
D1
D0
Internal LDO Output
Vpeak
0
0
0
0
1.3
0
0
0
1
1.4
0
0
1
0
1.5
0
0
1
1
1.6
0
1
0
0
1.7
0
1
0
1
1.8
0
1
1
0
1.9
0
1
1
1
2.0
1
0
0
0
2.1
1
0
0
1
2.2
1
0
1
0
2.3
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NCP2704
D3
D2
D1
D0
Internal LDO Output
Vpeak
1
0
1
1
2.4
1
1
0
0
2.5
1
1
0
1
2.6
1
1
1
0
2.7
1
1
1
1
2.8
This function helps to increase the output dynamic when external damping resistors are used.
STATUS REGISTER
This register gives the status of the fault which can occur in the NCP2704.
D7
D6
D5
D4
D3
D2
D1
D0
x
x
WSLDO
SC_LPP
SC_LPN
SC_HSL
SC_HSR
x
D1: This bit indicates that the current limitation of the pin HSR is activated (D1 = 1). It is automatically reset to 0 when the
fault disappears.
D2: This bit indicates that the current limitation of the pin HSL is activated (D2 = 1). It is automatically reset to 0 when the
fault disappears.
D3: This bit indicates that the current limitation of the pin LPN is activated (D3 = 1). It is automatically reset to 0 when the
fault disappears.
D4: This bit indicates that the current limitation of the pin LPP is activated (D4 = 1). It is automatically reset to 0 when the
fault disappears.
D5: This bit indicates that a wrong setting on the LDO control register has been done. This fault occurs when LDO setting >
HSVDD − 200 mV. It is automatically reset to 0 when the fault disappears.
Components Selection
Input Capacitor Selection
The input coupling capacitor blocs the DC voltage at the amplifier input. This capacitor creates a high−pass filter with Rin
(20 kW).
The size of the capacitor must be large enough to couple in low frequencies without severe attenuation in the audio bandwith
(20 Hz − 20 kHz).
The cut off frequency for the input high−pass filter is : Fc = 1 / (2hRinCin).
Charge Pump Capacitor Selection
Use ceramic capacitor with low ESR for better performances. X5R / X7R capacitor is recommended.
The flying capacitor serves to transfer charge during the generation of the negative voltage. Connect CFly as close as possible
to CPP and CPM.
The PVM capacitor must be equal at least to the CFly capacitor to allow maximum transfer charge. Connect CPVM as close
as possible to the PVM pin.
A value of 1 mF is recommended.
The following table suggests typical value and manufacturer :
Value
Reference
Package
Manufacturer
1 mF
C1005X5R0J105K
0402
TDK
1 mF
GRM155R60J105K16
0402
Murata
Lower value of capacitors can be used but the maximum output power is reduced and the device may not operate to
specifications.
Long Play True Ground Headphone Power Supply Decoupling Capacitor
The headphone amplifier requires the adequate decoupling capacitor in order to guarantee the best operation in terms of audio
performances. Use X5R / X7R ceramic capacitor and place it close to the HSVDD pin. A value of 1 mF is recommended.
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NCP2704
Class D Power Supply Decoupling Capacitor
The Class D amplifier requires an adequate decoupling amplifier in order to guarantee the best operation in terms of audio
performances. Use X5R / X7R ceramic capacitor and place it close to PVDD pin in order to reduce high frequency transient
spikes due to parasitic inductance. A value of 4.7 mF is recommended.
Layout Recommendations
For efficiency, noise and EMI standpoints, it is strongly recommended to use a power and ground plane in order to reduce
parasitic resistance and inductance.
For the same reason, it is strongly recommended for the Class D amplifier to keep the output traces short and well shielded
in order to avoid them acting as an antenna.
Route audio signal (input pins and HSL / HSR) far from HSVDD, CPP, CPM, PVM, PVDD, LPP, and LPN to avoid any
perturbation due to the switching.
Figure 27. PCB Layout Example
ORDERING INFORMATION
Device
NCP2704FCCT1G
Package
Shipping†
CSP − 20 − 2.5 x 2.0 mm
(Pb − Free)
3000 / Tape & Reel
http://onsemi.com
27
NCP2704
PACKAGE DIMENSIONS
20 PIN FLIP−CHIP, 2.5x2.0, 0.5P
CASE 499BH−01
ISSUE A
ÇÇ
PIN A1
REFERENCE
2X
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
4. DIE COAT, 0.04 THICK, PERMISSABLE ON THIS
SURFACE. DIE COAT THICKNESS IS INCLUDED
IN DIMENSIONS A AND A2.
A B
E
0.10 C
2X
0.10 C
DIM
A
A1
A2
b
D
E
e
TOP VIEW
A1
0.10 C
A2
0.05 C
20X
A
C
SIDE VIEW
NOTE 3
RECOMMENDED
SOLDER FOOTPRINT*
SEATING
PLANE
20X
20X
b
0.05 C A B
0.03 C
0.50 PITCH
0.25
e
e/2
0.50 PITCH
D
C
MILLIMETERS
MIN
MAX
0.54
0.66
--0.27
0.33
0.39
0.29
0.34
2.50 BSC
2.00 BSC
0.50 BSC
e
B
A
1
2
3
4
5
PACKAGE
OUTLINE
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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http://onsemi.com
28
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP2704/D