TI CD74HC195M High speed cmos logic 4-bit parallel access register Datasheet

[ /Title
(CD74
HC195
)
/Subject
(High
Speed
CMOS
Logic
4-Bit
Parallel
Access
Register)
/Autho
CD74HC195
Data sheet acquired from Harris Semiconductor
SCHS165
High Speed CMOS Logic
4-Bit Parallel Access Register
September 1997
Features
Description
• Asynchronous Master Reset
The device is useful in a wide variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high
speeds.
• J, K, (D) Inputs to First Stage
• Fully Synchronous Serial or Parallel Data Transfer
The two modes of operation, shift right (Q0-Q1) and parallel
load, are controlled by the state of the Parallel Enable (PE)
input. Serial data enters the first flip-flop (Q0) via the J and K
inputs when the PE input is high, and is shifted one bit in the
direction Q0-Q1-Q2-Q3 following each Low to High clock
transition. The J and K inputs provide the flexibility of the JKtype input for special applications and by tying the two pins
together, the simple D-type input for general applications.
The device appears as four common-clocked D flip-flops
when the PE input is Low. After the Low to High clock transition, data on the parallel inputs (D0-D3) is transferred to the
respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can
be achieved by tying the Qn outputs to the Dn-1 inputs and
holding the PE input low.
• Shift Right and Parallel Load Capability
• Complementary Output From Last Stage
• Buffered Inputs
• Typical fMAX = 50MHz at VCC = 5V,
CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
All parallel and serial data transfers are synchronous, occurring
after each Low to High clock transition. The CD74HC195 series
utilizes edge triggering; therefore, there is no restriction on the
activity of the J, K, Pn and PE inputs for logic operations, other
than set-up and hold time requirements. A Low on the
asynchronous Master Reset (MR) input sets all Q outputs Low,
independent of any other input condition.
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
Ordering Information
PInout
PART NUMBER
CD74HC195
(PDIP, SOIC)
TOP VIEW
MR 1
16 VCC
J 2
15 Q0
K 3
14 Q1
D0 4
13 Q2
D1 5
12 Q3
D2 6
11 Q3
D3 7
10 CP
GND 8
9 PE
TEMP. RANGE (oC)
CD74HC195E
-55 to 125
16 Ld PDIP
E16.3
CD74HC195M
-55 to 125
16 Ld SOIC
M16.15
NOTES:
1. When ordering, use the entire part number.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
PKG.
NO.
PACKAGE
1
File Number
1482.1
CD74HC195
Functional Diagram
PE D0 D1 D2 D3
9
4
5
6
7
2
J
10
CP
11
Q3
3
K
1
MR
15
14
13
12
Q0 Q1 Q2 Q3
TRUTH TABLE
INPUTS
OPERATING MODES
OUTPUT
MR
CP
PE
J
K
Dn
Q0
Q1
Q2
Q3
Q3
Asynchronous Reset
L
X
X
X
X
X
L
L
L
L
H
Shift, Set First Stage
H
↑
h
h
h
X
H
q0
q1
q2
q2
Shift, Reset First Stage
H
↑
h
l
l
X
L
q0
q1
q2
q2
Shift, Toggle First Stage
H
↑
h
h
l
X
q0
q0
q1
q2
q2
Shift, Retain First Stage
H
↑
h
l
h
X
q0
q0
q1
q2
q2
Parallel Load
H
↑
l
X
X
dn
d0
d1
d2
d3
d2
NOTE: H = High Voltage Level
L = Low Voltage Level,
X = Don’t Care
↑ = Transition from Low to High Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
h = Low Voltage Level One Set-up Time prior to the High to Low Clock Transition,
dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low to High Clock
Transition.
2
CD74HC195
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
190
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current (Note)
25oC
VCC (V)
-40oC TO 85oC -55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
NOTE: For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
3
CD74HC195
Prerequisite For Switching Function
PARAMETER
SYMBOL
Clock Frequency
fMAX
MR Pulse Width
-
tw
Clock Pulse Width
Removal Time,
MR to Clock
Switching Specifications
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
5
-
4
-
MHz
30
-
25
-
20
-
MHz
35
-
29
-
23
-
MHz
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
2
100
-
125
-
150
-
ns
4.5
20
-
25
-
30
-
ns
6
17
-
21
-
26
-
ns
-
tREM
-40oC TO 85oC -55oC TO 125oC
6
-
tH
25oC
4.5
-
tSU
Hold Time
J, K, PE to Clock
2
-
tw
Set-up Time
J, K, PE to Clock
PARAMETER
TEST
CONDITIONS VCC (V)
2
3
-
3
-
3
-
ns
4.5
3
-
3
-
3
-
ns
6
5
-
3
-
3
-
ns
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
-
Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC (V)
TYP
MAX
MAX
MAX
UNITS
2
-
175
220
265
ns
4.5
-
35
44
53
ns
6
-
30
37
45
ns
2
-
150
190
225
ns
4.5
-
30
38
45
ns
6
-
26
33
38
ns
HC TYPES
Propagation Delay, CP to
Output
Propagation Delay,
MR toOutput
Output Transition Times
(Figure 1)
Input Capacitance
CP to Qn Propagation Delay
tPLH, tPHL
tTLH, tTHL
CIN
CL = 50pF
CL = 50pF
-
2
-
75
95
110
ns
4.5
-
15
19
22
ns
6
-
13
16
19
ns
-
-
10
10
10
pF
tPLH, tPHL
CL = 15pF
5
14
-
-
-
ns
MR to Qn
tPHL
CL = 15pF
5
13
-
-
-
ns
Maximum Clock Frequency
fMAX
CL = 15pF
5
50
-
-
-
MHz
Power Dissipation
Capacitance (Notes 4, 5)
CPD
CL = 15pF
45
-
-
-
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per flip-flop.
5. PD = VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
4
CD74HC195
Test Circuit and Waveforms
tW
RESET
tr
CLOCK V
S
GND
tf
VCC
90%
10%
tW
Q
GND
90%
10%
tTLH
tPLH
0.5 VCC
tPHL
l/fMAX
tPLH tPHL
Q OR Q
VCC
VS
Q
VS
tREM
0.5 VCC
CLOCK
tTHL
0.5 VCC
VCC
GND
FIGURE 2. MASTER RESET PRE-REQUISITE AND
PROPAGATION DELAYS
FIGURE 1. CLOCK PRE-REQUISITE AND PROPAGATION
DELAYS AND OUTPUT TRANSITION TIMES
VALID
PE, K
VCC
VS
J
GND
th
tSU
CLOCK
0.5 VCC
GND
FIGURE 3. J, K OR PARALLEL ENABLE PRE-REQUISITE TIMES
5
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