PHILIPS N74F651AN Transceivers/register Datasheet

INTEGRATED CIRCUITS
74F651A/74F652A
Transceivers/registers
Product specification
Replaces datasheet 74F651/74F652/74F651A/74F652A of 1990 Oct 23
IC15 Data Handbook
1999 Jun 23
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
74F651A Octal transceiver/register, inverting (3-State)
74F652A Octal transceiver/register, non-inverting (3-State)
FEATURES
DESCRIPTION
• Combines 74F245 and two 74F374 type functions in one chip
• High impedance base inputs for reduced loading (70µA in high
The 74F651A and 74F652A transceivers/registers consist of bus
transceiver circuits with 3–State outputs, D–type flip–flops, and
control circuitry arranged for multiplexed transmission of data
directly from the input bus or the internal registers. Data on the A or
B bus will be clocked into the registers as the appropriate clock pin
goes high. Output enable (OEAB, OEBA) and select (SAB, SBA)
pins are provided for bus management.
and low states)
• Independent registers for A and B buses
• Multiplexed real-time and stored data
• Choice of non-inverting and inverting data paths
• 3-State outputs
• Industrial temperature range available (–40°C to +85°C) for
74F652A
TYPE
TYPICAL fmax
TYPICAL SUPPLY CURRENT( TOTAL)
74F651/74F652
110MHz
140mA
74F651A/74F652A
175MHz
110mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
INDUSTRIAL RANGE
VCC = 5V ±10%,
Tamb = –40°C to +85°C
24–pin plastic slim DIP (300mil)
N74F651AN, N74F652AN
I74F652AN
SOT222-1
24–pin plastic SOL
N74F651AD, N74F652AD
I74F652AD
SOT137-1
DESCRIPTION
PKG DWG #
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
74F (U.L.) HIGH/LOW
LOAD VALUE HIGH/LOW
A, B inputs
3.5/0.116
70µA/70µA
CPAB, CPBA
A–to–B, B–to–A clock inputs
1.0/0.033
20µA/20µA
SAB, SBA
A–to–B, B–to–A select inputs
1.0/0.033
20µA/20µA
OEAB, OEBA
A–to–B, B–to–A output enable inputs
1.0/0.033
20µA/20µA
A0 – A7, B0 – B7
A, B outputs for N74F651, N74F652
750/106.7
15mA/64mA
A0 – A7, B0 – B7
A, B outputs for N74F651A, N74F652A
750/80
15mA/48mA
A0 – A7, B0 – B7
A, B outputs for I74F652A
750/60
15mA/36mA
A0 – A7, B0 – B7
DESCRIPTION
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
1999 Jun 23
2
853–1126 21852
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
PIN CONFIGURATION
LOGIC SYMBOL
74F651A
74F651A
24 VCC
CPAB 1
4
A0 4
21 OEBA
A1 5
20 B0
A2 6
19 B1
A3 7
18 B2
A4 8
17 B3
A5 9
16 B4
A6 10
15 B5
A7 11
14 B6
GND 12
13 B7
1
2
8
9
10
11
CPAB
2
SAB
3
OEAB
23
CPBA
22
SBA
OEBA
B0 B1 B2 B3 B4 B5 B6 B7
20
19
18
17
16
VCC = Pin 24
GND = Pin 12
15
14
13
SF00402
LOGIC DIAGRAM
74F651A
22
1
21
IEC/IEEE SYMBOL
3
7
A0 A1 A2 A3 A4 A5 A6 A7
SF00401
23
6
22 SBA
OEAB 3
21
5
23 CPBA
SAB 2
OEBA
OEAB
CPBA
SBA
CPAB
SAB
EN1 [BA]
EN1 [AB]
G3
21
74F651A
3
23
22
1
2
G5
C6
I of 8 channels
G7
1D
C1
4
1
4D
1
7
20
1
5
7
6D
5
5
1
1
A0
20
B0
1D
19
6
18
7
17
8
16
9
15
10
14
11
13
C1
VCC = Pin 24
GND = Pin 12
SF00403
1999 Jun 23
4
2
3
to 7 other channels
SF00404
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
PIN CONFIGURATION
LOGIC SYMBOL
74F652A
74F652A
24 VCC
CPAB 1
4
23 CPBA
SAB 2
5
A0 4
21 OEBA
A1 5
20 B0
A2 6
19 B1
A3 7
18 B2
A4 8
17 B3
A5 9
16 B4
A6 10
15 B5
A7 11
14 B6
GND 12
13 B7
CPAB
2
SAB
3
OEAB
23
CPBA
22
SBA
21
2
4
OEBA
OEAB
CPBA
SBA
CPAB
SAB
EN1 [BA]
EN1 [AB]
19
18
17
16
15
14
13
SF00406
G3
21
74F652A
3
23
22
1
2
G5
C6
I of 8 channels
G7
5
1
1
4D
1
7
1D
C1
20
1
5
7
6D
5
11
LOGIC DIAGRAM
74F652A
1
10
OEBA
VCC = Pin 24
GND = Pin 12
IEC/IEEE SYMBOL
22
9
B0 B1 B2 B3 B4 B5 B6 B7
SF00405
3
8
A0 A1 A2 A3 A4 A5 A6 A7
1
20
23
7
22 SBA
OEAB 3
21
6
4
1
20
A0
2
B0
19
6
18
7
17
8
16
9
15
10
14
11
13
1D
C1
to 7 other channels
SF00407
1999 Jun 23
SF00408
4
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
transferred through the device in real time. The output enable pins
determine the direction of the data flow.
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the 74F651A
and 74F652A. The select pins determine whether data is stored or
BUS MANAGEMENT FUNCTIONS
BUS A
BUS A
BUS B
OEAB OEBA CPAB CPBA SAB SBA
L
L
X
X
X
STORAGE FROM
A, B, OR A AND B
REAL TIME BUS TRANSFER
BUS A TO BUS B
REAL TIME BUS TRANSFER
BUS B TO BUS A
BUS A
BUS B
H
H
X
X
L
BUS B
BUS A
OEAB OEBA CPAB CPBA SAB SBA
OEAB OEBA CPAB CPBA SAB SBA
L
TRANSFER STORED DATA
TO A AND/OR B
X
X
H
↑
X
X
X
L
X
X
↑
X
X
L
H
↑
↑
X
X
BUS B
OEAB OEBA CPAB CPBA SAB SBA
H
L
H or L H or L H
H
SF00409
FUNCTION TABLE
INPUTS
DATA I/O
OPERATING MODE
OEAB
OEBA
CPAB
CPBA
SAB
SBA
An
Bn
74F651A
74F652A
L
H
H or L
H or L
X
X
Input
Input
Isolation
Isolation
L
H
↑
↑
X
X
Input
Input
Store A and B data
Store A and B data
X
H
↑
H or L
X
X
Input
Unspecified*
Store A, hold B
Store A hold B
H
H
↑
↑
L
X
Input
Output
Store A in both registers
Store A in both registers
L
X
H or L
↑
X
X
Unspecified*
Input
Hold A, store B
Hold A, store B
L
L
↑
↑
X
L
Output
Input
Store B in both registers
Store B in both registers
L
L
X
X
X
L
Output
Input
Real time B data to A bus
Real time B data to A bus
L
L
X
H or L
X
H
Output
Input
Stored B data to A bus
Stored B data to A bus
H
H
X
X
L
X
Input
Output
Real time A data to B bus
Real time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored B data to A bus
Stored B data to A bus
Notes to function table
1. H = High-voltage level
2. L = Low-voltage level
3. * = The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are
always enabled, i.e., data at the bus pins will be stored on every low-to-high transition of the clock.
4. ↑ = Low-to-high clock transition
5. X = Don’t care
1999 Jun 23
5
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.
SYMBOL
PARAMETER
RATING
UNIT
V
VCC
Supply voltage
–0.5 to +7.0
VIN
Input voltage
–0.5 to +7.0
V
IIN
Input current
–30 to +5
mA
VOUT
Voltage applied to output in high output state
–0.5 to VCC
V
IOUT
Current applied to output in low output state
72
mA
Tamb
Operating free air temperature range
0 to +70
°C
–40 to +85
°C
Tstg
Storage temperature range
–65 to +150
°C
Commercial range
Industrial range
RECOMMENDED OPERATING CONDITIONS
SYMBOL
LIMITS
PARAMETER
MIN
NOM
MAX
5.0
5.5
UNIT
VCC
Supply voltage
4.5
VIH
High-level input voltage
2.0
VIL
Low-level input voltage
0.8
V
IIk
Input clamp current
–18
mA
IOH
High-level output current
–15
mA
IOL
O
Low level output current
Low-level
Commercial range
48
mA
Industrial range (74F652A only)
36
mA
0
+70
°C
–40
+85
°C
Tamb
1999 Jun 23
Operating free air temperature range
Commercial range
Industrial range (74F652A only)
6
V
V
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
SYMBOL
VOH
TEST CONDITIONS1
PARAMETER
VCC = MIN,
VIL = MAX,
VIH = MIN
High-level output voltage
VOL
O
Low level output voltage
Low-level
VIK
Input clamp voltage
VCC = MIN,
VIL = MAX
MAX,
VIH = MIN
IOH
3mA
O = –3mA
IOH = –15mA
IOL
O = MAX
LIMITS
MIN
±10%VCC
2.4
±5%VCC
2.7
±10%VCC
2.0
TYP2
VCC = MIN, II = IIK
UNIT
V
3.3
V
V
±10%VCC
±5%VCC
MAX
0.55
V
0.42
0.55
V
–0.73
–1.2
V
others
VCC = 0.0V, VI = 7.0V
100
µA
A0–A7, B0–B7
VCC = 5.5V, VI = 5.5V
1
mA
II
Input current at maximum input
voltage
IIH
High-level input current
OEAB, OEBA,
CPAB, CPBA,
SAB, SBA
VCC = MAX, VI = 2.7V
20
µA
IIL
Low-level input current
OEAB, OEBA,
CPAB, CPBA,
SAB, SBA
VCC = MAX, VI = 0.5V
–20
µA
IOZH + IIH
Off-state output current,
high-level voltage applied
A0–A7, B0–B7
VCC = MAX, VO = 2.7V
70
µA
IOZL + IIL
Off–state output current,
low–level voltage applied
A0–A7, B0–B7
VCC = MAX, VO = 0.5V
–70
µA
IO
Output current3
ICC
Supply current (total)
–160
mA
ICCH
VCC = MAX, V0 = 2.25V
VCC = MAX
–60
105
145
mA
ICCL
VCC = MAX
115
165
mA
ICCZ
VCC = MAX
115
160
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. IO is tested under conditions that produce current approximately one half of the true short–circuit output current (IOS).
1999 Jun 23
7
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
AC ELECTRICAL CHARACTERISTICS FOR 74F651A
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MAX
MIN
UNIT
MIN
TYP
MAX
Waveform 1
155
175
Waveform 1
4.5
5.5
7.0
7.5
10.0
10.5
4.0
5.0
11.0
11.0
ns
fmax
Maximum clock frequency
tPLH
tPHL
Propagation delay
CPAB or CPBA to An or Bn
140
ns
tPLH
tPHL
Propagation delay
An or Bn to Bn or An
Waveform 2, 3
2.5
4.0
4.5
6.5
7.5
9.0
2.0
4.0
8.5
10.0
ns
tPLH
tPHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2, 3
4.0
5.0
7.0
7.0
10.0
10.0
3.5
4.5
12.0
10.0
ns
tPZH
tPZL
Output enable time
OEAB or OEBA to An or Bn
Waveform 7, 8
3.0
3.5
5.0
6.0
8.0
8.5
2.5
3.0
8.5
9.0
ns
tPHZ
tPLZ
Output disable time
OEAB or OEBA to An or Bn
Waveform 7, 8
1.5
2.5
4.0
6.0
7.0
8.5
1.0
2.0
7.5
9.0
ns
AC SETUP REQUIREMENTS FOR 74F651A
LIMITS
SYMBOL
PARAMETER
TEST CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF, RL = 500Ω
MIN
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF, RL = 500Ω
MIN
UNIT
MAX
Waveform 4
3.5
4.0
4.0
4.5
ns
Waveform 4
0
0
0
0
ns
Setup time, high or low
OEBA to OEAB or OEAB to OEBA
Waveform 5, 6
5.0
5.0
5.0
5.0
ns
th (H)
th (L)
Hold time, high or low
OEBA to OEAB or OEAB to OEBA
Waveform 5, 6
0
0
0
0
ns
tw (H)
tw (L)
Pulse width, high or low
CPAB or CPBA
Waveform 1
4.5
3.5
4.5
4.0
ns
tsu (H)
tsu (L)
Setup time, high or low
An or Bn to CPAB or CPBA
th (H)
th (L)
Hold time, high or low
An or Bn to CPAB or CPBA
tsu (H)
tsu (L)
Note to AC setup requirements for 74F651A:
1. Setup time is to protect against surge current caused by enabling 16 outputs (48mA per output) simultaneously.
1999 Jun 23
8
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
AC ELECTRICAL CHARACTERISTICS FOR 74F652A
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF,
RL = 500Ω
MIN
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF,
RL = 500Ω
MIN
MAX
140
Tamb = –40°C to +85°C
VCC = +5.0V ± 10%
CL = 50pF,
RL = 500Ω
MIN
UNIT
MAX
fmax
Maximum clock frequency
Waveform 1
155
175
tPLH
tPHL
Propagation delay
CPAB or CPBA to An or Bn
Waveform 1
5.0
5.0
7.5
7.0
10.0
10.0
4.5
4.5
11.5
10.5
140
4.5
4.5
11.5
10.5
ns
ns
tPLH
tPHL
Propagation delay
An or Bn to Bn or An
Waveform 1
4.0
3.0
6.0
5.0
9.0
8.0
3.5
2.5
10.0
8.5
3.5
2.5
10.0
8.5
ns
tPLH
tPHL
Propagation delay
SAB or SBA to An or Bn
Waveform 2, 3
4.5
4.0
7.0
8.0
10.0
10.0
4.0
4.0
11.0
11.5
4.0
4.0
11.0
11.5
ns
tPZH
tPZL
Output enable time1
OEAB or OEBA to An or Bn
Waveform 7, 8
3.0
3.5
5.0
6.0
8.0
8.5
2.5
3.0
8.5
9.0
2.5
3.0
8.5
9.0
ns
tPHZ
tPLZ
Output disable time
OEAB or OEBA to An or Bn
Waveform 7, 8
1.5
2.5
4.0
6.0
7.0
8.5
1.0
2.0
7.5
9.0
1.0
2.0
7.5
9.0
ns
AC SETUP REQUIREMENTS FOR 74F652A
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C
VCC = +5.0V
CL = 50pF,
RL = 500Ω
MIN
tsu (H)
tsu (L)
Setup time, high or low
An or Bn to CPAB or CPBA
th (H)
th (L)
Hold time, high or low
An or Bn to CPAB or CPBA
tsu (H)
tsu (L)
TYP
MAX
Tamb = 0°C to +70°C
VCC = +5.0V ± 10%
CL = 50pF,
RL = 500Ω
MIN
Tamb = –40°C to +85°C
VCC = +5.0V ± 10%
CL = 50pF,
RL = 500Ω
MAX
MIN
UNIT
MAX
Waveform 4
3.5
4.0
4.0
4.5
4.0
4.5
ns
Waveform 4
0
0
0
0
0
0
ns
Setup time, high or low
OEBA to OEAB or OEAB to OEBA
Waveform 5, 6
5.0
5.0
5.0
5.0
5.0
5.0
ns
th (H)
th (L)
Hold time, high or low
OEBA to OEAB or OEAB to OEBA
Waveform 5, 6
0
0
0
0
0
0
ns
tw (H)
tw (L)
Pulse width, high or low
CPAB or CPBA
Waveform 1
4.0
3.5
4.5
4.0
4.5
4.0
ns
Note to AC setup requirements for 74F652A
1. Setup time is to protect against surge current caused by enabling 16 outputs (48mA per output) simultaneously.
1999 Jun 23
9
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
AC WAVEFORMS
For all waveforms, VM = 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
1/fmax
CPBA
or
CPAB
VM
An or Bn
VM
tw(H)
VM
SBA or SAB
VM
VM
tPHL
tPHL
VM
VM
An or Bn
tPLH
tPLH
tw(L)
VM
Bn or An
VM
An or Bn
SF00394
SF00395
Waveform 2. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
Waveform 1. Propagation delay for clock input to output, clock
pulse width, and maximum clock frequency
An or Bn
VM
tPLH
Bn or An
SBA or SAB
VM
An or Bn
tsu(H)
tPHL
VM
VM
CPBA
or
CPAB
An or Bn
VM
VM
VM
tsu(L)
th(H)
VM
VM
th(L)
VM
SF00397
SF00396
Waveform 3. Propagation delay for An to Bn or Bn to An and
SAB or SBA to An or Bn
OEBA
VM
tsu(L)
Waveform 4. Data setup time and hold times
VM
OEAB
th(L)
VM
tsu(H)
VM
th(H)
OEAB
VM
OEBA
VM
SF00410
SF00411
Waveform 5. OEBA to OEAB setup time and hold times
Waveform 6. OEAB to OEBA setup time and hold times
OEBA
OEBA
VM
VM
VM
OEAB
tPZH
An or Bn
VM
OEAB
tPHZ
VOH -0.3V
tPZL
An or Bn
VM
tPLZ
VM
0V
VOL +0.3V
SF00412
SF00413
Waveform 7. 3-State output enable time to high level and
output disable time from high level
1999 Jun 23
Waveform 8. 3-State output enable time to low level and
output disable time from low level
10
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
TEST CIRCUIT AND WAVEFORMS
VCC
7.0V
VIN
RL
VOUT
PULSE
GENERATOR
tw
90%
NEGATIVE
PULSE
VM
CL
AMP (V)
VM
10%
D.U.T.
RT
90%
10%
tTHL (tf )
tTLH (tr )
tTLH (tr )
tTHL (tf )
0V
RL
AMP (V)
90%
90%
Test Circuit for Open Collector Outputs
POSITIVE
PULSE
VM
VM
10%
TEST
tPLZ
tPZL
All other
SWITCH
closed
closed
open
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
10%
tw
SWITCH POSITION
0V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
family
amplitude VM
74F
3.0V
1.5V
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
SF00128
1999 Jun 23
11
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
DIP24: plastic dual in-line package; 24 leads (300 mil)
1999 Jun 23
12
SOT222-1
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
SO24: plastic small outline package; 24 leads; body width 7.5 mm
1999 Jun 23
13
SOT137-1
Philips Semiconductors
Product specification
Transceivers/registers
74F651A/74F652A
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1999
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 06-99
Document order number:
1999 Jun 23
14
9397 750 06142