CY7C1061AV33 16-Mbit (1M x 16) Static RAM Features Functional Description • High speed The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 10 ns • Low active power To write to the device, enable the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19). — 990 mW (max) • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power down when deselected • TTL compatible inputs and outputs • Easy memory expansion with CE1 and CE2 features • Available in Pb-free and non Pb-free 54-pin TSOP II package and non Pb-free 60-ball fine pitch ball grid array (FBGA) package To read from the device, enable the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory will appear on IO8 to IO15. See “Truth Table” on page 7 for a complete description of Read and Write modes. The input/output pins (IO0 through IO15) are placed in a high-impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a Write operation is in progress (CE1 LOW, CE2 HIGH, and WE LOW). Logic Block Diagram 1M x 16 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER IO0–IO7 IO8–IO15 A10 A11 A 12 A 13 A 14 A 15 A 16 A 17 A18 A19 COLUMN DECODER BHE WE OE BLE Cypress Semiconductor Corporation Document #: 38-05256 Rev. *G • 198 Champion Court • CE2 CE1 San Jose, CA 95134-1709 • 408-943-2600 Revised March 26, 2007 [+] Feedback CY7C1061AV33 Selection Guide –10 –12 Unit 10 12 ns Commercial 275 260 mA Industrial 275 260 Commercial/Industrial 50 50 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current mA Pin Configurations [1, 2] 1 NC 2 60-ball FBGA Top View 4 3 5 54-pin TSOP II (Top View) 6 NC NC NC NC BLE OE A0 A1 A2 CE2 A IO 8 BHE A3 A4 CE1 IO 0 B IO 9 IO 10 A5 A6 IO 1 IO 2 C VSS IO11 A17 A7 IO 3 VCC D VCC IO 12 NC A16 IO 4 VSS E IO 14 IO 13 A14 A15 IO 5 IO 6 F IO 15 DNU A12 A13 WE IO 7 G A9 A10 A11 A19 H A18 A8 IO 12 VCC IO 13 IO 14 VSS IO 15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 IO 0 VCC IO 1 IO 2 VSS IO 3 1 2 3 54 53 4 52 51 5 6 50 49 7 8 9 10 11 12 48 47 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 IO 11 VSS IO 10 IO 9 VCC IO 8 A5 A6 A7 A8 A9 NC OE VSS DNU BLE A10 A11 A12 A13 A14 IO 7 VSS IO 6 IO 5 VCC IO 4 NC NC NC NC NC NC NC Notes 1. NC pins are not connected on the die. 2. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper operation. Document #: 38-05256 Rev. *G Page 2 of 10 [+] Feedback CY7C1061AV33 Maximum Ratings DC Input Voltage [3] ............................... –0.5V to VCC + 0.5V Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Current into Outputs (LOW)......................................... 20 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Range Ambient Temperature VCC Supply Voltage on VCC to Relative GND [3] ... –0.5V to +4.6V Commercial 0°C to +70°C 3.3V ± 0.3V DC Voltage Applied to Outputs in High-Z State [3] ...................................–0.5V to VCC + 0.5V Industrial –40°C to +85°C DC Electrical Characteristics (Over the Operating Range) Parameter Description –10 Test Conditions VOH Output HIGH Voltage IOH = –4.0 mA VOL Output LOW Voltage IOL = 8.0 mA VIH Input HIGH Voltage Min –12 Max 2.4 Min Unit Max 2.4 0.4 V 0.4 V 2.0 VCC + 0.3 2.0 VCC + 0.3 V VIL Input LOW Voltage [3] –0.3 0.8 –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –1 +1 µA ICC VCC Operating Supply Current VCC = max, f = fmax = 1/tRC ISB1 Automatic CE Power-down Current —TTL Inputs ISB2 Automatic CE Power-down Current —CMOS Inputs Commercial 275 260 mA Industrial 275 260 mA CE2 <= VIL, max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fmax 70 70 mA CE2 <= 0.3V Commercial/ Industrial max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 50 50 mA Capacitance [4] Parameter Description CIN Input Capacitance COUT IO Capacitance Test Conditions TSOP II TA = 25°C, f = 1 MHz, VCC = 3.3V FBGA Unit 6 8 pF 8 10 pF AC Test Loads and Waveforms [5] 50Ω VTH = 1.5V OUTPUT Z0 = 50Ω (a) OUTPUT 30 pF* * Capacitive Load consists of all components of the test environment. 3.3V GND R1 317 Ω 3.3V 5 pF* ALL INPUT PULSES 90% 90% R2 351Ω INCLUDING JIG AND SCOPE (b) 10% 10% Rise time > 1V/ns (c) Fall time: > 1V/ns Notes 3. VIL (min) = –2.0V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1 ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document #: 38-05256 Rev. *G Page 3 of 10 [+] Feedback CY7C1061AV33 AC Switching Characteristics (Over the Operating Range) [6] Parameter –10 Description Min –12 Max Min Max Unit Read Cycle tpower VCC(typical) to the first access [7] 1 tRC Read Cycle Time 10 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW/CE2 HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low-Z tHZOE OE HIGH to High-Z CE1 HIGH/CE2 LOW to High-Z tPU CE1 LOW/CE2 HIGH to Power Up [9] tPD CE1 HIGH/CE2 LOW to Power Down tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low-Z tHZBE Byte Disable to High-Z 3 ns 6 ns ns 6 5 [9] 12 3 0 ns ns 1 5 tHZCE ns ns 6 0 ns ns 10 12 ns 5 6 ns 1 1 5 ns 6 ns [10, 11] tWC Write Cycle Time tSCE CE1 LOW/CE2 HIGH to Write End tAW Address Setup to Write End tHA Address Hold from Write End tSA Address Setup to Write Start tPWE WE Pulse Width tSD Data Setup to Write End tHD Data Hold from Write End 10 WE HIGH to Low-Z [8] tHZWE WE LOW to High-Z [8] tBW Byte Enable to End of Write tLZWE 10 5 [8] ns 12 3 1 CE1 LOW/CE2 HIGH to Low-Z Write Cycle 3 [8] ms 12 10 [8] tLZCE 1 12 ns 7 8 ns 7 8 ns 0 0 ns 0 0 ns 7 8 ns 5.5 6 ns 0 0 ns 3 3 ns 5 7 6 8 ns ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the “AC Test Loads and Waveforms [5]” on page 3, unless specified otherwise. 7. This part has a voltage regulator that steps down the voltage from 3V to 2V internally. tpower time must be provided initially before a Read/Write operation is started. 8. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms [5]” on page 3. Transition is measured ±200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05256 Rev. *G Page 4 of 10 [+] Feedback CY7C1061AV33 Data Retention Waveform DATA RETENTION MODE 3.0V VCC 3.0V VDR > 2V tR tCDR CE Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [12, 13] tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [13, 14] ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 12. Device is continuously selected. OE, CE, BHE or BHE, or both = VIL. CE2 = VIH. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document #: 38-05256 Rev. *G Page 5 of 10 [+] Feedback CY7C1061AV33 Switching Waveforms (continued) Write Cycle No. 1 (CE1 or CE2 Controlled) [15, 16] tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE tHD tSD DATA IO NOTE 17 VALID DATA tHZOE Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16] tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATA IO NOTE 17 tHD VALID DATA tHZWE tLZWE Notes 15. Data IO is high impedance if OE, or BHE or BLE or both = VIH. 16. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 17. During this period, the IOs are in output state and input signals should not be applied. Document #: 38-05256 Rev. *G Page 6 of 10 [+] Feedback CY7C1061AV33 Switching Waveforms (continued) Write Cycle No. 3 (BHE/BLE Controlled) tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD NOTE 17 DATA IO tHD VALID DATA Truth Table CE1 CE2 OE WE BLE BHE H X X X X X High-Z High-Z Power Down Standby (ISB) X L X X X X High-Z High-Z Power Down Standby (ISB) L H L H L L Data Out Data Out Read All Bits Active (ICC) L H L H L H Data Out High-Z Read Lower Bits Only Active (ICC) L H L H H L High-Z Data Out Read Upper Bits Only Active (ICC) L H X L L L Data In Data In Write All Bits Active (ICC) L H X L L H Data In High-Z Write Lower Bits Only Active (ICC) L H X L H L High-Z Data In Write Upper Bits Only Active (ICC) L H H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) Document #: 38-05256 Rev. *G IO0–IO7 IO8–IO15 Mode Power Page 7 of 10 [+] Feedback CY7C1061AV33 Ordering Information Speed (ns) 10 12 Ordering Code CY7C1061AV33-10ZXC CY7C1061AV33-10BAC CY7C1061AV33-10ZI CY7C1061AV33-10ZXI CY7C1061AV33-10BAXI CY7C1061AV33-12ZC CY7C1061AV33-12ZXC CY7C1061AV33-12BAC CY7C1061AV33-12ZXI Package Diagram 51-85160 51-85162 51-85160 51-85162 51-85160 51-85162 51-85160 Package Type 54-pin TSOP II (Pb-free) 60-ball FBGA 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball FBGA (Pb-free) 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball FBGA 54-pin TSOP II (Pb-free) Operating Range Commercial Industrial Commercial Industrial Contact local Cypress representative for availability of the these parts. Package Diagrams Figure 1. 54-pin TSOP II, 51-85160 51-85160-** Document #: 38-05256 Rev. *G Page 8 of 10 [+] Feedback CY7C1061AV33 Package Diagrams (continued) Figure 2. 60-ball FBGA (8 x 20 x 1.2 mm), 51-85162 TOP VIEW A1 CORNER 1 2 3 4 5 BOTTOM VIEW 6 A1 CORNER 6 5 4 3 2 1 DUMMY BALL (0.3) X12 Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) A B A G H C D E 0.75 F 18.00 20.00±0.10 E 2.625 B D 5.25 20.00±0.10 C F G H 0.75 DIMENSIONS IN MM 1.00 PART # A B 8.00±0.10 1.875 A BA60A STANDARD PKG. BK60A LEAD FREE PKG. 0.75 0.75 1.00 PKG WEIGHT: 0.30 gms 6.00 0.15 C 0.21±0.05 0.25 C 0.53±0.05 3.75 B 8.00±0.10 0.15(4X) C 1.20 MAX 0.36 SEATING PLANE 51-85162-*D All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05256 Rev. *G Page 9 of 10 © Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1061AV33 Document History Page Document Title: CY7C1061AV33 16-Mbit (1M x 16) Static RAM Document Number: 38-05256 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 113725 03/28/02 NSL New Data Sheet *A 117058 07/31/02 DFP Removed 15-ns bin *B 117989 08/30/02 DFP Added 8-ns bin Changed Icc for 8, 10, 12 bins tpower changed from 1 µs to 1 ms. Load Cap Comment changed (for Tx line load) tSD changed to 5.5 ns for the 10-ns bin Changed some 8-ns bin numbers (tHZ, tDOE, tDBE) Removed hz<lz comments from data sheet *C 120383 11/06/02 DFP Final data sheet Added note 3 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd Updated Input/Output Caps (for 48BGA only) to 8 pF/10 pF and for the 54-pin TSOP to 6/8 pF *D 124439 2/25/03 MEG Changed ISB1 from 100 mA to 70 mA Shaded fBGA production ordering information *E 492137 See ECN NXR Corrected Block Diagram on page #1 Removed 8 ns speed bin Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration Included Note #1 and 2 on page #2 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Table *F 508117 See ECN NXR Updated FBGA Pin Configuration Updated Ordering Information table *G 877322 See ECN VKN Updated Ordering Information table Document #: 38-05256 Rev. *G Page 10 of 10 [+] Feedback