TI LM5035A Pwm controller with integrated half-bridge and syncfet driver Datasheet

LM5035A
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SNVS537F – JANUARY 2008 – REVISED APRIL 2013
LM5035A/LM5035A-1 PWM Controller with Integrated Half-Bridge and SyncFET Drivers
Check for Samples: LM5035A
FEATURES
DESCRIPTION
•
•
The LM5035A Half-Bridge Controller/Gate Driver
contains all of the features necessary to implement
half-bridge topology power converters using voltage
mode control with line voltage feed-forward. The
LM5035A is a functional variant of the LM5035 halfbridge PWM controller. The VCC current limit
threshold has been increased to 35 mA. The soft start
and soft start currents have been increased from 50
µA to 100 µA. The BST UV threshold has been
lowered to less than the VCC UV threshold. The ratio
of the T1 and T2 delays on the SR1 and SR2 outputs
has been increased from 2:1 to 3:1. The floating highside gate driver is capable of operating with supply
voltages up to 105V. Both the high-side and low-side
gate drivers are capable of 2A peak. An internal high
voltage startup regulator is included, along with
programmable line undervoltage lockout (UVLO) and
overvoltage protection (OVP). The oscillator is
programmed with a single resistor to frequencies up
to 2MHz. The oscillator can also be synchronized to
an external clock. A current sense input and a
programmable timer provide cycle-by-cycle current
limit and adjustable hiccup mode overload protection.
The differences between LM5035, LM5035A,
LM5035B, and LM5035C are summarized in Table 2.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
105V / 2A Half-Bridge Gate Drivers
Synchronous Rectifier Control Outputs with
Programmable Delays
High Voltage (105V) Start-up Regulator
Voltage mode Control with Line Feed-Forward
and Volt • Second Limiting
Resistor Programmed, 2MHz Capable
Oscillator
Patent Pending Oscillator Synchronization
Programmable Line Under-Voltage Lockout
Line Over-Voltage Protection
Internal Thermal Shutdown Protection
Adjustable Soft-Start
Versatile Dual Mode Over-Current Protection
with Hiccup Delay Timer
Cycle-by-Cycle Over-Current Protection
Direct Opto-Coupler Interface
5V Reference Output
PACKAGES
•
•
•
HTSSOP-20
WQFN-24 (4mm x 5mm)
HTSSOP-28 (LM5035A-1 only)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LM5035A
SNVS537F – JANUARY 2008 – REVISED APRIL 2013
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Simplified Application Diagram
VPWR
LM5035A
VIN
HO
VOUT
UVLO
OVP
LO
RAMP
SR2
RT
SS
SR1
COMP
PGND
AGND
ERROR AMP
AND ISOLATION
Connection Diagram
RAMP
1
20
VIN
UVLO
2
19
REF
OVP
3
18
SR1
COMP
4
17
SR2
RT
5
16
VCC
EP
AGND
6
15
PGND
CS
7
14
LO
SS
8
13
13
HO
DLY
9
12
HS
RES
10
11
HB
Figure 1. LM5035A
20-Lead HTSSOP
(Top View )
2
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RAMP
NC
VIN
NC
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UVLO
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24
23
22
21
20
NC
1
19
REF
OVP
2
18
SR1
COMP
3
17
SR2
RT
4
16
VCC
AGND
5
15
PGND
CS
6
14
LO
SS
7
13
HO
8
9
10
11
12
DLY
RES
NC
HB
HS
EP
Figure 2. LM5035A
20-Lead HTSSOP
(Top View)
NC
1
28
VIN
NC
2
27
NC
NC
3
26
NC
NC
4
25
NC
RAMP
5
24
REF
UVLO
6
23
SR1
OVP
7
22
SR2
EP
COMP
8
21
13
VCC
RT
9
20
PGNDS
AGND
10
19
LO
CS
11
18
NC
SS
12
17
13
HO
DLY
13
16
HS
RES
14
15
HB
Figure 3. LM5035A–1
28-Lead HTSSOP
(Top View)
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Pin Descriptions for LM5035A and LM5035A–1
4
HTSSOP 20
PIN LM5035A
WQFN PIN
LM5035A
HTSSOP 28
PIN LM5035A-1
Name
Description
Application Information
1
23
5
RAMP
Modulator ramp signal
2
24
6
UVLO
Line Under-Voltage Lockout An external voltage divider from the
power source sets the shutdown and
standby comparator levels. When UVLO
reaches the 0.4V threshold the VCC and
REF regulators are enabled. When
UVLO reaches the 1.25V threshold, the
SS pin is released and the device enters
the active mode. Hysteresis is set by an
internal current sink that pulls 23 µA
from the external resistor divider.
3
2
7
OVP
4
3
8
5
4
6
7
An external RC circuit from VIN sets the
ramp slope. This pin is discharged at the
conclusion of every cycle by an internal
FET. Discharge is initiated by either the
internal clock or the Volt • Second clamp
comparator.
Line Over-Voltage
Protection
An external voltage divider from the
power source sets the shutdown levels.
The threshold is 1.25V. Hysteresis is set
by an internal current source that
sources 23µA into the external resistor
divider.
COMP
Input to the Pulse Width
Modulator
An external opto-coupler connected to
the COMP pin sources current into an
internal NPN current mirror. The PWM
duty cycle is maximum with zero input
current, while 1mA reduces the duty
cycle to zero. The current mirror
improves the frequency response by
reducing the AC voltage across the
opto-coupler detector.
9
RT
Oscillator Frequency
Control and Sync Clock
Input
Normally biased at 2V. An external
resistor connected between RT and
AGND sets the internal oscillator
frequency. The internal oscillator can be
synchronized to an external clock with a
frequency higher than the free running
frequency set by the RT resistor.
5
10
AGND
Analog Ground
Connect directly to Power Ground.
6
11
CS
Current Sense input for
current limit
If CS exceeds 0.25V, the output pulse
will be terminated, entering cycle-bycycle current limit. An internal switch
holds CS low for 50ns after HO or LO
switches high to blank leading edge
transients.
8
7
12
SS
Soft-start Input
An internal 110µA current source
charges an external capacitor to set the
soft-start rate. During a current limit
restart sequence, the internal current
source is reduced to 1.2µA to increase
the delay before retry.
9
8
13
DLY
Timing programming pin for An external resistor to ground sets the
the LO and HO to SR1 and timing for the non-overlap time of HO to
SR2 outputs.
SR1 and LO to SR2.
10
9
14
RES
Restart Timer
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If cycle-by-cycle current limit is
exceeded during any cycle, a 22 µA
current is sourced to the RES pin
capacitor.If the RES capacitor voltage
reaches 2.5V, the soft-start capacitor will
be fully discharged and then released
with a pull-up current of 1.2µA. After the
first output pulse at LO (when SS
>COMP offset, typically 1V), the SS pin
charging current will revert to 110µA.
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Pin Descriptions for LM5035A and LM5035A–1 (continued)
HTSSOP 20
PIN LM5035A
WQFN PIN
LM5035A
HTSSOP 28
PIN LM5035A-1
Name
11
11
15
HB
Boost voltage for the HO
driver
An external diode is required from VCC
to HB and an external capacitor is
required from HS to HB to power the HO
gate driver.
12
12
16
HS
Switch node
Connection common to the transformer
and both power switches. Provides a
return path for the HO gate driver.
13
13
17
HO
High side gate drive output. Output of the high side PWM gate
driver. Capable of sinking 2A peak
current
14
14
19
LO
Low side gate dfrive output. Output of the low side PWM gate driver.
Capable of sinking 2A peak current.
15
15
20
PGND
Power Ground
Connect directly to Analog Ground.
16
16
21
VCC
Output of the high voltage
start-up regulator.The VCC
voltage is regulated to
7.6V.
If an auxiliary winding raises the voltage
on this pin above the regulation setpoint,
the Start-up Regulator will shutdown,
thus reducing the internal power
dissipation.
17
17
22
SR2
Synchronous rectifier driver
output.
Control output of the synchronous FET
gate. Capable of 0.5A peak current.
18
18
23
SR1
Synchronous rectifier driver
output.
Control output of the synchronous FET
gate. Capable of 0.5A peak current.
19
19
24
REF
Output of 5V Reference
Maximum output current is 20mA.
Locally decoupled with a 0.1µF
capacitor.
20
21
28
VIN
Input voltage source
Input to the Start-up Regulator.
Operating input range is 13V to 100V
with transient capability to 105V. For
power sources outside of this range, the
LM5035A can be biased directly at VCC
by an external regulator.
1
NC
2
NC
3
NC
4
NC
18
NC
25
NC
26
NC
27
NC
EP
Description
Application Information
EP
EP
Exposed Pad, underside of
package
No electrical contact. Connect to system
ground plane for reduced thermal
resistance.
1
NC
No connection
No electrical contact.
10
NC
No connection
No electrical contact.
20
NC
No connection
No electrical contact.
22
NC
No connection
No electrical contact.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings (1) (2)
VIN to GND
-0.3V to 105V
HS to GND
-1V to 105V
HB to GND
-0.3V to 118V
HB to HS
-0.3V to 18V
VCC to GND
-0.3V to 16V
CS, RT, DLY to GND
-0.3V to 5.5V
COMP Input Current
10mA
All other inputs to GND
-0.3V to 7V
ESD Rating (3)
Human Body Model
2kV
Storage Temperature Range
-65°C to 150°C
Junction Temperature
150°C
(1)
(2)
(3)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2kV for all pins except HB, HO and HS
which are rated at 1.5kV.
Operating Ratings (1)
VIN Voltage
13V to 105V
External Voltage Applied to VCC
8V to 15V
Operating Junction Temperature
-40°C to +125°C
(1)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VVIN = 48V, VVCC = 10V externally applied, RRT = 15.0 kΩ, RDLY = 27.4kΩ, VUVLO = 3V, VOVP = 0V unless
otherwise stated. See (1) and (2).
Symbol
Parameter
Conditions
Min
Typ
Max
7.9
Units
Startup Regulator (VCC pin)
VCC voltage
IVCC = 10mA
7.3
7.6
IVCC(LIM)
VVCC
VCC current limit
VVCC = 7V
25
35
mA
VVCCUV
VCC Under-voltage threshold (VCC
increasing)
VIN = VCC, ΔVVCC from the regulation
setpoint
0.2
0.1
V
VCC decreasing
VCC – PGND
5.5
6.2
6.9
V
Startup regulator current
VIN = 90V, UVLO = 0V
30
70
µA
4
6
mA
5
5.15
V
25
50
mV
IVIN
Supply current into VCC from external Outputs & COMP open, VVCC = 10V,
source
Outputs Switching
V
Voltage Reference Regulator (REF pin)
VREF
REF Voltage
IREF = 0mA
REF Voltage Regulation
IREF = 0 to 10mA
REF Current Limit
REF = 4.5V
4.85
15
20
mA
1.212
1.25
1.288
V
23
27
µA
Under-Voltage Lock Out and shutdown (UVLO pin)
(1)
(2)
6
VUVLO
Under-voltage threshold
IUVLO
Hysteresis current
UVLO pin sinking
Under-voltage Shutdown Threshold
UVLO voltage falling
0.3
V
Under-voltage Standby Enable
Threshold
UVLO voltage rising
0.4
V
19
All limits are ensured. All electrical characteristics having room temperature limits are tested during production with TA = 25°C. All hot
and cold limits are ensured by correlating the electrical characteristics to process and temperature variations and applying statistical
process control.
Typical specifications represent the most likely parametric norm at 25°C operation
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Electrical Characteristics (continued)
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VVIN = 48V, VVCC = 10V externally applied, RRT = 15.0 kΩ, RDLY = 27.4kΩ, VUVLO = 3V, VOVP = 0V unless
otherwise stated. See (1) and (2).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1.212
1.25
1.288
V
19
23
27
µA
0.228
0.25
0.272
V
Over-Voltage Protection (OVP pin)
VOVP
Over-Voltage threshold
IOVP
Hysteresis current
OVP pin sourcing
Current Sense Input (CS Pin)
VCS
Current Limit Threshold
CS delay to output
CS from zero to 1V. Time for HO and LO to
fall to 90% of VCC. Output load = 0 pF.
80
Leading edge blanking time at CS
CS sink impedance (clocked)
ns
50
Internal FET sink impedance
ns
32
60
Ω
Current Limit Restart (RES Pin)
VRES
RES Threshold
2.4
2.5
2.6
V
Charge source current
VRES = 1.5V
16
22
28
µA
Discharge sink current
VRES = 1V
8
12
16
µA
Soft-Start (SS Pin)
ISS
Charging current in normal operation
VSS = 0
80
110
140
µA
Charging current during a hiccup
mode restart
VSS = 0
0.6
1.2
1.8
µA
Soft-stop Current Sink
VSS = 2.5V
80
110
140
µA
Frequency 1 (at HO, half oscillator
frequency)
RRT = 15 kΩ, TJ = 25°C
185
200
215
kHz
RRT = 15 kΩ, TJ = -40°C to 125°C
180
Frequency 2 (at HO, half oscillator
frequency)
RRT = 5.49 kΩ
430
Oscillator (RT Pin)
FSW1
FSW2
DC level
220
500
570
2
Input Sync threshold
2.5
3
kHz
V
3.4
V
PWM Controller (Comp Pin)
Delay to output
VPWM-OS
80
SS to RAMP offset
0.7
Minimum duty cycle
SS = 0V
Small signal impedance
ICOMP = 600µA, COMP current to PWM
voltage
1
ns
1.2
V
0
%
5000
Ω
0.25
V
Main Output Drivers (HO and LO Pins)
Output high voltage
IOUT = 50mA, VHB - VHO, VVCC - VLO
0.5
Output low voltage
IOUT = 100 mA
0.2
Rise time
CLOAD = 1 nF
15
ns
Fall time
CLOAD = 1 nF
13
ns
Deadtime, HO to LO, LO to HO
VDLY = VREF, ICOMP = 0mA
Peak source current
VHO,LO = 0V, VVCC = 10V
1.25
A
Peak sink current
VHO,LO = 10V, VVCC = 10V
2
A
HB Threshold
VCC rising
3.8
V
45
70
0.5
100
V
ns
Voltage Feed-Forward (RAMP Pin)
RAMP comparator threshold
COMP current = 0
2.4
Output high voltage
IOUT = 10mA, VVCC - VSR1, VVCC - VSR2
0.25
Output low voltage
IOUT = 20 mA (sink)
Rise time
CLOAD = 1 nF
2.5
2.6
V
Synchronous Rectifier Drivers (SR1, SR2)
0.1
0.08
V
0.2
40
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ns
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Electrical Characteristics (continued)
Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction
Temperature range. VVIN = 48V, VVCC = 10V externally applied, RRT = 15.0 kΩ, RDLY = 27.4kΩ, VUVLO = 3V, VOVP = 0V unless
otherwise stated. See (1) and (2).
Symbol
T1
T2
Parameter
Conditions
Fall time
CLOAD = 1 nF
20
ns
Peak source current
VSR = 0, VVCC = 10V
0.5
A
Peak sink current
VSR = VVCC, VVCC = 10V
0.5
A
Deadtime, SR1 falling to HO rising,
SR2 falling to LO rising
RDLY = 10k
33
ns
RDLY = 27.4k
Deadtime, HO falling to SR1 rising,
LO falling to SR2 rising
Min
68
Typ
86
RDLY = 100k
300
RDLY = 10k
18
RDLY = 27.4k
RDLY = 100k
20
29
Max
120
Units
ns
ns
ns
42
ns
80
ns
Shutdown temperature
165
°C
Hysteresis
20
°C
Thermal Shutdown
TSD
Thermal Resistance
8
θJA
Junction to ambient, 0 LFPM Air Flow
HTSSOP-20 package
40
°C/W
θJC
Junction to Case (EP) Thermal
resistance
HTSSOP-20 package
4
°C/W
θJA
Junction to ambient, 0 LFM Air Flow
WQFN-24 (4 mm x 5 mm)
40
°C/W
θJC
Junction to Case Thermal resistance
WQFN-24 (4 mm x 5 mm)
6
°C/W
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Typical Performance Characteristics
VVCC and VREF
vs
VVIN
VVCC
vs
IVCC
8
8
7
7
6
6
5
VVCC (V)
VREF
4
3
4
3
2
2
1
1
0
0
0
5
10
15
20
10
15
25
20
VVIN (V)
Figure 4.
Figure 5.
VREF
vs
IREF
Frequency
vs
RT
35
40
OSCILLATOR FREQUENCY (kHz)
1000
5
4
3
2
1
900
800
700
600
500
400
300
200
100
0
0
0
5
10
15
20
25
10
20
30
40
RRT (k:)
Figure 6.
Figure 7.
Oscillator Frequency
vs
Temperature
Soft-Start & Stop Current
vs
Temperature
SOFT-START and STOP CURRENT (PA)
405
RRT = 15k
400
395
390
-40
0
IREF (mA)
410
OSCILLATOR FREQUENCY (kHz)
5
IVCC (mA)
6
VREF (V)
5
0
40
80
120
120
50
30
116
29
SOFT-START
112
28
108
SOFT-STOP
27
104
26
100
25
96
24
92
23
88
22
RESTART
84
80
-40
TEMPERATURE (ºC)
RESTART CURRENT (PA)
VVCC and VREF (V)
VVCC
21
20
0
40
80
120
TEMPERATURE (ºC)
Figure 8.
Figure 9.
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Typical Performance Characteristics (continued)
RDLY
vs
Deadtime
Effective Comp Input Impedance
350
HO/LO to SR DEADTIME (ns)
9
8.5
RESISTANCE (:)
8
7.5
7
6.5
300
250
200
T1
150
100
6
50
5.5
0
T2
0
20
40
5
-60 -40 -20 0 20 40 60 80 100 120 140 160
60
80
100
RDLY (k:)
TEMPERATURE (°C)
Figure 10.
Figure 11.
SR "T1" Parameter
vs
Temperature
SR "T2" Parameter
vs
Temperature
32
105
100
31
95
30
T2 (ns)
T1 (ns)
90
85
80
29
28
RDLY = 27.4 k:
75
RDLY = 27.4 k:
27
70
65
-40
10
0
40
80
120
26
-40
0
40
80
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12.
Figure 13.
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Block Diagram
7.6V SERIES
REGULATOR
VIN
0.4V
SHUTDOWN
1.25V
UVLO-STANDBY
UVLO
VCC
LOGIC
VCC/REF
UVLO
5V
Reference
REF
23 PA
THERMAL
LIMIT
(165ºC)
23 PA
+5V
OVP
OVP-STANDBY
HB
1.25V
HO
Q
CLK
RT/SYNC
DRIVER
T
OSCILLATOR
SLOPE
PROPORTIONAL
TO VIN
Timer
Q
HS
VCC
S Q
R
RAMP
LO
DRIVER
FEED-FORWARD RAMP
REF
VCC
6k
COMP
1:1
SR1
PWM
1V
SS
VCC
LOGIC
SR2
SS Buffer
(Sink Only)
UVLOStandby
2.5V
MAX V*S
CLAMP
DLY
OVP-Standby
Shutdown
Soft-Start
Hiccup
2.5V
+5V
CS
D Q
0.25V
CLK + LEB
CLK
+5V
SS
SS
SOFT-START
110 PA
RESTART DELAY
RES
12 PA
NON-CURRENT
LIMIT CYCLE
PGND
1.2 PA
1 mA
SHUTDOWN
22 PA
CURRENT
LIMIT
CYCLE
110 PA
AGND
SOFT-STOP
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FUNCTIONAL DESCRIPTION
The LM5035A PWM controller contains all of the features necessary to implement half-bridge voltage-mode
controlled power converters. The LM5035A provides two gate driver outputs to directly drive the primary side
power MOSFETs and two signal level outputs to control secondary synchronous rectifiers through an isolation
interface. Secondary side drivers, such as the LM5110, are typically used to provide the necessary gate drive
current to control the sync MOSFETs. Synchronous rectification allows higher conversion efficiency and greater
power density than conventional PN or Schottky rectifier techniques. The LM5035A can be configured to operate
with bias voltages ranging from 8V to 105V. Additional features include line under-voltage lockout, cycle-by-cycle
current limit, voltage feed-forward compensation, hiccup mode fault protection with adjustable delays, soft-start, a
2MHz capable oscillator with synchronization capability, precision reference, thermal shutdown and
programmable volt•second clamping. These features simplify the design of voltage-mode half-bridge DC-DC
power converters. The Functional Block Diagram is shown in Block Diagram.
High-Voltage Start-up Regulator
The LM5035A contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected
directly to a nominal 48 VDC input voltage. The regulator input can withstand transients up to 105V. The
regulator output at VCC (7.6V) is internally current limited to 35 mA typical. When the UVLO pin potential is
greater than 0.4V, the VCC regulator is enabled to charge an external capacitor connected to the VCC pin. The
VCC regulator provides power to the voltage reference (REF) and the output drivers (LO, SR1 and SR2). When
the voltage on the VCC pin exceeds the UVLO threshold of 7.6V, the internal voltage reference (REF) reaches
its regulation setpoint of 5V and the UVLO voltage is greater than 1.25V, the controller outputs are enabled. The
value of the VCC capacitor depends on the total system design, and its start-up characteristics. The
recommended range of values for the VCC capacitor is 0.1 µF to 100 µF.
The VCC under-voltage comparator threshold is lowered to 6.2V (typical) after VCC reaches the regulation setpoint. If VCC falls below this value, the outputs are disabled, and the soft-start capacitor is discharged. If VCC
increases above 7.6V, the outputs will be enabled and a soft-start sequence will commence.
The internal power dissipation of the LM5035A can be reduced by powering VCC from an external supply. In
typical applications, an auxiliary transformer winding is connected through a diode to the VCC pin. This winding
must raise the VCC voltage above 8.3V to shut off the internal start-up regulator. Powering VCC from an
auxiliary winding improves efficiency while reducing the controller’s power dissipation. The under-voltage
comparator circuit will still function in this mode, requiring that VCC never falls below 6.2V during the start-up
sequence.
During a fault mode, when the converter auxiliary winding is inactive, external current draw on the VCC line
should be limited such that the power dissipated in the start-up regulator does not exceed the maximum power
dissipation of the IC package.
An external DC bias voltage can be used instead of the internal regulator by connecting the external bias voltage
to both the VCC and the VIN pins. The external bias must be greater than 8.3V to exceed the VCC UVLO
threshold and less than the VCC maximum operating voltage rating (15V).
Line Under-Voltage Detector
The LM5035A contains a dual level Under-Voltage Lockout (UVLO) circuit. When the UVLO pin voltage is below
0.4V, the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.4V but less
than 1.25V, the controller is in standby mode. In standby mode the VCC and REF bias regulators are active
while the controller outputs are disabled. When the VCC and REF outputs exceed the VCC and REF undervoltage thresholds and the UVLO pin voltage is greater than 1.25V, the outputs are enabled and normal
operation begins. An external set-point voltage divider from VIN to GND can be used to set the minimum
operating voltage of the converter. The divider must be designed such that the voltage at the UVLO pin will be
greater than 1.25V when VIN enters the desired operating range. UVLO hysteresis is accomplished with an
internal 23 µA current sink that is switched on or off into the impedance of the set-point divider. When the UVLO
threshold is exceeded, the current sink is deactivated to quickly raise the voltage at the UVLO pin. When the
UVLO pin voltage falls below the 1.25V threshold, the current sink is enabled causing the voltage at the UVLO
pin to quickly fall. The hysteresis of the 0.4V shutdown comparator is internally fixed at 100 mV.
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The UVLO pin can also be used to implement various remote enable / disable functions. Turning off a converter
by forcing the UVLO pin to the standby condition provides a controlled soft-stop. See the Soft-Start section for
more details.
Line Over Voltage / Load Over Voltage / Remote Thermal Protection
The LM5035A provides a multipurpose OVP pin that supports several fault protection functions. When the OVP
pin voltage exceeds 1.25V, the controller is held in standby mode which immediately halts the PWM pulses at
the HO and LO pins. In standby mode, the VCC and REF bias regulators are active while the controller outputs
are disabled. When the OVP pin voltage falls below the 1.25V OVP threshold, the outputs are enabled and
normal soft-start sequence begins. Hysteresis is accomplished with an internal 23 µA current source that is
switched on or off into the impedance of the OVP pin set-point divider. When the OVP threshold is exceeded, the
current source is enabled to quickly raise the voltage at the OVP pin. When the OVP pin voltage falls below the
1.25V threshold, the current source is disabled causing the voltage at the OVP pin to quickly fall.
Several examples of the use of this pin are provided in the Application Information section.
Reference
The REF pin is the output of a 5V linear regulator that can be used to bias an opto-coupler transistor and
external housekeeping circuits. The regulator output is internally current limited to 20mA (typical).
Cycle-by-Cycle Current Limit
The CS pin is driven by a signal representative of the transformer primary current. If the voltage sensed at CS
pin exceeds 0.25V, the current sense comparator terminates the HO or LO output driver pulse. If the high current
condition persists, the controller operates in a cycle-by-cycle current limit mode with duty cycle determined by the
current sense comparator instead of the PWM comparator. Cycle-by-cycle current limiting may trigger the hiccup
mode restart cycle depending on the configuration of the RES pin (see below).
A small R-C filter connect to the CS pin and located near the controller is recommended to suppress noise. An
internal 32Ω MOSFET connected to the CS input discharges the external current sense filter capacitor at the
conclusion of every cycle. The discharge MOSFET remains on for an additional 50 ns after the HO or LO driver
switches high to blank leading edge transients in the current sensing circuit. Discharging the CS pin filter each
cycle and blanking leading edge spikes reduces the filtering requirements and improves the current sense
response time.
The current sense comparator is very fast and responds to short duration noise pulses. Layout considerations
are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be
placed very close to the device and connected directly to the CS and AGND pins. If a current sense transformer
is used, both leads of the transformer secondary should be routed to the filter network, which should be located
close to the IC. If a sense resistor located in the source of the main MOSFET switch is used for current sensing,
a low inductance type of resistor is required. When designing with a current sense resistor, all of the noise
sensitive low power ground connections should be connected together near the AGND pin, and a single
connection should be made to the power ground (sense resistor ground point).
Overload Protection Timer
The LM5035A provides a current limit restart timer to disable the outputs and force a delayed restart (hiccup
mode) if a current limit condition is repeatedly sensed. The number of cycle-by-cycle current limit events required
to trigger the restart is programmable by the external capacitor at the RES pin. During each PWM cycle, the
LM5035A either sources or sinks current from the RES pin capacitor. If no current limit is detected during a cycle,
an 12 µA discharge current sink is enabled to pull the RES pin to ground. If a current limit is detected, the 12 µA
sink current is disabled and a 22µA current source causes the voltage at the RES pin to gradually increase. The
LM5035A protects the converter with cycle-by-cycle current limiting while the voltage at RES pin increases. If the
RES voltage reaches the 2.5V threshold, the following restart sequence occurs (also see Figure 14):
• The RES capacitor and SS capacitors are fully discharged
• The soft-start current source is reduced from 110 µA to 1 µA
• The SS capacitor voltage slowly increases. When the SS voltage reaches ≊1V, the PWM comparator will
produce the first narrow output pulse. After the first pulse occurs, the SS source current reverts to the normal
110 µA level. The SS voltage increases at its normal rate, gradually increasing the duty cycle of the output
drivers
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•
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If the overload condition persists after restart, cycle-by-cycle current limiting will begin to increase the voltage
on the RES capacitor again, repeating the hiccup mode sequence
If the overload condition no longer exists after restart, the RES pin will be held at ground by the 12 µA current
sink and normal operation resumes
The overload timer function is very versatile and can be configured for the following modes of protection:
1. Cycle-by-cycle only: The hiccup mode can be completely disabled by connecting a zero to 50 kΩ resistor
from the RES pin to AGND. In this configuration, the cycle-by-cycle protection will limit the output current
indefinitely and no hiccup sequences will occur.
2. Hiccup only: The timer can be configured for immediate activation of a hiccup sequence upon detection of
an overload by leaving the RES pin open circuit.
3. Delayed Hiccup: Connecting a capacitor to the RES pin provides a programmed interval of cycle-by-cycle
limiting before initiating a hiccup mode restart, as previously described. The dual advantages of this
configuration are that a short term overload will not cause a hiccup mode restart but during extended
overload conditions, the average dissipation of the power converter will be very low.
4. Externally Controlled Hiccup: The RES pin can also be used as an input. By externally driving the pin to a
level greater than the 2.5V hiccup threshold, the controller will be forced into the delayed restart sequence.
For example, the external trigger for a delayed restart sequence could come from an over-temperature
protection circuit or an output over-voltage sensor.
Current
Sense
Circuit
Current
Limit
CS
5V
Restart
Current
Source
Logic
0.25V
CLK
22 PA
RES
12 PA
CRES
SS
Voltage
Feedback
To Output
Drivers
COMP
PWM
2.5V
S
Drivers Off
1 PA
CSS
Restart
Comparator
R Q
Restart
Latch
110 PA
SS
110 PA
100 mV
SS
Logic
Drivers Off
Soft-start
LM5035A
Figure 14. Current Limit Restart Circuit
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2.5V
Current Limit Detected
at CS
RES
0V
5V
+110 PA
#1V
+1 PA
SS
LO
HO
t2
t1
t3
Figure 15. Current Limit Restart Timing
REF
5V
FEED-FORWARD RAMP
+
6k
_
1V
COMP
1:1
LM4041
Voltage
feedback
PWM
COMPARATOR
Potential across
Optocoupler detector
is constant (approx. 4.3V)
SOFT-START
LM5035A
Figure 16. Optocoupler to COMP Interface
Soft-Start
The soft-start circuit allows the regulator to gradually reach a steady state operating point, thereby reducing startup stresses and current surges. When bias is supplied to the LM5035A, the SS pin capacitor is discharged by an
internal MOSFET. When the UVLO, VCC and REF pins reach their operating thresholds, the SS capacitor is
released and charged with a 110 µA current source. The PWM comparator control voltage is clamped to the SS
pin voltage by an internal amplifier. When the PWM comparator input reaches 1V, output pulses commence with
slowly increasing duty cycle. The voltage at the SS pin eventually increases to 5V, while the voltage at the PWM
comparator increases to the value required for regulation as determined by the voltage feedback loop.
One method to shutdown the regulator is to ground the SS pin. This forces the internal PWM control signal to
ground, reducing the output duty cycle quickly to zero. Releasing the SS pin begins a soft-start cycle and normal
operation resumes. A second shutdown method is discussed in the UVLO section.
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Soft-Stop
If the UVLO pin voltage falls below the 1.25V standby threshold but above the 0.4V shutdown threshold, the 110
µA SS pin source current is disabled and a 110 µA sink current discharges the soft-start capacitor. As SS voltage
falls and clamps the PWM comparator input, the PWM duty cycle will gradually fall to zero. The soft-stop feature
produces a gradual reduction of the power converter output voltage. This soft-stop method of turning off the
converter reduces energy in the output capacitor before control of the main and synchronous rectification
MOSFETs is disabled. The PWM pulses may cease before the SS voltage reduces the duty cycle if the VCC or
REF voltage drops below the respective under-voltage thresholds during the soft-stop process.
PWM Comparator
The pulse width modulation (PWM) comparator compares the voltage ramp signal at the RAMP pin to the loop
error signal. This comparator is optimized for speed in order to achieve minimum controllable duty cycles. The
loop error signal is received from the external feedback and isolation circuit is in the form of a control current into
the COMP pin. The COMP pin current is internally mirrored by a matched pair of NPN transistors which sink
current through a 5 kΩ resistor connected to the 5V reference. The resulting control voltage passes through a 1V
level shift before being applied to the PWM comparator.
An opto-coupler detector can be connected between the REF pin and the COMP pin. Because the COMP pin is
controlled by a current input, the potential difference across the optocoupler detector is nearly constant. The
bandwidth limiting phase delay which is normally introduced by the significant capacitance of the opto-coupler is
thereby greatly reduced. Higher loop bandwidths can be realized since the bandwidth-limiting pole associated
with the opto-coupler is now at a much higher frequency. The PWM comparator polarity is configured such that
with no current into the COMP pin, the controller produces the maximum duty cycle at the main gate driver
outputs, HO and LO.
Feed-Forward Ramp and Volt • Second Clamp
An external resistor (RFF) and capacitor (CFF) connected to VIN, AGND, and the RAMP pin are required to create
the PWM ramp signal. The slope of the signal at RAMP will vary in proportion to the input line voltage. This
varying slope provides line feed-forward information necessary to improve line transient response with voltage
mode control. The RAMP signal is compared to the error signal by the pulse width modulator comparator to
control the duty cycle of the HO and LO outputs. With a constant error signal, the on-time (TON) varies inversely
with the input voltage (VIN) to stabilize the Volt • Second product of the transformer primary signal. The power
path gain of conventional voltage-mode pulse width modulators (oscillator generated ramp) varies directly with
input voltage. The use of a line generated ramp (input voltage feed-forward) nearly eliminates this gain variation.
As a result, the feedback loop is only required to make very small corrections for large changes in input voltage.
In addition to the PWM comparator, a Volt • Second Clamp comparator also monitors the RAMP pin. If the ramp
amplitude exceeds the 2.5V threshold of the Volt • Second Clamp comparator, the on-time is terminated. The CFF
ramp capacitor is discharged by an internal 32Ω discharge MOSFET controlled by the V•S Clamp comparator. If
the RAMP signal does not exceed 2.5V before the end of the clock period, then the internal clock will enable the
discharge MOSFET to reset capacitor CFF.
By proper selection of RFF and CFF values, the maximum on-time of HO and LO can be set to the desired
duration. The on-time set by the Volt • Second Clamp varies inversely to the line voltage because the RAMP
capacitor is charged by a resistor (RFF) connected to VIN while the threshold of the clamp is a fixed voltage
(2.5V). An example will illustrate the use of the Volt • Second Clamp comparator to achieve a 50% duty cycle
limit at 200kHz with a 48V line input. A 50% duty cycle at a 200kHz requires a 2.5µs on-time. To achieve this
maximum on-time clamp level:
§
¨
©
§ 2.5V -1
In ¨1© VIN
=
2.5 Ps + 0.25 Ps
In
§
¨1©
§
¨
©
TON + 10%
RFF x CFF =
2.5V -1
48V
= 51.4 Ps
(1)
The recommended capacitor value range for CFF is 100 pF to 1000 pF. 470 pF is a standard value that can be
paired with an 110 kΩ to approximate the desired 51.4µs time constant. If load transient response is slowed by
the 10% margin, the RFF value can be increased. The system signal-to-noise will be slightly decreased by
increasing RFF x CFF.
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Oscillator, Sync Capability
The LM5035A oscillator frequency is set by a single external resistor connected between the RT and AGND pins.
To set a desired oscillator frequency, the necessary RT resistor is calculated from:
§ 1
¨
© FOSC
§
¨
©
RT =
- 110 ns x 6.25 x 109
(2)
For example, if the desired oscillator frequency is 400kHz (HO and LO each switching at 200 kHz) a 15 kΩ
resistor would be the nearest standard one percent value.
Each output (HO, LO, SR1 and SR2) switches at half the oscillator frequency. The voltage at the RT pin is
internally regulated to a nominal 2V. The RT resistor should be located as close as possible to the IC, and
connected directly to the pins (RT and AGND). The tolerance of the external resistor, and the frequency
tolerance indicated in the Electrical Characteristics, must be taken into account when determining the worst case
frequency range.
The LM5035A can be synchronized to an external clock by applying a narrow pulse to the RT pin. The external
clock must be at least 10% higher than the free-running oscillator frequency set by the RT resistor. If the external
clock frequency is less than the RT resistor programmed frequency, the LM5035A will ignore the synchronizing
pulses. The synchronization pulse width at the RT pin must be a minimum of 15 ns wide. The clock signal should
be coupled into the RT pin through a 100 pF capacitor or a value small enough to ensure the pulse width at RT
is less than 60% of the clock period under all conditions. When the synchronizing pulse transitions low-to-high
(rising edge), the voltage at the RT pin must be driven to exceed 3.2V volts from its nominal 2 VDC level. During
the clock signal’s low time, the voltage at the RT pin will be clamped at 2 VDC by an internal regulator. The
output impedance of the RT regulator is approximately 100Ω. The RT resistor is always required, whether the
oscillator is free running or externally synchronized.
Gate Driver Outputs (HO & LO)
The LM5035A provides two alternating gate driver outputs, the floating high side gate driver HO and the ground
referenced low side driver LO. Each driver is capable of sourcing 1.25A and sinking 2A peak. The HO and LO
outputs operate in an alternating manner, at one-half the internal oscillator frequency. The LO driver is powered
directly by the VCC regulator. The HO gate driver is powered from a bootstrap capacitor connected between HB
and HS. An external diode connected between VCC (anode pin) and HB (cathode pin) provides the high side
gate driver power by charging the bootstrap capacitor from VCC when the switch node (HS pin) is low. When the
high side MOSFET is turned on, HB rises to a peak voltage equal to VVCC + VHS where VHS is the switch node
voltage.
The HB and VCC capacitors should be placed close to the pins of the LM5035A to minimize voltage transients
due to parasitic inductances since the peak current sourced to the MOSFET gates can exceed 1.25A. The
recommended value of the HB capacitor is 0.01 µF or greater. A low ESR / ESL capacitor, such as a surface
mount ceramic, should be used to prevent voltage droop during the HO transitions.
The maximum duty cycle for each output is limited to slightly less than 50% due to the internally fixed deadtime
and any programmed sync rectifier delay. The typical deadtime in this condition is 70 ns. The programmed sync
rectifier delay is determined by the DLY pin resistor. If the COMP pin is open circuit, the outputs will operate at
maximum duty cycle. The maximum duty cycle for each output can be calculated with the following equation:
1
T - T - T1
2 S D
Maximum Duty Cycle =
TS
(3)
Where TS is the period of one complete cycle for either the HO or LO outputs, TD is the internally fixed deadtime,
and T1 is the programmed sync rectifier delay. For example, if the oscillator frequency is 200 kHz, each output
will cycle at 100 kHz (TS = 10 µs). Using the nominal deadtime of 70 ns and no programmed delay, the maximum
duty cycle at this frequency is calculated to be 49.3%. Using a programmed sync rectifier delay of 100 ns, the
maximum duty cycle is reduced to 48.3%.
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HO
SR1
T1
T2
LO
SR2
T1
T2
Figure 17. HO, LO, SR1 and SR2 Timing Diagram
Synchronous Rectifier Control Outputs (SR1 & SR2)
Synchronous rectification (SR) of the transformer secondary provides higher efficiency, especially for low output
voltage converters. The reduction of rectifier forward voltage drop (0.5V - 1.5V) to 10mV - 200mV VDS voltage for
a MOSFET significantly reduces rectification losses. In a typical application, the transformer secondary winding is
center tapped, with the output power inductor in series with the center tap. The SR MOSFETs provide the ground
path for the energized secondary winding and the inductor current. Figure 17 shows that the SR2 MOSFET is
conducting while HO enables power transfer from the primary. The SR1 MOSFET must be disabled during this
period since the secondary winding connected to the SR1 MOSFET drain is twice the voltage of the center tap.
At the conclusion of the HO pulse, the inductor current continues to flow through the SR1 MOSFET body diode.
Since the body diode causes more loss than the SR MOSFET, efficiency can be improved by minimizing the T2
period while maintaining sufficient timing margin over all conditions (component tolerances, etc.) to prevent
shoot-through current. When LO enables power transfer from the primary, the SR1 MOSFET is enabled and the
SR2 MOSFET is off.
During the time that neither HO nor LO is active, the inductor current is shared between both the SR1 and SR2
MOSFETs which effectively shorts the transformer secondary and cancels the inductance in the windings. The
SR2 MOSFET is disabled before LO delivers power to the secondary to prevent power being shunted to ground.
The SR2 MOSFET body diode continues to carry about half the inductor current until the primary power raises
the SR2 MOSFET drain voltage and reverse biases the body diode. Ideally, dead-time T1 would be set to the
minimum time that allows the SR MOSFET to turn off before the SR MOSFET body diode starts conducting.
The SR1 and SR2 outputs are powered directly by the VCC regulator. Each output is capable of sourcing and
sinking 0.5A peak. Typically, the SR1 and SR2 signals control SR MOSFET gate drivers through a pulse
transformer. The actual gate sourcing and sinking currents are provided by the secondary-side bias supply and
gate drivers.
The timing of SR1 and SR2 with respect to HO and LO is shown in Figure 17. SR1 is configured out of phase
with HO and SR2 is configured out of phase with LO. The deadtime between transitions is programmable by a
resistor connected from the DLY pin to the AGND pin. Typically, RDLY is set in the range of 10kΩ to 100kΩ. The
deadtime periods can be calculated using the following formulae:
T1 = .003 x RDLY + 4.6 ns
T2 = .0007 x RDLY + 10.01 ns
(4)
(5)
To set the minimum (propagation delays only) deadtime, the DLY pin should be left open or connected to the
REF pin. Any resistor value above 300kΩ connected between the DLY pin and AGND will also provide the
minimum period (approximately 5 ns).
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Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the integrated circuit in the event the maximum rated
junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power
standby state with the output drivers (HO, LO, SR1 and SR2), the bias regulators (VCC and REF) disabled. This
helps to prevent catastrophic failures from accidental device overheating. During thermal shutdown, the soft-start
capacitor is fully discharged and the controller follows a normal start-up sequence after the junction temperature
falls to the operating level (145°C).
Applications Information
The following information is intended to provide guidelines for the power supply designer using the LM5035A.
VIN
The voltage applied to the VIN pin, which may be the same as the system voltage applied to the power
transformer’s primary (VPWR), can vary in the range of 13 to 105V. The current into VIN depends primarily on the
gate charge provided to the output drivers, the switching frequency, and any external loads on the VCC and REF
pins. It is recommended the filter shown in Figure 18 be used to suppress transients which may occur at the
input supply. This is particularly important when VIN is operated close to the maximum operating rating of the
LM5035A.
When power is applied to VIN and the UVLO pin voltage is greater than 0.4V, the VCC regulator is enabled and
supplies current into an external capacitor connected to the VCC pin. When the voltage on the VCC pin reaches
the regulation point of 7.6V, the voltage reference (REF) is enabled. The reference regulation set point is 5V. The
HO, LO, SR1 and SR2 outputs are enabled when the two bias regulators reach their set point and the UVLO pin
potential is greater than 1.25V. In typical applications, an auxiliary transformer winding is connected through a
diode to the VCC pin. This winding must raise the VCC voltage above 8.3V to shut off the internal start-up
regulator.
After the outputs are enabled and the external VCC supply voltage has begun supplying power to the IC, the
current into VIN drops below 1 mA. VIN should remain at a voltage equal to or above the VCC voltage to avoid
reverse current through protection diodes.
VPWR
50
VIN
LM5035A
0.1 PF
Figure 18. Input Transient Protection
FOR APPLICATIONS >100V
For applications where the system input voltage exceeds 100V or the IC power dissipation is of concern, the
LM5035A can be powered from an external start-up regulator as shown in Figure 19. In this configuration, the
VIN and the VCC pins should be connected together, which allows the LM5035A to be operated below 13V. The
voltage at the VCC pin must be greater than 8.3V yet not exceed 15V. An auxiliary winding can be used to
reduce the power dissipation in the external regulator once the power converter is active. The NPN base-emitter
reverse breakdown voltage, which can be as low as 5V for some transistors, should be considered when
selecting the transistor.
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CURRENT SENSE
The CS pin needs to receive an input signal representative of the transformer’s primary current, either from a
current sense transformer or from a resistor in series with the source of the LO switch, as shown in Figure 20
and Figure 21. In both cases, the sensed current creates a ramping voltage across R1, and the RF/CF filter
suppresses noise and transients. R1, RF and CF should be located as close to the LM5035A as possible, and the
ground connection from the current sense transformer, or R1, should be a dedicated track to the AGND pin. The
current sense components must provide greater than 0.25V at the CS pin when an over-current condition exists.
VPWR
VIN
8.3V - 15V
(from aux winding)
VCC
LM5035A
9V
Figure 19. Start-up Regulator for VPWR >100V
VPWR
Power
Transformer
Current
Sense
Q1
VIN
RF
CS
CF
R1
AGND
HO
Q2
LO
LM5035A
Figure 20. Current Sense Using Current Sense Transformer
VPWR
Power
Transformer
Q1
VIN
HO
Q2
LO
RF
CS
CF
R1
Current
Sense
AGND
LM5035A
Figure 21. Current Sense Using Current Sense Resistor (R1)
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If the current sense resistor method is used, the over-current condition will only be sensed while LO is driving the
low-side MOSFET. Over-current while HO is driving the high-side MOSFET will not be detected. In this
configuration, it will take 4 times as long for continuous cycle-by-cycle current limiting to initiate a restart event
since each over-current event during LO enables the 22µA RES pin current source for one oscillator period, and
then the lack of an over-current event during HO enables the 12µA RES pin current sink for one oscillator period.
The time average of this toggling is equivalent to a continuous 5 µA current source into the RES capacitor,
increasing the delay by a factor of four. The value of the RES capacitor can be reduced to decrease the time
before restart cycle is initiated.
When using the resistor current sense method, an imbalance in the input capacitor voltages may develop when
operating in cycle-by-cycle current limiting mode. If the imbalance persists for an extended period, excessive
currents in the non-sensed MOSFET, and possible transformer saturation may result. This condition is inherent
to the half-bridge topology operated with cycle-by-cycle current limiting and is compounded by only sensing in
one leg of the half-bridge circuit. The imbalance is greatest at large duty cycles (low input voltages). If using this
method, it is recommended that the capacitor on the RES pin be no larger than 220 pF. Check the final circuit
and reduce the RES capacitor further, or omit the capacitor completely to ensure the voltages across the bridge
capacitors remain balanced. The current limit value may decrease slightly as the RES capacitor is reduced.
HO, HB, HS and LO
Attention must be given to the PC board layout for the low-side driver and the floating high-side driver pins HO,
HB and HS. A low ESR/ESL capacitor (such as a ceramic surface mount capacitor) should be connected close
to the LM5035A, between HB and HS to provide high peak currents during turn-on of the high-side MOSFET.
The capacitor should be large enough to supply the MOSFET gate charge (Qg) without discharging to the point
where the drop in gate voltage affects the MOSFET RDS(ON). A value ten to twenty times Qg is recommended.
CBOOST = 20 x
Qg
VCC
(6)
The diode (DBOOST) that charges CBOOST from VCC when the low-side MOSFET is conducting should be capable
of withstanding the full converter input voltage range. When the high-side MOSFET is conducting, the reverse
voltage at the diode is approximately the same as the MOSFET drain voltage because the high-side driver is
boosted up to the converter input voltage by the HS pin, and the high side MOSFET gate is driven to the HS
voltage plus VCC. Since the anode of DBOOST is connected to VCC, the reverse potential across the diode is
equal to the input voltage minus the VCC voltage. DBOOST average current is less than 20mA in most
applications, so a low current ultra-fast recovery diode is recommended to limit the loss due to diode junction
capacitance. Schottky diodes are also a viable option, particularly for lower input voltage applications, but
attention must be paid to leakage currents at high temperatures.
The internal gate drivers need a very low impedance path to the respective decoupling capacitors; the VCC cap
for the LO driver and CBOOST for the HO driver. These connections should be as short as possible to reduce
inductance and as wide as possible to reduce resistance. The loop area, defined by the gate connection and its
respective return path, should be minimized.
The high-side gate driver can also be used with HS connected to PGND for applications other than a half bridge
converter (e.g. Push-Pull). The HB pin is then connected to VCC, or any supply greater than the high-side driver
undervoltage lockout (approximately 6.5V). In addition, the high-side driver can be configured for high voltage
offline applications where the high-side MOSFET gate is driven via a gate drive transformer.
PROGRAMMABLE DELAY (DLY)
The RDLY resistor programs the delays between the SR1 and SR2 signals and the HO and LO driver outputs.
Figure 17 shows the relationship between these outputs. The DLY pin is nominally set at 2.5V and the current is
sensed through RDLY to ground. This current is used to adjust the amount of deadtime before the HO and LO
pulse (T1) and after the HO and LO pulse (T2). Typically RDLY is in the range of 10kΩ to 100kΩ. The deadtime
periods can be calculated using the following formulae:
T1 = .003 x RDLY + 4.6 ns
T2 = .0007 x RDLY + 10.01 ns
(7)
(8)
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T1 and T2 can be set to minimum by not connecting a resistor to DLY, connecting a resistor greater than 300kΩ
from DLY to ground, or connecting DLY to the REF pin. This may cause lower than optimal system efficiency if
the delays through the SR signal transformer network, the secondary gate drivers and the SR MOSFETs are
greater than the delay to turn on the HO or LO MOSFETs. Should an SR MOSFET remain on while the opposing
primary MOSFET is supplying power through the power transformer, the secondary winding will experience a
momentary short circuit, causing a significant power loss to occur.
When choosing the RDLY value, worst case propagation delays and component tolerances should be considered
to assure that there is never a time where both SR MOSFETs are enabled AND one of the primary side
MOSFETs is enabled. The time period T1 should be set so that the SR MOSFET has turned off before the
primary MOSFET is enabled. Conversely, T1 and T2 should be kept as low as tolerances allow to optimize
efficiency. The SR body diode conducts during the time between the SR MOSFET turns off and the power
transformer begins supplying energy. Power losses increase when this happens since the body diode voltage
drop is many times higher than the MOSFET channel voltage drop. The interval of body diode conduction can be
observed with an oscilloscope as a negative 0.7V to 1.5V pulse at the SR MOSFET drain.
UVLO AND OVP VOLTAGE DIVIDER SELECTION FOR R1, R2, AND R3
Two dedicated comparators connected to the UVLO and OVP pins are used to detect under-voltage and overvoltage conditions. The threshold value of these comparators, VUVLO and VOVP, is 1.25V (typical). The two
functions can be programmed independently with two voltage dividers from VIN to AGND as shown in Figure 22
and Figure 23, or with a three-resistor divider as shown in Figure 24. Independent UVLO and OVP pins provide
greater flexibility for the user to select the operational voltage range of the system. Hysteresis is accomplished by
23 µA current sources (IUVLO and IOVP), which are switched on or off into the sense pin resistor dividers as the
comparators change state.
When the UVLO pin voltage is below 0.4V, the controller is in a low current shutdown mode. For a UVLO pin
voltage greater than 0.4V but less than 1.25V the controller is in standby mode. Once the UVLO pin voltage is
greater than 1.25V, the controller is fully enabled. Two external resistors can be used to program the minimum
operational voltage for the power converter as shown in Figure 22. When the UVLO pin voltage falls below the
1.25V threshold, an internal 23 µA current sink is enabled to lower the voltage at the UVLO pin, thus providing
threshold hysteresis. Resistance values for R1 and R2 can be determined from the following equations.
VHYS
R1 =
23 PA
(9)
R2 =
1.25V x R1
VPWR ± 1.25V ± (23 PA x R1)
(10)
where VPWR is the desired turn-on voltage and VHYS is the desired UVLO hysteresis at VPWR.
For example, if the LM5035A is to be enabled when VPWR reaches 34V, and disabled when VPWR is decreased
to 32V, R1 should be 87 kΩ, and R2 should be 3.54kΩ. The voltage at the UVLO pin should not exceed 7V at
any time. Be sure to check both the power and voltage rating (0603 resistors can be rated as low as 50V) for the
selected R1 resistor.
VPWR
LM5035A
R1
UVLO
1.25V
Disable Output Drivers
23 PA
R2
0.4V
Disable VCC and REF Regulators
Figure 22. Basic UVLO Configuration
22
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VPWR
LM5035A
5V
23 PA
R1
OVP
STANDBY
1.25V
R2
Figure 23. Basic Over-Voltage Protection
VPWR
LM5035A
R1
UVLO
1.25V
Disable Output Drivers
23 PA
0.4V
R2
Disable VCC and REF Regulators
5V
23 PA
OVP
1.25V
STANDBY
R3
Figure 24. UVLO/OVP Divider
The impedance seen looking into the resistor divider from the UVLO and OVP pins determines the hysteresis
level. UVLO and OVP enable and disable thresholds are calculated using the equations in the table below for the
three-resistor divider illustrated in Figure 24.
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Table 1. UVO/OVP Divider Formulas
§ R1
UVLOoff = 1.25V x ¨¨
©
(11)
UVLOon = UVLOoff + (23 µA x R1)
Outputs disabled due to VIN rising above OVP threshold
§ R1
OVPoff = 1.25V x ¨¨
©
Outputs enabled due to VIN falling below OVP threshold
+ R2 + R 3
R3
§
¨
¨
©
Outputs enabled due to VIN rising above UVLO threshold
+ R2 + R 3
R2 + R3
§
¨
¨
©
Outputs disabled due to VIN falling below UVLO threshold
(12)
OVPon = OVPoff - [23 µA x (R1 + R2)]
The typical operating ranges of undervoltage and overvoltage thresholds are calculated from the above
equations. For example, for resistor values R1 = 86.6kΩ, R2 = 2.10kΩ and R3 = 1.40kΩ the computed
thresholds are:
UVLO turn-off = 32.2V
UVLO turn-on = 34.2V
OVP turn-on = 78.4V
OVP turn-off = 80.5V
VPWR
LM5035A
R1
UVLO
1.25V
STANDBY
23 PA
OFF
STANDBY
0.4V
OFF
R2
Figure 25. Remote Standby and Disable Control
To maintain the threshold’s accuracy, a resistor tolerance of 1% or better is recommended.
The design process starts with the choice of the voltage difference between the UVLO enabling and disabling
thresholds. This will also approximately set the difference between OVP enabling and disabling regulation:
UVLOon - UVLOoff
R1 =
23 PA
(13)
Next, the combined resistance of R2 and R3 is calculated by choosing the threshold for the UVLO disabling
threshold:
1.25V x R1
RCOMBINED =
UVLOoff ± 1.25V
(14)
Then R3 is determined by selecting the OVP disabling threshold:
1.25V x (R1 + RCOMBINED)
R3 =
OVPoff
(15)
Finally, R3 is subtracted from RCOMBINED to give R2:
R2 = RCOMBINED - R3
24
(16)
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Remote configuration of the controller’s operational modes can be accomplished with open drain device(s)
connected to the UVLO pin as shown in Figure 25.
FAULT PROTECTION
The Over Voltage Protection (OVP) comparator of the LM5035A can be configured for line or load fault protection
or thermal protection using an external temperature sensor or thermistor. Figure 23 shows a line over voltage
shutdown application using a voltage divider between the input power supply, VPWR, and AGND to monitor the
line voltage.
Figure 26 demonstrates the use of the OVP pin for latched output over-voltage fault protection, using a zener
and opto-coupler. When VOUT exceeds the conduction threshold of the opto-coupler diode and zener, the optocoupler momentarily turns on Q1 and the LM5035A enters standby mode, disabling the drivers and enabling the
hysteresis current source on the OVP pin. Once the current source is enabled, the OVP voltage will remain at
2.3V (23 µA x 100 kΩ) without additional drive from the external circuit. If the opto-coupler transistor emitter were
directly connected to the OVP pin, then leakage current in the zener diode amplified by the opto-coupler’s gain
could falsely trip the protection latch. R1 and Q1 are added reduce the sensitivity to low level currents in the
opto-coupler. Using the values of Figure 26, the opto-coupler collector current must equal VBE(Q1) / R1 = 350 µA
before OVP latches. Once the controller has switched to standby mode, the outputs no longer switch but the
VCC and REF regulators continue functioning and supply bias to the external circuitry. VCC must fall below 6.2V
or the UVLO pin must fall below 0.4V to clear the OVP latch.
VREF
VOUT
R1
2k
LM5035A
5V
23 PA
Q1
OVP
R2
100k
1.25V
STANDBY
Figure 26. Latched Load Over-Voltage Protection
Figure 27 shows an application of the OVP comparator for Remote Thermal Protection using a thermistor (or
multiple thermistors) which may be located near the main heat sources of the power supply. The negative
temperature coefficient (NTC) thermistor is nearly logarithmic, and in this example a 100kΩ thermistor with the β
material constant of 4500 kelvins changes to approximately 2 kΩ at 130°C. Setting R1 to one-third of this
resistance (665Ω) establishes 130°C as the desired trip point (for VREF = 5V). In a temperature band from 20°C
below to 20°C above the OVP threshold, the voltage divider is nearly linear with 25 mV per°C sensitivity.
R2 provides temperature hysteresis by raising the OVP comparator input by R2 x 23 µA. For example, if a 22kΩ
resistor is selected for R2, then the OVP pin voltage will increase by 22 kΩ x 23 µA = 506 mV. The NTC
temperature must therefore fall by 506mV / 25mV per°C = 20°C before the LM5035A switches from the standby
mode to the normal mode.
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VREF
LM5035A
5V
23 PA
NTC
THERMISTOR
T
R2
OVP
STANDBY
1.25V
R1
Figure 27. Remote Thermal Protection
HICCUP MODE CURRENT LIMIT RESTART (RES)
The basic operation of the hiccup mode current limit restart is described in the functional description. The delay
time to restart is programmed with the selection of the RES pin capacitor CRES as illustrated in Figure 27.
In the case of continuous cycle-by-cycle current limit detection at the CS pin, the time required for CRES to reach
the 2.5V hiccup mode threshold is:
t1 =
CRES x 2.5V
22 PA
= 114 k: x CRES
(17)
For example, if CRES = 0.01 µF the time t1 is approximately 1.14 ms.
The cool down time, t2 is set by the soft-start capacitor (CSS) and the internal 1 µA SS current source, and is
equal to:
t2 =
CSS x 1V
1 PA
= 1 M: x CSS
(18)
If CSS = 0.01 µF t2 is ≊10 ms.
The soft-start time t3 is set by the internal 110 µA current source, and is equal to:
t3 =
CSS x 4V
= 40 k: x CSS
110 PA
(19)
If CSS = 0.01 µF t3 is ≊363 µs.
The time t2 provides a periodic cool-down time for the power converter in the event of a sustained overload or
short circuit. This off time results in lower average input current and lower power dissipation within the power
components. It is recommended that the ratio of t2 / (t1 + t3) be in the range of 5 to 10 to take advantage of this
feature.
If the application requires no delay from the first detection of a current limit condition to the onset of the hiccup
mode (t1 = 0), the RES pin can be left open (no external capacitor). If it is desired to disable the hiccup mode
entirely, the RES pin should be connected to ground (AGND).
26
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2.5V
Current Limit Detected
at CS
RES
0V
5V
+110 PA
#1V
+1 PA
SS
LO
HO
t1
t2
t3
Figure 28. Hiccup Over-Load Restart Timing
Printed Circuit Board Layout
The LM5035A Current Sense and PWM comparators are very fast, and respond to short duration noise pulses.
The components at the CS, COMP, SS, OVP, UVLO, DLY and the RT pins should be as physically close as
possible to the IC, thereby minimizing noise pickup on the PC board tracks.
Layout considerations are critical for the current sense filter. If a current sense transformer is used, both leads of
the transformer secondary should be routed to the sense filter components and to the IC pins. The ground side
of the transformer should be connected via a dedicated PC board track to the AGND pin, rather than through the
ground plane.
If the current sense circuit employs a sense resistor in the drive transistor source, low inductance resistors
should be used. In this case, all the noise sensitive, low-current ground tracks should be connected in common
near the IC, and then a single connection made to the power ground (sense resistor ground point).
The gate drive outputs of the LM5035A should have short, direct paths to the power MOSFETs in order to
minimize inductance in the PC board traces. The SR control outputs should also have minimum routing distance
through the pulse transformers and through the secondary gate drivers to the sync FETs.
The two ground pins (AGND, PGND) must be connected together with a short, direct connection, to avoid jitter
due to relative ground bounce.
If the internal dissipation of the LM5035A produces high junction temperatures during normal operation, the use
of multiple vias under the IC to a ground plane can help conduct heat away from the IC. Judicious positioning of
the PC board within the end product, along with use of any available air flow (forced or natural convection) will
help reduce the junction temperatures. If using forced air cooling, avoid placing the LM5035A in the airflow
shadow of tall components, such as input capacitors.
Application Circuit Example
The following schematic shows an example of a 100W half-bridge power converter controlled by the LM5035A.
The operating input voltage range (VPWR) is 36V to 75V, and the output voltage is 3.3V. The output current
capability is 30 Amps. Current sense transformer T2 provides information to the CS pin for current limit
protection. The error amplifier and reference, U3 and U5 respectively, provide voltage feedback via opto-coupler
U4. Synchronous rectifiers Q4, Q5, Q6 and Q7 minimize rectification losses in the secondary. An auxiliary
winding on transformer T1 provides power to the LM5035A VCC pin when the output is in regulation. The input
voltage UVLO thresholds are ≊34V for increasing VPWR, and ≊32V for decreasing VPWR. The circuit can be shut
down by driving the ON/OFF input (J2) below 1.25V with an open-collector or open-drain circuit. An external
synchronizing frequency can be applied through a 100pF capacitor to the RT input (U1 pin 5). The regulator
output is current limited at ≊34A.
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Table 2. Differences between LM5035, LM5035A, LM5035A-1, LM5035B, and LM5035C (1) (2)
Performance Feature:
LM5035
LM5035A
LM5035A-1
LM5035B
LM5035C
2:1
3:1
3:1
3:1
3:1
Soft-start: Hiccup Mode Charging
Current
50µA:1µA
100µA:1µA
100µA:1µA
100µA:1µA
100µA:1µA
Bootstrap (HB-HS) Under-Voltage
Lockout
5V
3.9V
3.9V
3.9V
3.9V
20mA (min)
25mA (min)
25mA (min)
40mA (min)
40mA (min)
High
High
High
Low
Low
Sync Rectifier Dead-time Ratio
(T1:T2)
Start-up Regulator Current
SR State in UVLO Shutdown and
Hiccup Current Limit
HO,LO On-Time at Max Duty Cycle
Soft-Stop after
UVLO
0.5*T-T1–70 ns
0.5*T-T1–70 ns
0.5*T-T1–70 ns
0.5*T-T1
0.5*T-T1
HO,LO
Yes
Yes
Yes
Yes
No
SR1,2
Yes
Yes
Yes
No
No
SR1, SR2 VOH (high state output)
Package
(1)
(2)
28
VCC
VCC
VCC
VCC
REF (5V)
HTSSOP-20,
WQFN-24
HTSSOP-20,
WQFN-24
HTSSOP-28
HTSSOP–20,
WQFN-24
HTSSOP-20,
WQFN-24
T1 = Delay from SR1, SR2 to leading edge of HO, LO
T = Period of HO or LO
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Figure 29. Evaluation Board Schematic
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REVISION HISTORY
Changes from Revision E (April 2013) to Revision F
•
30
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 29
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM5035AMH-1/NOPB
ACTIVE
HTSSOP
PWP
28
48
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5035
AMH-1
LM5035AMH/NOPB
ACTIVE
HTSSOP
PWP
20
73
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5035AMHX-1/NOPB
ACTIVE
HTSSOP
PWP
28
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LM5035AMHX/NOPB
ACTIVE
HTSSOP
PWP
20
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LM5035
AMH
LM5035ASQ/NOPB
ACTIVE
WQFN
NHZ
24
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
5035ASQ
-40 to 125
LM5035
AMH
LM5035
AMH-1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
8-Oct-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
LM5035AMHX-1/NOPB
HTSSOP
PWP
28
2500
330.0
16.4
LM5035AMHX/NOPB
HTSSOP
PWP
20
2500
330.0
LM5035ASQ/NOPB
WQFN
NHZ
24
1000
178.0
6.8
10.2
1.6
8.0
16.0
Q1
16.4
6.95
7.1
1.6
8.0
16.0
Q1
12.4
4.3
5.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5035AMHX-1/NOPB
HTSSOP
PWP
28
2500
367.0
367.0
35.0
LM5035AMHX/NOPB
HTSSOP
PWP
20
2500
367.0
367.0
35.0
LM5035ASQ/NOPB
WQFN
NHZ
24
1000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
PWP0020A
MXA20A (Rev C)
www.ti.com
PACKAGE OUTLINE
PWP0028A
PowerPAD TM - 1.1 mm max height
SCALE 1.800
PLASTIC SMALL OUTLINE
C
6.6
TYP
6.2
A
SEATING PLANE
PIN 1 ID
AREA
28
1
9.8
9.6
NOTE 3
0.1 C
26X 0.65
2X
8.45
14
B
15
4.5
4.3
NOTE 4
0.30
0.19
0.1
C A
28X
1.1 MAX
B
0.20
TYP
0.09
SEE DETAIL A
3.15
2.75
0.25
GAGE PLANE
5.65
5.25
THERMAL
PAD
0 -8
0.10
0.02
0.7
0.5
(1)
DETAIL A
TYPICAL
4214870/A 10/2014
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MO-153, variation AET.
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EXAMPLE BOARD LAYOUT
PWP0028A
PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(3.4)
NOTE 9
(3)
SOLDER
MASK
OPENING
28X (1.5)
28X (0.45)
SOLDER MASK
DEFINED PAD
1
28X (0.45)
28X (1.3)
28
26X
(0.65)
SYMM
(5.5)
(9.7)
SOLDER
MASK
OPENING
(1.3) TYP
14
15
( 0.2) TYP
VIA
(1.3)
SEE DETAILS
SYMM
(0.9) TYP
METAL COVERED
BY SOLDER MASK
(0.65) TYP
(5.8)
(6.1)
HV / ISOLATION OPTION
0.9 CLEARANCE CREEPAGE
OTHER DIMENSIONS IDENTICAL TO IPC-7351
IPC-7351 NOMINAL
0.65 CLEARANCE CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214870/A 10/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
PWP0028A
PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE
(3)
BASED ON
0.127 THICK
STENCIL
28X (1.5)
28X (0.45)
METAL COVERED
BY SOLDER MASK
1
28X (1.3)
28
26X (0.65)
28X (0.45)
(5.5)
BASED ON
0.127 THICK
STENCIL
SYMM
14
15
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SYMM
(5.8)
(6.1)
HV / ISOLATION OPTION
0.9 CLEARANCE CREEPAGE
OTHER DIMENSIONS IDENTICAL TO IPC-7351
IPC-7351 NOMINAL
0.65 CLEARANCE CREEPAGE
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE AREA
SCALE:6X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.127
0.152
0.178
3.55 X 6.37
3.0 X 5.5 (SHOWN)
2.88 X 5.16
2.66 X 4.77
4214870/A 10/2014
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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MECHANICAL DATA
NHZ0024B
SQA24B (Rev A)
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