LANSDALE ML145051RP 10-bit a/d converter with serial interface Datasheet

ML145050
ML145051
10-Bit A/D Converter
with Serial Interface - CMOS
Legacy Device: Motorola MC145050, MC145051
These ratio metric 10-bit ADCs have serial interface ports to provide
communication with MCUs and MPUs. Either a 10- or 16-bit format
can be used. The 16-bit format can be one continuous 16-bit stream or
two intermittent 8-bit streams. The converters operate from a single
power supply with no external trimming required. Reference voltages
down to 4.0 V are accommodated.
The ML145050 has the same pin out as the 8-bit ML145040 which
allows an external clock (ADCLK) to operate the dynamic A/D conversion sequence. The ML145051 has the same pin out as the 8-bit
ML145041 which has an internal clock oscillator and an end-of-conversion (EOC) output.
• 11 Analog Input Channels with Internal Sample-and-Hold
• Operating Temperature Range: – 40 to 125°C
• Successive Approximation Conversion Time:
ML145050 – 21 µs (with 2.1 MHz ADCLK)
ML145051 – 44 µs Maximum
• Maximum Sample Rate:
ML145050 – 38 ks/s
ML145051 – 20.4 ks/s
• Analog Input Range with 5-Volt Supply: 0 to 5 V
• Monotonic with No Missing Codes
• Direct Interface to Motorola SPI and National MICROWIRE
Serial Data Ports
• Digital Inputs/Outputs are TTL, NMOS, and CMOS Compatible
• Low Power Consumption: 14 mW
• Chip Complexity: 1630 Elements (FETs, Capacitors, etc.)
• See Application Note AN1062 for Operation with QSPI
P DIP 20 = RP
PLASTIC
CASE 738
SO 20W = -6P
SOG
CASE 751D
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 20
MC145050P
ML145050RP
SOG 20W
MC145050DW
ML145050-6P
P DIP 20
MC145051P
ML145051RP
SOG 20W
MC145051DW
ML145051-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
*ADCLK (ML145050); EOC (ML145051)
AN0
1
20
VDD
AN1
2
19
*
AN2
3
18
SCLK
AN3
4
17
Din
AN4
5
16
Dout
AN5
6
15
CS
AN6
7
14
Vref
AN7
8
13
VAG
AN8
9
12
AN10
VSS
10
11
AN9
MICROWARE is A Trademark Of National Semiconductor Corp.
Page 1 of 15
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LANSDALE Semiconductor, Inc.
ML145050, ML145051
BLOCK DIAGRAM
AN0 1
AN1 2
AN2 3
AN3 4
Vref
INTERNAL
TEST
VOLTAGES
ANALOG
MUX
AN7 8
9
AN8
11
AN9
AN10 12
AN11
AN12
AN13
17
Din
16
Dout
CS
SCLK
ADCLK (ML145050 ONLY)
EOC (ML145051 ONLY)
14
13
10-BIT RC DAC
WITH SAMPLE AND HOLD
MUX OUT
AN4 5
AN5 6
AN6 7
VAG
SUCCESSIVE APPROXIMATION
REGISTER
MUX ADDRESS
REGISTER
DATA REGISTER
AUTO-ZEROED
COMPARATOR
15
18
19
PIN 20 = VDD
PIN 10 = VSS
DIGITAL CONTROL
LOGIC
19
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage (Referenced to VSS)
– 0.5 to + 6.0
V
Vref
DC Reference Voltage
VAG to VDD + 0.1
V
VAG
Analog Ground
VSS – 0.1 to Vref
V
Vin
DC Input Voltage, Any Analog or Digital
Input
VSS – 0.5 to
VDD + 0.5
V
Vout
DC Output Voltage
VSS – 0.5 to
VDD + 0.5
V
DC Input Current, per Pin
± 20
mA
DC Output Current, per Pin
± 25
mA
DC Supply Current, VDD and VSS Pins
± 50
mA
– 65 to 150
C
260
C
Iin
Iout
IDD, ISS
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for
10 Seconds
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications
of any voltage higher than maximum rated
voltages to this high-impedance circuit. For
proper operation, Vin and Vout should be
constrained to the range VSS ≤ (Vin or Vout) ≤
VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VDD). Unused outputs must be left
open.
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Operation Ranges below..
OPERATION RANGES (Applicable to Guaranteed Limits)
Parameter
Value
Unit
4.5 to 5.5
V
DC Reference Voltage
VAG + 4.0 to VDD + 0.1
V
VAG
Analog Ground
VSS – 0.1 to Vref – 4.0
V
VAI
Analog Input Voltage (See Note)
VAG to Vref
V
Digital Input Voltage, Output Voltage
VSS to VDD
V
Symbol
VDD
DC Supply Voltage, Referenced to V SS
Vref
Vin, Vout
TA
Ambient Operating Temperature
– 40 to 125
C
NOTE: Analog input voltages greater than V ref convert to full scale. Input voltages less than V AG convert to zero. See V ref and VAG pin
descriptions.
Page 2 of 15
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DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to VSS, Full Temperature and Voltage Ranges per Operation Ranges Table, unless otherwise indicated)
Parameter
Symbol
Test Condition
Guaranteed
Limit
Unit
VIH
Minimum High-Level Input Voltage
(Din, SCLK, CS, ADCLK)
2.0
V
VIL
Maximum Low-Level Input Voltage
(Din, SCLK, CS, ADCLK)
0.8
V
VOH
Minimum High-Level Output Voltage
(Dout, EOC)
Iout = – 1.6 mA
Iout = – 20 µA
2.4
VDD – 0.1
V
VOL
Minimum Low-Level Output Voltage
(Dout, EOC)
Iout = + 1.6 mA
Iout = 20 µA
0.4
0.1
V
Maximum Input Leakage Current
(Din, SCLK, CS, ADCLK)
Vin = VSS or VDD
+ 2.5
µA
IOZ
Maximum Three-State Leakage Current (Dout)
Vout = VSS or VDD
+ 10
µA
IDD
Maximum Power Supply Current
Vin = VSS or VDD, All Outputs Open
2.5
mA
Iref
Maximum Static Analog Reference Current (Vref)
Vref = VDD, VAG = VSS
100
µA
IAl
Maximum Analog Mux Input Leakage Current between all
deselected inputs and any selected input (AN0 ± AN10)
VAl = VSS to VDD
+1
µA
Iin
A/D CONVERTER ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table; ML145050: 500 kHz ≤ ADCLK ≤ 2.1 MHz, unless otherwise noted)
Characteristic
Definition and Test Conditions
Guaranteed
Limit
Unit
Resolution
Number of bits resolved by the A/D converter
10
Bits
Maximum Nonlinearity
Maximum difference between an ideal and an actual ADC transfer function
±1
LSB
Maximum Zero Error
Difference between the maximum input voltage of an ideal and an actual
ADC for zero output code
±1
LSB
Maximum Full-Scale Error
Difference between the minimum input voltage of an ideal and an actual
ADC for full-scale output code
±1
LSB
Maximum Total Unadjusted Error
Maximum sum of nonlinearity, zero error, and full-scale error
±1
LSB
Maximum Quantization Error
Uncertainty due to converter resolution
± 1/2
LSB
Absolute Accuracy
Difference between the actual input voltage and the full-scale weighted
equivalent of the binary output code, all error sources included
± 1-1/2
LSB
Maximum Conversion Time
Total time to perform a single analog-to-digital conversion
ML145050
44
ML145051
44
ADCLK
cycles
µs
Data Transfer Time
Total time to transfer digital serial data into and out of the device
Sample Acquisition Time
Analog input acquisition time window
Minimum Total Cycle Time
Total time to transfer serial data, sample the analog input, and perform the
conversion
ML145050: ADCLK = 2.1 MHz, SCLK = 2.1 MHz
ML145051: SCLK = 2.1 MHz
Maximum Sample Rate
Page 3 of 15
Rate at which analog inputs may be sampled
ML145050: ADCLK = 2.1 MHz, SCLK = 2.1 MHz
ML145051: SCLK = 2.1 MHz
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10 to 16
SCLK
cycles
6
SCLK
cycles
µs
26
49
ks/s
38
20.4
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ML145050, ML145051
AC ELECTRICAL CHARACTERISTICS
(Full Temperature and Voltage Ranges per Operation Ranges Table)
Figure
Symbol
1
f
Guaranteed
Limit
Parameter
Clock Frequency, SCLK
Unit
Note: Refer to t wH, twL below
(10-bit xfer) Min
(11- to 16-bit xfer) Min
(10- to 16-bit xfer) Max)
0
Note 1
2.1
MHz
Clock Frequency, ADCLK
Note: Refer to t wH, twL below
Minimum
Maximum
500
2.1
kHz
MHz
1
f
1
twH
Minimum Clock High Time
ADCLK
SCLK
190
190
ns
1
twL
Minimum Clock Low Time
ADCLK
SCLK
190
190
ns
1, 7
tPLH, tPHL
Maximum Propagation Delay, SCLK to Dout
125
ns
1, 7
th
Minimum Hold Time, SCLK to Dout
10
ns
2, 7
tPLZ, tPHZ
Maximum Propagation Delay, CS to Dout High-Z
150
ns
2, 7
tPZL, tPZH
Maximum Propagation Delay, CS to Dout Driven
2 ADCLK cycles + 300
2.3
ns
µs
3
tsu
Minimum Setup Time, Din to SCLK
100
ns
3
th
Minimum Hold Time, SCLK to Din
0
ns
4, 7, 8
td
Maximum Delay Time, EOC to Dout (MSB)
ML145051
100
ns
5
tsu
Minimum Setup Time, CS to SCLK
ML145050
ML145051
2 ADCLK cycles + 425
2.425
ns
µs
–
tCSd
Minimum Time Required Between 10th SCLK Falling
Edge ( 0.8 V) and CS to Allow a Conversion
ML145050
ML145051
44
Note 2
ADCLK
cycles
–
tCAs
Maximum Delay Between 10th SCLK Falling Edge
( 2 V) and CS to Abort a Conversion
ML145050
36
ML145051
9
ADCLK
cycles
µs
0
ns
ML145051
2.35
µs
SCLK
ADCLK
Din, CS
1
250
10
ms
ns
µs
5
th
6, 8
tPHL
Maximum Propagation Delay, 10th SCLK to EOC
1
tr, tf
Maximum Input Rise and Fall Times
1, 4, 6 – 8
tTLH, tTHL
–
Cin
–
Cout
ML145050
ML145051
Minimum Hold Time, Last SCLK to CS
Maximum Output Transition Time, Any Output
Maximum Input Capacitance
300
ns
AN0 – AN10
ADCLK, SCLK, CS, Din
55
15
pF
Dout
15
pF
Maximum Three-State Output Capacitance
NOTES:
1. After the 10th SCLK falling edge (≤ 2 V), at least 1 SCLK rising edge (≥ 2 V) must occur within 38 ADCLKs (ML145050) or 18.5 µs
(ML145051).
2. On the ML145051, a CS edge may be received immediately after an active transition on the EOC pin.
Page 4 of 15
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ML145050, ML145051
SWITCHING WAVEFORMS
twL
SCLK
twH
tr
tf
2.0 V
0.8 V
2.0 V
CS
1/f
0.8 V
tPLH, tPHL
tPZH, tPZL
th
tPHZ, tPLZ
2.4 V
Dout
0.4 V
tTLH, tTHL
90%
2.4 V
0.4 V
Dout
Figure 1.
10%
Figure 2.
tTLH
EOC
VALID
2.4 V
0.4 V
2.0 V
0.8 V
Din
td
2.4 V
th
tsu
0.4 V
Dout
VALID MSB
2.0 V
SCLK
0.8 V
NOTE: Dout is driven only when CS is active (low).
Figure 3.
Figure 4.
2.0 V
CS
tsu
SCLK
SCLK
0.8 V
0.8 V
10TH
CLOCK
0.8 V
tPHL
th
FIRST
CLOCK
2.4 V
EOC
LAST
CLOCK
0.4 V
0.8 V
tTHL
Figure 5.
Figure 6.
VDD
TEST
POINT
VDD
TEST
POINT
2.18 k
Dout
DEVICE
UNDER
TEST
12 k
DEVICE
UNDER
TEST
100 pF
Figure 7. Test Circuit
Page 5 of 15
2.18 k
EOC
12 k
50 pF
Figure 8. Test Circuit
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PIN DESCRIPTIONS
DIGITAL INPUTS AND OUTPUT
The various serial bit-stream formats for the ML145050/51
are illustrated in the timing diagrams of Figures 9 through 14.
Table 1 assists in selection of the appropriate diagram. Note
that the ADCs accept 16 clocks which makes them SPI (Serial
Peripheral Interface) compatible.
Table 1. Timing Diagram Selection
No. of Clocks in
Serial Transfer
Using
CS
10
10
11 to 16
16
11 to 16
16
Yes
No
Yes
No
Yes
No
Serial Transfer
Interval
Don't Care
Don't Care
Shorter than Conversion
Shorter than Conversion
Longer than Conversion
Longer than Conversion
Figure
No.
9
10
11
12
13
14
CS
Active-Low Chip Select Input (Pin 15)
Chip select initializes the chip to perform conversions and
provides 3-state control of the data output pin (Dout). While
inactive high, CS forces Dout to the high-impedance state and
disables the data input (Din) and serial clock (SCLK) pins. A
high-to-low transition on CS resets the serial dataport and synchronizes it to the MPU data stream. CS can remain active
during the conversion cycle and can stay in the active low state
for multiple serial transfers or CS can be in active high after
each transfer. If CS is kept active low between transfers, the
length of each transfer is limited to either 10 or 16 SCLK
cycles. If CS is in the inactive high state between transfers,
each transfer can be anywhere from 10 to16 SCLK cycles
long. See the SCLK pin description for a more detailed discussion of these requirements.
On the ML145050/51 spurious chip selects caused by system
noise are minimized by the internal circuitry.
Any transitions on the ML145050 CS pin are recognized as
valid only if the level is maintained for a setup time plus two
falling edges of ADCLK after the transition.
Transitions on the ML145051 CS pin are recognized as valid
only if the level is maintained for about 2 ms after the transition.
NOTE
If CS is inactive high after the 10th SCLK cycleand then goes active low before the A/D conversion
is complete, the conversion is aborted and the chip
enters the initial state, ready for another serial transfer/conversion sequence. At this point, the output
data register contains the result from the conversion
before the aborted conversion. Note that the last
step of the A/D conversion sequence is to update the
output data register with the result. Therefore, if CS
goes active low in an attempt to abort the conversion too close to the end of the conversion
sequence, the result register may be corrupted and
the chip could be thrown out of sync with the
processor until CS is toggled again (refer to the AC
Electrical Characteristics in the spec tables).
Page 6 of 15
Dout
Serial Data Output of the A/D Conversion Result(Pin 16)
This output is in the high-impedance state when CS is in
active high. When the chip recognizes a valid active low on
CS, Dout is taken out of the high-impedance state and is driven with the MSB of the previous conversion result. (For thefirst transfer after power-up, data on Dout is undefined for the
entire transfer.) The value on Dout changes to the second most
significant result bit upon the first falling edge of SCLK. The
remaining result bits are shifted out in order, with the LSB
appearing on Dout upon the ninth falling edge of SCLK. Note
that the order of the transfer is MSB to LSB. Upon the 10th
falling edge of SCLK, Dout is immediately driven low (if
allowed by CS) so that transfers of more than 10 SCLKs read
zeroes as the unused LSBs.
When CS is held active low between transfers, Dout is driven from a low level to the MSB of the conversion result for
three cases: Case 1 – upon the 16th SCLK falling edge if the
transfer is longer than the conversion time (Figure 14); Case 2
– upon completion of a conversion for a 16-bit transfer interval
shorter than the conversion (Figure 12); Case 3– upon completion of a conversion for a 10-bit transfer (Figure 10).
Din
Serial Data Input (Pin 17)
The four-bit serial input stream begins with the MSB of the
analog mux address (or the user test mode) that is to be converted next. The address is shifted in on the first four rising
edges of SCLK. After the four mux address bits have been
received, the data on Din is ignored for the remainder of the
present serial transfer. See Table 2 in Applications Information.
SCLK
Serial Data Clock (Pin 18)
This clock input drives the internal I/O state machine to perform three major functions: (1) drives the data shift registers to
simultaneously shift in the next mux address from the Din pin
and shift out the previous conversion result on the Dout pin,
(2) begins sampling the analog voltage onto the RCDAC as
soon as the new mux address is available, and (3) transfers
control to the A/D conversion state machine (driven by
ADCLK) after the last bit of the previous conversion result has
been shifted out on the Dout pin.
The serial data shift registers are completely static, allowing
SCLK rates down to the DC. There are some cases, however,
that require a minimum SCLK frequency as discussed later in
this section. SCLK need not be synchronous to ADCLK. At
least ten SCLK cycles are required for each simultaneous data
transfer. If the 16-bit format is used, SCLK can be one continuous 16-bit stream or two intermittent 8-bit streams. After the
serial port has been initiated to perform a serial transfer*, the
new mux address is shifted in on the first
*The serial port can be initiated in three ways: (1) a recognized CS falling edge, (2) the end of an A/D conversion if the
port is perform-ing either a 10-bit or a 16-bit “shorter-thanconversion” transfer with CS active low between transfers,
and (3) the 16th falling edge of SCLK if the port is performing 16-bit “longer-than-conversion” transfers with CS active
low between transfers.
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four rising edges of SCLK, and the previous 10-bit conversion
result is shifted out on the first nine falling edges of SCLK.
After the fourth rising edge of SCLK, the new mux address is
available; therefore, on the next edge of SCLK (the fourth
falling edge), the analog input voltage on the selected mux
input begins charging the RC DAC and continues to do so until
the tenth falling edge of SCLK. After this tenth SCLK edge,
the analog input voltage is disabled from the RC DAC and the
RC DAC begins the “hold” portion of the A/D conversion
sequence. Also upon this tenth SCLK edge, control of the
internal circuitry is transferred to ADCLK which drives the
successive approximation logic to complete the conversion. If
16 SCLK cycles are used during each transfer, then there is a
constraint on the minimum SCLK frequency. Specifically,
there must be at least one rising edge on SCLK before the A/D
conversion is complete. If the SCLK frequency is too low and
a rising edge does not occur during the conversion, the chip is
thrown out of sync with the processor and CS needs to be toggled in order to restore proper operation. If 10 SCLKs are used
per transfer, then there is no lower frequency limit on SCLK.
Also note that if the ADC is operated such that CS is inactive
high between transfers, then the number of SCLK cycles per
transfer can be anything between 10 and 16 cycles, but the
“rising edge” constraint is still in effect if more than 10
SCLKs are used. (If CS stays active low for multiple transfers,
the number of SCLK cycles must be either 10 or 16.)
ADCLK
A/D Conversion Clock Input (Pin 19, ML145050 Only)
This pin clocks the dynamic A/D conversion sequence, and
may be asynchronous to SCLK. Control of the chip passes to
ADCLK after the tenth falling edge of SCLK. Control of the
chip is passed back to SCLK after the successive approximation conversion sequence is complete (44 ADCLK cycles), or
after a valid chip select is recognized. ADCLK also drives the
CS recognition logic. The chip ignores transitions on CS unless
the state remains for a setup time plus two falling edges of
ADCLK. The source driving ADCLK must be free running.
EOC
End-of-Conversion Output (Pin 19, ML145051 Only)
EOC goes low on the tenth falling edge of SCLK. A low-tohigh transition on EOC occurs when the A/D conversion is
complete and the data is ready for transfer.
ANALOG INPUTS AND TEST MODE
AN0 through AN10
Analog Multiplexer Inputs (Pins 1 – 9, 11, 12)
The input AN0 is addressed by loading $0 into the mux ad-
Page 7 of 15
dress register. AN1 is addressed by $1, AN2 by $2, 0, AN10 by
$A. Table 2 shows the input format for a 16-bit stream. The
mux features a break-before-make switching structure to minimize noise injection into the analog inputs. The source resistance driving these inputs must be ≤1 kΩ.
During normal operation, leakage currents through the analog mux from unselected channels to a selected channel and
leakage currents through the ESD protection diodes on the
selected channel occur. These leakage currents cause an offset
voltage to appear across any series source resistance on the
selected channel. Therefore, any source resistance greater than
1 kΩ (Lansdale test condition) may induce errors in excess of
guaranteed specifications.
There are three tests available that verify the functionality of
all the control logic as well as the successive approximation
comparator. These tests are performed by addressing $B, $C,
or $D and they convert a voltage of (Vref + VAG)/2,VAG, or
Vref, respectively. The voltages are obtained internally by sampling Vref or VAG onto the appropriate elements of the RC
DAC during the sample phase. Addressing $B, $C, or $D produces an output of $200 (half scale), $000, or $3FF (full
scale), respectively, if the converter is functioning properly.
However, deviation from these values occurs in the presence of
sufficient system noise (external to the chip) on VDD, VSS,
Vref, or VAG.
POWER AND REFERENCE PINS
VSS and VDD
Device Supply Pins (Pins 10 and 20)
VSS is normally connected to digital ground; VDD is connected to a positive digital supply voltage. Low frequency
(VDD – VSS) variations over the range of 4.5 to 5.5 volts do
not affect the A/D accuracy. (See the Operations Ranges Table
for restrictions on Vref and VAG relative to VDD and VSS.)
Excessive inductance in the VDD or VSS lines, as on automatic test equipment, may cause A/D offsets > ± 1 LSB. Use of a
0.1 µF bypass capacitor across these pins is recommended.
VAG and Vref
Analog Reference Voltage Pins (Pins 13 and 14)
Analog reference voltage pins which determine the lower
and upper boundary of the A/D conversion. Analog input voltages ≤ Vref produce a full scale output and input voltages ≤
VAG produce an output of zero. CAUTION: The analog input
voltage must be ≥ VSS and ≤ VDD. The A/D conversion result
is ratio metric to Vref – VAG. Vref and VAG must be as noisefree as possible to avoid degradation of the A/D conversion.
Ideally, Vref and VAG should be single-point connected to the
voltage supply driving the system's transducers. Use of a 0.22
µF bypass capacitor across these pins is strongly urged.
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CS
Dout
D9 – MSB
D8
1
SCLK
D7
2
D6
3
4
D5
D4
5
D3
6
D2
7
D1
8
9
HIGH IMPEDANCE
D0
D9
10
1
SAMPLE ANALOG INPUT
Din
A3
A2
A1
A3
A0
MSB
EOC
A/D CONVERSION
INTERVAL
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
INITIALIZE
RE-INITIALIZE
Figure 9. Timing for 10-Clock Transfer Using CS*
MUST BE HIGH ON POWER UP
CS
Dout
D9 – MSB
SCLK
1
D8
D7
2
D6
3
4
D5
5
D4
D3
6
D2
7
D1
8
9
D0
LOW LEVEL
D9
10
1
SAMPLE ANALOG INPUT
Din
A3
A2
A1
A0
A3
MSB
EOC
INITIALIZE
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A/D CONVERSION
INTERVAL
Figure 10. Timing for 10-Clock Transfer Not Using CS*
NOTES:
1. D9, D8, D7, 0 , D0 = the result of the previous A/D conversion.
2. A3, A2, A1, A0 = the mux address for the next A/D conversion.
* This figure illustrates the behavior of the ML145051. The ML145050 behaves identically except there is no EOC signal and the conversion time
is 44 ADCLK cycles (user-controlled time).
Page 8 of 15
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A0
D6
D5
D4
D2
D1
SAMPLE ANALOG INPUT
D3
D0
A/D CONVERSION
INTERVAL
HIGH
IMPEDANCE
RE-INITIALIZE
A3
D9
A1
A0
D6
D5
D4
D2
D1
SAMPLE ANALOG INPUT
D3
D0
A/D CONVERSION INTERVAL
LOW LEVEL
Figure 12. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Shorter Than Conversion)
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A2
D7
1
NOTES:
D9, D8, D7, . . . , D0 = the result of the previous A/D conversion.
A3, A2, A1, A0 = the mux address for the next A/D conversion.
*This figure illustrates the behavior of the ML145051. The ML145050 behaves identically except there is no EOC signal and the conversion time is 44 ADCLK cycles (user-controlled time).
MSB
A3
D8
MUST BE HIGH ON POWER UP
D9 – MSB
INITIALIZE
EOC
D in
SCLK
D out
CS
A1
D7
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A2
D8
LOW
LEVEL
Figure 11. Timing for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Shorter than Conversion)
A3
D9 – MSB
INITIALIZE
EOC
D in
SCLK
D out
CS
A3
D9
1
ML145050, ML145051
LANSDALE Semiconductor, Inc.
Issue B
Page 10 of 15
www.lansdale.com
D5
D4
D2
D1
SAMPLE ANALOG INPUT
D3
A1
D7
A0
D6
D5
D4
D2
D1
SAMPLE ANALOG INPUT
D3
D0
D0
A/D
CONVERSION
INTERVAL
NOTE
2
LOW
LEVEL
HIGH
IMPEDANCE
RE-INITIALIZE
A3
D9
A/D CONVERSION
INTERVAL
NOTE 2
LOW LEVEL
Figure 14. Timing for 16-Clock Transfer Not Using CS* (Serial Transfer Interval Longer Than Conversion)
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A2
A0
D6
1
D9
NOTES:
D9, D8, D7, . . . , D0 = the result of the previous A/D conversion.
A3, A2, A1, A0 = the mux address for the next A/D conversion.
*NOTES:
1. This figure illustrates the behavior of the ML145051. The ML145050 behaves identically except there is no EOC signal and the conversion time is 44 ADCLK cycles (user-controlled time).
2. The 11th SCLK rising edge must occur before the conversion is complete. Otherwise the serial port is thrown out of sync with the microprocessor for the remainder of the transfer.
MSB
A3
D8
MUST BE HIGH ON POWER UP
D9 – MSB
INITIALIZE
EOC
D in
SCLK
D out
CS
A1
D7
SHIFT IN NEW MUX ADDRESS,
SIMULTANEOUSLY SHIFT OUT PREVIOUS CONVERSION VALUE
A2
D8
Figure 13. Timing for 11- to 16-Clock Transfer Using CS* (Serial Transfer Interval Longer Than Conversion)
A3
D9 – MSB
INITIALIZE
EOC
D in
SCLK
D out
CS
A3
1
ML145050, ML145051
LANSDALE Semiconductor, Inc.
Issue B
LANSDALE Semiconductor, Inc.
ML145050, ML145051
Legacy Applications Information
DESCRIPTION
This example application of the ML145050/ML145051
ADCs interfaces three controllers to a microprocessor and
processes data in real-time for a video game. The standard joystick X-axis (left/right) and Y-axis (up/down) controls as well
as engine thrust controls are accommodated.
Figure 15 illustrates how the ML145050/ML145051 is used
as a cost-effective means to simplify this type of circuit design.
Utilizing one ADC, three controllers are interfaced to a CMOS
or NMOS microprocessor with a serial peripheral interface
(SPI) port. Processors with National Semiconductor's
MICROWIRE serial port may also be used. Full duplex operation optimizes throughput for this system.
DIGITAL DESIGN CONSIDERATIONS
Motorola's MC68HC05C4 CMOS MCU may be chosen to
reduce power supply size and cost. The NMOS MCUs maybe
used if power consumption is not critical. A VDD or VSS 0.1
µF bypass capacitor should be closely mounted to the ADC.
Both the ML145050 and ML145051 accommodate all the
analog system inputs. The ML145050, when used with a 2
MHz MCU, takes 27 µs to sample the analog input, perform
the conversion, and transfer the serial data at 2 MHz. Fortyfour ADCLK cycles (2 MHz at input pin 19) must be provided
and counted by the MCU before reading the ADC results. The
ML145051 has the end-of-conversion (EOC) signal (at output
pin 19) to define when data is ready, but has a slower 49 µs
cycle time. However, the 49 µs is constant for serial data rates
of 2 MHz independent of the MCU clock frequency. Therefore,
the ML145051 may be used with the CMOS MCU operating at
reduced clock rates to minimize power consumption without
severely sacrificing ADC cycle times, with EOC being used to
generate an interrupt. (The ML145051 may also be used with
MCUs which do not provide a system clock.)
ANALOG DESIGN CONSIDERATIONS
Controllers with output impedances of less than 1 kΩ maybe
directly interfaced to these ADCs, eliminating the need for
buffer amplifiers. Separate lines connect the Vref and VAG
pins on the ADC with the controllers to provide isolation from
system noise.
Although not indicated in Figure 15, the Vref and controller
output lines may need to be shielded, depending on their length
Page 11 of 15
and electrical environment. This should be verified during prototyping with an oscilloscope. If shielding is required, a twisted pair or foil-shielded wire (not coax) is appropriate for this
low frequency application. One wire of the pair or the shield
must be VAG.
A reference circuit voltage of 5 volts is used for this application. The reference circuitry may be as simple as tying VAG to
system ground and Vref to the system's positive supply. (See
Figure 16.) However, the system power supply noise may
require that a separate supply be used for the voltage reference.
This supply must provide source current forVref as well as
current for the controller potentiometers.
A bypass capacitor of approximately 0.22 µF across the Vref
and VAG pins is recommended. These pins are adjacent on the
ADC package which facilitates mounting the capacitor very
close to the ADC.
SOFTWARE CONSIDERATIONS
The software flow for acquisition is straight forward. The
nine analog inputs, AN0 through AN8, are scanned by reading
the analog value of the previously addressed channel into the
MCU and sending the address of the next channel to be read to
the ADC, simultaneously.
If the design is realized using the ML145050, 44 ADCLK
cycles (at pin 19) must be counted by the MCU to allow time
for A/D conversion. The designer utilizing the MC145051 has
the end-of-conversion signal (at pin 19) to define the conversion interval. EOC may be used to generate an interrupt, which
is serviced by reading the serial data from the ADC. The software flow should then process and format the data, and transfer
the information to the video circuitry for updating the display.
When these ADCs are used with a 16-bit (2-byte) transfer,
there are two types of offsets involved. In the first type of offset, the channel information sent to the ADCs is offset by 12
bits. That is, in the 16-bit stream, only the first 4 bits (4 MSBs)
contain the channel information. The balance of the bits are
don't cares. This results in 3 don't-care nibbles, as shown in
Table 2. The second type of offset is in the conversion result
returned from the ADCs; this is offset by 6 bits. In the 16-bit
stream, the first 10 bits (10 MSBs) contain the conversion
results. The last 6 bits are zeroes. The hexadecimal result is
shown in the first column of Table 3. The second column shows
the result after the offset is removed by a microprocessor routine. If the 16-bit format is used, these ADCs can transfer one
continuous 16-bit stream or two intermittent 8-bitstreams.
www.lansdale.com
Issue B
LANSDALE Semiconductor, Inc.
ML145050, ML145051
Legacy Applications Information
Table 2. Programmer 's Guide for 16-Bit Transfers:
Input Code
Input
Address
in Hex
Channel to be
Converted Next
Comment
$0XXX
$1XXX
$2XXX
$3XXX
$4XXX
$5XXX
$6XXX
$7XXX
$8XXX
$9XXX
$AXXX
$BXXX
$CXXX
$DXXX
$EXXX
$FXXX
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
AN11
AN12
AN13
None
None
Pin 1
Pin 2
Pin 3
Pin 4
Pin 5
Pin 6
Pin 7
Pin 8
Pin 9
Pin 11
Pin 12
Half Scale Test: Output = $8000
Zero Test: Output = $0000
Full Scale Test: Output = $FFC0
Not Allowed
Not Allowed
Table 3. Programmer 's Guide for 16-Bit Transfers:
Output Code
Conversion
Result Without
Offset Removed
Conversion
Result With
Offset Removed
$0000
$0040
$0080
$00C0
$0100
$0140
$0180
$01C0
$0200
$0240
$0280
$02C0
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
Zero
Zero + 1 LSB
Zero + 2 LSBs
Zero + 3 LSBs
Zero + 4 LSBs
Zero + 5 LSBs
Zero + 6 LSBs
Zero + 7 LSBs
Zero + 8 LSBs
Zero + 9 LSBs
Zero + 10 LSBs
Zero + 11 LSBs
$FF40
$FF80
$FFC0
$03FD
$03FE
$03FF
Full Scale – 2 LSBs
Full Scale – 1 LSB
Full Scale
+5V
0.22 µF
LEFT/RIGHT
UP/DOWN
CONTROLLER
#1
ENGINE THRUST
LEFT/RIGHT
UP/DOWN
CONTROLLER
#2
ENGINE THRUST
5 VOLT
REFERENCE
CIRCUIT
LEFT/RIGHT
CONTROLLER
#3
UP/DOWN
ENGINE THRUST
Vref
AN0
VDD
AN2
AN4
AN5
µP
SPI PORT
Dout
ADC
AN3
0.1 µF
CS
Din
SCLK
AN1
Value
ML145050
ML145051
ADCLK
(ML145050)
EOC
(ML145051)
AN6
AN7
AN8
VAG
AN9
AN10
VSS
VIDEO
CIRCUITRY
VIDEO
MONITOR
Figure 15. Joystick Interface
Page 12 of 15
www.lansdale.com
Issue B
LANSDALE Semiconductor, Inc.
ML145050, ML145051
Legacy Applications Information
DIGITAL + V
DO NOT CONNECT
AT IC
ANALOG + V
Vref
TO
JOYSTICKS
5V
SUPPLY
VDD
ML145050
ML145051
0.22 µF
VSS
VAG
ANALOG GND
0.1 µF
DO NOT CONNECT
AT IC
DIGITAL GND
Figure 16. Alternate Configuration Using the Digital Supply for the Reference Voltage
Compatible Motorola MCUs/MPUs
This is not a complete listing of Motorola's MCUs/MPUs.
Contact your Motorola representative if you need
additional information.
Instruction
Set
Memory (Bytes)
ROM
EEPROM
SPI
SCI
M6805
2096
2096
4160
4160
8K
4160
8K
7700
–
–
–
–
–
–
–
–
–
4160
–
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
M68000
–
–
–
Device
Number
MC68HC05C2
MC68HC05C3
MC68HC05C4
MC68HSC05C5
MC68HSC05C8
MC68HCL05C4
MC68HCL05C8
MC68HC05C8
MC68HC805C5
MC68HC000
SPI = Serial Peripheral Interface.
SCI = Serial Communication Interface.
✟ High Speed.
✟ Low Power.
Page 13 of 15
www.lansdale.com
Issue B
LANSDALE Semiconductor, Inc.
ML145050, ML145051
OUTLINE DIMENSIONS
P DIP 20 = RP
(ML145050RP, ML145051RP)
CASE 738-03
-A20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
11
B
1
1
0
C
-T-
L
K
SEATING
PLANE
M
E
G
N
F
J 20 PL
0.25 (0.010)
D 20 PL
0.25 (0.010)
Page 14 of 15
M
T
A
M
www.lansdale.com
M
T B
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.070
1.010
0.260
0.240
0.180
0.150
0.022
0.015
0.050 BSC
0.070
0.050
0.100 BSC
0.015
0.008
0.140
0.110
0.300 BSC
15°
0°
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.77
1.27
2.54 BSC
0.38
0.21
3.55
2.80
7.62 BSC
15°
0°
0.51
1.01
Issue B
LANSDALE Semiconductor, Inc.
ML145050, ML145051
OUTLINE DIMENSIONS
SOG 20W = -6P
(ML145050-6P, ML145051-6P)
CASE 751D-04
-A20
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOW ABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
11
-B-
P 10 PL
0.010 (0.25)
1
1
B
M
0
D 20 PL
0.010 (0.25)
M
M
T B
S
A
S
J
F
R X 45°
C
-TG 18 PL
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
12.65 12.95
7.60
7.40
2.65
2.35
0.49
0.35
0.90
0.50
1.27 BSC
0.32
0.25
0.25
0.10
7°
0°
10.05 10.55
0.75
0.25
INCHES
MIN
MAX
0.499 0.510
0.292 0.299
0.093 0.104
0.014 0.019
0.020 0.035
0.050 BSC
0.010 0.012
0.004 0.009
0°
7°
0.395 0.415
0.010 0.029
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights nor the rights of others. “Typical” parameters which
may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by the customer’s
technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
Page 15 of 15
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Issue B