CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 1.8-V PHASE LOCK LOOP CLOCK DRIVER FEATURES • • • • • • • • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate ( DDR II ) Applications Spread Spectrum Clock Compatible Operating Frequency: 125 MHz to 410 MHz Application Frequency: 160 MHz to 410 MHz Low Jitter (Cycle-Cycle): ±40 ps Low Output Skew: 35 ps Stabilization Time <6 µs Distributes One Differential Clock Input to 10 Differential Outputs • • • • • High-Drive Version of CDCUA877 52-Ball mBGA (MicroStar Junior™ BGA, 0,65-mm pitch) External Feedback Pins ( FBIN, FBIN ) are Used to Synchronize the Outputs to the Input Clocks Meets or Exceeds CUA877/CUA878 Specification PLL Standard for PC2-3200/4300/5300/6400 Fail-Safe Inputs DESCRIPTION The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time. The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0°C to 70°C. AVAILABLE OPTIONS (1) TA 52-Ball BGA (1) 0°C to 70°C CDCU2A877ZQL For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 2 Submit Documentation Feedback CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 Table 1. Terminal Functions NAME BGA MLF I/O DESCRIPTION AGND G1 7 AVDD H1 8 CK E1 4 I Clock input with a (10 kΩ to 100 kΩ) pulldown resistor CK F1 5 I Complementary clock input with a (10 kΩ to 100 kΩ) pulldown resistor FBIN E6 27 I Feedback clock input FBIN F6 26 I Complementary feedback clock input FBOUT H6 24 O Feedback clock output FBOUT G6 25 O Complementary feedback clock output OE F5 22 I Output enable (asynchronous) OS D5 21 I Output select (tied to GND or VDD) GND B2, B3, B4, B5, C2, C5, H2, H5, J2, J3, J4, J5 10 VDDQ D2, D3, D4, E2, E5, F2, G2, G3, G4, G5 1, 6, 9, 15, 20, 23, 28, 31, 36 Analog ground Analog power Ground Logic and output power Y[0:9] A2, A1, D1, 38, 39, 3, 11, 14, J1, K3, A5, A6, 34, 33, 29, 19, 16 D6, J6, K4 O Clock outputs Y[0:9] A3, B1, C1, 37, 40, 2, 12, 13, K1, K2, A4, 35, 32, 30, 18, 17 B6, C6, K6, K5 O Complementary clock outputs Table 2. Function Table INPUTS OUTPUTS Y PLL AVDD OE OS CK CK Y FBOUT FBOUT GND H X L H L L H Bypassed/Off GND H X H L H H L Bypassed/Off GND L H L H LZ LZ L H Bypassed/Off GND L L H L LZ Y7 Active LZ Y7 Active H L Bypassed/Off 1.8 V Nomnal L H L H LZ LZ L H On 1.8 V Nomnal L L H L LZ Y7 Active LZ Y7 Active H L On 1.8 V Nomnal H X L H L H L H On 1.8 V Nomnal H X H L H L H L On 1.8 V Nomnal X X LH L LZ LZ LZ LZ Off X X X H H Submit Documentation Feedback Reserved 3 CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 Figure 1. Logic Diagram (Positive Logic) ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.5 tp 2.5 V Input voltage range (2) (3) –0.5 to VDDQ + 0.5 V VO Output voltage range (2) (3) –0.5 to VDDQ + 0.5 V IIK Input clamp current, (VI < 0 or VI > VDDQ) ±50 mA IOK Output clamp voltage, (VO < 0 or VO > VDDQ) ±50 mA IO Continuous output current, (VO = 0 to VDDQ) ±50 mA IDDC Continuous current through each VDDQ or GND ±100 mA VDDQ AVDD Supply voltage range VI RθJA Thermal resistance, junction-to-ambient (4) RθJC Thermal resistance, junction-to-case (4) Tstg Storage temperature range (1) (2) (3) (4) 4 No airflow 151.9 Airllflow 150 ft/min 146.1 No airflow 102.4 –65 to 150 K/W °C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5 V maximum. The package thermal impedance is calculated in accordance with JESD51 and JEDEC2S1P (high-k board). Submit Documentation Feedback CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT 1.8 1.9 V 0.35 × VDDQ V VDDQ Output supply voltage AVDD Supply voltage (1) VIL Low-level input voltage (2) OE, OS VIH High-level input voltage (2) CK, CK IOH High-level output current (see Figure 2) –18 mA IOL Low-level output current (see Figure 2) 18 mA VIX Input differential-pair cross voltage VI Input voltage level VID Input differential voltage (2) (see Figure 4) TA Operating free-air temperature (1) (2) 1.7 NOM VDDQ 0.65 × VDDQ V (VDDQ/2)-0.15 (VDDQ/2)+0.15 V –0.3 VDDQ+0.3 V DC 0.3 VDDQ+0.4 V AC 0.6 VDDQ+0.4 V 0 70 °C The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are ensured. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 4 for definition. The CK and CK VIH and VIL limits define the dc low and high levels for the logic detect state. Submit Documentation Feedback 5 CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range PARAMETERLow-level output voltage VIK Input (cl inputs) VOH High-level output voltage TEST CONDITIONS II = –18 mA IOH = -100 Low-level output voltage IO(DL) Low-level output current, disabled VOD Differential output voltage (1) II Input current A 1.7 V to 1.9 V Input capacitance CI(∆) Change in input current (1) (2) 1.7 V MAX UNIT –1.2 V VDDQ – 0.2 V 1.1 0.1 V IOL = 18 mA 1.7 V 0.6 VO(DL) = 100 mV, OE = L 1.7 V 100 µA 1.7 V 0.6 V CK, CK 1.9 V ±250 OE, OS, FBIN, FBIN 1.9 V ±10 CK and CK = L 1.9 V 500 µA CK and CK = 410 MHz, All outputs are open (not connected to a PCB) 1.9 V 300 mA All outputs are loaded with 2 pF and 120-Ω termination resistor, CK and CK = 410 MHz 1.9 V 325 mA CK, CK VI = VDD or GND 1.8 V 2 3 FBIN, FBIN VI = VDD or GND 1.8 V 2 3 CK, CK VI = VDD or GND 1.8 V 0.25 FBIN, FBIN VI = VDD or GND 1.8 V 0.25 Supply current, dynamic ( IDDQ + IADD) (see for CPD calculation) CI TYP IOL = 100 µA IDD(LD) Supply current, static (IDDQ + IADD) IDD MIN 1.7 V IOH = –18 mA VOL AVDD, VDDG (2) µA pF pF VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 4 for a definition. Total IDD = IDDQ + IADD = fCK× CPD× VDDQ, solving for CPD = (IDDQ + IADD)/(fCK × VDDQ) where fCK is the input frequency, VDDQ is the power supply, and CPD is the power dissipation capacitance. TIMING REQUIREMENTS over recommended operating free-air temperature range MAX UNIT fCK Clock frequency (operating) (1) (2) PARAMETER AVDD, VDD = 1.8 V ±0.1 V 125 410 MHz fCK Clock frequency (application) (1) (3) AVDD, VDD = 1.8 V ±0.1 V 160 410 MHz tDC Duty cycle, input clock AVDD, VDD = 1.8 V ±0.1 V 40% 60% tL Stabilization time (4) AVDD, VDD = 1.8 V ±0.1 V (1) (2) (3) (4) 6 TEST CONDITIONS MIN TYP 6 µs The PLL must be able to handle spread spectrum induced skew. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). Application clock frequency indicates a range over which the PLL must meet all timing parameters. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specified by the static phase offset t(φ), after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode, and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Submit Documentation Feedback CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ten Enable time, OE to any Y/Y See Figure 12 8 ns tdis Disable time, OE to any Y/Y See Figure 12 8 ns Cycle-to-cycle period jitter (2) 160 MHz to 410 MHz, See Figure 5 Static phase offset time (3) tjit(cc+) tjit(cc-) t(φ) t(φ)dyn Dynamic phase offset tsk(o) Output clock skew (4) tjit(per) time, (4) Period jitter (5) (2) tjit(hper) Half-period jitter (5) (2) Σt(su) Σt(h) |tjit(per)| + |t(φ)dyn| + tsk(o) (6) |t(φ)dyn| + + tsk(o) (6) Input clock skew rate Output clock slew VOX 40 0 –40 SeeFigure 4 –50 50 ps See Figure 11 –20 20 ps 35 ps See Figure 7 160 MHz to 270 MHz, See Figure 8 –30 30 271 MHz to 410 MHz, See Figure 8 –20 20 160 MHz to 270 MHz, See Figure 9 –75 75 271 MHz to 410 MHz, See Figure 9 –50 50 271 MHz to 410 MHz 271 MHz to 410 MHz Slew rate, OE SR 0 rate (7) (8) Output differential-pair cross voltage (9) See Figure 3 and Figure 8 0.5 See Figure 3 and Figure 8 1 2.5 1.5 2.5 See Figure 3 and Figure 8 See Figure 2 SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (1) (2) (3) (4) (5) (6) (7) (8) (9) ps ps 80 ps 60 ps 4 V/ns 3 (VDDQ/2) – 0.1 (VDDQ/2) + 0.1 30 33 0% –0.5% 2 ps V kHz MHz There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables must be used. This parameter is assured by design and characterization. Phase static offset time does not include jitter. For full frequency range of 160MHz to 410MHz. Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. In the frequency range of 271 MHz to 410 MHz, the minimum and maximum values of tjit(per) and t(φ)dyn and the maximum value for tsk(o) must not exceed the corresponding minimum and maximum values of the 160 MHz to 270 MHz range. In addition, the sum of the specified values for |tjit(per)|, |t(φ)dyn|, and tsk(o) must meet the requirements for the Σt(su) and the sum of the specified values for |t(φ)dyn| and tsk(o) must meet the requirements for the Σt(h). The output slew rate is determined from the IBIS model into the load shown in Figure 4. To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. Output differential-pair cross voltage specified at the DRAM clock input or the test load. Submit Documentation Feedback 7 CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 Figure 2. Output Load Test Circuit 1 (Using High-Impedance Probe) Figure 3. Output Load Test Circuit 2 (Using SMA Coaxial Cable) Figure 4. IBIS Model Output Load 8 Submit Documentation Feedback CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 tc(n) tc(n+1) tc(n) tc(n+1) Figure 5. Cycle-To-Cycle Period Jitter t( )n t( )n t( )n Figure 6. Static Phase Offset Figure 7. Output Skew Submit Documentation Feedback 9 CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 (n) (n) Figure 8. Period Jitter (half period)n (half period)n (half period)n Figure 9. Half-Period Jitter Figure 10. Input and Output Slew Rates 10 Submit Documentation Feedback CDCU2A877 www.ti.com SCAS827 – AUGUST 2006 t( t( t( ) t( )dyn )dyn t( ) )dyn t( )dyn Figure 11. Dynamic Phase Offset Figure 12. Time Delay Between OE and Clock Output (Y, Y) A. Place the 2200-pF capacitor close to the PLL. B. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND via (farthest from the PLL). C. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8Ω dc maximum, 600Ω at 100 MHz). Figure 13. Recommended AVDD Filtering Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 12-Sep-2006 PACKAGING INFORMATION Orderable Device Status (1) CDCU2A877ZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 52 1000 Green (RoHS & no Sb/Br) SNAGCU Level-2-260C-1 YEAR CDCU2A877ZQLT ACTIVE BGA MI CROSTA R JUNI OR ZQL 52 250 SNAGCU Level-2-260C-1 YEAR Package Type Package Drawing Pins Package Eco Plan (2) Qty Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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