Maxim MAX9181 Low-jitter, low-noise lvpecl-to-lvds level translator in an sc70 package Datasheet

19-2415; Rev 1; 2/04
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
The MAX9181 is an LVPECL-to-LVDS level translator
that accepts a single LVPECL input and translates it to
a single LVDS output. It is ideal for interfacing between
LVPECL and LVDS interfaces in systems that require
minimum jitter, noise, power, and space.
Ultra-low, 23ps P-P added deterministic jitter and
0.6psRMS added random jitter ensure reliable communication in high-speed links that are highly sensitive to
timing errors, especially those incorporating clock-anddata recovery, PLLs, serializers, or deserializers. The
MAX9181’s switching performance guarantees a
400Mbps data rate, but minimizes radiated noise by
guaranteeing 0.5ns minimum output transition time.
The MAX9181 operates from a single 3.3V supply and
consumes only 10mA supply current over a -40°C to
+85°C temperature range. It is available in a tiny 6-pin
SC70 package (half the size of a SOT23). Refer to the
MAX9180 data sheet for a low-jitter, low-noise LVDS
repeater in an SC70 package.
Features
♦ Tiny SC70 Package
♦ Ultra-Low Jitter
23psP-P Added Deterministic Jitter
(223 - 1 PRBS)
0.6psRMS Added Random Jitter
♦ 0.5ns (min) Transition Time Minimizes Radiated
Noise
♦ 400Mbps Guaranteed Data Rate
♦ Low 10mA Supply Current
♦ Conforms to ANSI/EIA/TIA-644 LVDS Standard
♦ High-Impedance Inputs and Outputs in
Power-Down Mode
Applications
Ordering Information
Digital Cross-Connects
Add/Drop Muxes
Network Switches/Routers
PART
TEMP RANGE
PINPACKAGE
MAX9181EXT-T
-40°C to +85°C
6 SC70-6
TOP
MARK
ABI
Cellular Phone Base Stations
DSLAMs
Multidrop Buses
Pin Configuration
Typical Operating Circuit
TOP VIEW
VCC
MAX9181
3.3V
OUT- 1
6
OUT+
GND 2
5
VCC
IN- 3
4
IN+
MAX9181
OUT+
IN+
LVPECL
DRIVER
OUT-
LVDS
SIGNALS
IN-
GND
SC70
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX9181
General Description
MAX9181
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +4.0V
IN+, IN- to GND.....................................................-0.3V to +4.0V
OUT+, OUT- to GND .............................................-0.3V to +4.0V
Short-Circuit Duration (OUT+, OUT-) .........................Continuous
Continuous Power Dissipation (TA = +70°C)
6-Pin SC70 (derate 3.1mW/°C above +70°C) ..............245mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature ......................................................+150°C
ESD Protection
Human Body Model, IN+, IN-, OUT+, OUT- ....................±8kV
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, RL = 100Ω ±1%, |VID| = 0.05V to VCC, VCM = |VID / 2| to VCC - |VID / 2|, TA = -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = 3.3V, TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
7
50
-50
-7
mV
Figure 1
360
1328
kΩ
IN+ = 3.6V, IN- = 0V
-10
+2.7
+10
IN+ = 0V, IN- = 3.6V
-10
+2.7
+10
IN+ = 3.6V, IN- = 0V
-10
+2.7
+10
IN+ = 0V, IN- = 3.6V
-10
+2.7
+10
LVPECL INPUT
Differential Input High Threshold
VTH
Differential Input Low Threshold
VTL
Input Resistor
RIN
Input Current
IIN+, IIN-
Power-Off Input Current
IIN+, IIN-
VCC = 0V,
Figure 1
mV
µA
µA
LVDS OUTPUT
Differential Output Voltage
VOD
Figure 2
Differential Output Voltage
∆VOD
Figure 2
Offset (Common-Mode) Voltage
VOS
Figure 2
Change in VOS for
Complementary Output States
∆VOS
Figure 2
Output High Voltage
VOH
Output Low Voltage
VOL
250
1.125
mV
25
mV
1.25
1.375
V
0.005
25
mV
1.44
1.6
1.08
+250
+360
+450
OUT+ = 3.6V, other output open
-10
+0.02
+10
OUT- = 3.6V, other output open
-10
+0.02
+10
100
260
400
VOD+
IN+, IN- open
Power-Off Output Leakage
Current
IOOFF
VCC = 0V
Differential Output Resistance
RODIFF
VCC = 3.6V or 0V
ISC
450
0.9
Differential Output Voltage
Output Short Current
360
0.008
V
V
VID = 50mV, OUT+ = GND
-5
-15
VID = -50mV, OUT- = GND
-5
-15
10
15
mV
µA
Ω
mA
POWER SUPPLY
Supply Current
2
ICC
_______________________________________________________________________________________
mA
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
(VCC = 3.0V to 3.6V, RL = 100Ω ±1%, CL = 10pF, |VID| = 0.15V to VCC, VCM = |VID / 2| to VCC - |VID / 2|, TA = -40°C to +85°C, unless
otherwise noted. Typical values are at VCC = 3.3V, TA = +25°C.) (Notes 3, 4, 5) (Figures 3, 4)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Propagation Delay High
to Low
tPHLD
1.3
2.0
2.8
ns
Differential Propagation Delay Low to
High
tPLHD
1.3
2.0
2.8
ns
23
100
psP-P
Added Deterministic Jitter
Added Random Jitter
tDJ
400Mbps 223 - 1 PRBS data pattern
(Notes 6, 11)
tRJ
fIN = 200MHz (Notes 7, 11)
0.6
2.9
psRMS
Differential Part-to-Part Skew
tSKPP1
(Note 8)
0.16
0.6
ns
Differential Part-to-Part Skew
tSKPP2
(Note 9)
Switching Supply Current
ICCSW
1.5
ns
12.2
18
mA
ns
Rise Time
tTLH
0.5
0.67
1.0
Fall Time
tTHL
0.5
0.66
1.0
Input Frequency
fMAX
(Note 10)
200
ns
MHz
Note 1: All devices are 100% tested at TA = +25°C. Limits over temperature are guaranteed by design and characterization.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH, VTL, VOD, and ∆VOD.
Note 3: Guaranteed by design and characterization.
Note 4: Signal generator output (unless otherwise noted): frequency = 200MHz, 50% duty cycle, RO = 50Ω, tR = 1.5ns, and tF =
1.5ns (0% to 100%).
Note 5: CL includes scope probe and test jig capacitance.
Note 6: Signal generator output for tDJ: VOD = 150mV, VOS = 1.2V, tDJ includes pulse (duty cycle) skew.
Note 7: Signal generator output for tRJ: VOD = 150mV, VOS = 1.2V.
Note 8: tSKPP1 is the magnitude difference of any differential propagation delays between devices operating over rated conditions
at the same supply voltage, input common-mode voltage, and ambient temperature.
Note 9: tSKPP2 is the magnitude difference of any differential propagation delays between devices operating over rated conditions.
Note 10: Device meets VOD DC specifications and AC specifications while operating at fMAX.
Note 11: Jitter added to the input signal.
_______________________________________________________________________________________
3
MAX9181
AC ELECTRICAL CHARACTERISTICS
Typical Operating Characteristics
(VCC = 3.3V, RL = 100Ω ±1%, CL = 10pF, |VID| = 0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted. Signal generator output:
frequency = 200MHz, 50% duty cycle, RO = 50Ω, tR = 1.5ns, and tF = 1.5ns (0% to 100%), unless otherwise noted.)
SUPPLY CURRENT
vs. INPUT FREQUENCY
SUPPLY CURRENT (mA)
15
12
9
6
3
12.50
12.25
12.00
11.75
11.50
11.25
0
-40
25 50 75 100 125 150 175 200 225 250
5.08
5.07
5.06
-15
10
35
60
85
3.0
3.3
3.4
3.5
SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
1.09
1.08
1.07
1.06
1.500
1.475
1.450
1.425
1.400
1.375
1.05
1.350
3.2
3.3
3.4
3.5
3.1
SUPPLY VOLTAGE (V)
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
tPHLD
1.9
tPLHD
tTHL
725
700
675
tTLH
650
625
600
1.7
575
550
1.5
-40
-15
10
35
TEMPERATURE (°C)
60
85
3.4
SUPPLY VOLTAGE (V)
750
TRANSITION TIME (ps)
2.3
MAX9181 toc06
1.8
TRANSITION TIME
vs. SUPPLY VOLTAGE
MAX9181 toc07
2.5
DIFFERENTIAL PROPAGATION DELAY (ns)
tPLHD
1.9
SUPPLY VOLTAGE (V)
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
2.1
tPHLD
1.7
3.0
3.6
3.6
2.0
MAX9181 toc08
OUTPUT HIGH VOLTAGE (V)
1.525
2.1
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9181 toc05
MAX9181 toc04
1.550
1.10
3.1
3.2
TEMPERATURE (°C)
1.11
3.0
3.1
INPUT FREQUENCY (MHz)
1.12
4
5.09
5.05
11.00
0
MAX9181 toc03
12.75
5.10
OUTPUT SHORT-CIRCUIT CURRENT (mA)
MAX9181 toc02
13.00
MAX9181 toc01
18
SUPPLY CURRRENT (mA)
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
SWITCHING SUPPLY CURRENT
vs. TEMPERATURE
21
OUTPUT LOW VOLTAGE (V)
MAX9181
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
3.0
3.1
3.2
3.3
3.4
3.5
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3.6
3.5
3.6
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
DIFFERENTIAL OUTPUT VOLTAGE
vs. LOAD RESISTOR
TRANSITION TIME
vs. TEMPERATURE
TRANSITION TIME (ps)
700
650
tTLH, tTHL
600
550
500
450
MAX9181 toc10
750
600
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9181 toc09
800
500
400
300
200
100
0
400
-40
-15
10
35
60
85
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
1
OUT-
Inverting LVDS Output
2
GND
Ground
3
IN-
Inverting LVPECL-Compatible Input
4
IN+
Noninverting LVPECL-Compatible
Input
5
VCC
Power Supply. Bypass VCC to GND
with a 0.01µF ceramic capacitor.
6
OUT+
Noninverting LVDS Output
Table 1. Function Table (Figure 2)
INPUT, VID
OUTPUT, VOD
>50mV
High
<-50mV
Low
50mV > VID > -50mV
Indeterminate
Open
High
25
50
75
100
125
150
LOAD RESISTOR (Ω)
Detailed Description
The LVDS interface standard is a signaling method
intended for point-to-point communication over a controlled-impedance medium, as defined by the ANSI/
TIA/EIA-644 and IEEE 1596.3 standards. The LVDS
standard uses a lower voltage swing than other common communication standards, achieving higher data
rates with reduced power consumption while reducing
EMI emissions and system susceptibility to noise.
The MAX9181 is a 400Mbps LVDS translator intended
for high-speed, point-to-point, low-power applications.
The MAX9181 accepts differential LVPECL inputs and
produces an LVDS output. The input voltage range
includes signals from GND up to VCC, allowing interoperation with 3.3V LVPECL devices.
The MAX9181 provides a high output when the inputs
are open. See Table 1.
Note: VID = (IN+ - IN-), VOD = (OUT+ - OUT-)
High = 450mV ≥ VOD ≥ 250mV
Low = -250mV ≥ VOD ≥ -450mV
_______________________________________________________________________________________
5
MAX9181
Typical Operating Characteristics (continued)
(VCC = 3.3V, RL = 100Ω ±1%, CL = 10pF, |VID| = 0.2V, VCM = 1.2V, TA = +25°C, unless otherwise noted. Signal generator output:
frequency = 200MHz, 50% duty cycle, RO = 50Ω, tR = 1.5ns, and tF = 1.5ns (0% to 100%), unless otherwise noted.)
MAX9181
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
Applications Information
Supply Bypassing
Bypass V CC with a high-frequency surface-mount
ceramic 0.01µF capacitor as close to the device as
possible.
Differential Traces
Input and output trace characteristics affect the performance of the MAX9181. Use controlled-impedance differential traces. Ensure that noise couples as common
mode by running the traces within a differential pair
close together.
Maintain the distance within a differential pair to avoid
discontinuities in differential impedance. Avoid 90°
turns and minimize the number of vias to further prevent
impedance discontinuities.
match the differential characteristic impedance of the
transmission line.
Each line of a differential LVPECL link should be terminated through 50Ω to VCC - 2V or be replaced by the
Thevinin equivalent.
The LVDS output voltage level depends upon the differential characteristic impedance of the interconnect and
the value of the termination resistance. The MAX9181 is
guaranteed to produce LVDS output levels into 100Ω.
With the typical 3.6mA output current, the MAX9181 produces an output voltage of 360mV when driving a 100Ω
transmission line terminated with a 100Ω termination
resistor (3.6mA ✕ 100Ω = 360mV). For typical output levels with different loads, see the Differential Output
Voltage vs. Load Resistor curve in the Typical Operating
Characterics.
Cables and Connectors
The LVDS standards define signal levels for interconnect with a differential characteristic impedance and
termination of 100Ω. Interconnects with a characteristic
impedance and termination of 90Ω to 132Ω impedance
are allowed, but produce different signal levels (see
Termination).
LVPECL signals are typically specified for 50Ω singleended characteristic impedance interconnect terminated through 50Ω to VCC - 2V.
Use cables and connectors that have matched differential impedance to minimize impedance discontinuities.
Chip Information
TRANSISTOR COUNT: 401
PROCESS: CMOS
Termination
For point-to-point LVDS links, the termination resistor
should be located at the LVDS receiver input and
6
_______________________________________________________________________________________
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
VCC
OUT+
CL
RIN
IN+
IN+
OUT+
IN-
OUT-
PULSE
GENERATOR
RL
IN-
50Ω
50Ω
OUT-
RIN
CL
Figure 1. LVPECL Input Bias
Figure 3. Transition Time and Propagation Delay Test Circuit
OUT+
1.25V
1.20V
1.25V
1.20V
RL/2
IN+
IN-
VOD
VOS
RL/2
OUT-
Figure 2. DC Load Test Circuit
VCM = ((IN+) + (IN-))/2
INOV (DIFFERENTIAL)
VID
OV (DIFFERENTIAL)
IN+
tPHLD
tPLHD
OUTOV (DIFFERENTIAL)
OV (DIFFERENTIAL)
OUT+
80%
80%
OV (DIFFERENTIAL)
20%
OV (DIFFERENTIAL)
20%
VDIFF = (OUT+) - (OUT-)
VDIFF
tTLH
tTHL
Figure 4. Transition Time and Propagation Delay Timing Diagram
_______________________________________________________________________________________
7
MAX9181
Test Circuits and Timing Diagrams
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
SC70, 6L.EPS
MAX9181
Low-Jitter, Low-Noise LVPECL-to-LVDS Level
Translator in an SC70 Package
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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