Rev 0; 10/07 3.3V 26-Channel, Three-Stateable Transmission Gate Features The DS3690 is a 26-channel, three-stateable transmission gate designed for transparent digital signal transfer when enabled and fast-gated bus isolation when the device is disabled. Each of the 26 independent channels can be used for input, output, or I/O signal applications, with a typical signal propagation delay of less than 10ns. Using the logic-control input, all channels can be simultaneously enabled for bus transmission or forced to a high-impedance condition to isolate a critical component on that bus. The DS3690 operates on a single 3.3V (typical) power supply and is available in a space-saving 56-pin leadfree TQFN package. ♦ 26 Bidirectional Channels ♦ Low Propagation Delay (< 10ns typ) ♦ High-Speed On/Off Time (< 20ns typ) ♦ 2.7V to 3.6V Supply ♦ Wide Temperature Range: -55°C to +85°C ♦ TQFN Package (5mm x 11mm x 0.8mm) Ordering Information Applications POS Terminals PART TEMP RANGE PIN-PACKAGE PIN Pads DS3690T+ -55°C to +85°C 56 TQFN Cryptographic Processors DS3690T+TRL -55°C to +85°C 56 TQFN +Denotes a lead-free package. TRL = Tape and reel. Gaming Lottery Terminals Industrial Controls and Monitoring CH20B CH19B CH18B CH17B CH16B CH15B CH14B CH13B CH12B CH11B CH10B CH09B CH08B CH07B CH06B CH05B CH04B CH03B CH01B TOP VIEW CH02B Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CH24B 49 28 CH21B CH25B 50 27 CH22B CH26B 51 26 CH23B CE 52 25 GND DS3690 GND 53 24 VCC CH26A 54 23 CH23A EXPOSED PAD (ON BOTTOM) CH25A 55 22 CH22A CH24A 56 + CH03A CH04A CH05A CH06A CH07A CH08A CH09A CH10A CH20A CH02A CH19A 10 11 12 13 14 15 16 17 18 19 20 CH18A 9 CH17A 8 CH16A 7 CH15A 6 CH14A 5 CH13A 4 CH12A 3 CH11A 2 CH01A 21 CH21A 1 TQFN (5mm × 11mm × 0.8mm) Typical Operating Circuit appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS3690 General Description DS3690 3.3V 26-Channel, Three-Stateable Transmission Gate ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground......-0.5V to +6.0V Operating Temperature Range ...........................-55°C to +85°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature...................Refer to IPC/JEDEC J-STD-020 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA = -55°C to +85°C) MIN TYP MAX UNITS Supply Voltage PARAMETER SYMBOL VCC (Note 1) CONDITIONS 2.7 3.3 3.6 V Input Logic 1 VIH (Note 1) 0.7 x VCC VCC + 0.3 V Input Logic 0 VIL (Note 1) -0.3 0.3 x VCC V MAX UNITS 1 μA DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +3.6V, TA = -55°C to +85°C, unless otherwise noted.) PARAMETER Standby Current Input Leakage Current (CE) I/O Leakage Current SYMBOL ICC II I IO CONDITIONS MIN TYP CE = CH1 CH26 = VCC, IOUT = 0mA VIN = 0V to VCC, TA = +25°C -0.1 +0.1 μA CE = VIH -1.0 +1.0 μA MAX UNITS AC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +3.6V, TA = -55°C to +85°C, unless otherwise noted.) PARAMETER Propagation Delay (A to B or B to A) SYMBOL CONDITIONS MIN TYP t PD CE = VIL (Note 2) 10 ns Chip Enable to Output Valid tCEV (Notes 2, 3) 20 ns Chip Enable to Output Deselect tCEZ (Notes 2, 3) 20 ns Input to CE Setup Time t IS (Note 4) Skew Between Channels tS (Notes 5, 6) 0 AC TEST CONDITIONS Input Pulse Levels: VIL = 0.0V, VIH = 2.7V Input Pulse Rise and Fall Times: 5ns Input and Output Timing Reference Level: VCC/2 Output Load: CL (100pF) 2 _______________________________________________________________________________________ ns 1 ns 3.3V 26-Channel, Three-Stateable Transmission Gate DS3690 CAPACITANCE (TA = +25°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Capacitance (CE) CIN Not production tested 5 pF I/O Capacitance CIO Not production tested 8 pF Note 1: All voltages referenced to ground. Note 2: Typical waveform shown is labeled CHxxA (input) to CHxxB (output), and is identical in function when selecting pin CHxxB (as the input) to pin CHxxA (as the output). Note 3: Output reference level is VCC/2. Note 4: Input transitions prior to the CE falling edge are ignored (don’t care). Note 5: Propagation delay differential between any two channels when using a common input signal source. Note 6: Guaranteed by design and not 100% tested. Timing Diagrams CHxxA tPD tPD tPD CHxxB Figure 1. Digital Channel Propagation Delay CE CE tIS CHxxA DON'T CARE DON'T CARE CHxxA tCEZ tCEV CHxxB HIGH IMPEDANCE Figure 2. Digital Channels Enabled by CE CHxxB HIGH IMPEDANCE Figure 3. Digital Channels Disabled by CE _______________________________________________________________________________________ 3 Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) POWER-SUPPLY CURRENT vs. INPUT VOLTAGE CHANNEL ON-RESISTANCE CHANGE vs. INPUT VOLTAGE 1.E-05 1.E-06 TA = +85°C 1.E-07 TA = +25°C 1.E-08 IOUT = -0.1mA, CH1 20 DELTA RESISTANCE (Ω) 10 5 1.E-09 TA = -55°C 0 1.E-10 2.0 2.3 2.6 2.9 0.0 3.2 0.7 1.3 2.0 2.6 INPUT VOLTAGE (V) INPUT VOLTAGE (V) OUTPUT-VOLTAGE HIGH vs. OUTPUT CURRENT OUTPUT-VOLTAGE LOW vs. OUTPUT CURRENT VIN = +3.0V, CH1A–CH1B VIN = +0.3V, CH1A–CH1B 0.5 OUTPUTVOLTAGE (V) 3.1 3.0 2.9 2.8 2.7 3.3 0.6 DS3690 toc03 3.2 0.4 0.3 0.2 0.1 2.6 0.0 -5 -4 -3 -2 OUTPUT CURRENT (mA) 4 15 DS3690 toc04 SUPPLY CURRENT (A) 1.E-04 DS3690 toc02 CE = CH1A–CH26A, CH1B–CH26B = FLOAT 1.E-03 25 DS3690 toc01 1.E-02 OUTPUT VOLTAGE (V) DS3690 3.3V 26-Channel, Three-Stateable Transmission Gate -1 0 0 1 2 3 4 OUTPUT CURRENT (mA) _______________________________________________________________________________________ 5 3.3V 26-Channel, Three-Stateable Transmission Gate PIN NAME FUNCTION 1 CH01A 2 CH02A 3 PIN NAME FUNCTION Channel 1 Terminal A 30 CH19B Channel 19 Terminal B Channel 2 Terminal A 31 CH18B Channel 18 Terminal B CH03A Channel 3 Terminal A 32 CH17B Channel 17 Terminal B 4 CH04A Channel 4 Terminal A 33 CH16B Channel 16 Terminal B 5 CH05A Channel 5 Terminal A 34 CH15B Channel 15 Terminal B 6 CH06A Channel 6 Terminal A 35 CH14B Channel 14 Terminal B 7 CH07A Channel 7 Terminal A 36 CH13B Channel 13 Terminal B 8 CH08A Channel 8 Terminal A 37 CH12B Channel 12 Terminal B 9 CH09A Channel 9 Terminal A 38 CH11B Channel 11 Terminal B 10 CH10A Channel 10 Terminal A 39 CH10B Channel 10 Terminal B 11 CH11A Channel 11 Terminal A 40 CH09B Channel 9 Terminal B 12 CH12A Channel 12 Terminal A 41 CH08B Channel 8 Terminal B 13 CH13A Channel 13 Terminal A 42 CH07B Channel 7 Terminal B 14 CH14A Channel 14 Terminal A 43 CH06B Channel 6 Terminal B 15 CH15A Channel 15 Terminal A 44 CH05B Channel 5 Terminal B 16 CH16A Channel 16 Terminal A 45 CH04B Channel 4 Terminal B 17 CH17A Channel 17 Terminal A 46 CH03B Channel 3 Terminal B 18 CH18A Channel 18 Terminal A 47 CH02B Channel 2 Terminal B 19 CH19A Channel 19 Terminal A 48 CH01B Channel 1 Terminal B 20 CH20A Channel 20 Terminal A 49 CH24B Channel 24 Terminal B 21 CH21A Channel 21 Terminal A 50 CH25B Channel 25 Terminal B 22 CH22A Channel 22 Terminal A 51 CH26B 23 CH23A Channel 23 Terminal A 52 CE Channel 26 Terminal B Chip-Enable Input (Active Low) 24 VCC Supply Voltage 54 CH26A Channel 26 Terminal A 25, 53 GND Ground 55 CH25A Channel 25 Terminal A 26 CH23B Channel 23 Terminal B 56 CH24A Channel 24 Terminal A 27 CH22B Channel 22 Terminal B 28 CH21B Channel 21 Terminal B — EP 29 CH20B Channel 20 Terminal B Exposed Paddle. Must be connected to ground. _______________________________________________________________________________________ 5 DS3690 Pin Description DS3690 3.3V 26-Channel, Three-Stateable Transmission Gate Detailed Description Applications Information The DS3690 is a 26-channel, noninverting, bidirectional CMOS transmission gate, and is intended for use in applications where a downstream component must be isolated from a common control, address, or data bus in a timely fashion. Each of the 26 independent channels can be used for input, output, or I/O signal applications. The chip-enable input (CE) allows gated bus control for either signal transmission or bus isolation. Each independent channel consists of two pins (“CHxxA” and “CHxxB” where xx is 01–26). Since all 26 channels are capable of bidirectional function, either CHxxA or CHxxB can be selected as the input pin for any unidirectional signal requirements. A change of logic state on one side of any channel is directly reflected on the other side of that channel. Signal propagation delay (CHxxA to CHxxB, or CHxxB to CHxxA) is illustrated in Figure 1 as tPD. All channels can be simultaneously enabled or forced to a high-impedance state using the CE input. When CE becomes a logic zero, all channels are enabled for signal transmission within tCEV (see Figure 2). When CE becomes a logic one, all channels are forced to a high-impedance state within tCEZ (see Figure 3). Power-Supply Decoupling To achieve the best results when using the DS3690, decouple the power supply with a 0.1µF capacitor. Use a high-quality, ceramic surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, while ceramic capacitors have adequately high-frequency response for decoupling applications. Pin Connections For optimum circuit operation, connect pins 25 and 53 to a common ground. The exposed pad on the package bottom side should be connected to ground. To prevent an unused transmission channel from generating any undesired activity, it is recommended that one side of that unused channel be connected to ground (either the A or B terminal, at the designer’s discretion). Typical Operating Circuit +3.3V MICRO R/W CONTROL R/W CONTROL ADDRESS (A0–X) ADDRESS (A0–X) I/O (DQ0–X) BUS ENABLE 6 DS3690 I/O (DQ0–X) EXTERNAL MEMORY CE _______________________________________________________________________________________ 3.3V 26-Channel, Three-Stateable Transmission Gate Package Information (For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) VCC CE VCC CH01A CH01B CH02A CH02B CH03A CH03B PACKAGE TYPE DOCUMENT NO. 56 TQFN 21-0187 GND CH26A CH26B DS3690 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 7 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. DS3690 Functional Diagram