TI1 LMV651MF/NOPB Lmv65x 12-mhz, low voltage, low power amplifier Datasheet

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LMV651, LMV652, LMV654
SNOSAI7K – SEPTEMBER 2005 – REVISED MAY 2016
LMV65x 12-MHz, Low Voltage, Low Power Amplifiers
1 Features
3 Description
•
•
•
TI’s LMV65x devices are high-performance, lowpower operational amplifier ICs implemented with TI's
advanced VIP50 process. This family of parts
features 12 MHz of bandwidth while consuming only
116 μA of current, which is an exceptional bandwidth
to power ratio in this operational amplifier class. The
LMV65x devices are unity-gain stable and provide an
excellent solution for general-purpose amplification in
low-voltage, low-power applications.
1
•
•
•
•
•
•
•
•
Typical 5-V Supply, Unless Otherwise Noted
Specified 3-V and 5-V Performance
Low Power Supply Current
– LMV651: 116 μA
– LMV652: 118 μA per Amplifier
– LMV654: 122 μA per Amplifier
High Unity-Gain Bandwidth: 12 MHz
Maximum Input Offset Voltage: 1.5 mV
CMRR: 100 dB
PSRR: 95 dB
Input Referred Voltage Noise: 17 nV/√Hz
Output Swing With 2-kΩ Load, 120 mV from Rail
Total Harmonic Distortion: 0.003% at 1 kHz, 2 kΩ
Temperature Range: −40°C to 125°C
The operating supply voltage range for this family of
parts is from 2.7 V and 5.5 V. These operational
amplifiers can operate over a wide temperature range
(−40°C to 125°C), making them ideal for automotive
applications, sensor applications, and portable
equipment applications. The LMV651 is offered in the
ultra-tiny 5-pin SC70 and 5-pin SOT-23 package. The
LMV652 is offered in an 8-pin VSSOP package. The
LMV654 is offered in a 14-pin TSSOP package.
2 Applications
•
•
•
•
This family of low-voltage, low-power amplifiers
provides superior performance and economy in terms
of power and space usage. These operational
amplifiers have a maximum input offset voltage of 1.5
mV, a rail-to-rail output stage, and an input commonmode voltage range that includes ground. The
LMV65x provide a PSRR of 95 dB, a CMRR of 100
dB, and a total harmonic distortion (THD) of 0.003%
at 1-kHz frequency and 2-kΩ load.
Portable Equipment
Automotive
Battery-Powered Systems
Sensors and Instrumentation
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SC70 (5)
2.00 mm × 1.25 mm
LMV652
VSSOP (8)
3.00 mm × 3.00 mm
LMV654
TSSOP (14)
5.00 mm × 4.40 mm
LMV651
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Open-Loop Gain and Phase vs Frequency
120
CF
120
100
R1
1 k:
R2
100 k:
+
VIN
-
RB1
V
CC2
+
+
+
-
GAIN (dB)
CC1
80
60
60
40
R1
40
GAIN
20
20
0
0
-20
R2
100
VOUT
RB2
AV = -
PHASE
80
PHASE (q)
High Gain Wide Bandwidth Inverting Amplifier
= -100
-20
+
V = 5V
-40
100
1k
10k
100k
1M
10M
-40
100M
FREQUENCY (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV651, LMV652, LMV654
SNOSAI7K – SEPTEMBER 2005 – REVISED MAY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
3-V DC Electrical Characteristics..............................
5-V DC Electrical Characteristics..............................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
13
14
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Applications ................................................ 16
8.3 Dos and Don'ts ....................................................... 18
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Documentation Support .......................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
20
20
21
12 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (March 2013) to Revision K
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision I (March 2012) to Revision J
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 18
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SNOSAI7K – SEPTEMBER 2005 – REVISED MAY 2016
5 Pin Configuration and Functions
LMV651 DBV or DCK Package
5-Pin SC70 or SOT-23
Top View
LMV652 DGK Package
8-Pin VSSOP
Top View
LMV654 PW Package
14-Pin TSSOP
Top View
Pin Functions: LMV651
PIN
NAME
I/O
NO.
DESCRIPTION
–IN
3
I
Inverting Input
+IN
1
I
Noninverting Input
OUT
4
O
Output
V–
2
P
Negative supply input
V+
5
P
Positive Supply Input
Pin Functions: LMV652, LMV654
PIN
I/O
DESCRIPTION
NAME
VSSOP
TSSOP
–IN A
2
2
I
Inverting input, channel A
+IN A
3
3
I
Noninverting input, channel A
–IN B
6
6
I
Inverting input, channel B
+IN B
5
5
I
Noninverting input, channel B
–IN C
—
9
I
Inverting input, channel C
+IN C
—
10
I
Noninverting input, channel C
–IN D
—
13
I
Inverting input, channel D
+IN D
—
12
I
Noninverting input, channel D
OUT A
1
1
O
Output, channel A
OUT B
7
7
O
Output, channel B
OUT C
—
8
O
Output, channel C
OUT D
—
14
O
Output, channel D
V–
4
11
P
Negative (lowest) power supply
V+
8
4
P
Positive (highest) power supply
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6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
MIN
MAX
Differential input VID
Supply voltage (VS = V+ - V−)
6
V− − 0.3
Input or output pin voltage
Soldering information
V+ + 0.3
Infrared or convection (20 sec)
235
Wave soldering lead temperature (10 sec)
260
Junction temperature (3)
−65
Storage temperature, Tstg
(1)
(2)
(3)
UNIT
±0.3
V
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The maximum power dissipation is a function of TJ(MAX, θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA. All numbers apply for packages soldered directly onto a PC board.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM)
(1)
±2000
Machine model (2)
UNIT
V
±100
Human Body Model, applicable std. MIL-STD-883, Method 3015.7
Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22C101-C (ESD FICDM std. of JEDEC).
6.3 Recommended Operating Conditions
MIN
MAX
UNIT
Temperature
−40
125
°C
Supply voltage
2.7
5.5
V
6.4 Thermal Information
LMV652
LMV653
DCK
(SC70)
LMV651
DBV
(SOT-23)
DGK
(VSSOP)
PW
(TSSOP)
5 PINS
5 PINS
8 PINS
14 PINS
303.5
214.2
200.3
134.9
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
135.5
173.3
89.1
60.9
°C/W
RθJB
Junction-to-board thermal resistance
81.1
72.5
120.9
77.3
°C/W
ψJT
Junction-to-top characterization parameter
8.4
56.7
21.7
11.5
°C/W
ψJB
Junction-to-board characterization parameter
80.4
71.9
119.4
76.7
°C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
°C/W
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
UNIT
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SNOSAI7K – SEPTEMBER 2005 – REVISED MAY 2016
6.5 3-V DC Electrical Characteristics
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 3 V, V− = 0 V, VO = VCM = V+/2, and RL > 1 MΩ.
PARAMETER
MIN (1)
TEST CONDITIONS
TYP (2)
MAX (1)
0.1
±1.5
UNIT
VOS
Input offset voltage
TC VOS
Input offset average drift
6.6
IB
Input bias current (3)
80
120
nA
IOS
Input offset current
2.2
15
nA
CMRR
Common-mode rejection ratio
Over specified temperature range
87
0 ≤ VCM≤ 2 V
Over specified temperature range
3 ≤ V+ ≤ 5 V, VCM = 0.5
PSRR
Power supply rejection ratio
2.7 ≤ V+ ≤ 5.5 V,
VCM = 0.5
CMVR
AVOL
Input common-mode voltage
range
Large signal voltage gain
mV
2.7
μV/°C
100
dB
80
87
Over specified temperature range
95
81
87
Over specified temperature range
dB
95
81
CMRR ≥ 75 dB
0
2.1
CMRR ≥ 60 dB, over specified temperature range
0
2.1
0.3 ≤ VO ≤ 2.7, RL = 2 kΩ to V+/2
80
0.4 ≤ VO ≤ 2.6, RL = 2 kΩ to V+/2, over specified temperature range
76
0.3 ≤ VO ≤ 2.7, RL = 10 kΩ to V+/2
86
V
85
dB
93
+
0.4 ≤ VO ≤ 2.6, RL = 10 kΩ to V /2, over specified temperature
range
RL = 2 kΩ to V+/2
Output swing high
RL = 10 kΩ to V+/2
VO
80
Over specified temperature range
RL = 2 kΩ to V /2
RL = 10 kΩ to V+/2
Maximum continuous output
current
ISC
IS
Supply current per amplifier
Slew rate
GBW
Gain bandwidth product
en
Input-referred voltage noise
in
Input-referred current noise
THD
Total harmonic distortion
(1)
(2)
(3)
(4)
(5)
50
95
110
60
Over specified temperature range
Over specified temperature range
25
115
Over specified temperature range
Over specified temperature range
122
μA
140
175
V/μs
12
MHz
17
f = 1 kHz
17
f = 1 kHz, AV = 2, RL = 2 kΩ
140
3.0
f = 100 kHz
f = 1 kHz
140
175
Over specified temperature range
f = 100 kHz
mA
175
118
AV = +1, 10% to 90% (5)
65
75
Sinking (4)
LMV652
mV from
rail
125
60
17
LMV654
SR
45
Sourcing (4)
LMV651
95
120
Over specified temperature range
+
Output swing low
83
0.1
0.15
nV/√Hz
pA/√Hz
0.003%
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Positive current corresponds to current flowing into the device.
Slew rate is the average of the rising and falling slew rates.
The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output
current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads.
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6.6 5-V DC Electrical Characteristics
Unless otherwise specified, all limits are specified for TJ = 25°C, V+ = 5 V, V− = 0 V, VO = VCM = V+/2, and RL > 1 MΩ.
PARAMETER
VOS
Input offset voltage
TC VOS
Input offset average drift
IB
Input bias current
IOS
Input offset current
CMRR
Common-mode rejection ratio
AVOL
Large signal voltage gain
0.1
±1.5
90
0 ≤ VCM≤ 4 V
Over specified temperature range
Over specified temperature range
120
nA
2.2
15
nA
100
dB
95
81
87
mV
80
83
87
Over specified temperature range
UNIT
μV/°C
6.6
2.7 V ≤ V+ ≤ 5.5 V, VCM =
0.5 V
CMVR
MAX (1)
2.7
See (3)
Power supply rejection ratio
Input common-mode voltage
range
TYP (2)
Over specified temperature range
3 V ≤ V+ ≤ 5 V, VCM = 0.5 V
PSRR
MIN (1)
TEST CONDITIONS
dB
95
81
CMRR ≥ 80 dB
0
4.1
CMRR ≥ 68 dB, over specified temperature range
0
4.1
0.3 ≤ VO ≤ 4.7 V, RL = 2 kΩ to V+/2
79
0.4 ≤ VO ≤ 4.6 V, RL = 2 kΩ to V+/2, over specified temperature range
76
0.3 ≤ VO ≤ 4.7 V, RL = 10 kΩ to V+/2
87
V
84
dB
94
+
0.4 ≤ VO ≤ 4.6 V, RL = 10 kΩ to V /2, over specified temperature
range
RL = 2 kΩ to V+/2
Output swing high
RL = 10 kΩ to V+/2
VO
120
Over specified temperature range
RL = 2 kΩ to V /2
RL = 10 kΩ to V+/2
Over specified temperature range
Maximum continuous output
current
ISC
IS
Supply current per amplifier
LMV652
LMV654
SR
Slew rate
GBW
Gain bandwidth product
en
Input-referred voltage noise
in
Input-referred current noise
THD
Total harmonic distortion
(1)
(2)
(3)
(4)
(5)
6
Over specified temperature range
130
Over specified temperature range
80
95
18.5
mA
25
116
Over specified temperature range
Over specified temperature range
122
140
175
V/μs
12
MHz
17
f = 1 kHz
17
0.1
0.15
f = 1 kHz, AV = 2, RL = 2 kΩ
μA
3.0
f = 100 kHz
f = 1 kHz
140
175
Over specified temperature range
f = 100 kHz
140
175
118
AV = +1, VO = 1 VPP, 10% to 90% (5)
mV from
rail
150
70
Sinking (4)
LMV651
90
120
110
Sourcing (4)
140
185
75
+
Output swing low
84
nV/√Hz
pA/√Hz
0.003%
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Positive current corresponds to current flowing into the device.
The part is not short-circuit protected and is not recommended for operation with low resistive loads. Typical sourcing and sinking output
current curves are provided in Typical Characteristics and should be consulted before designing for heavy loads.
Slew rate is the average of the rising and falling slew rates.
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6.7 Typical Characteristics
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V−= 0 V, VCM= VS/2
180
180
160
140
140
IS (PA)
IS (PA)
125°C
160
25°C
120
125°C
25°C
120
-40°C
-40°C
100
100
80
2.7
3.2
3.7
4.2
4.7
80
2.7
5.2 5.5
3.2
3.7
4.2
4.7
5.2 5.5
VS (V)
VS (V)
Figure 1. Supply Current vs Supply Voltage (LMV651)
Figure 2. Supply Current per Channel vs Supply Voltage
(LMV652)
1
180
0.75
125°C
125°C
140
0.5
VOS (mV)
IS (PA)
160
25°C
120
0.25
0
25°C
-0.25
-40°C
-0.5
-40°C
100
-0.75
VS = 3V
-1
80
2.7
3.2
3.7
4.2
4.7
5.2 5.5
0
0.5
1
VS (V)
Figure 3. Supply Current per Channel vs Supply Voltage
(LMV654)
2
2.5
Figure 4. VOS vs VCM
1
1
0.75
0.75
125°C
0.5
0.5
0.25
0.25
0
VOS (mV)
VOS (mV)
1.5
VCM (V)
25°C
-0.25
0
25°C
-0.25
-40°C
-0.5
-0.5
-0.75
125°C
-40°C
-0.75
VS = 5V
-1
-1
0
1
2
3
4
5
2.7
VCM (V)
3.2
3.7
4.2
4.7
5.2 5.5
VS (V)
Figure 5. VOS vs VCM
Figure 6. VOS vs Supply Voltage
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Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V−= 0 V, VCM= VS/2
100
100
90
80
80
IBIAS (nA)
IBIAS (nA)
125°C
90
25°C
70
-40°C
125°C
70
25°C
-40°C
60
60
VS = 3V
VS = 5V
50
50
0.5
0
1.5
1
2
2.5
1
0
VCM (V)
3
4
5
4.6
5
VCM (V)
Figure 7. IBIAS vs VCM
Figure 8. IBIAS vs VCM
100
150
VOUT FROM RAIL (mV)
90
125°C
IBIAS (nA)
2
80
25°C
70
-40°C
125°C
120
90
25°C
60
60
30
50
0
-40°C
RL = 2 k:
2.7
3.2
3.7
4.2
5.2 5.5
4.7
3
3.4
VS (V)
3.8
4.2
VS (V)
Figure 9. IBIAS vs Supply Voltage
Figure 10. Positive Output Swing vs Supply Voltage
150
100
125°C
VOUT FROM RAIL (mV)
VOUT FROM RAIL (mV)
125°C
120
90
25°C
-40°C
60
30
80
60
40
25°C
-40°C
20
RL = 2 k:
RL = 10 k:
0
0
3
8
3.4
3.8
4.2
4.6
5
3
3.4
3.8
4.2
4.6
5
VS (V)
VS (V)
Figure 11. Negative Output Swing vs Supply Voltage
Figure 12. Positive Output Swing vs Supply Voltage
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Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V−= 0 V, VCM= VS/2
30
90
125°C
VS = 5V
25
25°C
60
ISOURCE (mA)
VOUT FROM RAIL (mV)
75
25°C
45
-40°C
30
-40°C
20
15
125°C
10
5
15
RL = 10 k:
0
0
3
3.4
3.8
4.2
4.6
5
0.25
0
0.5
VS (V)
Figure 13. Negative Output Swing vs Supply Voltage
1.25
1.5
50
VS = 5V
VS = 5V
-40°C
-40°C
40
40
25°C
25°C
ISINK (mA)
ISINK (mA)
1
Figure 14. Sourcing Current vs Output Voltage
50
30
125°C
20
10
0
0.75
VOUT FROM RAIL (V)
30
125°C
20
10
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45
VOUT FROM RAIL (V)
VOUT FROM RAIL (V)
Figure 15. Sinking Current vs Output Voltage (LMV651)
Figure 16. Sinking Current vs Output Voltage (LMV652)
50
180
180
RL = 2 k:
-40°C
150
120
120
GAIN (dB)
25°C
ISINK (mA)
150
PHASE
40
30
125°C
20
CL = 20 pF 90
90
CL = 100 pF
60
60
CL = 50 pF
GAIN
30
30
0
0
10
CL = 100 pF
-30
0
0
0.1
0.2
0.3
0.4
0.5
-60
100
-30
CL = 50 pF
1k
VOUT FROM RAIL (V)
Figure 17. Sinking Current vs Output Voltage (LMV654)
PHASE (°)
VS = 5V
10k
100k
1M
10M
-60
100M
FREQUENCY (Hz)
Figure 18. Open-Loop Gain and Phase With Capacitive Load
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Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V−= 0 V, VCM= VS/2
180
180
60
CL = 20 pF
150
RL = 2 k:
150
PHASE
50
120
120
GAIN (dB)
RL = 10:
60
60
GAIN
30
30
RL = 2 k:
0
PHASE (°)
90
90
PHASE MARGIN (°)
RL = 2 k:
0
40
30
20
VS = 3V
10
-30
-30
-60
100
1k
10k
100k
1M
-60
100M
10M
VS = 5V
0
100
10
FREQUENCY (Hz)
INPUT REFERRED CURRENT NOISE
(nV/ HZ)
INPUT REFERRED VOLTAGE NOISE
100
Figure 20. Phase Margin vs Capacitive Load (Stability)
10
10
1
(pA/ HZ)
Figure 19. Open-Loop Gain and Phase With Resistive Load
1
1
10
1k
100
1000
CL (pF)
10k
0.10
0.01
100k
1
10
100
10k
1k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. Input-Referred Voltage Noise vs Frequency
Figure 22. Input-Referred Current Noise vs Frequency
4
1
3
0.1
RISING
2.5
2
THD+N (%)
SLEW RATE (V/Ps)
3.5
FALLING
1.5
RL = 2 k:
0.01
RL = 100 k:
1
0.001 V = 3V
S
VIN = 1 kHz SINE WAVE
0.5
0
3
3.5
4
4.5
5
AV = +2
0.0001
0.001
0.01
Figure 23. Slew Rate vs Supply Voltage
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0.1
1
10
VOUT (V)
VS (V)
Figure 24. THD+N vs VOUT
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Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V−= 0 V, VCM= VS/2
1
1
VS = 3V
VIN = 1 VPP
AV = +2
0.1
THD+N (%)
THD+N (%)
0.1
RL = 2 k:
RL = 100 k:
0.01
RL = 2 k:
0.01
VS = 5V
VIN = 1 kHz SINE WAVE
RL = 100 k:
AV = +2
0.001
0.001
0.01
0.1
1
0.001
10
10
100
1k
10k
VOUT (V)
FREQUENCY (Hz)
Figure 25. THD+N vs VOUT
Figure 26. THD+N vs Frequency
100k
30
0.1
VS = 5V
VS = 5V
25
VIN = 2 VPP
CL = 15 pF, AV = +1
20
AV = +2
RL = 2 k:
VOUT (mV)
0.01
THD+N (%)
VIN = 20 mVPP, 20 kHz
15
RL = 100 k:
0.001
10
5
0
-5
-10
-15
-20
0.0001
10
100
1k
10k
100k
0
20
40
60
80
100
TIME (Ps)
FREQUENCY (Hz)
Figure 28. Small Signal Transient Response
Figure 27. THD+N vs Frequency
1.5
30
25
1
20
15
0.5
VOUT (mV)
VOUT (mV)
10
5
0
-5
VS = 5V
0
CL = 15 pF, AV = +1
VIN = 2 VPP, 20 kHz
-0.5
-10
-15
VS = 5V
-20
-1
CL = 125 pF, AV = +1
-25
VIN = 20 mVPP, 20 kHz
-30
0
20
40
-1.5
60
70
80
0
20
40
60
80
100
TIME (Ps)
TIME (Ps)
Figure 29. Small Signal Transient Response
Figure 30. Large Signal Transient Response
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Typical Characteristics (continued)
Unless otherwise specified, TA= 25°C, VS= 5 V, V+= 5 V, V−= 0 V, VCM= VS/2
120
120
VS = 5V, +PSRR
VS = 3V, +PSRR
100
100
VS = 5V, -PSRR
60
80
CMRR (dB)
PSRR (dB)
80
VS = 3V, -PSRR
60
40
40
20
20
0
0
10
100
1k
10k
100k
1M
10M
10
1k
100
FREQUENCY (Hz)
10k
100k
1M
FREQUENCY (Hz)
Figure 31. PSRR vs Frequency
Figure 32. CMRR vs Frequency
1000
ZOUT (W)
100
10
1
0.1
0.01
10
100
1k
10k 100k
1M
10M 100M
FREQUENCY (Hz)
Figure 33. Closed-Loop Output Impedance vs Frequency
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7 Detailed Description
7.1 Overview
TI’s LMV65x devices have 12 MHz of bandwidth, are unity-gain stable, and consume only 116 μA of current.
They also have a maximum input offset voltage of 1.5 mV, a rail-to-rail output stage, and an input common-mode
voltage range that includes ground. Lastly, these operational amplifiers provide a PSRR of 95 dB, a CMRR of
100 dB, and a total harmonic distortion (THD) of 0.003% at 1-kHz frequency and 2-kΩ load.
7.2 Functional Block Diagram
(Each Amplifier)
7.3 Feature Description
7.3.1 Low Voltage and Low Power Operation
The LMV65x have performance specified at supply voltages of 3 V and 5 V. These parts are specified to be
operational at all supply voltages between 2.7 V and 5.5 V. The LMV651 draws a low supply current of 116 μA,
the LMV652 draws 118 μA/channel and the LMV654 draws 122 μA/channel. This family of operational amplifiers
provides the low voltage and low power amplification that is essential for portable applications.
7.3.2 Wide Bandwidth
Despite drawing the very low supply current of 116 µA, the LMV65x manage to provide a wide unity-gain
bandwidth of 12 MHz. This is easily one of the best bandwidth to power ratios ever achieved, and allows these
operational amplifiers to provide wideband amplification while using the minimum amount of power. This makes
this family of parts ideal for low-power signal processing applications such as portable media players and other
accessories.
7.3.3 Low Input Referred Noise
The LMV65x provides a flatband input referred voltage noise density of 17 nV/√Hz, which is significantly better
than the noise performance expected from a low-power operational amplifiers. These operational amplifiers also
feature exceptionally low 1/f noise, with a very low 1/f noise corner frequency of 4 Hz. This makes these parts
ideal for low power applications which require decent noise performance, such as PDAs and portable sensors.
7.3.4 Ground Sensing and Rail-to-Rail Output
The LMV65x each have a rail-to-rail output stage, which provides the maximum possible output dynamic range.
This is especially important for applications requiring a large output swing. The input common-mode range of this
family of devices includes the negative supply rail which allows direct sensing at ground in a single-supply
operation.
7.3.5 Small Size
The small footprint of the packages for the LMV65x saves space on printed-circuit boards, and enables the
design of smaller and more compact electronic products. Long traces between the signal source and the
operational amplifier make the signal path susceptible to noise. By using a physically smaller package, these
operational amplifiers can be placed closer to the signal source, reducing noise pickup and enhancing signal
integrity.
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7.4 Device Functional Modes
7.4.1 Stability and Capacitive Loading
GAIN
If the phase margin of the LMV65x is plotted with respect to the capacitive load (CL) at its output, it is seen that
the phase margin reduces significantly if CL is increased beyond 100 pF. This is because the operational
amplifier is designed to provide the maximum bandwidth possible for a low supply current. Stabilizing it for higher
capacitive loads would have required either a drastic increase in supply current, or a large internal compensation
capacitance, which would have reduced the bandwidth of the operational amplifier. Hence, if these devices are to
be used for driving higher capacitive loads, they would have to be externally compensated.
STABLE
ROC ± 20 dB/decade
UNSTABLE
ROC = 40 dB/decade
0
FREQUENCY (Hz)
Figure 34. Gain vs Frequency for an Operational Amplifiers
An operational amplifier, ideally, has a dominant pole close to DC, which causes its gain to decay at the rate of
20 dB/decade with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains
the same until the unity-gain bandwidth of the operational amplifiers is stable. If, however, a large capacitance is
added to the output of the operational amplifier, it combines with the output impedance of the operational
amplifier to create another pole in its frequency response before its unity-gain frequency (see Figure 34). This
increases the ROC to 40 dB/decade and causes instability.
In such a case a number of techniques can be used to restore stability to the circuit. The idea behind all these
schemes is to modify the frequency response such that it can be restored to an ROC of 20 dB/decade, which
ensures stability.
7.4.2 In The Loop Compensation
Figure 35 illustrates a compensation technique, known as in-the-loop compensation, that employs an RC
feedback circuit within the feedback loop to stabilize a noninverting amplifier configuration. A small series
resistance, RS, is used to isolate the amplifier output from the load capacitance, CL, and a small capacitance, CF,
is inserted across the feedback resistor to bypass CL at higher frequencies.
VIN
+
ROUT
-
RS
CL
RL
CF
RF
RIN
Figure 35. In-the-Loop Compensation
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Device Functional Modes (continued)
The values for RS and CF are decided by ensuring that the zero attributed to CF lies at the same frequency as the
pole attributed to CL. This ensures that the effect of the second pole on the transfer function is compensated for
by the presence of the zero, and that the ROC is maintained at 20 dB/decade. For the circuit shown in Figure 35
the values of RS and CF are given by Equation 1. Values of RS and CF required for maintaining stability for
different values of CL, as well as the phase margins obtained, are shown in Table 1. RF and RIN are taken to be
10 kΩ, RL is 2 kΩ, while ROUT is taken as 340 Ω.
RS = ROUTRIN
RF
§ RF + 2RIN
CLROUT
CF = ¨¨
2
© RF
§
¨
¨
©
(1)
Table 1. Loop Compensation Values
CL (pF)
RS (Ω)
CF (pF)
PHASE MARGIN (°)
150
340
15
39.4
200
340
20
34.6
250
340
25
31.1
Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth.
The closed-loop bandwidth of the circuit is now limited by RF and CF.
7.4.3 Compensation By External Resistor
In some applications, it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the
loop compensation is not viable. A simpler scheme for compensation is shown in Figure 36. A resistor, RISO, is
placed in series between the load capacitance and the output. This introduces a zero in the circuit transfer
function, which counteracts the effect of the pole formed by the load capacitance, and ensures stability. The
value of RISO to be used should be decided depending on the size of CL and the level of performance desired.
Values ranging from 5 Ω to 50 Ω are usually sufficient to ensure stability. A larger value of RISO results in a
system with lesser ringing and overshoot, but it also limits the output swing and the short-circuit current of the
circuit.
Figure 36. Compensation by Isolation Resistor
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
With a low supply current, low power operation, and low harmonic distortion, the LMV65x devices are ideal for
wide-bandwidth, high gain amplification.
8.2 Typical Applications
8.2.1 High Gain, Low Power Inverting Amplifiers
CF
CC1
R1
1 k:
R2
100 k:
+
VIN
-
RB1
V
CC2
+
+
+
-
VOUT
RB2
AV = -
R2
R1
= -100
Figure 37. High Gain Inverting Amplifier
8.2.1.1 Design Requirements
The wide unity-gain bandwidth allows these parts to provide large gain over a wide frequency range, while
driving loads as low as 2 kΩ with less than 0.003% distortion.
8.2.1.2 Detailed Design Procedure
Figure 37 is an inverting amplifier, with a 100-kΩ feedback resistor, R2, and a 1-kΩ input resistor, R1, and
provides a gain of −100. With the LMV65x, these circuits can provide gain of −100 with a −3-dB bandwidth of
120 kHz, for a quiescent current as low as 116 μA. Coupling capacitors CC1 and CC2 can be added to isolate the
circuit from DC voltages, while RB1 and RB2 provide DC biasing. A feedback capacitor CF can also be added to
improve compensation.
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Typical Applications (continued)
Signal Amplitudee
8.2.1.3 Application Curve
Vout (1V/div)
Vin (10mV/div)
0
50
100
150
200
Time (us)
C001
Figure 38. High Gain Inverting Amplifier Results
8.2.2 High Gain, Low Power Noninverting Amplifiers
With a low supply current, low power operation, and low harmonic distortion, the LMV65x devices are ideal for
wide-bandwidth, high gain amplification. The wide unity-gain bandwidth allows these parts to provide large gain
over a wide frequency range, while driving loads as low as 2 kΩ with less than 0.003% distortion. Figure 39 is a
noninverting amplifier with a gain of 1001, can provide that gain with a −3-dB bandwidth of 12 kHz, for a similar
low quiescent power dissipation. With the LMV65x, these circuits can provide gain of −100 with a −3-dB
bandwidth of 120 kHz, for a quiescent current as low as 116 μA. Coupling capacitors CC1 and CC2 can be added
to isolate the circuit from DC voltages, while RB1 and RB2 provide DC biasing. A feedback capacitor CF can also
be added to improve compensation.
+
V
CC2
RB1
+
VIN
-
RB2
R1
1 k:
CC1
+
-
+
R2
1 M:
-
VOUT
CF
R2
AV = 1 +
R1
= 1001
Figure 39. High Gain Noninverting Amplifier
8.2.3 Active Filters
With a wide unity-gain bandwidth of 12 MHz, low input-referred noise density, and a low power supply current,
the LMV65x devices are well suited for low-power filtering applications. Active filter topologies, like the SallenKey low-pass filter shown in Figure 40, are very versatile, and can be used to design a wide variety of filters
(Chebyshev, Butterworth, or Bessel). The Sallen-Key topology, in particular, can be used to attain a wide range
of Q, by using positive feedback to reject the undesired frequency range.
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Typical Applications (continued)
In the circuit shown in Figure 40, the two capacitors appear as open circuits at lower frequencies and the signal
is simply buffered to the output. At high frequencies the capacitors appear as short circuits and the signal is
shunted to ground by one of the capacitors before it can be amplified. Near the cutoff frequency, where the
impedance of the capacitances is on the same order as Rg and Rf, positive feedback through the other capacitor
allows the circuit to attain the desired Q. The ratio of the two resistors, m2, provides a knob to control the value of
Q obtained.
C
2
m R
R
VIN
+
VOUT
C
RG
R1
Figure 40. Sallen-Key Low-Pass Filter
8.3 Dos and Don'ts
Do properly bypass the power supplies.
Do add series resistence to the output when driving capacitive loads, particularly cables, Muxes, and ADC inputs.
Do add series current limiting resistors and external Schottky clamp diodes if input voltage is expected to exceed
the supplies. Limit the current to 1 mA or less (1 kΩ per volt).
9 Power Supply Recommendations
For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI
recommends that 10-nF capacitors be placed as close as possible to the operational amplifier power supply pins.
For single supply, place a capacitor between V+ and V– supply leads. For dual supplies, place one capacitor
between V+ and ground, and one capacitor between V– and ground.
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10 Layout
10.1 Layout Guidelines
To properly bypass the power supply, several locations on a printed-circuit board need to be considered. A
6.8-µF or greater tantalum capacitor must be placed at the point where the power supply for the amplifier is
introduced onto the board. Another 0.1-µF ceramic capacitor must be placed as close as possible to the power
supply pin of the amplifier. If the amplifier is operated in a single power supply, only the V+ pin needs to be
bypassed with a 0.1-µF capacitor. If the amplifier is operated in a dual power supply, both V+ and V– pins must
be bypassed.
It is good practice to use a ground plane on a printed-circuit board to provide all components with a low inductive
ground connection.
Surface mount components in 0805 size or smaller are recommended in the LMV651-N application circuits.
Designers can take advantage of the VSSOP miniature sizes to condense board layout in order to save space
and reduce stray capacitance.
10.2 Layout Example
Figure 41. LMV65x Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMV651 PSPICE Model http://www.ti.com/lit/zip/snom064
LMV652 PSPICE Model http://www.ti.com/lit/zip/snom065
LMV654 PSPICE Model http://www.ti.com/lit/zip/snom066
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
TI Filterpro Software, http://www.ti.com/tool/filterpro
11.2 Documentation Support
11.2.1 Related Documentation
For additional applications, see the following:
AN-31 Op Amp Circuit Collection, SNLA140
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LMV651
Click here
Click here
Click here
Click here
Click here
LMV652
Click here
Click here
Click here
Click here
Click here
LMV654
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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25-Jan-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMV651MF/NOPB
ACTIVE
SOT-23
DBV
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
AY2A
LMV651MFX/NOPB
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
AY2A
LMV651MG/NOPB
ACTIVE
SC70
DCK
5
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
A93
LMV651MGX/NOPB
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
A93
LMV652MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AB3A
LMV652MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
AB3A
LMV654MT/NOPB
ACTIVE
TSSOP
PW
14
94
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV65
4MT
LMV654MTX/NOPB
ACTIVE
TSSOP
PW
14
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV65
4MT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
25-Jan-2016
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
LMV651MF/NOPB
SOT-23
LMV651MFX/NOPB
LMV651MG/NOPB
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.2
1.4
4.0
8.0
Q3
DBV
5
1000
178.0
8.4
SOT-23
DBV
5
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SC70
DCK
5
1000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV651MGX/NOPB
SC70
DCK
5
3000
178.0
8.4
2.25
2.45
1.2
4.0
8.0
Q3
LMV652MM/NOPB
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV652MMX/NOPB
VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LMV654MTX/NOPB
TSSOP
PW
14
2500
330.0
12.4
6.95
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
3.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV651MF/NOPB
SOT-23
DBV
5
1000
210.0
185.0
35.0
LMV651MFX/NOPB
SOT-23
DBV
5
3000
210.0
185.0
35.0
LMV651MG/NOPB
SC70
DCK
5
1000
210.0
185.0
35.0
LMV651MGX/NOPB
SC70
DCK
5
3000
210.0
185.0
35.0
LMV652MM/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LMV652MMX/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
LMV654MTX/NOPB
TSSOP
PW
14
2500
367.0
367.0
35.0
Pack Materials-Page 2
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