AD OP-184 Precision rail-to-rail input & output operational amplifier Datasheet

a
Precision Rail-to-Rail Input & Output
Operational Amplifiers
OP184/OP284/OP484
FEATURES
Single-Supply Operation
Wide Bandwidth: 4 MHz
Low Offset Voltage: 65 mV
Unity-Gain Stable
High Slew Rate: 4.0 V/ms
Low Noise: 3.9 nV/√Hz
APPLICATIONS
Battery Powered Instrumentation
Power Supply Control and Protection
Telecom
DAC Output Amplifier
ADC Input Buffer
PIN CONFIGURATIONS
8-Lead Epoxy DIP
(P Suffix)
8-Lead SO
(S Suffix)
NULL
1
8
NC
–IN A
2
7
V+
+IN A
3
6
OUT A
V–
4
5
NULL
NC = NO CONNECT
8-Lead Epoxy DIP
(P Suffix)
8-Lead SO
(S Suffix)
GENERAL DESCRIPTION
The OP184/OP284/OP484 are single, dual and quad singlesupply, 4 MHz bandwidth amplifiers featuring rail-to-rail inputs
and outputs. They are guaranteed to operate from +3 to +36 (or
± 1.5 to ± 18) volts and will function with a single supply as low
as +1.5 volts.
These amplifiers are superb for single supply applications requiring both ac and precision dc performance. The combination
of bandwidth, low noise and precision makes the OP184/OP284/
OP484 useful in a wide variety of applications, including filters
and instrumentation.
Other applications for these amplifiers include portable telecom
equipment, power supply control and protection, and as amplifiers or buffers for transducers with wide output ranges. Sensors
requiring a rail-to-rail input amplifier include Hall effect, piezo
electric, and resistive transducers.
The ability to swing rail-to-rail at both the input and output enables designers to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios.
The OP184/OP284/OP484 are specified over the HOT extended
industrial (–40°C to +125°C) temperature range. The single
and dual are available in 8-pin plastic DIP plus SO surface
mount packages. The quad OP484 is available in 14-pin plastic
DIPs and 14-lead narrow-body SO packages.
OP184
OP284
8
V+
2
7
OUT B
+IN A 3
6
–IN B
4
5
+IN B
OUT A 1
–IN A
V–
14-Lead Epoxy DIP
(P Suffix)
14-Lead Narrow-Body SO
(S Suffix)
OUT A 1
14 OUT D
–IN A 2
13 –IN D
+IN A
3
V+
4
+IN B
5
12 +IN D
OP484
11 V–
10 +IN C
–IN B 6
9
–IN C
OUT B 7
8
OUT C
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
OP184/OP284/OP484–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = +5.0 V, V
S
CM
= 2.5 V, TA = +258C unless otherwise noted)
Parameter
Symbol
Conditions
INPUT CHARACTERISTICS
Offset Voltage “OP184/284E” Grade
VOS
(Note 1)
–40°C ≤ TA ≤ +125°C
Offset Voltage “OP184/284F” Grade
VOS
Offset Voltage “OP484E” Grade
VOS
Offset Voltage “OP484F” Grade
VOS
Input Bias Current
IB
Input Offset Current
IOS
Input Voltage Range
Common-Mode Rejection Ratio
Common-Mode Rejection Ratio
Large Signal Voltage Gain
CMRR
CMRR
AVO
Bias Current Drift
∆IB/∆T
Min
Typ Max Units
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
60
–40°C ≤ TA ≤ +125°C
2
–40°C ≤ TA ≤ +125°C
VCM = 0 V to 5 V
VCM = 1.0 V to 4.0 V, –40°C ≤ TA ≤ +125°C
RL = 2 kΩ, 1 V ≤ VO ≤ 4 V
RL = 2 kΩ, –40°C ≤ TA ≤ +125°C
0
60
86
50
25
65
165
125
350
75
175
150
450
350
575
50
50
+5
240
150
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
VOH
VOL
IOUT
IL = 1.0 mA
IL = 1.0 mA
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Voltage Range
PSRR
ISY
VS
VS = +2.0 V to +10 V, –40°C ≤ TA ≤ +125°C
VO = 2.5 V, –40°C ≤ TA ≤ +125°C
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
Gain Bandwidth Product
Phase Margin
SR
ts
GBP
Øo
RL = 2 kΩ
To 0.01%, 1.0 V Step
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
+4.85
125
± 6.5
76
1.45
+36
+3
1.65
µV
µV
µV
µV
µV
µV
µV
µV
nA
nA
nA
nA
V
dB
dB
V/mV
V/mV
pA/°C
V
mV
mA
dB
mA
V
2.4
2.5
3.25
45
V/µs
µs
MHz
Degrees
0.3
3.9
0.4
µV p-p
nV/√Hz
pA/√Hz
NOTES
1
Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Specifications subject to change without notice.
–2–
REV. 0
OP184/OP284/OP484
ELECTRICAL CHARACTERISTICS (@ V = +3.0 V, V
S
CM
= 1.5 V, TA = +258C unless otherwise noted)
Parameter
Symbol
Conditions
Min
INPUT CHARACTERISTICS
Offset Voltage “OP184/284E” Grade
VOS
(Note 1)
–40°C ≤ TA ≤ +125°C
Offset Voltage “OP184/284F” Grade
VOS
Offset Voltage “OP484E” Grade
VOS
Offset Voltage “OP484F” Grade
VOS
Input Bias Current
IB
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Common-Mode Rejection Ratio
IOS
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
CMRR
CMRR
VCM = 0 V to 3 V
VCM = 0 V to 3 V, –40°C ≤ TA ≤ +125°C
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
VOH
VOL
IL = 1.0 mA
IL = 1.0 mA
+2.85
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
PSRR
ISY
VS = ± 1.25 V to ± 1.75 V
VO = 1.5 V, –40°C ≤ TA ≤ +125°C
76
DYNAMIC PERFORMANCE
Gain Bandwidth Product
GBP
NOISE PERFORMANCE
Voltage Noise Density
en
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
60
0
60
56
f = 1 kHz
NOTES
1
Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Specifications subject to change without notice.
REV. 0
Typ
–3–
Max
Units
65
165
125
350
100
200
150
450
350
575
50
+3
µV
µV
µV
µV
µV
µV
µV
µV
nA
nA
nA
V
dB
dB
125
V
mV
1.35
dB
mA
3
MHz
3.9
nV/√Hz
OP184/OP284/OP484
ELECTRICAL CHARACTERISTICS (@ V = 615.0 V, V
S
Parameter
Symbol
CM
= 0 V, TA = +258C unless otherwise noted)
Conditions
INPUT CHARACTERISTICS
Offset Voltage “OP184/284E” Grade VOS
Min Typ
(Note 1)
–40°C ≤ TA ≤ +125°C
Offset Voltage “OP284F” Grade
VOS
Offset Voltage “OP484E” Grade
VOS
Offset Voltage “OP484F” Grade
VOS
Input Bias Current
IB
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Common-Mode Rejection Ratio
Large Signal Voltage Gain
IOS
CMRR
CMRR
AVO
Offset Voltage Drift “E” Grade
Bias Current Drift
∆VOS/∆T
∆IB/∆T
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
80
–40°C ≤ TA ≤ +125°C
–40°C ≤ TA ≤ +125°C
VCM = –14.0 V to +14.0 V, –40°C ≤ TA ≤ +125°C
VCM = –15.0 V to +15.0 V
RL = 2 kΩ, –10 V ≤ VO ≤ 10 V
RL = 2 kΩ, –40°C ≤ TA ≤ +125°C
Max
Units
100
200
175
375
150
300
250
500
350
575
50
+15
µV
µV
µV
µV
µV
µV
µV
µV
nA
nA
nA
V
dB
dB
V/mV
V/mV
µV/°C
pA/°C
–15
86 90
80
150 1000
75
0.2
2.00
150
OUTPUT CHARACTERISTICS
Output Voltage High
Output Voltage Low
Output Current
VOH
VOL
IOUT
IL = 1.0 mA
IL = 1.0 mA
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
Supply Current/Amplifier
PSRR
ISY
ISY
VS = ± 2.0 V to ± 18 V, –40°C ≤ TA ≤ +125°C
VO = 0 V, –40°C ≤ TA ≤ +125°C
VS = ± 18 V, –40°C ≤ TA ≤ +125°C
90
DYNAMIC PERFORMANCE
Slew Rate
Full-Power Bandwidth
Settling Time
Gain Bandwidth Product
Phase Margin
SR
BWp
tS
GBP
Øo
RL = 2 kΩ
1% Distortion, RL = 2 kΩ, VO = 29 V p-p
To 0.01%, 10 V Step
2.4
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
en p-p
en
in
0.1 Hz to 10 Hz
f = 1 kHz
+14.8
V
–14.875 V
mA
± 10
2.0
2.25
dB
mA
mA
4.0
35
4
4.25
50
V/µs
kHz
µs
MHz
Degrees
0.3
3.9
0.4
µV p-p
nV/√Hz
pA/√Hz
NOTES
1
Input Offset Voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of power.
Specifications subject to change without notice.
WAFER TEST LIMITS (@ V = +5.0 V, V
S
CM
= 2.5 V, TA = +258C unless otherwise noted)
Parameter
Symbol
Offset Voltage OP284
Offset Voltage OP484
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
Supply Current/Amplifier
VOS
VOS
IB
IOS
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
Conditions
Limit
Units
VCM = +1 V to +4 V
VS = ± 2 V to ± 18 V
RL = 2 kΩ
IL = 1.0 mA
IL = 1.0 mA
VO = 0 V, RL = ∞
65
75
350
50
V– to V+
86
90
50
4.85
125
1.45
µV max
µV max
nA max
nA max
V min
dB min
dB min
V/mV min
V min
mV max
mA max
NOTE
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
–4–
REV. 0
OP184/OP284/OP484
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . ± 0.6 V
Output Short-Circuit Duration to GND3 . . . . . . . . Indefinite
Storage Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP184/OP284/OP484E, F . . . . . . . . . . . . –40°C to +125°C
Junction Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
Package Type
uJA3
uJC
Units
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
14-Pin Plastic DIP (P)
14-Pin SOIC (S)
103
158
83
92
43
43
39
27
°C/W
°C/W
°C/W
°C/W
OP284 Die Size 0.065 × 0.092 Inch, 5,980 Sq. Mils
Substrate (Die Backside) Is Connected to V–.
Transistor Count, 62.
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts unless
otherwise noted.
2
For input voltages greater than 0.6 volts, the input current should be limited to less
than 5 mA to prevent degradation or destruction of the input devices.
3
θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket
for cerdip and P-DIP packages; θJA is specified for device soldered in circuit board
for SOIC package.
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
OP184EP
OP184ES
OP184FP
OP184FS
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
8-Pin Plastic DIP
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
N-8
SO-8
N-8
SO-8
OP284EP
OP284ES
OP284FP
OP284FS
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
8-Pin Plastic DIP
8-Pin SOIC
8-Pin Plastic DIP
8-Pin SOIC
N-8
SO-8
N-8
SO-8
OP484EP
OP484ES
OP484FP
OP484FS
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
14-Pin Plastic DIP
14-Pin SOIC
14-Pin Plastic DIP
14-Pin SOIC
N-14
SO-14
N-14
SO-14
OP484 Die Size 0.080 × 0.110 Inch, 8,800 Sq. Mils
Substrate (Die Backside) Is Connected to V–.
Transistor Count, 120.
VCC
RB1
R4
R3
QB6
QB5
RB3
RB4
R11
TP
Q8
Q7
QL1
Q1
Q3
Q4
Q17
QB9
Q2
–IN
QB10
+IN
QL2
Q5
CC2
Q10
Q9
Q6
QB2
CB1 N+
Q16
Q12
Q11
JB1
OUT
C O
C FF
R6
Q18
QB3
M P+
R7
QB4
RB2
QB7
QB1
JB2
R1
R2
CC1
R5
QB8
Q13
R8
Q14
Q15
R9
R10
VEE
Figure 1. Simplified Schematic
REV. 0
–5–
OP184/OP284/OP484–Typical Performance Characteristics
300
240
300
VS = +3V
TA = +25°C
VCM = 1.5V
300
200
QUANTITY
180
150
120
150
100
90
60
50
30
0
100
Figure 2. Input Offset Voltage
Distribution
100
0
–100
–200
–300
VS = ±15V
OUTPUT VOLTAGE – mV
200
QUANTITY
120
150
100
90
15
Figure 8. Input Bias Current vs.
Common-Mode Voltage
VS = ±15V
–40°C ≤ TA ≤ +125°C
VCM = 2.5V
150
–10
–5
0
5
10
COMMON MODE VOLTAGE – Volts
1,000
250
180
–500
–15
0.25
0.50
0.75
1.0
1.25
1.5
OFFSET VOLTAGE DRIFT, TCVOS – µV/°C
300
VS = +5V
TA = +25°C
210
QUANTITY
0
Figure 5. Input Offset Voltage Drift
Distribution
300
240
200
–400
0
0
25
50
75
–100 –75 –50 –25
INPUT OFFSET VOLTAGE – µV
270
VS = ±15V
400
VS = +5V
–40°C ≤ TA ≤ +125°C
250
210
QUANTITY
500
INPUT BIAS CURRENT – nA
270
60
SOURCE
100
SINK
50
30
0
0
25
50
75
–100 –75 –50 –25
INPUT OFFSET VOLTAGE – µV
0
100
Figure 3. Input Offset Voltage
Distribution
75
50
VCM = VS / 2
–50
VS = +5V
–55
–60
–65
–70
VS = ±15V
25
–75
0
–125 –100 –75 –50 –25 0 25 50 75 100 125
INPUT OFFSET VOLTAGE – µV
–80
–40
Figure 4. Input Offset Voltage
Distribution
SUPPLY CURRENT/AMPLIFIER – mA
100
10
1.2
–45
INPUT BIAS CURRENT – nA
125
0.1
1
LOAD CURRENT – mA
Figure 9. Output Voltage to Supply
Rail vs. Load Current
–40
VS = ±15V
TA = +25°C
150
QUANTITY
10
0.01
0.25
0.50
0.75
1.0
1.25
1.5
OFFSET VOLTAGE DRIFT, TCVOS – µV/°C
Figure 6. Input Offset Voltage Drift
Distribution
200
175
0
25
85
TEMPERATURE – °C
Figure 7. Bias Current vs.
Temperature
–6–
125
1.1
VS = ±15V
1.0
0.9
0.8
VS = +5V
0.7
VS = +3V
0.6
0.5
–40
25
85
TEMPERATURE – °C
125
Figure 10. Supply Current vs.
Temperature
REV. 0
1.50
80
1.0
0.75
TA = +25°C
0.5
0.25
±2.5 ±5.0 ±7.5 ±10 ±12.5 ±15 ±17.5 ±20
SUPPLY VOLTAGE – Volts
45
20
90
10
135
0
180
–10
225
–20
270
OPEN-LOOP GAIN – dB
–I SC
30
–I SC
20
+ISC
10
VS = +5V, VCM = +2.5V
0
25
50
75
TEMPERATURE – °C
100
Figure 12. Short Circuit Current vs.
Temperature
0
30
45
20
90
10
135
0
180
–10
225
–20
270
0
30
45
20
90
10
135
0
180
–10
225
–20
270
–30
10k
1M
100k
FREQUENCY – Hz
10M
Figure 13. Open-Loop Gain and Phase
vs. Frequency (No Load)
REV. 0
100
1k
10k
100k
FREQUENCY – Hz
10M
40
30
20
10
0
–10
–20
–40
10
10M
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 18. Closed-Loop Gain vs.
Frequency (2 kΩ Load)
60
2k
VS = ±15V
–10V < VO < 10V
RL = 2kΩ
1.5k
1k
VS = +5V
1V < VO < 4V
RL = 2kΩ
500
0
–50
1M
VS = ±15V
RL = 2kΩ
TA = +25°C
VS = +3V
RL = 2kΩ
TA = +25°C
50
OPEN-LOOP GAIN – V/mV
40
–20
–30
2.5k
VS = +5V
TA = +25°C
NO LOAD
PHASE SHIFT – Degrees
50
100k
1M
FREQUENCY – Hz
Figure 15. Open-Loop Gain and Phase
vs. Frequency (No Load)
80
0
–10
50
40
–30
10k
125
10
Figure 17. Closed-Loop Gain vs.
Frequency (2 kΩ Load)
CLOSED-LOOP GAIN – dB
–25
20
60
VS = ±15V
TA = +25°C
NO LOAD
50
+ISC
40
30
–40
10
10M
CLOSED-LOOP GAIN – dB
40
VS = +5V
RL = 2kΩ
TA = +25°C
–30
80
60
VS = ±15V
60
100k
1M
FREQUENCY – Hz
Figure 14. Open-Loop Gain and Phase
vs. Frequency (No Load)
50
SHORT CIRCUIT CURRENT – mA
30
–30
10k
Figure 11. Supply Current vs. Supply
Voltage
0
–50
0
PHASE SHIFT – Degrees
0
40
CLOSED-LOOP GAIN – dB
50
PHASE SHIFT – Degrees
1.25
0
OPEN-LOOP GAIN – dB
60
50
VS = +3V
TA = +25°C
NO LOAD
60
OPEN-LOOP GAIN – dB
SUPPLY CURRENT (PER AMPLIFIER) – mA
OP184/OP284/OP484
–25
0
25
50
75
TEMPERATURE – °C
30
20
10
0
–10
–20
–30
100
Figure 16. Open-Loop Gain vs.
Temperature
–7–
40
125
–40
10
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 19. Closed-Loop Gain vs.
Frequency (2 kΩ Load)
OP184/OP284/OP484–Typical Performance Characteristics
300
240
AV = 100
150
120
90
60
30
AV = 1
1k
10k
100k
FREQUENCY – Hz
1M
Figure 20. Output Impedance vs.
Frequency
210
AV = 100
AV = 10
150
120
90
60
30
MAXIMUM OUTPUT SWING – Vp-p
AV = 1
1k
10k
100k
FREQUENCY – Hz
1M
70
60
10
–OS
50
40
+OS
30
20
10
210
120
150
120
90
10k
100k
1M
FREQUENCY – Hz
0
10
10M
100
CAPACITIVE LOAD – pF
AV = 10
30
7
+SLEW RATE
100
80
VS = ±15V
60
VS = +3V
10k
100k
FREQUENCY – Hz
VS = +5V
20
AV = 1
1M
10M
Figure 22. Output Impedance vs.
Frequency
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 25. CMRR vs. Frequency
–8–
VS = ±15V
RL = 2kΩ
5
–SLEW RATE
4
3
+SLEW RATE
2
–SLEW RATE
VS = +5V
RL = 2kΩ
1
0
–20
100
1000
Figure 27. Small Signal Overshoot
vs. Capacitive Load
TA = +25°C
40
1k
VS = ±2.5V
TA = +25°C, AVCL = 1
VIN = ±50mV
6
180
10M
1M
5
140
0
100
10k
100k
FREQUENCY – Hz
80
15
240
60
1k
Figure 26. PSRR vs. Frequency
VS = ±15V
VIN = ±14V
RL = 2kΩ
TA = +25°C
20
160
CMRR – dB
OUTPUT IMPEDANCE – Ω
AV = 100
VS = +3V
–40
100
10M
180
VS = +3V
TA = +25°C
VS = +5V
0
Figure 24. Maximum Output Swing
vs. Frequency
300
VS = ±15V
60
40
–20
100k
1M
FREQUENCY – Hz
25
0
1k
10M
Figure 21. Output Impedance vs.
Frequency
270
10k
80
20
SLEW RATE – V/µs
OUTPUT IMPEDANCE – Ω
240
0
100
1
VS = +5V
VIN = 0.5–4.5V
RL = 2kΩ
TA = +25°C
30
VS = ±15V
TA = +25°C
180
2
Figure 23. Maximum Output Swing
vs. Frequency
300
270
100
3
0
1k
10M
TA = +25°C
120
4
OVERSHOOT – %
180
140
PSRR – dB
AV = 10
210
0
100
160
5
VS = +5V
TA = +25°C
MAXIMUM OUTPUT SWING – Vp-p
OUTPUT IMPEDANCE – Ω
270
0
–50
–25
25
50
0
75
TEMPERATURE – °C
100
125
Figure 28. Slew Rate vs. Temperature
REV. 0
OP184/OP284/OP484
VS = ±15V
8
TA = +25°C
STEP SIZE – Volts
6
20
15
10
4
2
0
0.1%
0.01%
–2
–4
–6
5
–10
1
0
1000
10
100
FREQUENCY – Hz
Figure 29. Voltage Noise Density
vs. Frequency
120
VS = ±15V
100
80
VS = +3V
60
40
20
0
–20
–8
0
TA = +25°C
140
CHANNEL SEPARATION – dB
±2.5V ≤ VS ≤ ±15V
TA = +25°C
25
NOISE DENSITY – nV/√Hz
160
10
30
1
3
2
4
SETTLING TIME – µs
5
6
Figure 32. Settling Time vs. Step Size
–40
100
1k
10k
100k
FREQUENCY – Hz
1M
10M
Figure 35. Channel Separation
vs. Frequency
CURRENT NOISE DENSITY – pA/√Hz
10
±2.5V ≤ VS ≤ ±15V
TA = +25°C
8
100
90
VS = +5V
AV = 1
RL = OPEN
CL = 300pF
TA = +25°C
1s
VS = ±15V
AV = 100k
en = 0.3µVp-p
100
+400mV
90
6
4
0V
10
2
0
10
0%
0%
100mV
10mV
1
10
100
FREQUENCY – Hz
1µs
1000
Figure 30. Current Noise Density
vs. Frequency
Figure 33. 0.1 Hz to 10 Hz Noise
Figure 36. Small Signal Transient
Response
5
VS = +5V
TA = +25°C
4
3
100
STEP SIZE – Volts
90
1s
VS = +5V, 0V
AV = 100k
en = 0.3µVp-p
100
400mV
2
90
1
0.1%
0
VS = +5V
AV = 1
RL = 2kΩ
CL = 300pF
TA - +25°C
0.01%
–1
10
–2
0V
0%
–3
10
0%
10mV
100mV
1µs
–4
–5
0
1
3
2
4
SETTLING TIME – µs
5
6
Figure 31. Settling Time vs. Step Size
REV. 0
Figure 34. 0.1 Hz to 10 Hz Noise
–9–
Figure 37. Small Signal Transient
Response
OP184/OP284/OP484
0.1
200mV
90
100
200mV
0V
–200mV
VS = ±0.75V
AV = 1
NO LOAD
TA = +25°C
90
VO = ±0.75V
THD+N – %
VS = ±1.5V
AV = 1
NO LOAD
TA = +25°C
100
0V
10
–200mV
0%
100mV
1µs
The OP284 and OP484 are precision single-supply, rail-to-rail
operational amplifiers. Intended for the portable instrumentation marketplace, the OP184/OP284/OP484 combines the attributes of precision, wide bandwidth, and low noise to make it
a superb choice in those single supply applications that require
both ac and precision dc performance. Other low supply voltage
applications for which the OP284 is well suited are active filters,
audio microphone preamplifiers, power supply control, and telecom. To combine all of these attributes with rail-to-rail input/
output operation, novel circuit design techniques are used.
VPOS
R2
4k
I1
V01
Q1
Q3
+IN
D1
Q4
Q2
–IN
D2
V02
R3
3k
I2
0.0005
20
100
1k
FREQUENCY – Hz
10k 20k
Figure 40. Total Harmonic Distortion
vs. Frequency
Figure 39. Small Signal Transient
Response
APPLICATIONS
Functional Description
R1
4k
VO = ±1.5V
0.001
500ns
Figure 38. Small Signal Transient
Response
VO = ±2.5V
10
0%
100mV
AV = 1000
VS = ±2.5V
R L = 2kΩ
0.010
stage. A key issue in the input stage is the behavior of the input
bias currents over the input common-mode voltage range. Input
bias currents in the OP284 are the arithmetic sum of the base
currents in Q1-Q3 and in Q2-Q4. As a result of this design
approach, the input bias currents in the OP284 not only exhibit
different amplitudes, but also exhibit different polarities. This
effect is best illustrated in Figure 8. It is, therefore, of paramount importance that the effective source impedances connected to the OP284’s inputs be balanced for optimum dc and
ac performance.
To achieve rail-to-rail output, the OP284 output stage design
employs a unique topology for both sourcing and sinking current. This circuit topology is illustrated in Figure 42. As previously mentioned, the output stage is voltage-driven from the
second gain stage. The signal path through the output stage is
inverting; that is, for positive input signals, Q1 provides the base
current drive to Q6 so that it conducts (sinks) current. For
negative input signals, the signal path via Q1-Q2-D1-Q4-Q3
provides the base current drive for Q5 to conduct (source) current. Both amplifiers provide output current until they are
forced into saturation, which occurs at approximately 20 mV
from negative rail and 100 mV from the positive supply rail.
R4
3k
VPOS
VNEG
R4
I2
INPUT FROM
SECOND GAIN
STAGE
Figure 41. OP284 Equivalent Input Circuit
For example, Figure 41 illustrates a simplified equivalent circuit
for the OP184/OP284/OP484’s input stage. It is comprised of
an NPN differential pair, Q1-Q2, and a PNP differential pair,
Q3-Q4, operating concurrently. Diode network D1-D2 serves
to clamp the applied differential input voltage to the OP284,
thereby protecting the input transistors against avalanche damage. Input stage voltage gains are kept low for input rail-to-rail
operation. The two pairs of differential output voltages are connected to the OP284’s second stage, which is a compound folded
cascode gain stage. It is also in the second gain stage where the
two pairs of differential output voltages are combined into a
single-ended output signal voltage used to drive the output
–10–
Q5
Q3
Q1
VOUT
R1
Q6
R2
Q4
D1
Q2
R5
I1
R3
R6
VNEG
Figure 42. OP284 Equivalent Output Circuit
REV. 0
OP184/OP284/OP484
Thus, the saturation voltage of the output transistors sets the
limit on the OP284’s maximum output voltage swing. Output
short circuit current limiting is determined by the maximum
signal current into the base of Q1 from the second gain stage.
Under output short circuit conditions, this input current level is
approximately 100 µA. With transistor current gains around
200, the short circuit current limits are typically 20 mA. The
output stage also exhibits voltage gain. This is accomplished by
use of common-emitter amplifiers, and as a result, the voltage
gain of the output stage (thus, the open-loop gain of the device)
exhibits a dependence to the total load resistance at the output
of the OP284.
R2
R1
Figure 44. A Resistance in Series with an Input Limits
Overvoltage Currents to Safe Values
As with any semiconductor device, if conditions exist where the
applied input voltages to the device exceed either supply voltage,
the device’s input overvoltage I-V characteristic must be considered. When an overvoltage occurs, the amplifier could be damaged, depending on the magnitude of the applied voltage and
the magnitude of the fault current. Figure 43 illustrates the over
voltage I-V characteristic of the OP284. This graph was generated with the supply pins connected to GND and a curve
tracer’s collector output drive connected to the input.
5
4
INPUT CURRENT – mA
3
2
1
0
–1
–2
–4
–5
5
Figure 43. Input Overvoltage I-V Characteristics of the
OP284
As shown in the figure, internal p-n junctions to the OP284 energize and permit current flow from the inputs to the supplies
when the input is 1.8 V more positive and 0.6 V more negative
than the respective supply rails. As illustrated in the simplified
equivalent circuit shown in Figure 41, the OP284 does not have
any internal current limiting resistors; thus, fault currents can
quickly rise to damaging levels.
REV. 0
Output Phase Reversal
Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs
are driven beyond their useful common-mode range. Typically
for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range. With these
devices, external clamping diodes, with the anode connected to
ground and the cathode to the inputs, prevent input signal excursions from exceeding the device’s negative supply (i.e.,
GND), preventing a condition that could cause the output voltage to change phase. JFET-input amplifiers may also exhibit
phase reversal, and, if so, a series input resistor is usually required to prevent it.
Designing Low Noise Circuits in Single Supply Applications
This input current is not inherently damaging to the device,
provided that it is limited to 5 mA or less. For the OP284, once
the input exceeds the negative supply by 0.6 V, the input current quickly exceeds 5 mA. If this condition continues to exist,
an external series resistor should be added at the expense of additional thermal noise. Figure 44 illustrates a typical noninverting configuration for an overvoltage protected amplifier where
the series resistance, RS, is chosen such that:
RS =
For example, a 1 kΩ resistor will protect the OP284 against
input signals up to 5 V above and below the supplies. For other
configurations where both inputs are used, then each input
should be protected against abuse with a series resistor. Again,
in order to ensure optimum dc and ac performance, it is recommended to balance source impedance levels. For more information on the general overvoltage characteristics of amplifiers,
please refer to the 1993 System Applications Guide, Section 1,
pages 56-69. This reference textbook is available from the Analog Devices Literature Center.
The OP284 is free from reasonable input voltage range restrictions, provided that input voltages no greater than the supply
voltages are applied. Although the device’s output will not
change phase, large currents can flow through the input protection diodes as was shown in Figure 43. Therefore, the technique
recommended in the Input Overvoltage Protection section
should be applied to those applications where the likelihood of
input voltages exceeding the supply voltages is high.
–3
4
VOUT
VIN
Input Overvoltage Protection
– 5 – 4 – 3 – 2 –1 0
1
2
3
INPUT VOLTAGE – Volts
1/2
OP284
In single supply applications, devices like the OP284 extend the
dynamic range of the application through the use of rail-to-rail
operation. In fact, the OP284 family is the first of its kind to
combine single supply, rail-to-rail operation and low noise in
one device. It is the first device in the industry to exhibit an
input noise voltage spectral density of less than 4 nV/√Hz at
1 kHz. It was also designed specifically for low-noise, singlesupply applications, and as such, some discussion on circuit
noise concepts in single supply applications is appropriate.
VIN ( MAX ) –V SUPPLY
5 mA
–11–
OP184/OP284/OP484
Referring to the op amp noise model circuit configuration illustrated in Figure 45, the expression for an amplifier’s total
equivalent input noise voltage for a source resistance level RS is
given by:
[
]
2
enT = 2 ( enR )2 + ( inOA × R )2 + ( enOA ) , units in V
Hz
where RS = 2R = Effective, or equivalent, circuit source
resistance,
(enOA)2 = Op amp equivalent input noise voltage spectral
power (1 Hz BW),
(inOA)2 = Op amp equivalent input noise current spectral
power (1 Hz BW),
(enR)2 = Source resistance thermal noise voltage power =
(4kTR),
k = Boltzmann’s constant = 1.38 × 10–23 J/K, and
T = Ambient temperature of the circuit, in Kelvin, =
273.15 + TA (°C)
e NR
R
"NOISELESS"
e NOA
i NOA
IDEAL
NOISELESS
OP AMP
e NR
R
"NOISELESS"
i NOA
RS = 2R
Figure 45. Op Amp Noise Circuit Model Used to
Determine Total Circuit Equivalent Input Noise Voltage
and Noise Figure
Since circuit SNR is the critical parameter in the final analysis,
the noise behavior of a circuit is often expressed in terms of its
noise figure, NF. Noise figure is defined as the ratio of a
circuit’s output signal-to-noise to its input signal-to-noise. An
expression of a circuit’s NF in dB, and in terms of the operational amplifier’s voltage and current noise parameters defined
previously, is given by:
  (e
)2 + (inOA RS )2  
NF (dB) = 10 log 1 +  nOA

 
 
(enRS )2
where NF (dB) = Noise figure of the circuit, expressed in dB,
RS = Effective, or equivalent, source resistance presented
to amplifier,
(enOA)2 = OP284 noise voltage spectral power (1 Hz BW),
(inOA)2 = OP284 noise current spectral power (1 Hz BW),
(enRS)2 = Source resistance thermal noise voltage power
= (4kTRS),
Circuit noise figure is straightforward to calculate because the
signal level in the application is not required to determine it.
However, many designers using NF calculations as the basis for
achieving optimum SNR believe that low noise figure is equal to
low total noise. In fact, the opposite is true, as illustrated in
Figure 47. Here, the noise figure of the OP284 is expressed as a
function of the source resistance level. Note that the lowest
noise figure for the OP284 occurs at a source resistance level of
10 kΩ. However, Figure 46 shows that this source resistance
level and the OP284 generate approximately 14 nV/√Hz of total
equivalent circuit noise. Signal levels in the application would
invariably be increased to maximize circuit SNR—not an option
in low voltage, single supply applications.
As a design aid, Figure 46 illustrates the total equivalent input
noise of the OP284 and the total thermal noise of a resistor for
comparison. Note that for source resistance less than 1 kΩ, the
equivalent input noise voltage of the OP284 is dominant.
10
9
NOISE FIGURE – dB
8
100
EQUIVALENT THERMAL NOISE – nV/√Hz
FREQUENCY = 1kHz
TA = +25°C
FREQUENCY = 1kHz
TA = +25°C
OP284 TOTAL
EQUIVALENT NOISE
7
6
5
4
3
2
1
10
0
100
RESISTOR THERMAL
NOISE ONLY
1k
10k
100k
TOTAL SOURCE RESISTANCE, RS – Ω
Figure 47. OP284 Noise Figure vs. Source Resistance
1
100
1k
10k
100k
TOTAL SOURCE RESISTANCE, RS – Ω
Figure 46. OP284 Total Noise vs. Source Resistance
In single supply applications, therefore, it is recommended for
optimum circuit SNR to choose an operational amplifier with
the lowest equivalent input noise voltage and to choose source
resistance levels consistent in maintaining low total circuit noise.
–12–
REV. 0
OP184/OP284/OP484
RP1
1kΩ
Overdrive Recovery
The overdrive recovery time of an operational amplifier is the
time required for the output voltage to recover to its linear region from a saturated condition. The recovery time is important
in applications where the amplifier must recover quickly after a
large transient event. The circuit shown in Figure 48 was used
to evaluate the OP284’s overload recovery time. The OP284
takes approximately 2 µs to recover from positive saturation and
approximately 1 µs to recover from negative saturation.
VIN
+3V
RP2
1kΩ
2
C1
AC CMRR
TRIM
5pF–40pF
R3
1.1kΩ
1
A1
6
P1
500Ω
8
7
A2
VOUT
4
R2
1.1kΩ
R4
10kΩ
R1
9.53kΩ
R2
10kΩ
R1
10kΩ
5
3
A1, A2 = 1/2 OP284
R4
GAIN = 1 + –––
R3
SET R2 = R3
R1 + P1 = R4
C2
+5V
Figure 49. A Single Supply, +3 V Low Noise Instrumentation Amplifier
2
R3
9kΩ
8
1/2
3 OP284
1
VOUT
A +2.5 V Reference from a +3 V Supply
4
VIN
10V STEP
–5V
Figure 48. Output Overload Recovery Test Circuit
A Single-Supply, +3 V Instrumentation Amplifier
The OP284’s low noise, wide bandwidth, and rail-to-rail input/
output operation makes it ideal for low supply voltage applications such as in a two op amp instrumentation amplifier as
shown in Figure 49. The circuit uses the classic two op amp instrumentation amplifier topology with four resistors to set the
gain. The transfer equation of the circuit is identical to that of a
noninverting amplifier. Resistors R2 and R3 should be closely
matched to each other as well as to resistors (R1 + P1) and R4
to ensure good common-mode rejection performance. Resistor
networks should be used in this circuit for R2 and R3 because
they exhibit the necessary relative tolerance matching for good
performance. Matched networks also exhibit tight relative resistor temperature coefficients for good circuit temperature stability. Trimming potentiometer P1 is used for optimum dc CMR
adjustment, and C1 is used to optimize ac CMR. With the circuit values as shown, circuit CMR is better than 80 dB over the
frequency range of 20 Hz to 20 kHz. Circuit RTI (Referred-toInput) noise in the 0.1 Hz to 10 Hz band is an impressively low
0.45 µV p-p. Resistors RP1 and RP2 serve to protect the
OP284’s inputs against input overvoltage abuse. Capacitor C2
can be included to the limit circuit bandwidth and, therefore,
wide bandwidth noise in sensitive applications. The value of
this capacitor should be adjusted depending on the required
closed-loop bandwidth of the circuit. The R4-C2 time constant
creates a pole at a frequency equal to:
f (3 dB) =
In many single-supply applications, the need for a 2.5 V reference often arises. Many commercially available monolithic
2.5 V references require at least a minimum operating supply of
4 V. The problem is exacerbated when the minimum operating
supply voltage is +3 V. The circuit illustrated in Figure 50 is an
example of a +2.5 V reference that operates from a single +3 V
supply. The circuit takes advantage of the OP284’s rail-to-rail
input/output voltage ranges to amplify an AD589’s 1.235 V
output to +2.5 V. The OP284’s low TCVOS of 1.5 µV/°C helps
maintain an output voltage temperature coefficient that is dominated by the temperature coefficients of R2 and R3. In this
circuit with 100 ppm/°C TCR resistors, the output voltage
exhibits a temperature coefficient of 200 ppm/°C. Lower tempco
resistors are recommended for more accurate performance over
temperature.
One measure of the performance of a voltage reference is its
capacity to recover from sudden changes in load current. While
sourcing a steady-state load current of 1 mA, this circuit recovers to 0.01% of the programmed output voltage in 1.5 µs for a
total change in load current of ± 1 mA.
+3V
+3V
R1
17.4kΩ
3
8
1/2
2 OP284
4
AD589
R3
100kΩ
1
2 π R4 C2
R2
100kΩ
0.1µF
1
+2.5VREF
P1
5kΩ
RESISTORS = 1%, 100ppm/°C
POTENTIOMETER = 10 TURN, 100ppm/°C
Figure 50. A +2.5 V Reference that Operates on a Single
+3 V Supply
REV. 0
–13–
OP184/OP284/OP484
For the element values shown, the Monitor Output’s transfer
characteristic is 2.5 V/A.
A +5 V Only, 12-Bit DAC Swings Rail-to-Rail
The OP284 is ideal for use with a CMOS DAC to generate a
digitally-controlled voltage with a wide output range. Figure 51
shows a DAC8043 used in conjunction with the AD589 to generate a voltage output from 0 V to 1.23 V. The DAC is actually
operating in “voltage switching” mode where the reference is
connected to the current output, IOUT, and the output voltage is
taken from the VREF pin. This topology is inherently noninverting as opposed to the classic current output mode, which is
inverting and not usable in single supply applications.
RSENSE
0.1Ω
0.1µF
R1
100Ω
AD589
3
IOUT
RFB
8
1/2
AD284
1
4
M1
Si9433
VDD
3
2
MONITOR
OUTPUT
8
1.23V
+3V
+3V
+5V
R1
17.8kΩ
IL
+3V
2
S
G
D
R2
2.49kΩ
VREF 1
DAC8043
+5V
GND CLK SR1 LD
4
7
6
5
DIGITAL
CONTROL
R3
232Ω
1%
R2
32.4kΩ
1%
Figure 52. A High-Side Load Current Monitor
3
8
1/2
OP284
2
1
Capacitive Load Drive Capability
D
VOUT = –––– (5V)
4096
4
R4
100kΩ
1%
Figure 51. A +5 V Only, 12-Bit DAC Swings Rail-to-Rail
In this application the OP284 serves two functions. First, it
buffers the high output impedance of the DAC’s VREF pin,
which is on the order of 10 kΩ. The op amp provides a low
impedance output to drive any following circuitry. Second, the
op amp amplifies the output signal to provide a rail-to-rail output swing. In this particular case, the gain is set to 4.1 so that
the circuit generates a 5 V output when the DAC output is at
full scale. If other output voltage ranges are needed, such as 0 V
≤ VOUT ≤ 4.095 V, the gain can be easily changed by adjusting
the values of R2 and R3.
The OP284 exhibits excellent capacitive load driving capabilities. It can drive up to 1 nF as shown in Figure 27. Even
though the device is stable, a capacitive load does not come
without penalty in bandwidth. The bandwidth is reduced to
under 1 MHz for loads greater than 2 nF. A “snubber” network
on the output does not increase the bandwidth, but it does significantly reduce the amount of overshoot for a given capacitive
load. A snubber consists of a series R-C network (RS, CS), as
shown in Figure 53, connected from the output of the device to
ground. This network operates in parallel with the load capacitor, CL, to provide the necessary phase lag compensation. The
value of the resistor and capacitor is best determined empirically.
+5V
0.1µF
VIN
100mVp-p
A High-Side Current Monitor
In the design of power supply control circuits, a great deal of
design effort is focused on ensuring a pass transistor’s long-term
reliability over a wide range of load current conditions. As a
result, monitoring and limiting device power dissipation is of
prime importance in these designs. The circuit illustrated in
Figure 52 is an example of a +3 V, single-supply high-side current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current
power supply with crowbar protection. This design uses an
OP284’s rail-to-rail input voltage range to sense the voltage
drop across a 0.1 Ω current shunt. A p-channel MOSFET used
as the feedback element in the circuit converts the op amp’s differential input voltage into a current. This current is applied to
R2 to generate a voltage that is a linear representation of the
load current. The transfer equation for the current monitor is
given by:
R

Monitor Output = R2 ×  SENSE  × IL
 R1 
1/2
OP284
VOUT
RS
50Ω
CS
100nF
CL
1nF
Figure 53. Snubber Network Compensates for Capacitive
Load
The first step is to determine the value of the resistor RS. A
good starting value is 100 Ω (typically, the optimum value will
be less than 100 Ω). This value is reduced until the small-signal
transient response is optimized. Next, CS is determined—10 µF
is a good starting point. This value is reduced to the smallest
value for acceptable performance (typically, 1 µF). For the case
of a 10 nF load capacitor on the OP284, the optimal snubber
network is a 20 Ω in series with 1 µF. The benefit is immediately apparent as shown in the scope photo in Figure 54. The
top trace was taken with a 1 nF load, and the bottom trace was
taken with the 50 Ω, 100 nF snubber network in place. The
amount of overshoot and ringing is dramatically reduced. Table I
below illustrates a few sample snubber networks for large load
capacitors.
–14–
REV. 0
OP184/OP284/OP484
Figure 55 shows such a regulator set up using an OP284 plus a
low RDS(ON), P-channel MOSFET pass device. Part of the low
dropout performance of this circuit is provided by Q1, which
has a rating of 0.11 Ω with a gate drive voltage of only 2.7 V.
This relatively low gate drive threshold allows operation of the
regulator on supplies as low as 3 V without compromising overall performance.
µs
100
90
1nF LOAD
ONLY
SNUBBER
IN
CIRCUIT
10
The circuit’s main voltage control loop operation is provided by
U1B, half of the OP284. This voltage control amplifier amplifies the 2.5 V reference voltage produced by three terminal U2,
a REF192. The regulated output voltage VOUT is then:
0%
50mv
50mv
2µs
Figure 54. Overshoot and Ringing Is Reduced by Adding a
“Snubber” Network in Parallel with the 1 nF Load
(
VOUT =VOUT 2 1 + R2
R3
For this example, since VOUT of 4.5 V with VOUT2 = 2.5 V requires a U1B gain of 1.8 times, R3 and R2 are chosen for a ratio
of 1.2:1 or 10.0 kΩ:8.06 kΩ (using closest 1% values). Note
that for the lowest VOUT dc error, R2iR3 should be maintained
equal to R1 (as here), and the R2-R3 resistors should be stable,
close tolerance metal film types. The table in Figure 55 summarizes R1-R3 values for some popular voltages. However,
note that, in general, the output can be anywhere between
VOUT2 and the 12 V maximum rating of Q1.
Table I. Snubber Networks for Large Capacitive Loads
Load Capacitance
(CL)
Snubber Network
(RS, CS)
1 nF
10 nF
100 nF
50 Ω, 100 nF
20 Ω, 1 µF
5 Ω, 10 µF
A Low Dropout Regulator with Current Limiting
While the low voltage saturation characteristic of Q1 is a key
part of the low dropout, another component is a low current
sense comparison threshold with good dc accuracy. Here, this
is provided by current sense amplifier U1A, which is provided
by a 20 mV reference from the 1.235 V AD589 reference diode
D2 and the R7-R8 divider. When the product of the output
current and the RS value match this voltage threshold, the current control loop is activated, and U1A drives Q1’s gate through
D1. This causes the overall circuit operation to enter current
mode control with a current limit ILIMIT defined as:
Many circuits require stable regulated voltages relatively close,
in potential to an unregulated input source. This “low dropout”
type of regulator is readily implemented with a rail-to-rail output op amp such as the OP284 because the wide output swing
allows easy drive to a low saturation voltage pass device. Furthermore, it is particularly useful when the op amp also enjoys a
rail-rail input feature, as this factor allows it to perform highside current sensing for positive rail current limiting. Typical examples are voltages developed from 3 V to 9 V range system
sources or anywhere where low dropout performance is required
for power efficiency. The 4.5 V case here works from 5 V nominal sources with worst-case levels down to 4.6 V or less.
(
R7
V

ILIMIT =  R(D2) 
 RS  R7 + R8
C4
0.1µF
RS
0.05Ω
+VS
VS > VOUT + 0.1V
R7
4.99kΩ
R6
4.99kΩ
D2
AD589
3
)
8
U1A
OP284
1
)
Q1
SI9433DY
R5
22.1kΩ
D1
1N4148
2
R8
301kΩ
4
R4
2.21kΩ
C1
0.01µF
C5
0.01µF
R9
27.4kΩ
6
7
D3
1N4148
C3
0.1µF
VC
OPTIONAL
ON/OFF CONTROL INPUT
CMOS HI (OR OPEN) = ON
LO = OFF
5
R11
1kΩ
R1
4.53kΩ
U2
2 REF192
VOUT2
2.5V
3
R10
1kΩ
R2
8.06kΩ
OUTPUT TABLE
6
4
U1B
OP284
C2
1µF
R3
10kΩ
VOUT R1
R2
R3
5.0V
4.5V
3.3V
3.0V
10.0k
8.06k
3.24k
2.00k
10.0k
10.0k
10.0k
10.0k
4.99k
4.53k
2.43k
1.69k
VIN COMMON
C6
10µF
VOUT COMMON
Figure 55. A Low Dropout Regulator with Current Limiting
REV. 0
VOUT =
4.5V @ 350mA
(SEE TABLE)
–15–
OP184/OP284/OP484
Obviously, it is desirable to keep this comparison voltage small,
since it becomes a significant portion of the overall dropout
voltage. Here, the 20 mV reference is higher than the typical
offset of the OP284 but still reasonably low as a percentage of
VOUT (< 0.5%). In adapting the limiter for other ILIMIT levels,
sense resistor RS should be adjusted along with R7-R8, to maintain this threshold voltage between 20 mV and 50 mV.
physiological signals, such as heart rates, blood pressure readings, EEGs, EKGs, etc. This notch filter effectively squelches
60 Hz pickup at a filter Q of 0.75. Substituting 3.16 kΩ resistors for the 2.67 kΩ in the twin-T section (R1 through R5)
configures the active filter to reject 50 Hz interference.
R2
2.67kΩ
+3V
Performance of the circuit is excellent. For the 4.5 V output
version, the measured dc output change for a 225 mA load
change was on the order of a few microvolts while the dropout
voltage at this same current level was about 30 mV. The current
limit as shown is 400 mA, which allows the circuit to be used at
levels up to 300 mA or more. While the Q1 device can actually
support currents of several amperes, a practical current rating
takes into account the SO-8 device’s 2.5 W, 25°C dissipation.
Because a short circuit current of 400 mA at an input level of 5
V will cause a 2 W dissipation in Q1, other input conditions
should be considered carefully in terms of Q1’s potential overheating. Of course, if higher powered devices are used for Q1,
this circuit can support outputs of tens of amperes as well as the
higher VOUT levels noted above.
The circuit shown can be used either as a standard low dropout
regulator, or it can be used with ON/OFF control. By
driving Pin 3 of U1 with the optional logic control signal VC, the
output is switched between ON and OFF. Note that when the
output is OFF in this circuit, it is still active (i.e., not an open circuit). This is because the OFF state simply reduces the voltage
input to R1, leaving the U1A/B amplifiers and Q1 still active.
When ON/OFF control is used, resistor R10 should be used
with U1 to speed ON-OFF switching and to allow the output of
the circuit to settle to a nominal zero voltage. Components D3
and R11 also aid in speeding up the ON-OFF transition by providing a dynamic discharge path for C2. OFF-ON transition
time is less than 1 ms, while the ON-OFF transition is longer
but under 10 ms.
A +3 V, 50 Hz/60 Hz Active Notch Filter with False Ground
To process signals in a single-supply system, it is often best
to use a false ground biasing scheme. A circuit that uses this
approach is illustrated in Figure 56. In this circuit, a false-ground
circuit biases an active notch filter used to reject 50 Hz/60 Hz
power line interference in portable patient monitoring equipment. Notch filters are quite commonly used to reject power
line frequency interference that often obscures low frequency
R1
2.67kΩ
A1
VIN
C1
1µF
4
2
3
C2
1µF
5
1
A2
11
R3
2.67kΩ
R6
10kΩ
R4
2.67kΩ
C3
2µF
(1µF x 2)
R5
1.33kΩ
(2.67kΩ ÷ 2)
7
VO
6
R8
1kΩ
R7
1kΩ
R11
10kΩ
Q = 0.75
C5
0.03µF
+3V
R9
20kΩ
R12
150Ω
9
A3
8
10
C4
1µF
R10
20kΩ
NOTE: FOR 50Hz APPLICATIONS
CHANGE R1–R4 TO 3.1kΩ
AND R5 TO 1.58kΩ (3.16kΩ ÷ 2).
1.5V
C6
1µF
A1, A2, A3 = OP484
Figure 56. A +3 V Single Supply, 50/60 Hz Active Notch
Filter with False Ground
Amplifier A3 is the heart of the false-ground bias circuit. It
simply buffers the voltage developed at R9 and R10 and is the
reference for the active notch filter. Since the OP484 exhibits a
rail-to-rail input common-mode range, R9 and R10 are chosen
to split the +3 V supply symmetrically. An in-the-loop compensation scheme is used around the OP484 that allows the op amp
to drive C6, a 1 µF capacitor, without oscillation. C6 maintains
a low impedance ac ground over the operating frequency range
of the filter.
The filter section uses a OP484 in a twin-T configuration whose
frequency selectivity is very sensitive to the relative matching of
the capacitors and resistors in the twin-T section. Mylar is the
material of choice for the capacitors, and the relative matching
of the capacitors and resistors determines the filter’s pass band
symmetry. Using 1% resistors and 5% capacitors produces
satisfactory results.
–16–
REV. 0
OP184/OP284/OP484
*OP284 SPICE Macro-model
9/94 / Rev. A
*
ARG/ADI
*
* Copyright 1995 by Analog Devices
*
* Refer to “README.DOC” file for License Statement. Use of
this model
* indicates your acceptance of the terms and provisions in the
License
* Statement.
*
* Node assignments
*
noninverting input
*
| inverting input
*
| | positive supply
*
| | | negative supply
*
| | | | output
*
| | | | |
.SUBCKT OP284
1 2 99 50 45
*
* INPUT STAGE
*
Q1
5
2
3
QIN 1
Q2
6
11
3
QIN 1
Q3
7
2
4
QIP 1
Q4
8
11
4
QIP 1
DC1
2
11
DC
DC2
11 2
DC
Q5
4
9
99
QIP 1
Q6
9
9
99
QIP 1
Q7
3
10
50
QIN 1
Q8
10 10
50
QIN 1
R1
99 5
4E3
R2
99 6
4E3
R3
7
50
4E3
R4
8
50
4E3
IREF
9
10
50.5E-6
EOS
1
11
POLY(2) (22,98) (14,98) -25E-6 1E-2 1
IOS
2
1
5E-9
CIN
1
2
2E-12
GN1
98 1
(17,98) 1E-3
GN2
98 2
(23,98) 1E-3
*
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
*
VN1
13 98
DC 2
VN2
98 15
DC 2
DN1
13 14
DEN
DN2
14 15
DEN
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
*
VN3
16 98
DC 2
VN4
98 18
DC 2
DN3
16 17
DIN
DN4
17 18
DIN
*
* 2ND CURRENT NOISE SOURCE WITH FLICKER
NOISE
*
VN5
19 98
DC 2
VN6
98 24
DC 2
REV. 0
DN5
19 23
DIN
DN6
23 24
DIN
*
* GAIN STAGE
*
EREF 98 0
POLY(2) (99,0) (50,0) 0 0.5 0.5
G1
98 20
POLY(2) (6,5) (8,7) 0 0.5E-3 0.5E-3
R9
20 98
1E3
*
* COMMON MODE STAGE WITH ZERO AT 100Hz
*
ECM 98 21
POLY(2) (1,98) (2,98) 0 0.5 0.5
R10
21 22
1
R11
22 98
100E-6
C4
21 22
1.592E-3
*
* NEGATIVE ZERO AT 20MHz
*
E1
27 98
(20,98) 1E6
R17
27 28
1
R18
28 98
1E-6
C8
25 26
7.958E-9
ENZ
25 98
(27,28) 1
VNZ
26 98
DC 0
FNZ
27 28
VNZ -1
*
* POLE AT 40MHz
*
G4
98 29
(28,98) 1
R19
29 98
1
C9
29 98
3.979E-9
*
* POLE AT 40MHz
*
G5
98 30
(29,98) 1
R20
30 98
1
C10
30 98
3.979E-9
*
* OUTPUT STAGE
*
ISY
99 50
0.276E-3
GIN
50 31
POLY(1) (30,98) .862574E-6 505.879E-6
RIN
31 50
2.75E6
VB
99 32
0.7
Q11
32 31
33
QON 1
R21
33 34
4.5E3
I1
34 50
50E-6
R22
99 35
6E3
Q12
36 36
35
QOP 1
I2
36 50
50E-6
R23
99 37
2.6E3
R24
34 38
5E3
Q13
39 36
37
QOP 1
Q14
39 38
40
QON 1.5
R25
40 50
40
Q15
39 39
41
QON 1
R26
41 42
1E3
R27
99 43
220
Q16
44 44
43
QOP 1.5
Q17
44 39
42
QON 1
R28
42 50
2E3
VSCP 99 97
DC 0
–17–
OP184/OP284/OP484
FSCP 46 99
VSCP 1
RSCP 46 99
40
Q20
44 46
99
QOP 1
Q18
45 44
97
QOP 4.5
Q19
45 34
51
QON 4.5
VSCN 51 50
DC 0
FSCN 50 47
VSCN 1
RSCN 47 50
40
Q21
34 47
50
QON 1
CC2
31 45
20E-12
CF1
31 34
15E-12
CF2
31 42
15E-12
CO1
34 45
15E-12
CO2
42 45
5E-12
D3
45 99
DX
D4
50 45
DX
.MODEL DC D(IS=130E-21)
.MODEL DX D()
.MODEL DEN D(RS=100 KF=12E-15 AF=1)
.MODEL DIN D(RS=5.358 KF=56E-15 AF=1)
.MODEL QIN NPN(BF=200 VA=200 IS=0.5E-16)
.MODEL QIP PNP(BF=100 VA=60 IS=0.5E-16)
.MODEL QON NPN(BF=200 VA=200 IS=0.5E-16 RC=50)
.MODEL QOP PNP(BF=200 VA=200 IS=0.5E-16 RC=160)
.ENDS
–18–
REV. 0
OP184/OP284/OP484
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Epoxy DIP
(P Suffix)
14-Lead Epoxy DIP
(P Suffix)
0.795 (20.19)
0.725 (18.42)
0.430 (10.92)
0.348 (8.84)
8
5
1
0.280 (7.11)
0.240 (6.10)
4
PIN 1
0.210 (5.33)
MAX
0.060 (1.52)
0.015 (0.38)
14
8
1
7
0.325 (8.25)
0.300 (7.62)
0.130
(3.30)
MIN
0.022 (0.558)
0.070 (1.77) SEATING
PLANE
0.100
0.014 (0.356) (2.54) 0.045 (1.15)
BSC
0.160 (4.06)
0.115 (2.93)
0.210 (5.33)
MAX
0.015 (0.381)
0.008 (0.204)
0.3444 (8.75)
0.3367 (8.55)
14
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
REV. 0
0.0500 0.0192 (0.49)
(1.27) 0.0138 (0.35) 0.0098 (0.25)
BSC
0.0075 (0.19)
0.1574 (4.00)
0.1497 (3.80)
1
4
0.0098 (0.25)
0.0040 (0.10)
8
0.2440 (6.20)
0.2284 (5.80)
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
14-Lead Narrow-Body SO
(S Suffix)
5
1
0.100 0.070 (1.77)
(2.54) 0.045 (1.15)
BSC
0.022 (0.558)
0.014 (0.356)
0.1968 (5.00)
0.1890 (4.80)
8
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
8-Lead SO
(S Suffix)
0.2440 (6.20)
0.2284 (5.80)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.195 (4.95)
0.115 (2.93)
0.280 (7.11)
0.240 (6.10)
PIN 1
0.0196 (0.50)
x 45°
0.0099 (0.25)
8°
0°
7
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
0.0500 (1.27)
0.0160 (0.41)
SEATING
PLANE
–19–
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0098 (0.25)
0.0138 (0.35)
0.0075 (0.19)
0.0196 (0.50)
x 45°
0.0099 (0.25)
8°
0°
0.0500 (1.27)
0.0160 (0.41)
–20–
PRINTED IN U.S.A.
C2167–12–10/96