Holtek HT85F2270 Standard 8051 8-bit flash mcu Datasheet

Standard 8051 8-Bit Flash MCU
HT85F2260
HT85F2270
HT85F2280
Revision: V1.00
Date: ������������
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Table of Contents
1 Features.................................................................................................................. 14
CPU Features.................................................................................................................... 14
Peripheral Features............................................................................................................ 15
3 Selection Table....................................................................................................... 17
4 Block Diagram........................................................................................................ 18
5 Pin Assignment...................................................................................................... 19
6 Pin Descriptions.................................................................................................... 20
7 Absolute Maximum Ratings.................................................................................. 23
8 D.C. Characteristics............................................................................................... 23
9 A.C. Characteristics............................................................................................... 25
10 ADC Electrical Characteristics .......................................................................... 26
11 DAC Electrical Characteristics........................................................................... 26
12 Comparator Electrical Characteristics.............................................................. 27
13 Power on Reset Electrical Characteristics........................................................ 28
14 System Architecture............................................................................................ 28
15 Program Counter................................................................................................. 29
16 Stack..................................................................................................................... 29
17 Arithmetic and Logic Unit – ALU........................................................................ 30
18 Flash Program Memory....................................................................................... 31
Structure............................................................................................................................. 31
Special Vectors.................................................................................................................. 31
In-Circuit Programming – ICP............................................................................................ 32
On-Chip Debug Support – OCDS...................................................................................... 32
In-Application Programming – IAP..................................................................................... 33
Flash Program Memory Resisters...................................................................................... 33
Flash Memory Read/Write Operations............................................................................... 37
Unlocking the Flash Memory......................................................................................................... 37
Page Erase Operation................................................................................................................... 38
Byte Read Operation..................................................................................................................... 39
Byte Write Operation..................................................................................................................... 40
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Table of Contents
2 General Description .............................................................................................. 16
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Program Memory Protection.............................................................................................. 42
Memory Protection Control Bytes.................................................................................................. 42
19 RAM Data Memory............................................................................................... 46
Structure............................................................................................................................. 46
Register Banks................................................................................................................... 50
Special Function Registers................................................................................................ 52
ACC Register – Accumulator......................................................................................................... 53
B Register ..................................................................................................................................... 53
SP Register – Stack Pointer.......................................................................................................... 53
DPL, DPH, DPL1, DPH1 Registers – Data Pointer Registers....................................................... 53
Data Pointer Select Registers....................................................................................................... 54
Data Pointer Control Register....................................................................................................... 54
Program Status Word.................................................................................................................... 56
20 Oscillators............................................................................................................ 57
System Oscillator Overview............................................................................................... 57
System Clock Configuration............................................................................................... 57
External High Speed Crystal Oscillator – HXT.............................................................................. 57
Internal High Speed RC Oscillator – HIRC.................................................................................... 58
External Low Speed Crystal Oscillator – LXT................................................................................ 58
Internal Low Speed RC Oscillator – LIRC..................................................................................... 59
21 Operating Modes and System Clocks............................................................... 60
System Clocks Description................................................................................................ 60
Phase Locked Loop – PLL................................................................................................. 64
Changing the PLL Frequency........................................................................................................ 64
Operation Modes................................................................................................................ 66
NORMAL Mode............................................................................................................................. 66
IDLE Mode.................................................................................................................................... 66
Power-Down Mode........................................................................................................................ 66
Power Control Register...................................................................................................... 67
Standby Current Considerations........................................................................................ 67
Wake-up............................................................................................................................. 68
22 Watchdog Timer................................................................................................... 69
Watchdog Registers........................................................................................................... 70
Watchdog Timer Clock Source........................................................................................... 73
Watchdog Timer Operation................................................................................................ 73
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Table of Contents
Bit Addressable Space....................................................................................................... 50
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
23 Low Voltage Detector – LVD............................................................................... 75
LVD Register...................................................................................................................... 75
LVD Operation.................................................................................................................... 75
24 Reset and Initialisation........................................................................................ 76
Reset Overview.................................................................................................................. 76
Reset Source Register – RSTSRC............................................................................................... 77
Power-on Reset............................................................................................................................. 78
RESET Pin Reset.......................................................................................................................... 79
Low Voltage Reset – LVR.............................................................................................................. 80
Watchdog Reset ........................................................................................................................... 81
Missing Clock Detect Reset.......................................................................................................... 82
Comparator 0 Reset...................................................................................................................... 83
Software Resets............................................................................................................................ 84
SRST Register Software Reset..................................................................................................... 84
WDTCR Register Software Reset................................................................................................. 85
LVRCR Register Software Reset................................................................................................... 85
ROM Code Check Reset............................................................................................................... 86
Reset Initial Conditions...................................................................................................... 86
25 Interrupts.............................................................................................................. 92
Interrupt Registers.............................................................................................................. 92
Interrupt Operation........................................................................................................... 104
Interrupt Priority................................................................................................................ 107
Priority Levels.............................................................................................................................. 107
Priority Control Registers............................................................................................................ 109
External Interrupt.............................................................................................................. 112
Comparator Interrupt........................................................................................................ 113
A/D Converter Interrupt.................................................................................................... 114
Timer/Counter Interrupt.................................................................................................... 114
Time Base Interrupts........................................................................................................ 114
I2C Interface Interrupt....................................................................................................... 115
SPI Interface Interrupt...................................................................................................... 116
UART Interface Interrupt.................................................................................................. 116
LVD Interrupt.................................................................................................................... 116
Interrupt Wake-up Function.............................................................................................. 117
Programming Considerations........................................................................................... 117
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Table of Contents
Reset Operations............................................................................................................... 77
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
26 Input/Output Ports............................................................................................. 118
Input/Output Port Overview.............................................................................................. 118
Register Description......................................................................................................... 119
PnM0/PnM1 Registers – Port Mode Registers............................................................................ 121
P0WAKE Register – Port 0 Wake-up.......................................................................................... 123
SRCR Register – Slew Rate Control........................................................................................... 123
Quasi-bidirectional I/O – All Ports................................................................................................ 124
Push-pull Output – Ports 0~3 Only.............................................................................................. 125
Open-drain Output – Ports 0~3 Only........................................................................................... 125
Input Only – Ports 0~3 Only........................................................................................................ 125
Programming Considerations........................................................................................... 126
27 Timer/Event Counters....................................................................................... 127
Timer/Event Counter Summary........................................................................................ 127
28 Timer/Event Counters 0, 1, 3............................................................................ 128
Introduction...................................................................................................................... 128
Timer 0/Timer 1/Timer 3 Register Description.................................................................. 129
Mode 0 – 13-bit Counter/Timer Mode Operation.............................................................. 136
Mode 1 – 16-bit Counter/Timer Mode Operation.............................................................. 136
Mode 2 – 8-bit Auto-reload Counter/Timer Mode Operation............................................ 137
Mode 3 – Two 8-Bit Timers/Counters Mode Operation – Timer 0 Only............................ 138
29 Timer 2 with Additional 4-channel PCA........................................................... 139
Introduction...................................................................................................................... 139
Timer 2............................................................................................................................. 141
Timer function.............................................................................................................................. 141
Event Counter function................................................................................................................ 141
Gated Timer function................................................................................................................... 141
Timer 2 with PCA.............................................................................................................. 142
Timer 2 Register Description............................................................................................ 143
Capture Modes................................................................................................................. 146
Capture On Edge Mode.............................................................................................................. 146
Capture On Write Mode............................................................................................................... 146
Compare Modes............................................................................................................... 147
Compare Mode 0......................................................................................................................... 147
Compare Mode 1......................................................................................................................... 149
Reload Mode.................................................................................................................... 151
Programmable Clock Output Mode.................................................................................. 152
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Table of Contents
I/O Pin Structures............................................................................................................. 124
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
30 Analog to Digital Converter – ADC .................................................................. 153
A/D Overview................................................................................................................... 153
A/D Converter Register Description................................................................................. 154
A/D Converter Data Registers – ADRL, ADRH................................................................ 154
A/D Converter Control Registers – ADCR0, ADCR1, ADCR2, ADPGA........................... 154
A/D Converter Clock Source............................................................................................ 159
A/D Input Pins.................................................................................................................. 159
Temperature Sensor......................................................................................................... 160
A/D Reference Voltage Source........................................................................................ 160
Summary of A/D Conversion Steps.................................................................................. 161
A/D Conversion Timing.................................................................................................... 162
Programming Considerations........................................................................................... 163
A/D Transfer Function...................................................................................................... 163
31 Digital to Analog Converter – DAC................................................................... 164
DAC Register Description................................................................................................ 164
DAC Operation................................................................................................................. 166
DAC Reference Voltage Source....................................................................................... 167
Programming Considerations........................................................................................... 167
32 Voltage Reference Generator........................................................................... 168
Voltage Reference Generator Operation.......................................................................... 168
33 Comparators...................................................................................................... 170
Comparator Operation..................................................................................................... 170
Comparator Registers...................................................................................................... 171
Comparator Interrupt........................................................................................................ 176
Comparator Reset Function............................................................................................. 176
Programming Considerations........................................................................................... 176
2
34 I C Serial Interface............................................................................................. 177
I2C Interface Operation..................................................................................................... 177
I2C Registers.................................................................................................................... 178
I2C Bus Communication................................................................................................... 182
I2C Bus Start Signal..................................................................................................................... 183
Slave Address............................................................................................................................. 183
I2C Bus Read/Write Signal........................................................................................................... 183
I2C Bus Slave Address Acknowledge Signal............................................................................... 183
I2C Bus Data and Acknowledge Signal........................................................................................ 184
I2C Status Codes......................................................................................................................... 185
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Table of Contents
A/D Operation.................................................................................................................. 158
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
35 Serial Interface – SPI......................................................................................... 190
SPI Interface Operation.................................................................................................... 190
SPI Features............................................................................................................................... 191
SPI Registers................................................................................................................... 192
SPI Communication......................................................................................................... 195
UART Overview................................................................................................................ 198
UART0 Features.......................................................................................................................... 198
UART1 Features.......................................................................................................................... 198
Basic UART Data Transfer Scheme............................................................................................ 199
UART0 Operating Description.......................................................................................... 200
UART0 External Pin Interfacing................................................................................................... 200
UART0 Register Description....................................................................................................... 201
UART0 Operating Modes............................................................................................................ 205
UART0 Multiprocessor Communication ..................................................................................... 209
UART0 Baud Rate Setup............................................................................................................ 209
UART1 Operating Description.......................................................................................... 210
UART1 External Pin Interfacing................................................................................................... 210
UART1 Register Description........................................................................................................211
UART1 Operating Modes............................................................................................................ 214
UART1 Multiprocessor Communication...................................................................................... 216
UART1 Baud Rate Setup............................................................................................................ 216
37 Instruction Set.................................................................................................... 217
Introduction...................................................................................................................... 217
Read-Modify-Write Instruction.......................................................................................... 222
38 Package Information......................................................................................... 223
48-pin LQFP (7mm×7mm) Outline Dimensions............................................................... 224
64-pin LQFP (7mm×7mm) Outline Dimensions............................................................... 225
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Table of Contents
36 UART Serial Interfaces – UART0 and UART1.................................................. 198
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
List of Tables
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List of Tables
Program Memory Register List................................................................................................................. 33
FMAR0 Register – Flash Program Memory Address Register 0.............................................................. 33
FMAR1 Register – Flash Program Memory Address Register 1.............................................................. 34
FMAR2 Register – Flash Program Memory Address Register 2.............................................................. 34
FMDR Register – Flash Program Memory Data Register........................................................................ 34
FMCR Register – Flash Program Memory Control Register.................................................................... 35
FMKEY Register – Flash Program Memory Unlock Key Data Register................................................... 36
FMSR Register – Flash Program Memory Status Register...................................................................... 36
HT85F2260 Program Memory Contents................................................................................................... 43
HT85F2270 Program Memory Contents................................................................................................... 44
HT85F2280 Program Memory Contents................................................................................................... 44
Security Bytes........................................................................................................................................... 44
General Purpose Data RAM, 20H~2FH, Bit Address Map....................................................................... 50
Special Function Register Bit Addresses Map.......................................................................................... 51
Special Function Register Map................................................................................................................. 52
DPS Register – Data Pointer Select Register........................................................................................... 54
DPC Register – Data Pointer Control Register......................................................................................... 55
PSW Register – Program Status Word Register...................................................................................... 56
Crystal Recommended Capacitor Values................................................................................................. 58
32768Hz Crystal Recommended Capacitor Values.................................................................................. 59
System Clock Control Register – SCCR................................................................................................... 62
High Speed Oscillator Control Register – HSOCR................................................................................... 63
Low Speed Oscillator Control Register – LSOCR.................................................................................... 63
PLL Control Register – PLLCR................................................................................................................. 65
PCON Register – Power Control Register................................................................................................ 67
WDT Register Contents............................................................................................................................ 70
IEN0 Register........................................................................................................................................... 70
IEN1 Register........................................................................................................................................... 71
WDTREL Register.................................................................................................................................... 71
WDTCR Register...................................................................................................................................... 72
IP0 Register.............................................................................................................................................. 72
Watchdog Timer Enable/Disable Control.................................................................................................. 73
LVDCR Register....................................................................................................................................... 75
Reset Source Summary............................................................................................................................ 76
RSTSRC Register..................................................................................................................................... 77
LVRCR Register....................................................................................................................................... 80
IP0 Register.............................................................................................................................................. 81
T2CON1 Register..................................................................................................................................... 82
CP0CR Register....................................................................................................................................... 83
Software Reset Summary......................................................................................................................... 84
SRST Register.......................................................................................................................................... 84
WDTCR Register...................................................................................................................................... 85
LVRCR Register....................................................................................................................................... 85
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
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List of Tables
Interrupt Register Bit Naming Conventions.............................................................................................. 92
Interrupt Register Contents....................................................................................................................... 93
IEN0 Register........................................................................................................................................... 93
IEN1 Register........................................................................................................................................... 94
IEN2 Register........................................................................................................................................... 94
IEN3 Register........................................................................................................................................... 95
IRCON Register........................................................................................................................................ 96
IRCON2 Register...................................................................................................................................... 97
S0CON Register....................................................................................................................................... 98
S1CON Register....................................................................................................................................... 99
TCON Register....................................................................................................................................... 100
T2CON Register..................................................................................................................................... 101
T3CON Register..................................................................................................................................... 101
SPSTA Register...................................................................................................................................... 102
CPICR Register...................................................................................................................................... 103
I2CCON Register.................................................................................................................................... 104
Low byte of Interrupt Priority Register 0: IP0.......................................................................................... 109
High byte of Interrupt Priority Register 0: IP0H....................................................................................... 109
Low byte of Interrupt Priority Register 1: IP1...........................................................................................110
High byte of Interrupt Priority Register 1: IP1H........................................................................................110
Low byte of Interrupt Priority Register 2: IP2...........................................................................................111
High byte of Interrupt Priority Register 2: IP2H........................................................................................111
Low byte of Interrupt Priority Register 3: IP3...........................................................................................111
How byte of Interrupt Priority Register 3: IP3H........................................................................................112
External Interrupt Trigger Type................................................................................................................112
CPICR Register.......................................................................................................................................113
TBCR Register.........................................................................................................................................115
I/O Port Function Summary.....................................................................................................................118
I/O Register List.......................................................................................................................................119
P0 Register..............................................................................................................................................119
P1 Register..............................................................................................................................................119
P2 Register............................................................................................................................................. 120
P3 Register............................................................................................................................................. 120
P4 Register............................................................................................................................................. 120
P5 Register............................................................................................................................................. 120
Port 0 Mode Control................................................................................................................................ 121
P0M0 Register........................................................................................................................................ 121
P0M1 Register........................................................................................................................................ 121
Port 1 Mode Control................................................................................................................................ 121
P1M0 Register........................................................................................................................................ 121
P1M1 Register........................................................................................................................................ 121
Port 2 Mode Control................................................................................................................................ 122
P2M0 Register........................................................................................................................................ 122
P2M1 Register........................................................................................................................................ 122
Port 3 Mode Control................................................................................................................................ 122
P3M0 Register........................................................................................................................................ 122
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
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List of Tables
P3M1 Register........................................................................................................................................ 122
P0WAKE Register................................................................................................................................... 123
SRCR Register....................................................................................................................................... 123
Timer Function Summary........................................................................................................................ 127
Timer0/Timer1/Timer3 Register List........................................................................................................ 129
TL0 Register .......................................................................................................................................... 129
TH0 Register .......................................................................................................................................... 130
TL1 Register........................................................................................................................................... 130
TH1 Register........................................................................................................................................... 131
TL3 Register........................................................................................................................................... 131
TH3 Register........................................................................................................................................... 132
TMOD Register....................................................................................................................................... 132
TCON Register....................................................................................................................................... 133
T3CON Register .................................................................................................................................... 134
TMPRE Register..................................................................................................................................... 135
13-bit Counter Data................................................................................................................................ 136
Timer 2 with PCA Modules Operating Modes Summary......................................................................... 139
Timer 2 with PCA Modules I/O Pins........................................................................................................ 139
Timer 2 Register List............................................................................................................................... 143
CCEN Register ...................................................................................................................................... 143
T2CON Register..................................................................................................................................... 144
T2CON1 Register .................................................................................................................................. 145
A/D Converter Register List.................................................................................................................... 154
A/D Data Registers................................................................................................................................. 154
ADCR0 Register .................................................................................................................................... 155
ADCR1 Register..................................................................................................................................... 156
ADCR2 Register..................................................................................................................................... 157
ADPGA Register..................................................................................................................................... 158
A/D Clock Period Examples.................................................................................................................... 159
A/D Converter Voltage Reference Select............................................................................................... 160
DAH Register.......................................................................................................................................... 164
DAL Register........................................................................................................................................... 164
DACTRL Register................................................................................................................................... 164
DAC Converter Voltage Reference Select.............................................................................................. 167
Internal Voltage Reference Enable/Disable Control............................................................................... 168
Comparator Registers List...................................................................................................................... 171
CP0CR Register..................................................................................................................................... 172
CP1CR Register..................................................................................................................................... 173
CPHCR Register..................................................................................................................................... 174
CPICR Register...................................................................................................................................... 175
I2C Register List ..................................................................................................................................... 178
I2CCON Register.................................................................................................................................... 178
I2CLK Register....................................................................................................................................... 179
I2CSTA Register..................................................................................................................................... 180
I2CDAT Register..................................................................................................................................... 180
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
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List of Tables
I2CADR Register.................................................................................................................................... 180
I2C Status in Master Transmitter Mode................................................................................................... 185
I2C Status in Master Receiver Mode ...................................................................................................... 186
I2C Status in Slave Receiver Mode......................................................................................................... 187
I2C Status in Slave Transmitter Mode..................................................................................................... 188
I2C Status: Miscellaneous States ........................................................................................................... 189
SPI Register List..................................................................................................................................... 192
SPDAT Register...................................................................................................................................... 192
SPCON Register..................................................................................................................................... 193
SPSTA Register...................................................................................................................................... 194
UART0 Register List............................................................................................................................... 201
S0BUF Register – UART0 Data register................................................................................................ 201
S0CON Register – UART0 Control register............................................................................................ 202
S0RELL Register – UART0 Reload Low Register.................................................................................. 203
S0RELH Register – UART0 Reload High Register................................................................................ 203
SPPRE Register – UART Clock Prescaler Register............................................................................... 203
SBRCON Register.................................................................................................................................. 204
PCON Register....................................................................................................................................... 204
UART0 Operating Modes....................................................................................................................... 205
Mode 0.................................................................................................................................................... 205
UART1 Register List................................................................................................................................211
S1BUF Register – UART1 Data register.................................................................................................211
S1CON Register – UART1 Control register............................................................................................ 212
S1RELL Register – UART1 Reload Low Register.................................................................................. 213
S1RELH Register – UART1 Reload High Register................................................................................ 213
SPPRE Register – UART Clock Prescaler Register............................................................................... 213
UART1 Operating Modes....................................................................................................................... 214
Notes on Data Addressing Modes.......................................................................................................... 217
Notes on Program Addressing Modes.................................................................................................... 217
Arithmetic Operations............................................................................................................................. 218
Logic Operations..................................................................................................................................... 219
Data transfer Operations........................................................................................................................ 220
Program Branches.................................................................................................................................. 221
Boolean Manipulation............................................................................................................................. 222
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
List of Figures
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List of Figures
Stack Block Diagram................................................................................................................................ 29
Program Memory Structure...................................................................................................................... 31
Unlock Procedure Flowchart..................................................................................................................... 37
Page Erase Flowchart.............................................................................................................................. 38
Byte Read Flowchart................................................................................................................................ 39
Byte Write Flowchart (FMCR.0=1, FMCR.6=0)........................................................................................ 40
Byte Write Flowchart (FMCR.0=1, FMCR.6=1)........................................................................................ 41
Internal Data Memory Structure................................................................................................................ 47
HT85F2270/HT85F2280 XDATA............................................................................................................... 48
HT85F2260 XDATA................................................................................................................................... 49
DPTRn Registers Control Block Diagram................................................................................................. 53
Crystal/Resonator Oscillator – HXT.......................................................................................................... 58
External LXT Oscillator – LXT................................................................................................................... 59
System Clock Configurations.................................................................................................................... 61
PLL Frequency Changing......................................................................................................................... 64
Watchdog Timer........................................................................................................................................ 69
Watchdog Timer Refresh Operation......................................................................................................... 74
Power-On Reset Timing ........................................................................................................................... 78
Interrupt Structure................................................................................................................................... 105
Interrupt Flowchart.................................................................................................................................. 106
Time Base Clock Source Select..............................................................................................................114
Quasi-bidirectional I/O Structure............................................................................................................. 124
Push-pull Output Structure..................................................................................................................... 125
Open-drain Output Structure.................................................................................................................. 125
Input Only Structure................................................................................................................................ 125
Mode 0 and Mode 1 Block Diagram – Timer 0, 1, 3............................................................................... 136
Mode 2 Block Diagram – Timer 0, 1, 3................................................................................................... 137
Mode 3 Block Diagram – Timer 0........................................................................................................... 138
Timer 2 with PCA Modules Block Diagram............................................................................................. 140
Capture Modes Block Diagram............................................................................................................... 146
Compare Mode 0 – Module 1, Module 2, Module 3................................................................................ 147
Compare Mode 0 – Module 0................................................................................................................. 148
Compare Mode 0 Timing Diagram.......................................................................................................... 148
Compare Mode 1 – Module1, Module2, Module 3.................................................................................. 149
Compare Mode 1 – Module 0................................................................................................................. 149
Compare Mode 1 Timing Diagram.......................................................................................................... 150
Reload Mode – Module 0........................................................................................................................ 151
Timer2 Clock Output Block Diagram....................................................................................................... 152
Programmable Clock Output Timing Diagram – Module 0..................................................................... 152
A/D Converter Structure......................................................................................................................... 153
A/D Conversion Timing........................................................................................................................... 162
Ideal A/D Transfer Function (PGA=1)..................................................................................................... 163
DAC Basic Operational Block Diagram.................................................................................................. 166
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
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List of Figures
Voltage Reference Generator Block Diagram......................................................................................... 169
Comparator 0.......................................................................................................................................... 170
Comparator 1.......................................................................................................................................... 171
I2C Master Slave Bus Connection........................................................................................................... 177
I2C Interface Operation Flow................................................................................................................... 177
I2C Block Diagram................................................................................................................................... 181
I2C Bus Initialisation Flow Chart ............................................................................................................. 182
I2C Communication Timing Diagram....................................................................................................... 184
Single SPI Master and single Slave Connection.................................................................................... 190
SPI Interface Block Diagram................................................................................................................... 191
SPI Master Mode Timing........................................................................................................................ 195
SPI Slave Mode Timing – CPHA=0........................................................................................................ 196
SPI Slave Mode Timing – CPHA=1........................................................................................................ 196
SPI Transfer Control Flowchart............................................................................................................... 197
Basic UART Data Transfer Diagram....................................................................................................... 199
UART 0 Block Diagram........................................................................................................................... 200
UART0 Mode 0 Timing Diagram............................................................................................................. 205
UART0 Mode 1 Timing Diagram............................................................................................................. 206
UART0 Mode 2 Timing Diagram............................................................................................................. 207
UART0 Mode 3 Timing Diagram............................................................................................................. 208
UART0 Baud Rate Generator................................................................................................................. 209
UART1 Block Diagram............................................................................................................................ 210
UART1 Mode A Timing Diagram............................................................................................................. 214
UART1 Mode B Timing Diagram............................................................................................................ 215
UART1 Baud Rate Generator................................................................................................................. 216
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
1
Features
CPU Features
Features
■■ Operating Voltage:
●● fSYS=3.6864MHz: 2.2V~5.5V
●● fSYS=8MHz: 2.2V~5.5V
●● fSYS=12MHz: 2.7V~5.5V
●● fSYS=24MHz: 4.5V~5.5V
■■ Program Memory Capacity: 16K×8~64K×8
■■ Data Memory Capacity: 1280×8~2304×8
■■ High performance 1-T architecture: 8051
■■ Up to 32MIPS with 32MHz system clock at VDD=5V
■■ 8051 compatible instruction set
■■ Flexible Power-down and wake-up functions to reduce power consumption
■■ Oscillator types:
●● External high frequency crystal
●● Internal high frequency RC
●● External low frequency crystal
●● Internal low frequency RC
■■ Multi-mode operation: Normal, Idle and Power-Down Modes
■■ Fully integrated internal 3.6864MHz oscillator requires no external components
■■ Internal PLL to multiply oscillator frequency up to 1~8 times for high speed system clock
■■ Watchdog Timer function
■■ Missing Clock Detector
■■ Dual 16-bit data pointers with addition arithmetic operation
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Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Peripheral Features
■■ Multi-channel 12-bit resolution A/D converter
■■ Single 12-bit D/A Converter
■■ Serial SPI Interface
■■ I2C Interface
Features
■■ Dual UART Interfaces
■■ Dual Comparator functions
■■ Up to 48 bidirectional I/O lines
■■ 16-bit Programmable Counter Array with 5 Capture/Compare Modules
■■ 16-bit Programmable Counter Array
■■ Single Time-Base functions for generation of fixed time interrupt signal
■■ Internal Temperature Sensor
■■ Low voltage reset function
■■ Low voltage detect function
■■ Package types: 48-LQFP and 64-LQFP
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Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
2
General Description
The HT85F22x0 series of devices are Flash Memory A/D type high performance 1-T architecture
8051-Based microcontrollers. Offering users the convenience of Flash Memory multi-programming
features, these devices also include a wide range of functions and features.
A full choice of both internal and external high and low speed oscillators are provided with the
internal oscillators requiring no external components for its implementation. A fully internal Phase
Locked Loop and the ability to operate and switch dynamically between a range of operating
modes using different clock sources gives users the ability to optimise microcontroller operation
and minimize power consumption.
The inclusion of flexible I/O programming features, Time-Base functions along with many other
features ensure that the device will find excellent use in applications such as electronic metering,
environmental monitoring, handheld instruments, household appliances, electronically controlled
tools, motor driving in addition to many others.
The HT85F22x0 series are Flash devices offering the advantages of easy and effective in-circuit
program updates. In addition, an EV chip, HT85V2280, includes an OCDS (On-Chip Debug
Support) interface for the In-Circuit Emulator.
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General Description
Analog features include a multi-channel 12-bit A/D converter, a 12-bit D/A converter and dual
comparator functions. Multiple timers provide timing, capture, event counter and programmable
clock output functions. Communication with the outside world is catered for by including fully
integrated SPI, I 2C and UART interface functions, popular interfaces which provide designers
with a means of easy communication with external peripheral hardware. Protective features such
as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector and Missing Clock
Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation
is maintained in hostile electrical environments.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
3
Selection Table
Most features are common to all devices, the main feature distinguishing them are Program
Memory and Data memory capacity, A/D channels, UART numbers and packages. The following
table summarises the main features of each device.
VDD
Program
Memory
Data
Memory
I/O
Ext.
Interrupt
HT85F2260
2.2V~5.5V
16K×8
1280×8
32
7
4
CCU×4
1
HT85F2270
2.2V~5.5V
32K×8
2304×8
48
7
4
CCU×4
1
HT85F2280
2.2V~5.5V
64K×8
2304×8
48
7
4
CCU×4
1
Part No.
A/D
D/A
Comparator
I2C
SPI
HT85F2260
12-bit×7
12-bit×1
2
√
√
1
√
48LQFP
HT85F2270
12-bit×9
12-bit×1
2
√
√
2
√
48/64 LQFP
HT85F2280
12-bit×9
12-bit×1
2
√
√
2
√
48/64 LQFP
16-bit Timer 16-bit PCA
UART
Temp.
Sensor
Time Base
package
Note: CCU stands for Compare/Capture Unit.
Rev. 1.00
17 of 226
May 15, 2013
Selection Table
Part No.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
4
Block Diagram
The following block diagram illustrates the main functional blocks.
Block Diagram
3.6864MHz
×
Rev. 1.00
32768Hz
I
×
18 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Pin Assignment

Pin Assignment


5

Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the “/”
sign can be used for higher priority.
2. For both the 48 LQFP-A and 64 LQFP-A packages, both real IC and OCDS EV IC share the same
package.
Rev. 1.00
19 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
6
Pin Descriptions
Pin Name
P0.0/ICPDA/TDA
P0.1/C1OUT
P0.2/SSN
P0.3/SCK
P0.4/MISO
P0.5/MOSI
P0.6/SCL
P0.7/SDA
P1.0/INT3/CC0
P1.1/INT4/CC1
P1.2/INT5/CC2
Rev. 1.00
Function
OPT
P0.0
P0M0
P0M1
P0WAKE
I/T
O/T
Description
ICPDA
—
TDA
—
P0.1
P0M0
P0M1
P0WAKE
ST
CMOS General purpose I/O. Register selected I/O mode and wake-up
C1OUT
—
—
CMOS Comparator 1 Output
P0.2
P0M0
P0M1
P0WAKE
ST
CMOS General purpose I/O. Register selected I/O mode and wake-up
SSN
—
ST
P0.3
P0M0
P0M1
P0WAKE
ST
CMOS General purpose I/O. Register selected I/O mode and wake-up
SCK
—
ST
CMOS SPI Clock
P0.4
P0M0
P0M1
P0WAKE
ST
CMOS General purpose I/O. Register selected I/O mode and wake-up
MISO
—
ST
CMOS SPI Master In Slave Out pin
P0.5
P0M0
P0M1
P0WAKE
ST
CMOS General purpose I/O. Register selected I/O mode and wake-up
MOSI
—
ST
CMOS SPI Master Out Slave In pin
P0.6
P0M0
P0M1
P0WAKE
ST
CMOS General purpose I/O. Register selected I/O mode and wake-up
SCL
—
—
NMOS I2C Clock
P0.7
P0M0
P0M1
P0WAKE
ST
CMOS General purpose I/O. Register selected I/O mode and wake-up
SDA
—
—
NMOS I2C Data
P1.0
P1M0
P1M1
ST
CMOS General purpose I/O. Register selected I/O mode
General purpose I/O. Register selected I/O mode and wake-up
ST
CMOS
ICP Data Input/Output
Debug Data Input/Output
—
—
SPI Slave select Input
INT3
—
ST
CC0
—
ST
CMOS Compare/Capture input/output for PCA module 0
P1.1
P1M0
P1M1
ST
CMOS General purpose I/O. Register selected I/O mode
—
External Interrupt 3 Input
INT4
—
ST
CC1
—
ST
CMOS Compare/Capture input/output for PCA module 1
P1.2
P1M0
P1M1
ST
CMOS General purpose I/O. Register selected I/O mode
INT5
—
ST
CC2
—
ST
—
External Interrupt 4 Input
External Interrupt 5 Input
CMOS Compare/Capture input/output for PCA module 2
20 of 226
May 15, 2013
Pin Descriptions
With the exception of the power pins, all pins on these devices can be referenced by their Port
name, e.g. P0.0, P0.1 etc, which refer to the digital I/O function of the pins. However these Port
pins are also shared with other function such as the Analog to Digital Converter, Serial Port pins
etc. The function of each pin is listed in the following table, however the details behind how each
pin is configured is contained in other sections of the datasheet.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Pin Name
P1.3/INT6/CC3
P1.4/INT2
P1.6/T2
P1.7
P2.0~P2.6
P2.7/T3
P3.0/RXD0
P3.1/TXD0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/RXD1
P3.7/TXD1
P4.0/AIN.0
P4.1/AIN.1
P4.2/AIN.2
Rev. 1.00
OPT
I/T
P1.3
P1M0
P1M1
O/T
Description
ST
INT6
—
ST
CC3
—
ST
CMOS Compare/Capture input/output for PCA module 3
P1.4
P1M0
P1M1
ST
CMOS General purpose I/O. Register selected I/O mode
INT2
—
ST
P1.5
P1M0
P1M1
ST
T2EX
—
ST
P1.6
P1M0
P1M1
ST
CMOS General purpose I/O. Register selected I/O mode
T2
—
ST
CMOS Timer 2 external input or Timer 2 programmable clock output
P1.7
P1M0
P1M1
ST
CMOS General purpose I/O. Register selected I/O mode
P2.0~P2.6
P2M0
P2M1
ST
CMOS General purpose I/O. Register selected I/O mode
P2.7
P2M0
P2M1
ST
CMOS General purpose I/O. Register selected I/O mode
T3
—
ST
P3.0
P3M0
P3M1
ST
RXD0
—
ST
P3.1
P3M0
P3M1
ST
CMOS General purpose I/O. Register selected I/O mode
TXD0
—
—
CMOS UART0 Transmit Data Output
P3.2
P3M0
P3M1
ST
CMOS General purpose I/O. Register selected I/O mode
INT0
—
ST
P3.3
P3M0
P3M1
ST
INT1
—
ST
P3.4
P3M0
P3M1
ST
T0
—
ST
P3.5
P3M0
P3M1
ST
T1
—
ST
P3.6
P3M0
P3M1
ST
RXD1
—
ST
P3.7
P3M0
P3M1
ST
CMOS General purpose I/O. Register selected I/O mode
TXD1
—
—
CMOS UART1 Transmit Data Output
P4.0
P4M0
P4M1
ST
CMOS General purpose I/O. Register selected I/O mode
AIN.0
—
AN
P4.1
P4M0
P4M1
ST
AIN.1
—
AN
P4.2
P4M0
P4M1
ST
AIN.2
—
AN
CMOS General purpose I/O. Register selected I/O mode
—
—
External Interrupt 6 Input
External Interrupt 2 Input
CMOS General purpose I/O. Register selected I/O mode
—
—
Timer 2 capture trigger
Timer 3 External Input
CMOS General purpose I/O. Register selected I/O mode
—
—
UART0 Receive Data Input
External Interrupt 0 Input
CMOS General purpose I/O. Register selected I/O mode
—
External Interrupt 1 Input
CMOS General purpose I/O. Register selected I/O mode
—
Timer 0 External Input
CMOS General purpose I/O. Register selected I/O mode
—
Timer 1 External Input
CMOS General purpose I/O. Register selected I/O mode
—
—
UART1 Receive Data Input
ADC Input Channel 0
CMOS General purpose I/O. Register selected I/O mode
—
ADC Input Channel 1
CMOS General purpose I/O. Register selected I/O mode
—
ADC Input Channel 2
21 of 226
May 15, 2013
Pin Descriptions
P1.5/T2EX
Function
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Pin Name
P4.3/AIN.3
P4.4/AIN.4
P4.6/AIN.6
P4.7/AIN.7
P5.0~P5.3
P5.4/C0OUT
P5.5/XT1
P5.6/XT2
P5.7/DAC
CP0-/CP0+
CP1-/CP1+
OSC1
OSC2
RESET/ICPCK/TCK
OPT
I/T
P4.3
P4M0
P4M1
O/T
Description
ST
AIN.3
—
AN
P4.4
P4M0
P4M1
ST
AIN.4
—
AN
P4.5
P4M0
P4M1
ST
AIN.5
—
AN
P4.6
P4M0
P4M1
ST
AIN.6
—
AN
P4.7
P4M0
P4M1
ST
AIN.7
—
AN
P5.0~P5.3
P5M0
P5M1
ST
CMOS General purpose I/O. Register selected I/O mode
P5.4
P5M0
P5M1
ST
CMOS General purpose I/O. Register selected I/O mode
C0OUT
—
—
CMOS Comparator 0 Output
P5.5
P5M0
P5M1
ST
CMOS General purpose I/O. Register selected I/O mode
XT1
—
LXT
P5.6
P5M0
P5M1
ST
XT2
—
—
P5.7
P5M0
P5M1
ST
CMOS General purpose I/O. Register selected I/O mode
CMOS DAC Output
CMOS General purpose I/O. Register selected I/O mode
—
ADC Input Channel 3
CMOS General purpose I/O. Register selected I/O mode
—
ADC Input Channel 4
CMOS General purpose I/O. Register selected I/O mode
—
ADC Input Channel 5
CMOS General purpose I/O. Register selected I/O mode
—
ADC Input Channel 6
CMOS General purpose I/O. Register selected I/O mode
—
—
ADC Input Channel 7
Low Frequency Crystal Oscillator
CMOS General purpose I/O. Register selected I/O mode
LXT
Low Frequency Crystal Oscillator
DAC
—
—
CP0-
—
AN
—
CP0+
—
AN
—
Comparator 0 Non-Inverting Input
CP1-
—
AN
—
Comparator 1 Inverting Input
Comparator 0 Inverting Input
CP1+
—
AN
—
Comparator 1 Non-Inverting Input
OSC1
—
HXT
—
High Frequency Crystal Oscillator
OSC2
—
—
HXT
RESET
—
ST
—
High Frequency Crystal Oscillator
RESET pin
ICPCK
—
ST
—
ICP Clock Input
TCK
—
ST
—
Debug Clock Input
VREF
VREF
—
AN
—
Reference Voltage for ADC/DAC
VDD
VDD
—
PWR
—
Positive Power supply for CORE
VCCA1
VCCA1
—
PWR
—
Positive Power supply for I/O pad
VCCA2
VCCA2
—
PWR
—
Positive Power supply for DAC
VCCA3
VCCA3
—
PWR
—
Positive Power supply for ADC
VSS
—
PWR
—
Negative Power supply
VSS
Pin Descriptions
P4.5/AIN.5
Function
Note: I/T: Input type;
O/T: Output type;
ST: Schmitt Trigger input
OPT: Optional by configuration option (CO) or register option
PWR: Power;
NMOS: NMOS output
CMOS: CMOS output;
AN: Analog input pin
LXT: low frequency crystal oscillator;
HXT: high frequency crystal oscillator
Where devices exist in more than one package type the table reflects the situation for the package with the
largest number of pins. For this reason not all pins described in the table may exist on all package types.
Rev. 1.00
22 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
7
Absolute Maximum Ratings
Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute
Maximum Ratings” may cause substantial damage to the device. Functional operation of
this device at other conditions beyond those listed in the specification is not implied and
prolonged exposure to extreme conditions may affect device reliability.
8
D.C. Characteristics
Ta=25°C
Symbol
Parameter
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
VDD1
Operating Voltage
(High Frequency Internal RC OSC)
—
fOSC=fSYS=3.6864MHz
(PLL disabled)
2.2
—
5.5
V
VDD2
Operating Voltage
(Crystal OSC)
—
fOSC=fSYS=8MHz
(PLL disabled)
2.2
—
5.5
V
VDD3
Operating Voltage
(PLL)
—
fOSC=4MHz (Crystal OSC)
fSYS=12MHz (PLL × 3)
2.7
—
5.5
V
VDD4
Operating Voltage
(PLL)
—
fOSC=4MHz (Crystal OSC)
fSYS=16MHz (PLL × 4)
3.3
—
5.5
V
VDD5
Operating Voltage
(PLL)
—
fOSC=4MHz (Crystal OSC)
fSYS=24MHz (PLL × 6)
4.5
—
5.5
V
IDD1
Operating Current
(High Frequency Internal RC OSC)
3V
No load, fOSC=fSYS=3.6864MHz ,
(PLL disabled) ADC off, DAC off,
WDT enable
—
5.0
8.0
—
10.0
15.0
IDD2
Operating Current
(Crystal OSC)
3V
No load, fOSC=fSYS=8MHz ,
(PLL disabled)
ADC off, DAC off, WDT enable
—
6.0
8.5
—
12.5
20
IDD3
Operating Current (PLL)
No load, fOSC=4MHz (Crystal OSC)
fSYS=12MHz (PLL × 3)
ADC off, DAC off, WDT enable
—
8.0
12.0
—
16
25
—
20
30
mA
—
28
40
mA
5V
5V
3V
5V
IDD4
Operating Current (PLL)
5V
No load,
fOSC=4MHz (Crystal OSC)
fSYS=16MHz (PLL × 4)
ADC off, DAC off, WDT enable
IDD5
Operating Current (PLL)
5V
No load,
fOSC=4MHz (Crystal OSC)
fSYS=24MHz (PLL × 6)
ADC off, DAC off, WDT enable
Rev. 1.00
23 of 226
mA
mA
mA
May 15, 2013
Absolute Maximum Ratings
Supply Voltage ................................................................................................. VSS-0.3V to V DD+6.0V
Input Voltage .................................................................................................... VSS-0.3V to V DD+0.3V
Storage Temperature ....................................................................................................-50°C to 125°C
Operating Temperature ................................................................................................. -40°C to 85°C
IOL Total .......................................................................................................................................150mA
IOH Total.................................................................................................................................... -100mA
Total Power Dissipation ............................................................................................................500mW
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Symbol
Parameter
Test Conditions
Conditions
VDD
ISTB1
Stanby Current
(Power-Down mode)(HIRC off, HXT off)
3V
ISTB2
Stanby Current (Idle)
(HIRC off, HXT on)
3V
5V
No load, fOSC=4MHz (Crystal OSC)
fSYS off, ADC off, DAC off,
LVD/LVR disable, WDT enable,
5V
No load, All peripherals off
Min.
Typ.
Max.
—
—
1.5
—
—
2.5
—
1.5
2.5
—
3.5
5.0
Unit
μA
mA
Input Low Voltage (except RESET pin)
—
quasi-bidirection mode
0
—
0.2VDD
V
Input High Voltage (except RESET pin)
—
quasi-bidirection mode
0.8VDD
—
VDD
V
VIL2
Input Low Voltage (RESET pin)
—
—
0
—
0.4VDD
V
VIH2
Input High Voltage (RESET pin)
—
—
0.9VDD
—
VDD
V
2.2V
—
6.0
—
3.3V VOL=0.4V
—
9.0
—
5.0V
—
12.0
—
2.2V
—
-1.0
—
3.3V VOH=0.9VDD
—
-2.0
—
5.0V
—
-4.0
—
—
-40
—
—
-80
—
—
-160
—
IOL
IOH1
IOH2
I/O Port Sink Current
I/O Port Source Current
(push-pull mode for Ports 0, 1, 2, 3)
2.2V
I/O Port Source Current
3.3V VOH=0.9VDD
(quasi-bidirection mode for Ports 0, 1, 2, 3, 4, 5)
5.0V
mA
mA
μA
IIL
Logical 0 input current, Ports 0, 1, 2, 3, 4, 5
(quasi-bidirection mode)
5V
VIN=0.4V
—
—
-50
μA
ITL
Logical 1 to 0 transition
Current, Ports 0, 1, 2, 3, 4, 5
(quasi-bidirection mode)
5V
VIN=2.4V
—
—
-950
μA
ILI
Input Leakage current, Ports 0, 1, 2, 3
(input mode)
5V
0.45V<VIN<VDD-0.3
—
—
±10
μA
VBG
Bandgap reference with buffer voltage
(for A/D type MCU Tiny Power IP)
—
—
-3%
1.1
+3%
V
IBG
Additional Power Consumption if Reference
with Buffer is used (for A/D type MCU)
—
—
—
200
300
μA
ILVR
Additional Power Consumption if LVR is used
(for Tiny Power IP)
3V
—
75
100
—
75
100
ILVD
Additional Power Consumption if LVD is used
(for Tiny Power IP)
3V
—
75
100
—
75
100
5V
5V
LVR enable
LVD enable
VLVR1
LVR Enable, 2.1V select
2.1
VLVR2
LVR Enable, 2.55V select
2.55
VLVR3
Low Voltage Reset Voltage
—
VLVR4
LVR Enable, 3.15V select
-5%
3.15
LVR Enable, 4.0V select
4.0
VLVD1
LVD Enable, 2.0V Select
2.0
VLVD2
LVD Enable, 2.2V Select
2.2
VLVD3
LVD Enable, 2.4V Select
2.4
VLVD4
LVD Enable, 2.7V Select
VLVD5
Low Voltage Detector Voltage
—
LVD Enable, 3.0V Select
-5%.
2.7
3.0
VLVD6
LVD Enable, 3.3V Select
3.3
VLVD7
LVD Enable, 3.6V Select
3.6
VLVD8
LVD Enable, 4.2V Select
4.2
Rev. 1.00
24 of 226
μA
μA
+5%
V
+5%
V
May 15, 2013
D.C. Characteristics
VIL1
VIH1
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
9
A.C. Characteristics
Ta=25°C
Symbol
fSYS2
System clock (Crystal OSC)
System clock (PLL)
fLIRC
32kHz Internal RC oscillator
fHIRC
3.6864MHz Internal RC oscillator
fTIMER
Timer Input Frequency (T0~T3)
tRES
External Reset Minimum Low Pulse width
VDD
Conditions
Min.
Typ.
Max. Unit
2.2V~5.5V
0.4
—
8
2.7V~5.5V PLL Disable
0.4
—
12
4.5V~5.5V
0.4
—
24
4.5V~5.5V Crystal OSC=4MHz, PLL Enable
5V
Ta=25°C
2.2V~5.5V Ta=-40°C~85°C
4
—
32
-10%
32
+10%
-50%
32
+60%
3V
Ta=25°C
-3%
3.6864 +3%
5V
Ta=25°C
-3%
3.6864 +3%
MHz
MHz
kHz
MHz
2.2V~5.5V fSYS=8MHz
0
—
2
2.7V~5.5V fSYS=12MHz
0
—
3
4.5V~5.5V fSYS=24MHz
0
—
6
1
3.3
5
μs
100
220
500
μs
—
tSYS
—
—
tMCD
Missing Clock Detector Timeout
—
Time from last system clock to
reset initiation
tSST
System start-up timer period (Power-up or
wake-up from Power-Down mode when
the main oscillator is off or system clock is
switching between HXT and HIRC)
—
fSYS=HXT or HIRC
—
1024
MHz
tRSTD
System Reset Delay Time (LVR reset)
—
—
16
32
64
ms
tSRESET
Software Reset Width to Reset
—
—
45
90
120
μs
tHTO
HIRC Turn On Period
2.2V~5.5V HIRC OFF → ON
—
200
—
μs
tINT
External Interrupt Minimum Pulse Width
—
—
4
—
tSYS
tLVR
Low Voltage Width to Reset
—
120
240
480
μs
Rev. 1.00
MCU is in Normal mode or Idle
mode
25 of 226
—
May 15, 2013
A.C. Characteristics
fSYS1
Parameter
Test Conditions
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
10
ADC Electrical Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
A/D Converter Operating Voltage
VADI
A/D Converter Input Voltage
VREF
A/D Converter Reference Voltage
Conditions
—
—
—
—
2.7
—
VREF available
0
—
VREF
VREF not available
0
—
AVDD
—
—
DNL
Differential Non-linearity
—
AVDD=5V
VREF=AVDD
tADCK=1μs
INL
Integral Non-linearity
—
AVDD=5V
VREF=AVDD
tADCK =1μs
IADC
Additional Power Consumption if A/D Converter is used
3V
5V
tADCK
A/D Converter Clock Period
—
tADC
A/D Conversion Time (Include Sample and Hold Time)
—
tADS
A/D Converter Sampling Time
—
tON2ST
ADC on to ADC start
—
11
Min. Typ. Max. Unit
No load, tADCK=0.5μs
—
5.5
V
V
2
—
AVDD
V
-2
—
+2
LSB
-4
—
+4
LSB
—
1.00 1.40
mA
—
1.30 2.00
mA
0.5
—
10
μs
—
16
—
tADCK
—
—
4
—
tADCK
—
2
—
—
μs
12 bit ADC
DAC Electrical Characteristics
VDD=3V, AV+=3.0V, VREF=2.4V, no output load unless otherwise specified
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Static Performance
Resolution
—
Integral Nonlinearity
—
—
±2
—
LSB
Differential Nonlinearity
—
—
—
±1
LSB
12
bits
—
±3
±30
mV
Gain Error
—
—
±20
±60
mV
Output Sink Current
—
—
300
—
μA
—
15
—
mA
Offset Error
Output Short-Circuit Current
Rev. 1.00
Data Word=0x014
Data Word=0xFFF
26 of 226
May 15, 2013
ADC Electrical Characteristics
AVDD
VDD
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
12
Comparator Electrical Characteristics
Ta=25°C
Parameter
Symbol
Test Conditions
VDD
Conditions
—
Min. Typ.
Max.
Unit
—
5.5
V
LVDCR=00h, ADCR1=08h, i.e. select
5V internal bandgap voltage output (x2)
as VREFI
—
—
10
μA
Comparator power-down current
5V Comparator disable
—
—
0.1
μA
mV
Comparator operating voltage
—
—
Comparator operating current
—
VCMPOS
Comparator input offset voltage
5V
-10
—
+10
VHP1
Positive Hysteresis 1
5V CP(n)HP[1:0]=00b
—
—
0
1
mV
VHP2
Positive Hysteresis 2
5V CP(n)HP[1:0]=01b
3
6
10
mV
VHP3
Positive Hysteresis 3
5V CP(n)HP[1:0]=10b
6
13
20
mV
VHP4
Positive Hysteresis 4
5V CP(n)HP[1:0]=11b
12
25
40
mV
VHN1
Negative Hysteresis 1
5V CP(n)HN[1:0]=00b
—
0
1
mV
VHN2
Negative Hysteresis 2
5V CP(n)HN[1:0]=01b
3
6
10
mV
VHN3
Negative Hysteresis 3
5V CP(n)HN[1:0]=10b
6
13
20
mV
VHN4
Negative Hysteresis 4
5V CP(n)HN[1:0]=11b
12
25
40
mV
VCM
Comparator common mode voltage range —
—
VSS
—
VDD-1.4V
V
AOL
Comparator open loop gain
—
60
80
—
dB
tPD
Comparator response time
—
4
—
μs
—
3V
5V
With 100mV overdrive
Note: Measured with comparator one input pin at VCM=(VDD-1.4)/2 while the other pin input transition from VSS to
(VCM +100mV) or from VDD to (VCM -100mV).
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Comparator Electrical Characteristics
2.2
—
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
13
Power on Reset Electrical Characteristics
Ta=25°C
Symbol
Test Conditions
Parameter
VDD
Conditions
Min.
Typ.
Max.
Unit
VDD Start Voltage to ensure Power-on Reset
—
—
—
—
100
mV
RRPOR
VDD Rising Rate to ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD stays at VPOR to ensure
Power-on Reset
—
—
1
—
—
ms
14
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed
to their internal system architecture. The range of devices take advantage of the usual features
found within 8051-based microcontrollers providing increased speed of operation and enhanced
performance. The pipelining scheme is implemented in such a way that instruction fetching and
instruction execution are overlapped, hence most instructions are effectively executed in one clock
cycle, with the exception of branch or call instructions. Compared with classic MCU architecture,
the 8051-based core runs at a much higher speed and with greatly reduced power consumption. An
8-bit wide ALU is used in practically all operations of the 8051 compatible instruction set. It carries
out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc.
The internal data path is simplified by moving data through the Accumulator and the ALU. Certain
internal registers are implemented in the Data Memory and can be directly or indirectly addressed.
The simple addressing methods of these registers along with additional architectural features
ensure that a minimum of external components is required to provide a functional I/O control
system with maximum reliability and flexibility.
Rev. 1.00
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May 15, 2013
Power on Reset Electrical Characteristics
VPOR
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
15
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
next instruction to be executed. It is automatically incremented by one each time an instruction
is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a
non-consecutive Program Memory address.
16
Stack
This is a special part of the memory which is used to save the contents of the Program Counter
only. The stack is located in the 256 byte Data memory; therefore, the depth can be extended
up to 256 levels. The activated level is indexed by the Stack Pointer, SP, and is neither readable
nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program
Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by
a return instruction, RET or RETI, the Program Counter is restored to its previous value from the
stack. After a device reset, the Stack Pointer will point to the location 0x07, the top of the stack.
Note that if the data memory has been used as the stack area, it should not be used as general
purpose Data RAM.
P ro g ra m
T o p o f S ta c k
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
B o tto m
C o u n te r
S ta c k L e v e l 3
o f S ta c k
P ro g ra m
M e m o ry
S ta c k L e v e l 2 5 6
Stack Block Diagram
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded
but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or
RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer
to use the structure more easily. However, when the stack is full, a CALL subroutine instruction
can still be executed which will result in a stack overflow. Precautions should be taken to avoid
such cases which might cause unpredictable program branching.
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Program Counter
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control
by loading the required address into the Program Counter. For conditional skip instructions, once
the condition has been met, the next instruction, which has already been fetched during the present
instruction execution, is discarded and a dummy cycle takes its place while the correct instruction
is obtained.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
17
Arithmetic and Logic Unit – ALU
■■ Arithmetic operations: ADD, ADDC, SUBB, DA, MUL, DIV
■■ Logic operations: ANL, ORL, XRL, CLR, CPL
■■ Rotation: RL, RLC, RR, RRC, SWAP
■■ Increment and Decrement: INC, DEC
■■ Branch decision: JC, JNC, JB, JNB, JBC, ACALL, LCALL, RET, RETI, AJMP, SJMP, JMP, JZ,
JNZ, CJNE, DJNZ
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Arithmetic and Logic Unit – ALU
The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic
and logic operations of the instruction set. Connected to the main microcontroller data bus,
the ALU receives related instruction codes and performs the required arithmetic or logical
operations after which the result will be placed in the specified register. As these ALU calculation
or operations may result in carry, borrow or other status changes, the status register will be
correspondingly updated to reflect these changes. The ALU supports the following functions:
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
18
Flash Program Memory
Structure
The Program Memory has a capacity from 16K×8 to 64K×8. The Program Memory is addressed
by the Program Counter and also contains data, table information and interrupt entries. Table data,
which can be setup in any location within the Program Memory, is addressed by a separate table
pointer register.
Special Vectors
Within the Program Memory, certain locations are reserved for the reset and interrupts. The
location 000H is reserved for use by the device reset for program initialisation. After a device reset
is initiated, the program will jump to this location and begin execution.
HT85F2260
HT85F2270
HT85F2280
0000H
Reset
Reset
Reset
0003H
00ABH
Interrupt
Vector
Interrupt
Vector
Interrupt
Vector
3FFFH
8 bits
7FFFH
8 bits
FFFFH
8 bits
Program Memory Structure
Rev. 1.00
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May 15, 2013
Flash Program Memory
The Program Memory is the location where the user code or program is stored. For these devices
the Program Memory is Flash type, which means it can be programmed and re-programmed
a large number of times, allowing the user the convenience of code modification on the same
device. By using the appropriate programming tools, these Flash devices offer users the flexibility
to conveniently debug and develop their applications while also offering a means of field
programming and updating.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
In-Circuit Programming – ICP
The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows:
Holtek Writer Pins
MCU Programming Pins
ICPDA
P0.0/ICPDA
Function
ICPCK
RESET/ICPCK
VDD
VDD
Power Supply
VSS
VSS
Ground
Programming Serial Data/Address
Programming Serial Clock
The Program Memory can be programmed serially in-circuit using the interface on pins ICPDA
and ICPCK. Data is downloaded and uploaded serially on a single pin with an additional line for the
clock. Two additional lines are required for the power supply. The technical details regarding the
in-circuit programming of the device are beyond the scope of this document and will be supplied in
supplementary literature. The Flash Program Memory Read/Write function is implemented using a
series of registers.
On-Chip Debug Support – OCDS
An EV chip, HT85V2280, is provided which includes all the HT85F2280 functions as well as an
“On-Chip Debug” interface for emulation of the HT85F2280/2270/2260 devices. To minimise
the difference between the real IC (the volume-production version) and the EV chip (the device
with the debug interface), a protocol converter is implemented to translate the external 2-wire
connections (TCK and TDA) into 4 internal JTAG signals (TCK, TMS, TDI, and TDO) and vice
versa. Users can use the EV chip device to emulate the real chip device behavior by connecting
the TDA and TCK pins to the related Holtek development tools. The TDA pin is the OCDS
Data/Address input/output pin while the TCK pin is the OCDS clock input pin. When users use the
EV chip for debugging, other functions which are shared with the TDA and TCK pins in the actual
MCU device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared
with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For
a more detailed OCDS description, refer to the corresponding user’s guide.
Rev. 1.00
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Flash Program Memory
The provision of Flash type Program Memory provides the user with a means of convenient
and easy upgrades and modifications to their programs on the same device. As an additional
convenience, Holtek has provided a means of programming the microcontroller in-circuit using
a four-line serial interface. This provides manufacturers with the possibility of manufacturing
their circuit boards complete with a programmed or un-programmed microcontroller, and then
programming or upgrading the program at a later stage. This enables product manufacturers to
easily keep their manufactured products supplied with the latest program releases without removal
and re-insertion of the device.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
In-Application Programming – IAP
An In-Application Programming interface is provided to allow the end user’s application to erase
and reprogram the user code memory. No extra code memory block (bootloader) is required to
update the firmware or non-volatile data. Firmware for the IAP and the code memory to be updated
are physically on the same IP. Users could update firmware or non-volatile data except for the sector
where IAP is located and run. A firmware library is used to provide APIs for flash programming.
With regard to the Flash Program Memory registers, there are three address registers, one 8-bit
data register and three control registers, located in the Special Function Registers. Read and Write
operations to the Flash memory are carried out in 8-bit data operations using the address and data
registers and the control registers. The address registers are named FMAR0, FMAR1 and FMAR2,
the data register is named FMDR, and the three control registers are named FMKEY, FMCR
and FMSR. As these registers are located in Special Function Register area, they can be directly
accessed in the same was as any other Special Function Register.
Program Memory Register List
Name
Bit
7
6
5
4
3
2
1
0
FMAR0
FADDR7
FADDR6
FADDR5
FADDR4
FADDR3
FADDR2
FADDR1
FADDR0
FMAR1
FADDR15
FADDR14
FADDR13
FADDR12
FADDR11
FADDR10
FADDR9
FADDR8
FMAR2
INBLK
FADDR22
FADDR21
FADDR20
FADDR19
FADDR18
FADDR17
FADDR16
FMDR
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
FMKEY
FMKEY7
FMKEY6
FMKEY5
FMKEY4
FMKEY3
FMKEY2
FMKEY1
FMKEY0
FMCR
FMCR.7
FMCR.6
—
—
—
FMCR.2
FMCR.1
FMCR.0
FMSR
UNLOCK
—
—
—
FMPF
FMSEF
FMBF
FMBUSY
FMAR0 Register – Flash Program Memory Address Register 0
SFR Address: FAh
Bit
7
6
5
4
3
2
1
0
Name
FADDR7
FADDR6
FADDR5
FADDR4
FADDR3
FADDR2
FADDR1
FADDR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
Flash Program Memory address
Flash Program Memory address bit 7~bit 0
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Flash Program Memory
Flash Program Memory Resisters
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
FMAR1 Register – Flash Program Memory Address Register 1
SFR Address: FBh
Bit
7
6
5
4
3
2
1
0
Name
FADDR15
FADDR14
FADDR13
FADDR12
FADDR11
FADDR10
FADDR9
FADDR8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
FMAR2 Register – Flash Program Memory Address Register 2
SFR Address: FCh
Bit
7
6
5
4
3
2
1
0
Name
INBLK
FADDR22
FADDR21
FADDR20
FADDR19
FADDR18
FADDR17
FADDR16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6~0
INBLK: Flash memory access block selection
0: Main Flash program memory area
1: Information block area
Flash Program Memory address
Flash Program Memory address bit 22~bit 16
FMDR Register – Flash Program Memory Data Register
SFR Address: FDh
Bit
7
6
5
4
3
2
1
0
Name
FDAT7
FDAT6
FDAT5
FDAT4
FDAT3
FDAT2
FDAT1
FDAT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
Flash Program Memory Data register
Flash Program Memory Data bit 7~bit 0
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Flash Program Memory
Flash Program Memory address
Flash Program Memory address bit 15~bit 8
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
FMCR Register – Flash Program Memory Control Register
SFR Address: F8h
Bit
7
6
5
4
3
2
1
0
Name
FMCR.7
FMCR.6
—
—
—
FMCR.2
FMCR.1
FMCR.0
R/W
R/W
R/W
—
—
—
R/W
R/W
R/W
POR
0
1
—
—
—
0
0
0
Bit 7
Bit 5~3
Bit 2
Bit 1
Bit 0
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Flash Program Memory
Bit 6
FMCR.7: Flash Memory Read/Write/Erase enable control bit
0: Disable
1: Enable
As this bit is cleared automatically by hardware soon after a command is initiated, when
the MCU reads this bit it will always obtain a zero value.
FMCR.6: Flash Memory Byte Write/Page Erase control bit
0: For an un-written byte (0xFF) within a page, a write operation is allowed. But for
those written bytes (except for 0xFF), a re-write operation is prohibited to avoid
Flash errors. The writing time is shorter.
1: Before the main program executes a byte write operation, a page erase operation
is automatically executed. Any location within the page is then rewritable, but the
write time is longer. Note that the security bytes 00h~1Fh in the ID block page 0
can only be written once.
Unimplemented, read as “0”
FMCR.2: Flash Memory Page Erase control bit
0: Disable
1: Enable
This bit should be cleared manually.
FMCR.1: Flash Memory Byte Read control bit
0: Disable
1: Enable
This bit should be cleared manually.
FMCR.0: Flash Memory Byte Write control bit
0: Disable
1: Enable
This bit should be cleared manually.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
FMKEY Register – Flash Program Memory Unlock Key Data Register
SFR Address: F9h
Bit
7
6
5
4
3
2
1
0
Name
FMKEY7
FMKEY6
FMKEY5
FMKEY4
FMKEY3
FMKEY 2
FMKEY 1
FMKEY 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
FMSR Register – Flash Program Memory Status Register
SFR Address: E2h
Bit
7
6
5
4
3
2
1
0
Name
UNLOCK
—
—
—
FMPF
FMSEF
FMBF
FMBUSY
R/W
R
—
—
—
R
R
R
R
POR
0
—
—
—
0
0
0
0
Bit 7
Bit 6~4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
UNLOCK: Flash memory Control Registers Unlock flag
0: Indicated Flash Memory Controller is locked
1: Indicated Flash Memory Controller is unlocked
Unimplemented, read as “0”
FMPF: Flash Memory Controller Procedure flag
0: The Flash Memory Controller Procedure Flag is cleared to 0 if FMSEF=1,
or if FMBF=1 or if the IAP Procedure has ended.
1: Flash Memory Controller Procedure is corrected
FMSEF: Flash Memory Controller Security Error Flag
0: Manipulation of Flash Memory does not violate the security rules
1: Manipulation of Flash Memory violates the security rules
After a flash memory manipulation, this bit must be checked to determine if the Flash
Memory manipulation has violated the security rules or not.
FMBF: Flash Memory Controller Break Flag
0: Manipulation of Flash Memory does not violate the security rules or lock rules or
FMCR mode change
1: Manipulation of Flash Memory violates the security rules or lock rules or FMCR
mode change
FMBUSY: Flash Memory Controller Status indication bit
0: Not erasing or rewriting
1: Busy
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May 15, 2013
Flash Program Memory
Flash Memory Unlock Key Data register Unlock Data bits 7~bit 0
The FMKEY register is the Flash Memory Unlock key data register. If a correct key
data sequence has been written into this register, the Flash memory will release its
locked status; otherwise, the Flash memory will remain in its locked status. The correct
sequence to be written is 55H, AAH, 00H and then FFH. It is recommended to write
the key data sequence to the FMKEY register in four consecutive instructions. When
the program memory is in an unlocked status, writing any data to the FMKEY register
will result in the program memory being locked again. If there is no need to update the
program memory, it’s strongly recommended to lock the program memory at all times.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Flash Memory Read/Write Operations
The flash memory can be read from and written to using register operations. To ensure protection
of application data certain protection measures have to be first carried out before any read and
write operations are executed on the Flash Memory.
Unlocking the Flash Memory
START
Bit UNLOCK is 0
Flash memor� is in
locked state
F�KEY = 0x��;
F�KEY = 0xAA;
F�KEY = 0x00;
F�KEY = 0xFF;
For example� 4 consecutive
statements in C language
Bit UNLOCK is 1
Flash memor� is in
unlocked state
END
Unlock Procedure Flowchart
Rev. 1.00
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Flash Program Memory
Before writing data to the Flash Memory it must first be unlocked. This is implemented by writing
a correct data sequence to the Flash Memory Unlock key register, FMKEY. It is recommended
to write the data sequence to the FMKEY register in 4 consecutive instructions. The following
flowchart illustrates the unlock procedure.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Page Erase Operation
The Flash Memory must be first unlocked before implementing a page erase procedure. The
flash memory address is setup using the control registers, FMAR0, FMAR1 and FMAR2. The
Flash Memory Page Erase function is selected by the control bit, FMCR.2, in the FMCR register.
Setting the FMCR.7 bit high will start the Page Erase procedure. When the procedure has finished,
the MCU will continue to run automatically. The following flowchart illustrates the Page Erase
procedure.
Flash Program Memory
Flash memory controller must be
In unlocked state
START
FMCR Bit 2 = 1
Write FMAR2
Write FMAR1
Write FMAR0
FMCR Bit 7 = 1
This will trigger page-erasing action
Check FMSR Bit 1 = 1
Yes
No
MCU waits for page-erasing finished.
Then MCU continues to run.
END
Page Erase Flowchart
Rev. 1.00
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Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Byte Read Operation
The Flash memory must be first unlocked before implementing a byte read procedure. The flash
memory address is setup using the control registers, FMAR0, FMAR1 and FMAR2. The Flash
Memory Page Read function is selected by the control bit, FMCR.1, in the FMCR register. When
the FMCR.7 bit is set high the Byte Read procedure will be initiated. When the procedure is ready,
the MCU will continue to run automatically. The following flowchart illustrates the Byte Read
procedure.
Flash Program Memory
Flash memory controller must be
In unlocked state
START
FMCR Bit 1 = 1
Write FMAR2
Write FMAR1
Write FMAR0
FMCR Bit 7 = 1
This will trigger byte-reading action
Check FMSR Bit 1 = 1
Yes
No
Read FMDR
No
End Reading
Yes
END
Byte Read Flowchart
Rev. 1.00
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May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Byte Write Operation
START
Flash memory controller
must be In unlocked state
FMCR Bit 0 = 1 and
FMCR Bit 6 = 0 (*)
Write FMAR2
Write FMAR1
Write FMAR0
Update the Page Buffer
By writing FMDR
Enter memory
dump procedure
MCU waits for memory
dump finished and then
MCU continues to run.
Yes
FMARx reach the
page boundary?
No
More Data?
Yes
No
FMCR Bit 7 = 1
Yes
Check FMSR Bit 1 = 1
No
MCU waits for byte-writing
finished and then
MCU continues to run.
Write next page
if desired
Byte Write Flowchart (FMCR.0=1, FMCR.6=0)
Rev. 1.00
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Flash Program Memory
The Flash Memory must be first unlocked before implementing a Byte Write procedure. The first
step is to assign the target memory page and erase it. Refer to the Page Erase Operation section
for details. The Flash Memory Byte Write function is controlled by the control bits, FMCR.0 and
FMCR.6, in the FMCR register. Data is first written into the FMDR register to update the Page
Buffer. The Flash memory will check if the memory address has reached the page boundary. If the
boundary has been reached or there is no more data, then set the FMCR.0 bit to high to enable the
Byte Write function. When the FMCR.7 bit is set high the Byte Write procedure will be executed.
When the procedure is ready, the MCU will continue to run automatically. The following flowchart
illustrates the Byte Write procedure.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
START
Flash memory controller
must be In unlocked state
FMCR Bit 0 = 1 and
FMCR Bit 6 = 1 (*)
Flash Program Memory
Write FMAR2
Write FMAR1
Write FMAR0
Update the Page Buffer
By writing FMDR
Enter memory
dump procedure
MCU waits for memory
dump finished and then
MCU continues to run.
Yes
FMARx reach the
page boundary?
No
More Data?
Yes
No
FMCR Bit 7 = 1
Yes
Check FMSR Bit 1 = 1
No
MCU waits for byte-writing
finished and then
MCU continues to run.
Write next page
if desired
Byte Write Flowchart (FMCR.0=1, FMCR.6=1)
Rev. 1.00
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May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Program Memory Protection
Memory Protection Control Bytes
The protection of program code memory is categorised to two types: Security Type 1 and Security
Type 2.
■■ Security Type 1
For the HT85F2280 device, the inhibit bytes SECURITY1[0:15] are located at the address
0x00~0x0F of the ID block page 0. If a value, with the exception of 0FFH, is written into these
bytes, the sectors corresponding to SECURITY1[0:15] cannot be programmed, erased or read by
the ICP. For the IAP program, when in the OCDS mode, any sector N with a security mechanism
can be protected from being programmed, erased or read by the OCDSINSTR instruction. But
when in the main program, all sector N with security or not, can be programmed, erased or read
by the IAP. For the MOVC instructions, any sector N with security mechanism cannot be read by
the ocdsinstr instruction when in the OCDS mode, but still can be read by MOVC instructions
when in the main program. Since these bytes can only be written once, to release the respective
sectors in the unprotected mode, the device must be erased.
The following table illustrates the protection status when in the OCDS/ICP/IAP/MOVC modes
when the SECURITY1[0:15] bytes are written with a value other than 0FFH:
SECURITY1[N]
N=0~15
ICP
IAP
M
O
V
C
Program
Erase
Read
Protect
Sector #
Remove
Protection
X
X
N/A(1)
N
Erase All
OCDS(5)
X(3)
X
X(4)
N
Erase All
Main Program
O(3)
O
O
N
Erase All
OCDS(5)
N/A(2)
X(4)
N
Erase All
Main Program
N/A(2)
O
N
Erase All
Note: (1) “N/A” means no path to read ROM code.
(2) “N/A” means none of these functions.
(3) “X” stands for inhibited; “O” stands for enabled.
(4) If a read operation is inhibited, reading the Flash will return a fixed Flash code of 00H.
(5) When in the OCDS mode, only the OCDSINSTR instruction has the security protection
mechanism.
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Flash Program Memory
The flash program memory is partitioned into 2 memory blocks. One is the main memory block
and the other is the ID block. The ID block size is 256 bytes and is used to setup the protected
sectors. This memory protection function is used to protect the Program Memory from improper
Program, Erase or Read operations. The flash program memory is divided into several sectors
related to the memory size. Each sector has a capacity of 4K bytes. The memory protection
function is implemented by register control. If a value, with the exception of 0FFH, is written into
the corresponding control register, the corresponding sector program memory protection function
will be enabled. This program memory sector will then be unable to be programmed, erased or read
by corresponding instructions. In this way, the user can select which block of the flash memory is
to be protected.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
SECURITY2[N]
N=0~15
ICP
IAP
M
O
V
C
OCDS(5)
Main Program
OCDS
(5)
Main Program
Program
Erase
Read
Protect
Sector #
Remove
Protection
X
X
N/A(1)
N
Erase All
X(3)
X
X(4)
N
Erase All
X
X
X
N
Erase All
N/A
(4)
X
N
Erase All
N/A(2)
X(4)
N
Erase All
(3)
(2)
(4)
Note: (1) “N/A” means no path to read ROM code.
(2) “N/A” means none of these functions.
(3) “X” stands for inhibited; “O” stands for enabled.
(4) If a read operation is inhibited, reading to the Flash will return a fixed Flash code of 00H.
(5) When in the OCDS mode, only the OCDSINSTR instruction has the security protection
mechanism.
The following tables illustrate the corresponding address ID sectors and the inhibited bytes.
HT85F2260 Program Memory Contents
The HT85F2260 program memory is divided into 4 sectors, each with a capacity of 4k bytes.
Page
Address
0x00~0x03
0
1
Rev. 1.00
Description
SECURITY1[0]~SECURITY1[3]
0x04~0x0F
Not used
0x10~0x13
SECURITY2[0]~SECURITY2[3]
0x14~0x1F
Not used
0x20~0x6F
Reserved
0x70~0x7F
Reserved
0x80~0x83
Reserved
0x84~0x8F
Reserved
0x90~0x93
Reserved
0x94~0x9F
Reserved
0xA0~0xEF
Reserved
0xF0~0xFF
Reserved
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Flash Program Memory
■■ Security Type 2
For the HT85F2280 device, the inhibit bytes SECURITY2[0:15] are located at the addresses
0x10~0x1F of the ID block page 0. If a value, with the exception of 0FFH, is written into these
bytes, the sectors corresponding to SECURITY2[0:15] cannot be programmed, erased or read
when in any mode. Since these bytes can only be written once, to release the respective sectors
in the unprotected mode, the device must be erased.
The following table illustrates the protection state in the OCDS/ICP/IAP/MOVC modes when
the SECURITY2[0:15] bytes are written with a value other than 0FFH:
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
HT85F2270 Program Memory Contents
The HT85F2270 program memory is divided into 8 sectors, each with a capacity of 4k bytes.
Page
Address
0
SECURITY1[0]~SECURITY1[7]
0x08~0x0F
Not used
0x10~0x17
SECURITY2[0]~SECURITY2[7]
0x18~0x1F
Not used
0x20~0x6F
Reserved
0x70~0x7F
Reserved
0x80~0x87
Reserved
0x88~0x8F
Reserved
0x90~0x97
Reserved
0x98~0x9F
Reserved
0xA0~0xEF
Reserved
0xF0~0xFF
Reserved
Flash Program Memory
1
Description
0x00~0x07
HT85F2280 Program Memory Contents
The HT85F2280 program memory is divided into 16 sectors, each with a capacity of 4k bytes.
Page
Address
0
1
Description
0x00~0x0F
SECURITY1[0]~SECURITY1[15]
0x10~0x1F
SECURITY2[0]~SECURITY2[15]
0x20~0x6F
Reserved
0x70~0x7F
Reserved
0x80~0x8F
Reserved
0x90~0x9F
Reserved
0xA0~0xEF
Reserved
0xF0~0xFF
Reserved
Security Bytes
Name
Description
SECURITY1[N]
Sector N Program/Erase Inhibited Bytes
0xFF: unprotected
Else: protected
SECURITY2[N]
Sector N Access Inhibited Bytes
0xFF: unprotected
Else: protected
Note: N=0~15
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Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
These two types of flash memory inhibited bytes, SECURITY1[N] and SECURITY2[N], are used
for Program Memory protection. However, the SECURITY2[N] bytes have the higher priority. If
data has be written to the SECURITY2[N] bytes, the corresponding sectors will be protected and
cannot be read from or written to, no matter what data is in the SECURITY1[N] bytes. Note that
the Flash Memory protect function will not affect the instruction fetched by the MCU core. The
accompanying table illustrates the inhibited bytes priority.
SECURITY2[N] SECURITY1[N]
0FFH
Other values
except 0FFH
0FFH
Program Sector N is not protected
Can be erased and programmed.
Can be read by flash control registers related to the IAP and OCDS(note) and
the MOVC instructions.
Other values
except 0FFH
Sector N is inhibited from Programming/Erasing
Can not be erased and programmed by the ICP or flash control registers
related to the OCDS(note).
Can be erased and programmed by flash control registers related to the IAP.
Can be read by flash control registers related to the IAP and the MOVC
instructions.
X
Sector N is inhibited from Programming/Erasing/Accessing (instruction fetch
is still allowed)
Can not be erased and programmed by the ICP or flash control registers
related to the IAP and OCDS(note).
Can not be read by the ICP or flash control registers related to the IAP and
OCDS(note) and the MOVC instructions.
Note: Here “OCDS” stands for executing OCDSINSTR instruction when in the OCDS mode.
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Flash Program Memory
0FFH
Privilege
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
19
RAM Data Memory
Structure
The Data Memory is subdivided into two blocks, Internal Data RAM (IDATA) and On-Chip
External Data RAM (XDATA), which are implemented in 8-bit wide RAM. The IDATA is
subdivided into two sections, known as the Upper section and the Lower section. The Upper section
includes two blocks, the Special Function Registers, SFR, and the 128-byte General Purpose RAM.
The Special Function Register can be accessed using direct addressing methods while the 128-byte
General Purpose RAM must be accessed using indirect addressing methods.
The upper section 128-byte RAM has an address range of 80H to FFH, and is assigned to both
the General Purpose memory and the Special Function Registers. Although the address range is
identical these two RAM sections are physically separate, they are distinguished by their different
addressing methodology. Using direct addressing instructions will point to the SFR registers while
indirect addressing instructions will point to the upper 128-byte General Purpose RAM.
The lower section 128-byte RAM is dedicated to the General Purpose RAM, and consists of an
80-byte General Purpose RAM section, four 8-byte register banks and 16-bytes of Bit-Addressable
Space. The lower section can be accessed both by Indirect and Direct addressing methods. The
16-byte Bit-Addressable Space, which can be addressed by both byte format and 128 bit location
format, is located from at the address range, 20H to 2FH. The four register banks, each of which
contains eight bytes of general purpose registers, are located at the address range 00H to 1FH.
The XDATA is assigned as General Purpose Data RAM and can only be accessed using indirect
addressing. The HT85F2270 and HT85F2280 have 2048-bytes of XDATA while the HT85F2260
has 1024-bytes of XDATA.
Note that the internal data memory is also used as a software stack. The designer must initiate the
stack pointer register, namely SP, in the application program.
The following diagram illustrates the memory structure and their various access methods.
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RAM Data Memory
The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where
temporary information is stored. Divided into several sections, the first of these is an area of RAM
where special function registers are located. These registers have fixed locations and are necessary
for correct operation of the devices. Many of these registers can be read and written to directly
under program control, however, some remain protected from user manipulation. The second area
of Data Memory is reserved for general purpose use. All locations within this area are read and
write accessible under program control. The Data Memory also includes the Bit-Addressable Space
and four Register Banks.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
FFH
…
…
…
80H
…
7FH…
…
30H
Lower
Section
(128 bytes)
20H
18H
10H
08H
00H
Upper 128 Bytes
General Purpose RAM
(Indirect Access)
Special Function Registers
(Direct Access)
RAM Data Memory
Upper
Section
(128 bytes)
Lower 80 Bytes
General Purpose RAM
Bit-Addressable Space
Both direct and
indirect access
Register Bank 3
Register Bank 2
Register Bank 1
Register Bank 0
8-bit
Internal Data Memory Structure
Rev. 1.00
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Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
FFFFH
RAM Data Memory
(RESERVED)
0800H
07FFH
…
…
RAM (2048 bytes)
0000H
8-bit
HT85F2270/HT85F2280 XDATA
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Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
FFFFH
RAM Data Memory
(RESERVED)
0400H
03FFH
…
…
RAM (1024 bytes)
0000H
8-bit
HT85F2260 XDATA
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May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Register Banks
There are four register banks, with addresses from 00H to 1FH, with each bank containing eight
bytes. The active bank is selected by the control bits, RS1 and RS0, in the PSW register. It should
be noted that only one bank can be enabled at any time. This total of 32 bytes are used as General
Purpose data memory, which can be accessed by either direct or indirect instructions.
Some instructions in the 8051 language allow for single bit addressing. These single bit instructions
can only be used in the bit addressable data memory area, located both in the General Purpose Data
RAM and the Special Function Register area. Note that these bit addressable registers are both byte
and bit addressable.
The 16 bytes bit addressable registers of the General Purpose Data RAM, located from 20H to
2FH, can address up to 128 individual bits. Each bit has its corresponding bit address from 00H
to 7FH. For example, bit 0 of the 20H register is mapped to the bit address 00H, bit 7 of the 20H
register is mapped to the bit address 07H and bit 7 of the 2FH register is mapped to the bit address
7FH. The accompanying table illustrates the Bit-Addressable register map description for General
Purpose Data RAM, 20H~2FH. Using the bit operational instruction, such as SETB or CLR on the
bit address can implement operations on the corresponding bit of the register. For example:
SETB 00H
SETB 07H
CLR 25H
CLR 7FH
;
;
;
;
Set the bit 0
Set the bit 7
Clear the bit
Clear the bit
of the register location 20H to “1”
of the register location 20H to “1”
5 of the register location 24H to “0”
7 of the register location 2FH to “0”
General Purpose Data RAM, 20H~2FH, Bit Address Map
Rev. 1.00
Low 3-bit Address
High 5-bit
Address
0H
1H
2H
3H
4H
5H
6H
7H
78H
0x2F.0
0x2F.1
0x2F.2
0x2F.3
0x2F.4
0x2F.5
0x2F.6
0x2F.7
70H
0x2E.0
0x2E.1
0x2E.2
0x2E.3
0x2E.4
0x2E.5
0x2E.6
0x2E.7
68H
0x2D.0
0x2D.1
0x2D.2
0x2D.3
0x2D.4
0x2D.5
0x2D.6
0x2D.7
60H
0x2C.0
0x2C.1
0x2C.2
0x2C.3
0x2C.4
0x2C.5
0x2C.6
0x2C.7
58H
0x2B.0
0x2B.1
0x2B.2
0x2B.3
0x2B.4
0x2B.5
0x2B.6
0x2B.7
50H
0x2A.0
0x2A.1
0x2A.2
0x2A.3
0x2A.4
0x2A.5
0x2A.6
0x2A.7
48H
0x29.0
0x29.1
0x29.2
0x29.3
0x29.4
0x29.5
0x29.6
0x29.7
40H
0x28.0
0x28.1
0x28.2
0x28.3
0x28.4
0x28.5
0x28.6
0x28.7
38H
0x27.0
0x27.1
0x27.2
0x27.3
0x27.4
0x27.5
0x27.6
0x27.7
30H
0x26.0
0x26.1
0x26.2
0x26.3
0x26.4
0x26.5
0x26.6
0x26.7
28H
0x25.0
0x25.1
0x25.2
0x25.3
0x25.4
0x25.5
0x25.6
0x25.7
20H
0x24.0
0x24.1
0x24.2
0x24.3
0x24.4
0x24.5
0x24.6
0x24.7
18H
0x23.0
0x23.1
0x23.2
0x23.3
0x23.4
0x23.5
0x23.6
0x23.7
10H
0x22.0
0x22.1
0x22.2
0x22.3
0x22.4
0x22.5
0x22.6
0x22.7
08H
0x21.0
0x21.1
0x21.2
0x21.3
0x21.4
0x21.5
0x21.6
0x21.7
00H
0x20.0
0x20.1
0x20.2
0x20.3
0x20.4
0x20.5
0x20.6
0x20.7
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RAM Data Memory
Bit Addressable Space
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
There are also 16 bytes of bit addressable registers located in the SFR which are both byte and bit
addressable. These bit addressable registers in the SFR are registers whose addresses end with the
low 3-bit address of “000b”, such as 80h, 88h, 90h…F8h, etc. The accompanying table illustrates
the Bit-Addressable registers in the SFR. Using special instructions, such as SETB and CLR, can
implement operations on the individual bit. For example:
SETB
CLR
ACC.3
ACC.3
; Set the bit 3 of the ACC register to “1”
; Clear the bit 3 of the ACC register to “0”
Low 3-bit Address
High 5-bit
Address
0H
1H
2H
3H
4H
5H
6H
7H
F8h
FMCR.0
FMCR.1
FMCR.2
—
—
—
FMCR.6
FMCR.7
F0h
B.0
B.1
B.2
B.3
B.4
B.5
B.6
B.7
E8h
SPCON.0
SPCON.1
SPCON.2
SPCON.3
SPCON.4
SPCON.5
SPCON.6
SPCON.7
ACC.2
ACC.3
ACC.4
ACC.5
ACC.6
ACC.7
E0h
ACC.0
ACC.1
D8h
—
—
D0h
PSW.0
PSW.1
PSW.2
PSW.3
PSW.4
PSW.5
PSW.6
I2CCON.2 I2CCON.3 I2CCON.4 I2CCON.5 I2CCON.6
—
PSW.7
C8h
T2CON.0
T2CON.1
T2CON.2
T2CON.3
T2CON.4
T2CON.5
T2CON.6
—
C0h
—
IRCON.1
IRCON.2
IRCON.3
IRCON.4
IRCON.5
IRCON.6
IRCON.7
B8h
IP0.0
IP0.1
IP0.2
IP0.3
IP0.4
IP0.5
IP0.6
—
B0h
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
A8h
IEN0.0
IEN0.1
IEN0.2
IEN0.3
IEN0.4
IEN0.5
IEN0.6
IEN0.7
A0h
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
98h
S0CON.0
S0CON.1
S0CON.2
S0CON.3
S0CON.4
S0CON.5
S0CON.6
S0CON.7
90h
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
88h
TCON.0
TCON.1
TCON.2
TCON.3
TCON.4
TCON.5
TCON.6
TCON.7
80h
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
Notes: 1. address in this table is “bit address”
2. “—” is stand for unimplemented
Rev. 1.00
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RAM Data Memory
Special Function Register Bit Addresses Map
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Special Function Registers
Special Function Register Map
Low 3-bit Address
High 5-bit
Address
0H
1H
2H
3H
4H
5H
6H
7H
F8h
FMCR
FMKEY
FMAR0
FMAR1
FMAR2
FMDR
T2CON1
RSTSRC
F0h
B
ADCR0
ADCR1
ADCR2
ADPGA
ADRL
ADRH
SRST
E8h
SPCON
I2CLK
LVRCR
LVDCR
SCCR
PLLCR
LSOCR
HSOCR
E0h
ACC
SPSTA
FMSR
SPDAT
IP1
IP1H
IP2
IP2H
D8h
I2CCON
P5
I2CDAT
I2CADR
SBRCON
I2CSTA
CP0CR
CP1CR
D0h
PSW
—
—
—
—
—
—
—
C8h
T2CON
IEN3
CRCL
CRCH
TL2
TH2
IP3
IP3H
C0h
IRCON
CCEN
CCL1
CCH1
CCL2
CCH2
CCL3
CCH3
B8h
IP0
IP0H
S0RELH
S1RELH
—
CPHCR
CPICR
IRCON2
B0h
P3
P4
TBCR
DACTRL
DAL
DAH
P3M0
P3M1
A8h
IEN0
IEN1
S0RELL
—
—
—
P2M0
P2M1
A0h
P2
T3CON
TL3
TH3
SRCR
SPPRE
P1M0
P1M1
98h
S0CON
S0BUF
IEN2
S1CON
S1BUF
S1RELL
P0M0
P0M1
90h
P1
P0WAKE
DPS
DPC
—
—
WDTCR
—
88h
TCON
TMOD
TL0
TL1
TH0
TH1
—
TMPRE
80h
P0
SP
DPL
DPH
DPL1
DPH1
WDTREL
PCON
Notes: “—“: unimplemented
Most of the Special Function Registers will be described in detail under the function that they
are related to. In this section a register description is provided for those registers which are not
described elsewhere.
Rev. 1.00
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RAM Data Memory
To ensure successful operation of the microcontroller, certain internal registers, known as Special
Function Registers or SFRs for short, are implemented in the Data Memory area. These registers
ensure correct operation of internal functions such as timers, interrupts, etc., as well as external
functions such as I/O data control. The SFRs are located at the address range 80H to FFH in
the upper section and are addressed directly. All can be addressed by byte but some are also
bit-addressable. The following table shows the SFR register list. Note that some of the registers are
defined by standard 8051 protocol while others are defined by Holtek.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
ACC Register – Accumulator
B Register
The B register is used as a general purpose register for these devices. It is used during multiplying
and division instructions.
SP Register – Stack Pointer
The Stack Pointer register is 8 bits wide. It denotes the top of the Stack, which is the last used
value. The user can place the Stack anywhere in the internal scratchpad Data Memory by setting
the Stack Pointer to the desired location, although the lower bytes are normally used for working
registers. After a reset, the Stack Pointer is initialised to 07H. This causes the stack to begin at
location 08H. It is used to store the return address of the main program before executing interrupt
routines or subprograms. The SP is incremented before executing a PUSH or CALL instruction and
it is decremented after executing a POP, RET or RETI instruction.
DPL, DPH, DPL1, DPH1 Registers – Data Pointer Registers
The Data Pointer (DPTR) registers, DPL, DPH, DPL1 and DPH1, although having their locations
in normal Data Memory register space, do not actually physically exist as normal registers.
Indirect addressing instructions for Data Memory data manipulation use these Indirect Addressing
Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory
address is specified. Actions on the DPTR registers will result in no actual read or write operation
to these registers but rather to the memory location specified by their corresponding Memory
Pointer for the MOVX, MOVC or JMP instructions. The DPTR registers can be operated as two
16-bit registers or four individual 8-bit registers. There are two sets of 16-bit Data Pointer register:
DPTR1 and DPTR. The DPTR register is composed of DPL and DPH, while the DPTR1 register
is composed of DPL1 and DPH1. They are generally used to access external code or data space
using instructions such as MOVC A,@A+DPTR or MOVX A,@DPTR respectively. The selection
of DPTR or DPTR1 is controlled by the DPS0 bit. Setting the DPS0 bit high will select the DPTR1
register, otherwise the DPTR register is selected.
DPTR
DPH
DPL
0
DPTR1
DPH1
DPL1
1
DPS0
Data Memory
DPTRn Registers Control Block Diagram
Rev. 1.00
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May 15, 2013
RAM Data Memory
The Accumulator is central to the operation of any microcontroller and is closely related with
operations carried out by the ALU. The Accumulator is the place where all intermediate results
from the ALU are stored. Without the Accumulator it would be necessary to write the result of
each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads. Data transfer operations usually involve
the temporary storage function of the Accumulator; for example, when transferring data between
one user-defined register and another, it is necessary to do this by passing the data through the
Accumulator as no direct transfer between two registers is permitted.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Data Pointer Select Registers
The devices contain up to two data pointers, depending on configuration. Each of these registers
can be used as 16-bits address source for indirect addressing. The DPS register serves to select the
active data pointer register.
DPS Register – Data Pointer Select Register
SFR Address: 92h
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
DPS0
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Bit 0
Unimplemented, read as “0”
DPS0: Data Pointer Register select
0: DPTR selected
1: DPTR1 selected
This bit is used to determine if the accessing addresses are sourced from either DPTR or
DPTR1 when executing Read and Write instructions.
Data Pointer Control Register
This register is used to control whether the DPTR auto-increment/auto-decrement has a value
of either 1 or 2, and auto-switching between active DPTRs functions. The auto-switching active
DPTR function is controlled by the DPC3 bit in the DPC register. The content of this bit will be
loaded to the DPS register after a MOVX @ DPTR instruction is executed. The auto-modification
function is controlled by the DPC0 bit. When this bit is enabled, the current DPTR can be
automatically increased or decreased by 1 or 2 positions selected by the DPC1 and DPC2 bits.
There are separate DPC register controls for each DPTR, to provide flexibility during data transfer
operations. The actual DPC register is selected using the DPS register. If the DPS0 bit is set high,
then DPTR1 is selected, and the DPC register is used as the DPTR1 control register. If the DPS0 bit
is cleared to zero, the DPTR is selected, and the DPC register is used as the DPTR control register.
Rev. 1.00
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RAM Data Memory
Bit
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
DPC Register – Data Pointer Control Register
SFR Address: 93h
Bit
6
5
4
3
2
1
0
Name
—
—
—
—
DPC3
DPC2
DPC1
DPC0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 2
Bit 1
Bit 0
Unimplemented, read as “0”
DPC3: Next Data Pointer select
The content of this bit will be loaded to the “DPS” register after each MOVX @DPTR
instruction is executed.
Note that this feature is always enabled, therefore for each of the “DPC” register this
field has to contain a different value pointing to itself so that the auto-switching does
not occur with default (reset) values.
DPC2: Auto-modification size
0: Modified size by 1
1: Modified size by 2
The current DPTR will be automatically modified by size, selected by the DPC2 bit,
after each MOVX @DPTR instruction when DPC0=1.
DPC1: the current DPTR Auto-modification direction
0: Automatically incremented
1: Automatically decremented
The current DPTR will be automatically decremented or incremented, selected by the
DPC1 bit, after each MOVX @DPTR instruction when DPC0=1.
DPC0: Auto-modification control bit
0: Disable
1: Enable
When this bit is set to high, enables auto-modification of the current DPTR after each
MOVX @DPTR instruction.
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RAM Data Memory
Bit 7~4
Bit 3
Rev. 1.00
7
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Program Status Word
This register contains the Parity flag (P), General purpose flag 1 (F1), overflow flag (OV), Register
bank select control bits (RS0, RS1), General purpose flag 0 (F0), Auxiliary Carry flag (AC) and
Carry flag (CY). These arithmetic/logical operation and system management flags are used to
record the status and operation of the microcontroller. Note that the Parity bit can only be modified
by hardware depending upon the ACC state.
Bit
7
6
5
4
3
2
1
0
Name
CY
AC
F0
RS1
RS0
OV
F1
P
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4~3
Bit 2
Bit 1
Bit 0
Rev. 1.00
CY: Carry flag
0: No carry-out
1: An operation results in a carry during arithmetic operations and accumulator for
Boolean operations.
AC: Auxiliary flag
0: No auxiliary carry
1: An operation results in a carry out of the low nibbles in addition, or no borrow
from the high nibble into the low nibble on subtraction.
F0: General Purpose Flag 0
This bit is used as a general purpose flag by the application program.
RS1~RS0: Select Data Memory Banks
00: Bank 0
01: Bank 1
10: Bank 2
11: Bank 3
RS1
RS0
Selected Register Bank
0
0
Bank 0
Locations (within Internal Data Area)
00H – 07H
0
1
Bank 1
08H – 0FH
1
0
Bank 2
10H – 17H
1
1
Bank 3
18H – 1FH
OV: Overflow flag
0: No overflow
1: An operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit or vice versa.
F1: General Purpose Flag 1
This bit is used as a general purpose flag by the application program.
P: Parity flag
0: Accumulator contains an even number of ‘1’s
1: Accumulator contains an odd number of ‘1’s
This bit is used to indicate the number of ‘1’s in the Accumulator.
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RAM Data Memory
PSW Register – Program Status Word Register
SFR Address: D0h
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
20
Oscillators
Various oscillator options offer the user a wide range of functions according to their various
application requirements. The flexible features of the oscillator functions ensure that the best
optimisation can be achieved in terms of speed and power saving. Oscillator selections and
operation are selected using internal registers.
In addition to being the source of the main system clock the oscillators also provide clock sources
for the Watchdog Timer and Time Base functions. External oscillators requiring some external
components as well as two fully integrated internal oscillators, requiring no external components,
are provided to form a wide range of both fast and slow system oscillators. After a reset occurs the
HIRC oscillator is selected as the initial system clock but can be later switched by the application
program using the clock control register.
Type
Name
Function
Freq.
Pins
External High Speed Crystal
HXT
Precision High Speed System Clock
400kHz~24MHz
OSC1/OSC2
Internal High Speed RC
HIRC High Speed System Clock
3.6864MHz
—
32768Hz
XT1/XT2
32kHz
—
External Low Speed Crystal
LXT
Internal Low Speed RC
LIRC WDT and Time Base Clock
Precision WDT and Time Base Clock
System Clock Configuration
There are four oscillators, two high speed oscillators and two low speed oscillators. The high speed
oscillators are the external crystal, HXT, and the internal RC oscillator, HIRC, which are used as
the system oscillators. The two low speed oscillators are the external 32768Hz oscillator, LXT,
and the internal 32kHz RC oscillator, LIRC, which are used as peripheral clocks for the Watchdog
Timer and Time Base functions.
External High Speed Crystal Oscillator – HXT
The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and
feedback for oscillation. However, for some crystals and most resonator types, to ensure oscillation
and accurate frequency generation, it is necessary to add two small value external capacitors,
C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or
resonator manufacturer’s specification. The external crystal frequency can be multiplied from 1
to 8 times using the internal PLL. For example, if a 4MHz crystal is used for oscillator and if the
PLL is selected as 8 times, the system clock can be increased to 32MHz. Note that if the internal
PLL is enabled, the external crystal frequency should be fixed at 4MHz; otherwise, an unexpected
frequency will be generated. When the internal PLL function is not to be used, the external crystal
frequency can be within the range, from 400kHz to 24MHz.
Rev. 1.00
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Oscillators
System Oscillator Overview
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Oscillators
Crystal/Resonator Oscillator – HXT
Crystal Recommended Capacitor Values
Crystal Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
24MHz
10pF
10pF
12MHz
10pF
10pF
8 MHz
10pF
10pF
4 MHz
20pF
20pF
400kHz
300pF
300pF
Note: C1 and C2 values are for guidance only.
Internal High Speed RC Oscillator – HIRC
The internal RC oscillator is a fully integrated system oscillator requiring no external components.
The internal RC oscillator has a single frequency of 3.6864MHz. Device trimming during the
manufacturing process and the inclusion of internal frequency compensation circuits are used to
ensure that the influence of the power supply voltage, temperature and process variations on the
oscillation frequency are minimised. The internal RC oscillator frequency can be multiplied from
1 to 8 times using the internal PLL. If the HIRC oscillator is used as the system oscillator, then the
OSC1 and OSC2 pins should be left unconnected.
External Low Speed Crystal Oscillator – LXT
The external low speed crystal oscillator, LXT, is used as the clock source for the Watchdog Timer
and the Time Base functions. When the microcontroller enters the IDLE Mode, the CPU clock is
switched off to stop microcontroller activity and to conserve power, however the LXT oscillator
will continue to run and can maintain WDT and Time Base operation if it is selected as their clock
source. The LXT oscillator is implemented using a 32768Hz crystal connected to pins XT1/XT2.
However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary
to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be
selected in consultation with the crystal or resonator manufacturer’s specification.
Rev. 1.00
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May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Oscillators
External LXT Oscillator – LXT
32768Hz Crystal Recommended Capacitor Values
LXT Oscillator C1 and C2 Values
Crystal Frequency
C1
C2
32768Hz
10pF
10pF
Note: C1 and C2 values are for guidance only.
Internal Low Speed RC Oscillator – LIRC
The internal low speed oscillator, LIRC, is a fully self-contained free running on-chip RC
oscillator, used as a clock source for the Watchdog Timer and the Time Base functions. When
the microcontroller enters the IDLE Mode, the CPU clock is switched off to stop microcontroller
activity and to conserve power, however the LIRC oscillator will continue to run and can maintain
WDT and Time Base operation if it is selected as their clock source. The LIRC oscillator has
a typical frequency of 32kHz at 5V and requires no external components, however its actual
frequency may vary with temperature and supply voltage. For precise low speed oscillator
functions the LXT oscillator should be used.
Rev. 1.00
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May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
21
Operating Modes and System Clocks
Present day applications require that their microcontrollers have high performance but often still
demand that they consume as little power as possible, conflicting requirements that are especially
important in battery powered portable applications. This usually requires the microcontroller can
provide a range of clock sources which can be dynamically selected.
The fast clocks required for high performance will inherently have a higher power consumption
and of course vice-versa, lower speed clocks will have a lower power consumption. As Holtek has
provided these devices with a range of oscillators and a PLL function the user can optimise the
system clock frequency to achieve the best performance/power ratio. In addition to the two high
frequency system oscillators, two low frequency 32kHz oscillators are also provided as clock
sources for the WDT and Time Base.
The MCU system clock is sourced from the high speed external crystal, HXT oscillator, or internal,
HIRC oscillator. These oscillators can be used directly as the system clock and can be routed via an
internal PLL to give a wide range of operating frequencies. The PLL frequency can be dynamically
changed to suit varying operating conditions and to achieve maximum performance.
The system clock, namely f SYS, can also be used as a clock source for the peripheral functions, such
as WDT, Time Base, Timers, UART, I2C, SPI, ADC and DAC. Refer to the related sections for the
clock source selections.
Rev. 1.00
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Operating Modes and System Clocks
System Clocks Description
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
External
Cr�stal
Oscillator
HXT
�
U
X
Internal RC
Oscillator
HIRC
X1~X8
CPU clock
PLL�[�:0]
PLLSRC
IDL bit
- enable/disable CPU clock
SCKS[1:0]
fSYS
HIRCEN bit
enable/disable
fSYS/16
Internal RC
Oscillator
LIRC
External Cr�stal
Oscillator
LXT
�
U
X
��k
�
U
X
fWDT
Watchdog
Timer
WDTCS
LSOSEL
fSYS/4 or fSYS/1�8
PD bit
- enable/disable
selected oscillators
�
U
X
fTB
Time Base
TBCK[1:0]
System Clock Configurations
Rev. 1.00
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Operating Modes and System Clocks
HXTEN bit
enable/disable
�
U
X
PLL
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
There are two additional internal 32kHz low frequency clocks for the peripheral circuits. These are
the external crystal LXT oscillator and the internal LIRC oscillators. The selection is implemented
using the LSOSEL bit in the LSOCR register. There is a low frequency oscillator status bit,
LSORDY, to indicate the “ready or not” status of the low frequency oscillator. This bit is common
to both low frequency oscillators, and should be monitored by the program to indicate the “ready or
not” status of the oscillator before it is used for instruction execution. This bit will be automatically
cleared to zero during low speed oscillator switching and set high once the chosen oscillator is stable.
System Clock Control Register – SCCR
SFR Address: ECh
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
SCKS1
SCKS0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Bit 1~0
Rev. 1.00
Unimplemented, read as “0”
SCKS1, SCKS0: High Frequency System clock select
00: HIRC oscillator clock source
01: HIRC oscillator clock source
10: HXT oscillator clock source
11: PLL clock source
The HIRC will be the default system clock source after a power on reset.
When switching between different clock sources an oscillator stabilisation time delay
must be provided before continuing with program execution.
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Operating Modes and System Clocks
The main system clock source, known as f SYS, and which is used by the CPU and the peripheral
functions, can come from one of three sources. These are the internal HIRC oscillator, the external
crystal HXT oscillator or a frequency multiplied version of these oscillators using the internal
PLL. The selection is implemented using the SCKS0 and SCKS1 bits in the SCCR register. The
HXT and HIRC oscillators also have independent enable control bits, which are the HXTEN and
HIRCEN bits in the HSOCR register. There are also two oscillator status bits, HIRCRDY and
HXTRDY, in the HSOCR register to indicate whether the oscillators are ready for operation. After
power on, these bits should be monitored by the program to indicate the “ready or not” status of the
respective oscillator, before they are used with instruction execution. After power on, the device
will automatically select the HIRC oscillator as its default system clock, which can be changed later
by the application program.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
High Speed Oscillator Control Register – HSOCR
SFR Address: EFh
Bit
7
6
5
4
3
2
1
0
Name
—
—
HXTRDY
HIRCRDY
—
—
HXTEN
HIRCEN
R/W
—
—
R
R
—
—
R/W
R/W
POR
—
—
0
1
—
—
0
1
Bit 4
Bit 3~2
Bit 1
Bit 0
Unimplemented, read as “0”
HXTRDY: HXT oscillator ready indication bit
0: Not ready
1: Ready
This is the external high frequency oscillator, HXT, ready indication bit which indicates
if the HXT oscillator is stable or not. This bit will be cleared to zero by hardware when
the device is powered on. After power on, if the HXT oscillator is selected, the bit will
change to a high level when the external high frequency oscillator is stable.
HIRCRDY: HIRC oscillator ready indication bit
0: Not ready
1: Ready
This is the internal high frequency oscillator, HIRC, ready indication bit which indicates
if the HIRC oscillator is stable or not. This bit will be cleared to zero by hardware when
the HIRC function is disabled. After power on, if the HIRC oscillator is enabled, the bit
will change to a high level when the internal high frequency oscillator is stable.
Unimplemented, read as “0”
HXTEN: HXT control bit
0: Disable
1: Enable
HIRCEN: HIRC control bit
0: Disable
1: Enable
After power on, this bit will be set high thus selecting the HIRC as the initial system
oscillator.
Low Speed Oscillator Control Register – LSOCR
SFR Address: EEh
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
LSORDY
—
—
LSOSEL
—
R/W
—
—
—
R
—
—
R/W
—
POR
—
—
—
1
—
—
0
—
Bit 7~5
Bit 4
Bit 3~2
Bit 1
Bit 0
Rev. 1.00
Unimplemented, read as “0”
LSORDY: Low speed oscillator ready indication flag
0: Not ready
1: Ready
This is the common ready flag for the two low speed oscillators, LIRC and LXT,
which indicates if the low speed oscillator is stable or not. During low speed oscillator
switching this bit will be automatically cleared to zero by the hardware.
Unimplemented, read as “0”
LSOSEL: Low frequency oscillator select bit
0: LIRC
1: LXT
Unimplemented, read as “0”
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Operating Modes and System Clocks
Bit 7~6
Bit 5
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Phase Locked Loop – PLL
All devices contain a fully internal PLL function which is used to multiply the frequency of the
selected high speed oscillator, either HIRC or HXT. As all PLL functions are internal, no external
components, including those for the loop filter, are required.
Changing the PLL Frequency
After the PLL is enabled and is being used as the system clock, its frequency can be changed
dynamically by the application program, by programming the PLLM0~PLLM2 bits in the PLLCR
register. However the program must execute this operation in a specific way to ensure stable
frequency switching. There are a total of eight different PLL frequency multiplier selections,
however during dynamic PLL frequency changing, the multiplier value should only be changed
one stage at a time. In addition a recommended delay of at least 10 instruction cycles, which can
be implemented by 10 NOP instructions, should be inserted after each frequency multiplier stage
change to allow the PLL to re-lock and stabilise. Note that the PLLRDY bit will remain at a high
level during any dynamic PLL frequency change and cannot be used to indicate PLL stability after
the PLL changes frequency. The accompanying flowchart illustrates this point.
Example: Change the system clock from 8 MHz to 16 MHz
PLLCR register
PLLM 2:0 bits=001
NOP × 10
PLLCR register
PLLM 2:0 bits=010
NOP × 10
PLLCR register
PLLM 2:0 bits=011
NOP × 10
fSYS=8MHz
Delay to allow PLL to lock
fSYS=12MHz
Delay
fSYS=16MHz
Delay
16MHz system clock now ready for use
Note: 4MHz HXT external crystal oscillator
PLL Frequency Changing
Rev. 1.00
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Operating Modes and System Clocks
The PLL is enabled by the PLLEN bit in the PLLCR register. After being enabled the PLL must
be given a certain amount of time to lock and stabilise. After the PLL is enabled the PLLRDY bit
should be monitored to indicate when the PLL has locked and is ready for use. If the PLL function
is disabled, then the high frequency oscillators can be used directly as the system clock. The PLL
input clock source, from either the HIRC or HXT oscillators, is determined by the PLLSRC bit in
the PLLCR register. The frequency multiplier range has a range of one to eight times, selected by
the PLLM0~PLLM2 bits in the PLLCR register.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
PLL Control Register – PLLCR
SFR Address: EDh
Bit
7
6
Name
PLLEN
R/W
R/W
POR
0
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2~0
Rev. 1.00
4
3
2
1
0
PLLRDY
—
R
—
PLLSRC
—
PLLM2
PLLM1
PLLM0
R/W
—
R/W
R/W
0
—
R/W
0
—
0
0
0
PLLEN: PLL enable/disable control
0: PLL disable
1: PLL enable
PLLRDY: PLL output ready indication flag
0: Not ready
1: Ready
After the PLL is enabled this bit is used to indicate when the PLL is locked and ready
for use. This bit will be initially cleared to zero by hardware when the device is powered
on. The bit will be cleared to zero if the PLL is in use and is then disabled but will not
be cleared if the PLL changes frequency.
Unimplemented, read as “0”
PLLSRC: PLL Clock Source Select
0: HIRC clock source
1: HXT clock source
Note that if the PLL clock source is selected to be the external oscillator, HXT, the
crystal frequency should be 4MHz.
Unimplemented, read as “0”
PLLM2, PLLM1, PLLM0: PLL Frequency Multiplier select
000: ×1
001: ×2
010: ×3
011: ×4
100: ×5
101: ×6
110: ×7
111: ×8
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Operating Modes and System Clocks
Bit 6
5
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Operation Modes
NORMAL Mode
IDLE Mode
Power-Down Mode
CPU Clock
Operating Mode
On
Off
Off
Peripheral Clock(Note)
On
On
Off
Low Frequency XTAL Oscillator (LXT)
On (LSOSEL=1)/Off
On (LSOSEL=1)/Off
Off
Low Frequency Internal RC Oscillator (LIRC) On (LSOSEL=0)/Off
On (LSOSEL=0)/Off
Off
High Frequency XTAL Oscillator (HXT)
On (HXTEN=1)/Off
Off
On (HIRCEN=1)/Off
Off
On (HXTEN=1)/Off
High Frequency Internal RC Oscillator (HIRC) On (HIRCEN=1)/Off
Note: Peripheral Clock is the clock for Timer 0, Timer 1, Timer 2, Timer 3, PCA, UART0, UART1, I2C,
SPI, ADC, and DAC.
NORMAL Mode
As the name suggests this is the main operating mode where all of the selected oscillators and
clocks are active and the microcontroller has all of its functions operational and where the system
clock is provided directly by one of the high speed oscillators, HXT, HIRC or the PLL.
IDLE Mode
The IDLE Mode is entered when the IDL bit in the PCON register is set high. When the instruction
that sets the IDL bit high is executed the CPU operation will be inhibited, however, the high
frequency clock source will continue to run and can continue to provide a clock source for the
peripheral functions if selected. The low frequency clock sources will also remain operational and
can also provide a clock source for the WDT and Time Base functions, if they are enabled and if
their clock source is not selected to come from the system clock.
Power-Down Mode
The Power-Down Mode is entered when the PD bit in the PCON register is set high. When the
instruction that sets the PD bit high is executed the all oscillators will stop thus inhibiting both
CPU and peripheral functions such as the WDT and Time Base if they are enabled.
Rev. 1.00
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Operating Modes and System Clocks
There are three different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirements of the application. There is one mode allowing normal operation of the
microcontroller, the NORMAL Mode, in which all oscillators and function remain active. There
are also two low power modes, the IDLE mode and the Power-Down Mode. In the IDLE mode,
the microcontroller CPU will stop and instruction execution will cease, however, the high speed
oscillators will continue to run and can continue to provide a clock source for the peripheral
functions such as WDT, Time Base, Timers, UARTs, I 2C, SPI, ADC and DAC. The slow speed
oscillators will also continue to run and keep the WDT and Time Base functions active, if their
clock sources are not the system clock. In the Power-Down mode all oscillators are stopped and
therefore all functions cease operation.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Power Control Register
Two bits, PD and IDL, in the PCON register control overall mode selection.
PCON Register – Power Control Register
SFR Address: 87h
7
6
5
4
3
2
1
0
SMOD
—
—
—
—
GF0
PD
IDL
R/W
R/W
—
—
—
R
R/W
R/W
R/W
POR
0
—
—
—
1
0
0
0
Bit 7
Bit 6~3
Bit 2
Bit 1
Bit 0
SMOD: Serial Port 0 double baud rate select
Described elsewhere
Unimplemented
GF0: General Purpose bit
PD: Power-Down Mode control bit
0: No Power-Down – selected oscillators running
1: Power-Down – all oscillators stopped
Setting the PD bit to high will enable the Power-Down mode function. This bit will be
cleared by hardware before entering the Power-Down mode and always read as “0”.
IDL: IDLE Mode control bit
0: No Idle Mode – CPU clock running
1: Idle Mode – CPU clock stopped
Setting the IDL bit to high will enable IDLE mode function. This bit will be cleared by
hardware before entering the IDLE mode and always read as “0”. Note that if the PD bit
is set high, to enable the Power-Down Mode, then the condition of the IDL bit will be
overridden.
Standby Current Considerations
As the main reason to stop the oscillators is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several micro-amps, there are other considerations
which must also be taken into account by the circuit designer if the power consumption is to be
minimised.
Special attention must be made to the I/O pins on the device. All high-impedance input pins must
be connected to either a fixed high or low level as any floating input pins could create internal
oscillations and result in increased current consumption. Care must also be taken with the loads,
which are connected to I/O pins, which are setup as outputs. These should be placed in a condition
in which minimum current is drawn or connected only to external circuits that do not draw current,
such as other CMOS inputs. And for power saving purpose, all the analog modules have to be
disabled using the application program before MCU enter the IDLE or Power-Down mode.
The high speed and low speed oscillators will continue to run when in the IDLE Mode and will
thus consume some power.
Rev. 1.00
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Operating Modes and System Clocks
Bit
Name
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Wake-up
After the system enters the IDLE or Power-Down Mode, it can be woken up from one of various
sources listed as follows:
■■ An external reset
■■ An external low level on any P0 I/O pin
■■ A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset,
however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated.
Pins P0 [0:7] can be setup via the P0WAKE register to permit a low level on the pin to wake-up
the system. When an I/O pin wake-up occurs, the program will resume execution at the instruction
following the point where the PD or IDL control bits were set high.
If the system is woken up by an interrupt, then two possible situations may occur. The first is
where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case
the program will resume execution at the instruction following the control bits settings. In this
situation, the interrupt which woke-up the device will not be immediately serviced, but will rather
be serviced later when the related interrupt is finally enabled or when a stack level becomes free.
The other situation is where the related interrupt is enabled and the stack is not full, in which case
the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering
the IDLE or Power-Down modes, then any interrupt requests will not generate a wake-up function
and the related interrupt will be ignored. No matter what the source of the wake-up event is, once
a wake-up event occurs, the program can check if the system clock is stable or not by examining
the oscillator status bits. It is recommended that these bits are examined before proceeding with
instruction execution after a wake up.
Rev. 1.00
68 of 226
May 15, 2013
Operating Modes and System Clocks
■■ A system interrupt
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
22
Watchdog Timer
Watchdog Counter Registers
fSYS
÷16
÷16
WDTL
WDTH
LIRC
LXT
WDTCS
Refresh
Control
Bits
WDT
SWDT
WDT
Software
Reset
Latch
LSOSEL
WDTREL
Refresh
Value
Watchdog Timer
Rev. 1.00
69 of 226
May 15, 2013
Watchdog Timer
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused
by the program jumping to unknown locations or entering endless program loops, due to certain
uncontrollable external events such as electrical noise. Its basic structure is a 16-bit timer which
when it overflows will execute an MCU reset operation. The accompanying diagram illustrates the
basic operational block diagram.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Watchdog Registers
WDT Register Contents
Name
Bit
7
6
5
4
3
2
1
0
IEN0
(EAL)
WDT
(ET2)
(ES0)
(ET1)
(EX1)
(ET0)
(EX0)
(EX3)
IEN1
(EXEN2)
SWDT
(ET3)
(ECMP)
(EX6)
(EX5)
(EX4)
WDTREL
D7
D6
D5
D4
D3
D2
D1
D0
WDTCR
WE4
WE3
WE2
WE1
WE0
—
—
WDTCS
IP0
—
WDTS
(PT2)
(PS0)
(PT1)
(PX1)
(PT0)
(PX0)
Note: The bit and flag names in brackets are used to manage other functions and not related to the
WDT control.
IEN0 Register
SFR Address: A8h
Bit
7
6
5
4
3
2
1
0
Name
EAL
WDT
ET2
ES0
ET1
EX1
ET0
EX0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
EAL: Master interrupt global enable
Described elsewhere
WDT: Watchdog timer refresh flag
Setting this bit to “1” is the first step in initiating a Watchdog Timer refresh action. This
WDT bit must be set immediately before setting the SWDT bit in the IEN1 register. The
two instructions should be executed consecutively and not have any other instruction in
between to prevent an unintentional watchdog timer refresh. This bit will be cleared by
hardware automatically. This bit is always read as 0.
ET2: Timer2 interrupt enable
Described elsewhere
ES0: Serial Port 0 interrupt enable
Described elsewhere
ET1: Timer1 overflow interrupt enable
Described elsewhere
EX1: External interrupt 1 enable
Described elsewhere
ET0: Timer0 overflow interrupt enable
Described elsewhere
EX0: External interrupt 0 enable
Described elsewhere
70 of 226
May 15, 2013
Watchdog Timer
There are several registers for overall watchdog timer operation. The WDTREL register is used to
setup the reload value of the Watchdog Timer. The remaining four registers are control registers
which setup the operating and control function of the WDT function. The WDTCR register
controls the WDT enable/disable operation, software reset and clock source select functions. The
WDT and SWDT bits, located in the IEN0 and IEN1 registers respectively, are used to refresh the
WDT counter to prevent the WDT overflow and reset the device. The WDTS bit in the IP0 register
is used to indicate that a WDT software reset has been generated. For details regarding the WDT
software reset function, refer to the datasheet Reset section for details.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
IEN1 Register
SFR Address: A9h
Bit
7
6
Name
EXEN2
R/W
R/W
POR
0
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4
3
2
1
0
SWDT
ET3
ECMP
EX6
EX5
EX4
EX3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
EXEN2: Timer2 external reload interrupt enable
Described elsewhere
SWDT: Watchdog timer start/refresh flag
This bit is used to activate and refresh the watchdog timer.
When this bit is set to “1” directly after the WDT bit is set, a watchdog timer refresh
will be enabled. This bit will be cleared by hardware automatically. This bit is always
read as 0.
ET3: Timer 3 overflow interrupt enable
Described elsewhere
ECMP: Comparator overall interrupt enable
Described elsewhere
EX6: External interrupt 6 enable
Described elsewhere
EX5: External interrupt 5 enable
Described elsewhere
EX4: External interrupt 4 enable
Described elsewhere
EX3: External interrupt 3 enable
Described elsewhere
WDTREL Register
SFR Address: 86h
Bit
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
7
Watchdog reload value
Reload value for the highest 8 bits of the watchdog timer.
This value is loaded to the Watchdog Timer when a refresh is triggered by the
consecutive setting of bits, WDT and SWDT.
71 of 226
May 15, 2013
Watchdog Timer
Bit 6
5
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
WDTCR Register
SFR Address: 96h
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
—
—
WDTCS
R/W
R/W
R/W
R/W
R/W
R/W
—
—
R/W
POR
0
1
0
1
0
—
—
0
Bit 7~3
IP0 Register
SFR Address: B8h
Bit
7
6
5
4
3
2
1
0
Name
—
WDTS
PT2
PS0
PT1
PX1
PT0
PX0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
Unimplemented, read as “0”
WDTS: Watchdog timer reset indication flag
0: No Watchdog timer reset
1: Watchdog timer reset
PT2: Timer 2 Interrupt priority low
Described elsewhere
PS0: UART 0 Interrupt priority low
Described elsewhere
PT1: Timer 1 Interrupt priority low
Described elsewhere
PX1: External interrupt 1 priority low
Described elsewhere
PT0: Timer 0 Interrupt priority low
Described elsewhere
PX0: External interrupt 0 priority low
Described elsewhere
72 of 226
May 15, 2013
Watchdog Timer
Bit 2~1
Bit 0
WE4~WE0: WDT function software control
10101: Disable
01010: Enable - default
Other values: Reset MCU
Unimplemented, read as “0”
WDTCS: Watchdog clock (f WDT) select
0: LIRC or LXT
1: f SYS/16
Note that the WDTCR value will default to 01010000B after any reset resource which
means that the WDT will be enabled after any reset takes place. For more details
regarding the reset operation, refer to the Reset section.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Watchdog Timer Clock Source
Watchdog Timer Operation
The Watchdog Timer operates by providing a device reset when its 16-bit timer overflows. The
WDT is formed of two 8-bit registers, WDTL and WDTH, both of which are inaccessible to the
application program. The WDTH register of the Watchdog Timer is reloaded with the contents of
the WDTREL register. In the application program and during normal operation the user has to
strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from
executing a reset. This is done by setting the WDT and SWDT bits. If the program malfunctions
for whatever reason, jumps to an unknown location, or enters an endless loop, these clear-bit
instructions will not be executed in the correct manner as setup up by the user, in which case the
Watchdog Timer will overflow and reset the device. There are five bits, WE4~WE0, in the WDTCR
register to enable/disable the Watchdog Timer. The WE4~WE0 bits must be set to a specific value
of “10101” to disable the WDT. A value of “01010” will enable the WDT while any other value will
execute an MCU reset. Using this methodology, enhanced device protection is provided. After
power on, these bits will have a value of “01010” which is the WDT enable setup value, and the
WDT function will be enabled and began counting. The application program can disable the WDT
at the beginning of the program if it is not required.
Watchdog Timer Enable/Disable Control
WE4~WE0 Bits
WDT Function
01010B
Enable
10101B
Disable
Other values
Reset MCU
The watchdog timer must be refreshed regularly to prevent the reset request signal, WDTS,
from becoming active. This requirement imposes an obligation on the programmer to issue two
consecutive instructions. The first instruction is to set the WDT bit of the IEN0 register and the
second one is to set the SWDT bit in the IEN1 register. The maximum allowed delay time between
setting the WDT and SWDT bits is one instruction cycle, which means the instructions which set
the both bits should not be separated by any other instruction. If these instructions are not executed
consecutively then the WDT refresh procedure is incomplete and an unexpected WDT reset will
take place.
After the application program has set both the WDT and SWDT bits and the WDT refreshed, the
WDT bit as well the SWDT bit will be automatically cleared by hardware. The 8 high-order bits
of the Watchdog Timer are re-loaded with the contents of the WDTREL register. The larger the
WDTREL value, the shorter the WDT time out will be. For the maximum WDT time out value, the
WDTREL register should be cleared to zero.
Rev. 1.00
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May 15, 2013
Watchdog Timer
The Watchdog Timer clock source is provided by an internal clock which is in turn supplied by
one of three sources selected by the WDTCS bit in the WDTCR register: a 32kHz clock or f SYS/16.
The 32kHz clock can be sourced from either the LXT or LIRC oscillators, selected by the LSOSEL
bit in the LSOCR register. The Watchdog Timer source clock is then subdivided by a ratio of 16 to
give a longer timeout. The LIRC internal oscillator has an approximate period of 32kHz at a supply
voltage of 5V. However, it should be noted that this specified internal clock period can vary with
VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768kHz
crystal. The other Watchdog Timer clock source option is the f SYS/16 clock.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
WDT running
Program sets WDT bit
Must not insert other
instructions here
Watchdog Timer
Program sets SWDT bit
WDT loaded with WDTREL
register value
H/W auto Clear WDT bit
H/W auto Clear SWDT bit
WDT continues running
Watchdog Timer Refresh Operation
Rev. 1.00
74 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
23
Low Voltage Detector – LVD
LVD Register
The Low Voltage Detector function is controlled using a single register with the name LVDCR.
Three bits in this register, LVDS2~LVDS0, are used to select one of eight fixed voltages below
which a low voltage condition will be determined. The LVDEN bit is used to control the overall
on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector.
Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage
detector will consume a certain amount of power, it may be desirable to switch off the circuit when
not in use, an important consideration in power sensitive battery powered applications.
LVDCR Register
SFR Address: EBh
Bit
7
6
5
4
3
2
1
0
Name
LVDEN
—
—
—
—
LVDS2
LVDS1
LVDS0
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
0
0
0
Bit 7
Bit 6~3
Bit 2~0
LVDEN: LVD Function Control
0: Disable
1: Enable
Unimplemented, read as "0"
LVDS2~LVDS0: Select LVD Voltage
000: 2.0V
001: 2.2V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.2V
LVD Operation
The Low Voltage Detector function operates by comparing the power supply voltage, V DD, with
a pre-specified voltage level stored in the LVDCR register. This has a range of between 2.0V and
4.2V. When the power supply voltage, V DD, falls below this pre-determined value and if the LVD
interrupt function is enabled, the LVD interrupt will take place and the interrupt request flag,
LVDF, in the IRCON2 register, will be set high. The LVDF bit will be cleared to low by hardware
automatically. The LVD interrupt can cause the device to wake-up from the IDLE Mode. If the
Low Voltage Detector wake up function is not required then the LVDF flag should be first set high
and disable the LVD interrupt function before the device enters the IDLE Mode. When the device
is powered down the low voltage detector will be disabled to reduce the power consumption.
Rev. 1.00
75 of 226
May 15, 2013
Low Voltage Detector – LVD
Each device has a Low Voltage Detector function, also known as LVD. This enables the device
to monitor the power supply voltage, V DD, and provide an interrupt should it fall below a certain
level. This function may be especially useful in battery applications where the supply voltage will
gradually reduce as the battery ages, as it allows a battery low early warning signal to be generated.
The LVD function can also generate an interrupt signal if required.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
24
Reset and Initialisation
Reset Overview
The most important reset condition is after power is first applied to the microcontroller. In this
case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well
defined state and ready to execute the first program instruction. After this power-on reset, certain
important internal registers will be set to defined states before the program instructions commence
execution. One of these registers is the Program Counter, which will be reset to zero forcing the
microcontroller to begin program execution from the lowest Program Memory address.
The devices provide several reset sources to generate the internal reset signal, providing extended
MCU protection. The different types of resets are listed in the accompanying table.
Reset Source Summary
No.
Reset Name
1
Power-On Reset
2
Reset Pin
3
Low-Voltage Reset
4
LVRCR Register Setting Software
Reset
Notes
POR
PORF
RSTSRC Auto generated at power on
RESET
XRSTF
RSTSRC Hardware Reset
LVR
LVRF
RSTSRC Low VDD voltage
—
LRF
RSTSRC Write to LVRCR register
WDT
WDTS
—
WRF
MCD
MCDF
RSTSRC
To enable – set MCD bit in
MISC register
To enable – set CP0RST bit
in CP0CR register
5
Watchdog Reset
6
WDTCR Register Setting Software
Reset
7
Missing Clock Detection Reset
8
Comparator 0 Output Reset
—
CMP0F
RSTSRC
9
SRST Register Setting Software
Reset
—
SRSTREQ
SRST
—
—
—
10 ROM Code Check Reset
Rev. 1.00
Abbreviation Indication Bit Register
76 of 226
IP0
Watchdog overflow
RSTSRC Write to WDTCR register
Write to SRST register
—
May 15, 2013
Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside parameters. A hardware reset will of course
be automatically implemented after the device is powered-on, however there are a number of other
hardware and software reset sources that can be implemented dynamically when the device is
running.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Reset Operations
After the initial power on reset, there are many ways in which a microcontroller reset can occur,
through events occurring both internally and externally.
Reset Source Register – RSTSRC
All of the bits in the RSTSRC register are read only and can therefore not be cleared by the
application program after one of the relevant reset occurs. After one of these reset occurs and the
relevant bit is high to indicate its occurrence, the bit can only be cleared by hardware when another
different reset type occurs.
RSTSRC Register
SFR Address: FFh
Bit
7
6
5
4
3
2
1
0
Label
—
LRF
WRF
MCDF
CMP0F
LVRF
XRSTF
PORF
R/W
—
R
R
R
R
R
R
R
POR
—
0
0
0
0
x
0
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
Unimplemented, read as “0”
LRF: LVRCR Register Setting Software Reset Indication Flag
0: No LVRCR Setting Software Reset
1: LVRCR Software Reset
WRF: WDTCR Register Setting Software Reset Indication Flag
0: No WDTCR Setting Software Reset
1: WDTCR Setting Software Reset
MCDF: Missing Clock Detection Reset Indication Flag
0: No Missing Clock Detection Reset
1: Missing Clock Detection Reset
CMP0F: Comparator 0 Reset Indication Flag
0: No Comparator 0 Reset
1: Comparator 0 Reset
LVRF: Low-Voltage Reset Indication Flag
0: No Low-Voltage Reset
1: Low-Voltage Reset
XRSTF: External Pin Reset Indication Flag
0: No External Reset
1: External Reset
PORF: Power-on Reset Indication Flag
0: No Power-on Reset
1: Power-on Reset
77 of 226
May 15, 2013
Reset and Initialisation
After a reset occurs the device will be reset to some initial condition. Several registers are used to
indicate which actual reset type caused the device to reset. Seven of the possible reset sources will
be indicated by the reset source register, RSTSRC. The additional reset sources are indicated by the
SRSTREQ bit in the SRST register for the Software Reset and the WDTS bit in the IP0 register for
the Watchdog reset. And the MCU reset can also caused by ROM Code Check.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Power-on Reset
The most fundamental and unavoidable reset is the one that occurs after power is first applied to
the microcontroller. As well as ensuring that the Program Memory begins execution from the first
memory address, a power-on reset also ensures that certain other registers are preset to known
conditions. The entire I/O data and port mode registers will power up to ensure that all pins will be
first set to the quasi-bidirection structure.
VDD
tSST
SST Time-out
Chip Reset
Power-On Reset Timing
Rev. 1.00
78 of 226
May 15, 2013
Reset and Initialisation
Although the microcontroller has an internal RC reset function, if the VDD power supply rise
time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be
incapable of providing proper reset operation. For this reason it is recommended that an external
RC network is connected to the RESET pin, whose additional time delay will ensure that the
RESET pin remains low for an extended period to allow the power supply to stabilise. During this
time delay, normal operation of the microcontroller will be inhibited. After the RESET line reaches
a certain voltage value, the reset delay time of tSST, which is equal to 1024 system clock pulses, is
invoked to provide an extra delay time after which the microcontroller will begin normal operation.
The abbreviation SST in the figures stands for System Start-up Timer. When the Power-on reset
takes place, the PORF bit in the RSTSRC register will be set high to indicate this reset.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
RESET Pin Reset
For most applications a resistor connected between VDD and the RESET pin and a capacitor
connected between VSS and the RESET pin will provide a suitable external reset circuit. Any
wiring connected to the RESET pin should be kept as short as possible to minimise any stray noise
interference. For applications that operate within an environment where more noise is present the
Enhanced Reset Circuit shown is recommended.
Reset and Initialisation
VDD
100kΩ
RESET
0.1µF
Basic Reset Circuit
VDD
100kΩ
0.01μF
RESET
10kΩ
0.1μF
Enhanced Reset Circuit
This type of reset occurs when the microcontroller is already running and the RESET pin is
forcefully pulled low by external hardware such as an external switch. In this case as in the case
of other resets, the Program Counter will reset to zero and program execution initiated from this
point. Note that, during the power-up sequence, the reset circuit should make sure that the external
reset to be released after the internal power-on reset is over plus a suitable delay time. To improve
the noise immunity, the low portion of external reset signal must be greater than that specified by
tRES in the A.C. characteristics, for the internal logic to recognise a valid reset. When a RESET pin
reset takes place, the XRSTF bit in the RSTSRC register will be set high to indicate this reset.
Rev. 1.00
79 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Low Voltage Reset – LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of
the device and provide an MCU reset should the value fall below a certain predefined level.
LVRCR Register
SFR Address: EAh
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0
Rev. 1.00
LVS7~LVS0: LVR Voltage Select control
01010101: 2.1V
00110011: 2.55V
10011001: 3.15V
10101010: 4.0V
Any other value: Generates MCU reset – register is reset to POR value
When an actual low voltage condition occurs, as specified by the above defined LVR
voltage value, an MCU reset will be generated. The reset operation will be activated
after 2~3 LIRC clock cycles. In this situation this register contents will remain the same
after such a reset occurs.
Any register value, other than the four defined values above, will also result in the
generation of an MCU reset. The reset operation will be activated after 2~3 LIRC clock
cycles. However in this situation this register contents will be reset to the POR value.
80 of 226
May 15, 2013
Reset and Initialisation
The LVR function is always enabled with a specific LVR voltage, V LVR. If the supply voltage of
the device drops to within a range of 0.9V~V LVR such as might occur when changing the battery
in battery powered applications, the LVR will automatically reset the device internally and the
LVRF bit in the RSTSRC register will also be set to1. For a valid LVR signal, a low voltage, i.e., a
voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the
A.C. characteristics. If the low voltage state does not exceed this value, the LVR will ignore the
low supply voltage and will not perform a reset function. The actual VLVR value can be selected by
the LVSn bits in the LVRCR register. If the LVS7~LVS0 bits are changed to some certain values
by the environmental noise, the LVR will reset the device after 2~3 LIRC clock cycles. When this
happens, the LRF bit in the RSTSRC register will be set to 1. After power on the register will have
the value of 01010101B. Note that the LVR function will be automatically disabled when the device
enters the power-down mode.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Watchdog Reset
All devices contain a Watchdog Timer which is used as a protection feature. The Watchdog
Timer has to be periodically cleared by the application program and prevented from overflowing
during normal MCU operation. However should the program enter an endless loop or should
external environmental conditions such as noise causes the device to jump to unpredicted program
locations, the Watchdog Timer will overflow from FFFFh to 0000h, and generate an MCU reset.
Refer to the Watchdog Timer section for more details regarding the Watchdog Timer operation.
IP0 Register
SFR Address: B8h
Bit
7
6
Name
—
WDTS
PT2
PS0
PT1
PX1
PT0
PX0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
5
4
3
2
1
0
Unimplemented, read as “0”
WDTS: Watchdog timer reset indication flag
0: No Watchdog timer reset
1: Watchdog timer reset
This bit must be cleared by the application program as it will not be automatically
cleared by hardware.
PT2: Timer 2 Interrupt priority
Described elsewhere
PS0: Serial Port 0 Interrupt priority
Described elsewhere
PT1: Timer 1 Interrupt priority
Described elsewhere
PX1: External interrupt 1 priority
Described elsewhere
PT0: Timer 0 Interrupt priority
Described elsewhere
PX0: External interrupt 0 priority
Described elsewhere
81 of 226
May 15, 2013
Reset and Initialisation
When a Watchdog Reset occurs the WDTS bit in the IP0 register will be set to indicate the reset
source. Note that this bit must be reset by the application program.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Missing Clock Detect Reset
The device provides a missing clock detection function which can generate a reset in the absence
of a system clock. The missing clock detect reset function is enabled by setting the MCD bit in the
T2CON1 register. If the MCD bit is set high and if there is a system clock missing event happens,
then the Missing Clock Detect reset will be generated. The MCDF bit in the RSTSRC register is
used to indicate a missing clock reset source.
Bit
7
6
5
4
3
2
1
0
Label
—
—
—
MCD
T2OI
T2OE
—
—
R/W
—
—
—
R/W
R/W
R/W
—
—
POR
—
—
—
0
1
0
—
—
Bit 7~5
Bit 4
Bit 3
Bit 2
Bit 1~0
Rev. 1.00
Unimplemented, read as “0”
MCD: Missing Clock Detection Reset control
0: Disable
1: Enable
Note that this bit should be cleared manually before entering the Power-Down mode, or
it will cause a “Missing Clock Reset” after entering the Power-Down mode.
T2OI: Timer 2 output initial state
Described elsewhere
T2OE: Timer 2 output enable bit
Described elsewhere
Unimplemented, read as “0”
82 of 226
May 15, 2013
Reset and Initialisation
T2CON1 Register
SFR Address: FEh
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Comparator 0 Reset
Comparator 0 contains an output reset function which can provide a reset when the output of
Comparator 0 changes state. The Comparator 0 reset function is enabled by setting the CP0RST
bit in the CP0CR register. If the CP0RST is set high, the comparator 0 output bit, CP0OUT, will
determine if a Comparator 0 reset is generated or not. The CP0RSTL bit determines which polarity
of the CP0OUT bit generates the reset, The CMP0F bit in the RSTSRC register is used to indicate
the Comparator 0 reset source.
Bit
7
6
5
4
3
2
1
0
Label
—
CP0ON
CP0POL
CP0OUT
CP0OS
CP0RSTL
CP0RST
—
R/W
—
R/W
R/W
R
R/W
R/W
R/W
—
POR
—
0
0
0
1
0
0
—
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
Unimplemented, read as “0”
CP0ON: Comparator 0 on/off bit
Described elsewhere
CP0POL: Comparator 0 output polarity
Described elsewhere
CP0OUT: Comparator 0 output bit
Described elsewhere
CP0OS: Comparator 0 output path selection
Described elsewhere
CP0RSTL: Comparator 0 output reset selection – CP0RST=1
0: CP0OUT=0 will reset MCU
1: CP0OUT=1 will reset MCU
CP0RST: Comparator 0 output reset MCU control
0: Disable
1: Enable
Unimplemented, read as “0”
83 of 226
May 15, 2013
Reset and Initialisation
CP0CR Register
SFR Address: DEh
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Software Resets
There are three ways to generate Software Reset, each of which are generated by writing certain
values to the SRST register, the WDTCR register or the LVRCR register.
Software Reset Summary
Software Reset Name
SRST Register
Register
Bit
Operation
SRSTREQ Write two successive “1” values to this bit
WDTRCR Register
WDTCR
WE4~WE0 Write value other than “10101” or “01010”
LVRCR Register
LVRCR
LVS7~LVS0
Write value other than “01010101”, “00110011”, “011001”
or “10101010”
SRST Register Software Reset
A software reset will be generated after two consecutive instructions to write a high value to the
SRSTREQ bit in the SRST register. The same bit can be used to identify the reset source.
SRST Register
SFR Address: F7h
Bit
7
6
5
4
3
2
1
0
Label
—
—
—
—
—
—
—
SRSTREQ
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit 7~1
Bit 0
Rev. 1.00
Unimplemented, read as “0”
SRSTREQ: Software reset request.
Writing a ‘0’ value to this bit will have no effect.
A single ‘1’ value write to this bit will have no effect.
Two consecutive ‘1’ value writes to this bit will generate a software reset.
Reading this bit can indicate the reset source:
0: No software reset
1: Software reset
This bit must be cleared by the application program as it will not be automatically
cleared by hardware.
84 of 226
May 15, 2013
Reset and Initialisation
SRST
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
WDTCR Register Software Reset
A WDTCR software reset will be generated when a value other than “10101” or “01010”, exist in
the highest five bits of the WDTCR register. The WRF bit in the RSTSRC register will be set high
when this occurs, thus indicating the generation of a WDTCR software reset.
WDTCR Register
SFR Address: 96h
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
—
—
WDTCS
R/W
R/W
R/W
R/W
R/W
R/W
—
—
R/W
POR
0
1
0
1
0
—
—
0
Bit 7~3
Bit 2~1
Bit 0
WE4~WE0: WDT function software control
10101: Disable
01010: Enable – default
Other values: Reset MCU
If the MCU reset is caused by WE[4:0] in WDTC software reset, the WRF flag of
RSTSRC register will be set.
Unimplemented, read as “0”
WDTCS: Watchdog clock (f WDT) select
Described elsewhere
LVRCR Register Software Reset
An LVRCR software reset will be generated when a value other than “01010101”, “00110011”,
“10011001” and “10101010”, exist in the LVRCR register. The LRF bit in the RSTSRC register
will be set high when this occurs, thus indicating the generation of an LVRCR software reset. The
LVRCR register value will be rest to a value of 01010101B after any reset other than the LVR reset,
and will remain unchanged after an LVR reset or during a WDT time out in the Power-Down mode.
LVRCR Register
SFR Address: EAh
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit 7~0
Rev. 1.00
LVS7~LVS0: LVR Voltage Select control
01010101: 2.1V – default value
00110011: 2.55V
10011001: 3.15V
10101010: 4.0V
Any other value: Generates MCU reset – register is reset to POR value
85 of 226
May 15, 2013
Reset and Initialisation
Bit
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
ROM Code Check Reset
ID block addresses 0xF0~0xFF can be written into ROM codes such as the following table shows,
or a value of FFH which means no ROM codes are written into these addresses. When reading the
option table, the hardware will automatically compare with the ROM code pattern, if any one of the
ID block addresses has a mismatch, the MCU will automatically reset and re-read the option table
until all the ID block addresses are matched.
ROM code
0xF0
01H/FFH
0xF1
23H/FFH
0xF2
45H/FFH
0xF3
67H/FFH
0xF4
89H/FFH
0xF5
ABH/FFH
0xF6
CDH/FFH
0xF7
EFH/FFH
0xF8
FEH/FFH
0xF9
DCH/FFH
0xFA
BAH/FFH
0xFB
98H/FFH
0xFC
76H/FFH
0xFD
54H/FFH
0xFE
32H/FFH
0xFF
10H/FFH
Reset and Initialisation
ID block address
Reset Initial Conditions
The different types of reset described affect the reset flags in different ways. The following table
indicates the way in which the various components of the microcontroller are affected after a
power-on reset occurs.
Item
Program Counter
Condition After RESET
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer/Even Counters
Timer/Even Counters will be turned off
Input/Output Ports
I/O ports will be setup as a quasi-bidirection structure
Stack Pointer
Set to 007H value
The different kinds of resets all affect the internal registers of the microcontroller in different ways.
To ensure reliable continuation of normal program execution after a reset occurs, it is important to
know what condition the microcontroller is in after a particular reset occurs. The following table
describes how each type of reset affects each of the microcontroller internal registers.
Rev. 1.00
86 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Register Name
Program Counter
Power-On Reset
External Reset
WDT Time-out
Reset
Software Reset
0000h
0000h
0000h
1111_1111b
1111_1111b
1111_1111b
1111_1111b
SP
0000_0111b
0000_0111b
0000_0111b
0000_0111b
DPL
0000_0000b
0000_0000b
0000_0000b
0000_0000b
DPH
0000_0000b
0000_0000b
0000_0000b
0000_0000b
DPL1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
DPH1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
WDTREL
0000_0000b
0000_0000b
uuuu_uuuub
0000_0000b
PCON
0---_1000b
0---_1000b
0---_1000b
0---_1000b
TCON
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TMOD
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TL0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TL1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TH0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TH1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TMPRE
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P1
1111_1111b
1111_1111b
1111_1111b
1111_1111b
P0WAKE
0000_0000b
0000_0000b
0000_0000b
0000_0000b
DPS
----_---0b
----_---0b
----_---0b
----_---0b
DPC
----_0000b
----_0000b
----_0000b
----_0000b
WDTCR
0101_0--0b
0101_0--0b
0101_0--ub
0101_0--0b
S0CON
0000_0000b
0000_0000b
0000_0000b
0000_0000b
S0BUF
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IEN2
----_-000b
----_-000b
----_-000b
----_-000b
S1CON
0-00_0000b
0-00_0000b
0-00_0000b
0-00_0000b
S1BUF
0000_0000b
0000_0000b
0000_0000b
0000_0000b
S1RELL
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P0M0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P0M1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P2
1111_1111b
1111_1111b
1111_1111b
1111_1111b
T3CON
0000_--00b
0000_--00b
0000_--00b
0000_--00b
TL3
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TH3
0000_0000b
0000_0000b
0000_0000b
0000_0000b
SRCR
--00_0000b
--00_0000b
--00_0000b
--00_0000b
SPPRE
- - - - _ 1111 b
- - - - _ 1111 b
- - - - _ 1111 b
- - - - _ 1111 b
P1M0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P1M1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IEN0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IEN1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
S0RELL
1101_1001b
1101_1001b
1101_1001b
1101_1001b
P2M0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P2M1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P3
1111_1111b
1111_1111b
1111_1111b
1111_1111b
P4
1111_1111b
1111_1111b
1111_1111b
1111_1111b
TBCR
0 - 0 0 _ - 111 b
0 - 0 0 _ - 111 b
0 - 0 0 _ - 111 b
0 - 0 0 _ - 111 b
DACTRL
000-_--00b
000-_--00b
000-_--00b
000-_--00b
DAL
0000_----b
0000_----b
0000_----b
0000_----b
DAH
1000_0000b
1000_0000b
1000_0000b
1000_0000b
Rev. 1.00
87 of 226
May 15, 2013
Reset and Initialisation
0000h
P0
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
External Reset
WDT Time-out
Reset
Software Reset
P3M0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P3M1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IP0
-000_0000b
-000_0000b
-100_0000b
-000_0000b
IP0H
--00_0000b
--00_0000b
--00_0000b
--00_0000b
S0RELH
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
S1RELH
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
CPHCR
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CPICR
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IRCON2
----_0000b
----_0000b
----_0000b
----_0000b
IRCON
0000_000-b
0000_000-b
0000_000-b
0000_000-b
CCEN
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCL1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCH1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCL2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCH2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCL3
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCH3
0000_0000b
0000_0000b
0000_0000b
0000_0000b
T2CON
-000_0000b
-000_0000b
-000_0000b
-000_0000b
IEN3
----_0000b
----_0000b
----_0000b
----_0000b
CRCL
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CRCH
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TL2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TH2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IP3
----_0000b
----_0000b
----_0000b
----_0000b
IP3H
----_0000b
----_0000b
----_0000b
----_0000b
PSW
0000_0000b
0000_0000b
0000_0000b
0000_0000b
I2CCON
-000_00--b
-000_00--b
-000_00--b
-000_00--b
P5
1111_1111b
1111_1111b
1111_1111b
1111_1111b
I2CDAT
0000_0000b
0000_0000b
0000_0000b
0000_0000b
I2CADR
0000_0000b
0000_0000b
0000_0000b
0000_0000b
SBRCON
00--_----b
00--_----b
00--_----b
00--_----b
I2CSTA
1111 _ 1 - - - b
1111 _ 1 - - - b
1111 _ 1 - - - b
1111 _ 1 - - - b
CP0CR
-000_100-b
-000_100-b
-000_100-b
-000_100-b
CP1CR
-000_1---b
-000_1---b
-000_1---b
-000_1---b
ACC
0000_0000b
0000_0000b
0000_0000b
0000_0000b
SPSTA
0000_----b
0000_----b
0000_----b
0000_----b
FMSR
0---_0000b
0---_0000b
0---_0000b
0---_0000b
SPDAT
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IP1
--00_0000b
--00_0000b
--00_0000b
--00_0000b
IP1H
--00_0000b
--00_0000b
--00_0000b
--00_0000b
IP2
----_-000b
----_-000b
----_-000b
----_-000b
IP2H
----_-000b
----_-000b
----_-000b
----_-000b
SPCON
0001_0100b
0001_0100b
0001_0100b
0001_0100b
I2CLK
0001_1001b
0001_1001b
0001_1001b
0001_1001b
LVRCR
0101_0101b
0101_0101b
0101_0101b
0101_0101b
LVDCR
0---_-000b
0---_-000b
0---_-000b
0---_-000b
SCCR
----_--00b
----_--00b
----_--00b
----_--00b
PLLCR
00-0_-000b
00-0_-000b
00-0_-000b
00-0_-000b
Rev. 1.00
88 of 226
May 15, 2013
Reset and Initialisation
Power-On Reset
Register Name
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
External Reset
WDT Time-out
Reset
Software Reset
LSOCR
---1_--0-b
---1_--0-b
---1_--0-b
---1_--0-b
HSOCR
--01_--01b
--01_--01b
--01_--01b
--01_--01b
B
0000_0000b
0000_0000b
0000_0000b
0000_0000b
ADCR0
0110_0000b
0110_0000b
0110_0000b
0110_0000b
ADCR1
00-0_0000b
00-0_0000b
00-0_0000b
00-0_0000b
ADCR2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
ADPGA
----_-000b
----_-000b
----_-000b
----_-000b
ADRL(ADRFS=0)
0000_----b
0000_----b
0000_----b
0000_----b
ADRH(ADRFS=0)
0000_0000b
0000_0000b
0000_0000b
0000_0000b
SRST
----_---0b
----_---0b
----_---0b
----_---1b
FMCR
01--_-000b
01--_-000b
01--_-000b
01--_-000b
FMKEY
0000_0000b
0000_0000b
0000_0000b
0000_0000b
FMAR0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
FMAR1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
FMAR2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
FMDR
0000_0000b
0000_0000b
0000_0000b
0000_0000b
T2CON1
---0_10--b
---u_10--b
---u_10--b
---u_10--b
RSTSRC
-000_0x01b
-000_0010b
-000_0000b
-000_0000b
Register Name
WDTCR Reset
LVR Reset
LVRCR Reset
Comparator0 Reset
0000h
0000h
0000h
0000h
0000h
P0
1111_1111b
1111_1111b
1111_1111b
1111_1111b
1111_1111b
SP
0000_0111b
0000_0111b
0000_0111b
0000_0111b
0000_0111b
DPL
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
DPH
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
DPL1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
DPH1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
WDTREL
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
PCON
0---_1000b
0---_1000b
0---_1000b
0---_1000b
0---_1000b
TCON
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TMOD
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TL0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TL1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TH0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TH1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TMPRE
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P1
1111_1111b
1111_1111b
1111_1111b
1111_1111b
1111_1111b
P0WAKE
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
DPS
----_---0b
----_---0b
----_---0b
----_---0b
----_---0b
DPC
----_0000b
----_0000b
----_0000b
----_0000b
----_0000b
WDTCR
0101_0--0b
0101_0--0b
0101_0--0b
0101_0--0b
0101_0--0b
S0CON
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
S0BUF
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IEN2
----_-000b
----_-000b
----_-000b
----_-000b
----_-000b
S1CON
0-00_0000b
0-00_0000b
0-00_0000b
0-00_0000b
0-00_0000b
S1BUF
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
Program Counter
Rev. 1.00
89 of 226
MCD Reset
May 15, 2013
Reset and Initialisation
Power-On Reset
Register Name
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Register Name
LVR Reset
LVRCR Reset
Comparator0 Reset
MCD Reset
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P0M0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P0M1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P2
1111_1111b
1111_1111b
1111_1111b
1111_1111b
1111_1111b
T3CON
0000_--00b
0000_--00b
0000_--00b
0000_--00b
0000_--00b
TL3
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TH3
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
SRCR
--00_0000b
--00_0000b
--00_0000b
--00_0000b
--00_0000b
SPPRE
- - - - _ 1111 b
- - - - _ 1111 b
- - - - _ 1111 b
- - - - _ 1111 b
- - - - _ 1111 b
P1M0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P1M1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IEN0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IEN1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
S0RELL
1101_1001b
1101_1001b
1101_1001b
1101_1001b
1101_1001b
P2M0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P2M1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P3
1111_1111b
1111_1111b
1111_1111b
1111_1111b
1111_1111b
P4
1111_1111b
1111_1111b
1111_1111b
1111_1111b
1111_1111b
TBCR
0 - 0 0 _ - 111 b
0 - 0 0 _ - 111 b
0 - 0 0 _ - 111 b
0 - 0 0 _ - 111 b
0 - 0 0 _ - 111 b
DACTRL
000-_--00b
000-_--00b
000-_--00b
000-_--00b
000-_--00b
DAL
0000_----b
0000_----b
0000_----b
0000_----b
0000_----b
DAH
1000_0000b
1000_0000b
1000_0000b
1000_0000b
1000_0000b
P3M0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
P3M1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IP0
-000_0000b
-000_0000b
-000_0000b
-000_0000b
-000_0000b
IP0H
--00_0000b
--00_0000b
--00_0000b
--00_0000b
--00_0000b
S0RELH
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
S1RELH
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
- - - - _ - - 11 b
CPHCR
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CPICR
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IRCON2
----_0000b
----_0000b
----_0000b
----_0000b
----_0000b
IRCON
0000_000-b
0000_000-b
0000_000-b
0000_000-b
0000_000-b
CCEN
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCL1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCH1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCL2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCH2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCL3
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CCH3
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
T2CON
-000_0000b
-000_0000b
-000_0000b
-000_0000b
-000_0000b
IEN3
----_0000b
----_0000b
----_0000b
----_0000b
----_0000b
CRCL
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
CRCH
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TL2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
TH2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IP3
----_0000b
----_0000b
----_0000b
----_0000b
----_0000b
IP3H
----_0000b
----_0000b
----_0000b
----_0000b
----_0000b
PSW
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
I2CCON
-000_00--b
-000_00--b
-000_00--b
-000_00--b
-000_00--b
Rev. 1.00
90 of 226
May 15, 2013
Reset and Initialisation
WDTCR Reset
S1RELL
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Register Name
LVR Reset
LVRCR Reset
Comparator0 Reset
MCD Reset
1111_1111b
1111_1111b
1111_1111b
1111_1111b
1111_1111b
I2CDAT
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
I2CADR
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
SBRCON
00--_----b
00--_----b
00--_----b
00--_----b
00--_----b
I2CSTA
1111 _ 1 - - - b
1111 _ 1 - - - b
1111 _ 1 - - - b
1111 _ 1 - - - b
1111 _ 1 - - - b
CP0CR
-000_100-b
-000_100-b
-000_100-b
-000_100-b
-000_100-b
CP1CR
-000_1---b
-000_1---b
-000_1---b
-000_1---b
-000_1---b
ACC
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
SPSTA
0000_----b
0000_----b
0000_----b
0000_----b
0000_----b
FMSR
0---_0000b
0---_0000b
0---_0000b
0---_0000b
0---_0000b
SPDAT
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
IP1
--00_0000b
--00_0000b
--00_0000b
--00_0000b
--00_0000b
IP1H
--00_0000b
--00_0000b
--00_0000b
--00_0000b
--00_0000b
IP2
----_-000b
----_-000b
----_-000b
----_-000b
----_-000b
IP2H
----_-000b
----_-000b
----_-000b
----_-000b
----_-000b
SPCON
0001_0100b
0001_0100b
0001_0100b
0001_0100b
0001_0100b
I2CLK
0001_1001b
0001_1001b
0001_1001b
0001_1001b
0001_1001b
LVRCR
0101_0101b
uuuu_uuuub
0101_0101b
0101_0101b
0101_0101b
LVDCR
0---_-000b
0---_-000b
0---_-000b
0---_-000b
0---_-000b
SCCR
----_--00b
----_--00b
----_--00b
----_--00b
----_--00b
PLLCR
00-0_-000b
00-0_-000b
00-0_-000b
00-0_-000b
00-0_-000b
LSOCR
---1_--0-b
---1_--0-b
---1_--0-b
---1_--0-b
---1_--0-b
HSOCR
--01_--01b
--01_--01b
--01_--01b
--01_--01b
--01_--01b
B
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
ADCR0
0110_0000b
0110_0000b
0110_0000b
0110_0000b
0110_0000b
ADCR1
00-0_0000b
00-0_0000b
00-0_0000b
00-0_0000b
00-0_0000b
ADCR2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
ADPGA
----_-000b
----_-000b
----_-000b
----_-000b
----_-000b
ADRL(ADRFS=0)
0000_----b
0000_----b
0000_----b
0000_----b
0000_----b
ADRH(ADRFS=0)
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
SRST
----_---0b
----_---0b
----_---0b
----_---0b
----_---0b
FMCR
01--_-000b
01--_-000b
01--_-000b
01--_-000b
01--_-000b
FMKEY
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
FMAR0
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
FMAR1
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
FMAR2
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
FMDR
0000_0000b
0000_0000b
0000_0000b
0000_0000b
0000_0000b
T2CON1
---u_10--b
---u_10--b
---u_10--b
---u_10--b
---1_10--b
RSTSRC
-010_0000b
-000_0100b
-100_0000b
-000_1000b
-001_0000b
Note: "-" not implement
"u" stands for "unchanged"
"x" stands for "unknown"
Rev. 1.00
91 of 226
May 15, 2013
Reset and Initialisation
WDTCR Reset
P5
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
25
Interrupts
Interrupt Registers
Overall interrupt control, which means interrupt enabling, priority and request flag setting, is
controlled using several registers. By controlling the appropriate enable bits in these registers each
individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding
request flag will be automatically set by the microcontroller. The global enable control bit if cleared
to zero will disable all interrupts.
Overall interrupt control, which basically means the setting of request f lags when certain
microcontroller conditions occur and the setting of interrupt enable bits by the application program,
is controlled by a series of registers, located in the Special Function Registers , as shown in the
accompanying table. Each register contains a number of enable bits to enable or disable individual
registers as well as interrupt flags to indicate the presence of an interrupt request.
Interrupt Register Bit Naming Conventions
Function
Global
Comparator
INTn Pin
A/D Converter
Request Flag
Notes
EAL
—
ECMP
CMPF
Overall Comparator Interrupt
CP0IEN
CP0IF
Comparator 0 Interrupt
CP1IEN
CP1IF
EXn
—
Comparator 1 Interrupt
IEn
n=0~1
IEXn
n=2~6
EADC
IADC
—
Time Base
ETB
TBF
—
I 2C
EI2C
SI
—
SPI
ESPI
SPIF
WCOL
SSERR
MODF
The same interrupt vector with INT2
LVD
ELVD
LVDF
ESn
RI0/TI0, RI1/TI1
n=0~1
ETn
TFn
n=0~3
EXEN2
EXF2
UART n
Timer n
Timer 2 External Reload
Rev. 1.00
Enable Bit
92 of 226
—
—
May 15, 2013
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an
internal function such as a Timer/Event Counter or Time Base requires microcontroller attention,
their corresponding interrupt will enforce a temporary suspension of the main program allowing
the microcontroller to direct attention to their respective needs. These devices contain multiple
external interrupt pins, while the internal interrupts are generated by the various functions such as
Timer/Event Counters, Time Base, Comparator, LVD, I2C, SPI, UART and the A/D converter. In
addition, the interrupt priority can be controlled using registers.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Interrupt Register Contents
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IEN0
EAL
(WDT)
ET2
ES0
ET1
EX1
ET0
EX0
IEN1
EXEN2
(SWDT)
ET3
ECMP
EX6
EX5
EX4
EX3
IEN2
—
—
—
—
—
ES1
ELVD
EX2
IEN3
—
—
—
—
ETB
EADC
EI2C
ESPI
EXF2
TF2
IEX6
IEX5
IEX4
IEX3
IEX2
—
—
—
—
—
LVDF
TBF
CMPF
IADC
S0CON
(SM0)
(SM1)
(SM20)
(REN0)
(TB80)
(RB80)
TI0
RI0
S1CON
(SM)
—
(SM21)
(REN1)
(TB81)
(RB81)
TI1
RI1
TCON
TF1
(TR1)
TF0
(TR0)
IE1
IT1
IE0
IT0
T2CON
—
I3FR
I2FR
(T2R1)
(T2R0)
(T2CM)
(T2I1)
(T2I0)
T3CON
(GATE3)
(C/T3)
(T3M1)
(T3M0)
—
—
TF3
(TR3)
SPSTA
SPIF
WCOL
SSERR
MODF
—
—
—
—
CPICR
CP1IF
CP1IEN
CP1P1
CP1P0
CP0IF
CP0IEN
CP0P1
CP0P0
I2CCON
—
(ENSI)
(STA)
(STO)
SI
(AA)
—
—
Note: The bits in brackets are used to manage other functions and not related to the interrupt control.
IEN0 Register
SFR Address: A8h
Bit
7
6
5
4
3
2
1
0
Name
EAL
WDT
ET2
ES0
ET1
EX1
ET0
EX0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
EAL: Master interrupt global enable
0: Disable
1: Enable
WDT: Watchdog timer refresh flag
Described elsewhere
ET2: Timer 2 interrupt enable
0: Disable
1: Enable
ES0: UART0 interrupt enable
0: Disable
1: Enable
ET1: Timer 1 interrupt enable
0: Disable
1: Enable
EX1: External interrupt 1 enable
0: Disable
1: Enable
ET0: Timer 0 interrupt enable
0: Disable
1: Enable
EX0: External interrupt 0 enable
0: Disable
1: Enable
93 of 226
May 15, 2013
Interrupts
IRCON
IRCON2
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
IEN1 Register
SFR Address: A9h
Bit
7
6
Name
EXEN2
R/W
R/W
POR
0
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4
3
2
1
0
SWDT
ET3
ECMP
EX6
EX5
EX4
EX3
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
2
1
0
EXEN2: Timer 2 external reload interrupt enable
0: Disable
1: Enable
SWDT: Watchdog timer start/refresh flag
Described elsewhere
ET3: Timer3 interrupt enable
0: Disable
1: Enable
ECMP: Comparator overall interrupt enable
0: Disable
1: Enable
EX6: External interrupt 6 enable
0: Disable
1: Enable
EX5: External interrupt 5 enable
0: Disable
1: Enable
EX4: External interrupt 4 enable
0: Disable
1: Enable
EX3: External interrupt 3 enable
0: Disable
1: Enable
Interrupts
Bit 6
5
IEN2 Register
SFR Address: 9Ah
Bit
6
5
4
3
Name
—
—
—
—
—
ES1
ELVD
EX2
R/W
—
—
—
—
—
R/W
R/W
R/W
POR
—
—
—
—
—
0
0
0
Bit 7~3
Bit 2
Bit 1
Bit 0
Rev. 1.00
7
Unimplemented, read as “0”
ES1: UART1 interrupt enable
0: Disable
1: Enable
ELVD: LVD interrupt enable
0: Disable
1: Enable
EX2: External interrupt 2 enable
0: Disable
1: Enable
94 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
IEN3 Register
SFR Address: C9h
Bit
6
5
4
3
2
1
0
Name
—
—
—
—
ETB
EADC
EI2C
ESPI
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 2
Bit 1
Bit 0
Unimplemented, read as "0"
ETB: Time Base interrupt enable
0: Disable
1: Enable
EADC: ADC interrupt enable
0: Disable
1: Enable
EI2C: I2C interrupt enable
0: Disable
1: Enable
ESPI: SPI interrupt enable
0: Disable
1: Enable
95 of 226
Interrupts
Bit 7~4
Bit 3
Rev. 1.00
7
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
IRCON Register
SFR Address: C0h
Bit
7
Name
R/W
POR
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
5
4
3
2
1
0
EXF2
TF2
IEX6
IEX5
IEX4
IEX3
IEX2
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
0
0
0
0
0
0
0
—
EXF2: Timer 2 external reload interrupt request flag
0: No request
1: Interrupt request
The EXF2 bit will be set high by a negative transition on the T2EX pin. This bit must
be cleared using the application program. The EXF2 bit will be invalid in the Timer 2
Timer/Counter mode.
TF2: Timer 2 overflow interrupt request flag
0: No request
1: Interrupt request
This bit must be cleared using the application program.
IEX6: External interrupt 6 interrupt request flag
0: No request
1: Interrupt request
This bit is triggered by rising edge of external interrupt INT6. The IEX6 flag also will
be set high when Timer 2 compare mode is enabled and counter value (TH2, TL2)
is equal to Compare/Capture register 3 (CCH3, CCL3). Once the program into the
interrupt subroutine, the IEX6 flag will be cleared by hardware automatically.
IEX5: External interrupt 5 interrupt request flag
0: No request
1: Interrupt request
This bit is triggered by rising edge of external interrupt INT5. The IEX5 flag also will
be set high when Timer 2 compare mode is enabled and counter value (TH2, TL2)
is equal to Compare/Capture register 2 (CCH2, CCL2). Once the program into the
interrupt subroutine, the IEX5 flag will be cleared by hardware automatically.
IEX4: External interrupt 4 interrupt request flag
0: No request
1: Interrupt request
This bit is triggered by rising edge of external interrupt INT4. The IEX4 flag also will
be set high when Timer 2 compare mode is enabled and counter value (TH2, TL2)
is equal to Compare/Capture register 1 (CCH1, CCL1). Once the program into the
interrupt subroutine, the IEX4 flag will be cleared by hardware automatically.
IEX3: External interrupt 3 interrupt request flag
0: No request
1: Interrupt request
This bit is triggered by falling or rising edge of external interrupt INT3. The IEX3 flag
also will be set high when Timer 2 compare mode is enabled and counter value (TH2,
TL2) is equal to Compare/Reload/Capture register (CRCH, CRCL). Once the program
into the interrupt subroutine, the IEX3 flag will be cleared by hardware automatically.
IEX2: External interrupt 2 interrupt request flag
0: No request
1: Interrupt request
This bit is triggered by falling or rising edge of external interrupt INT2. This bit will be
cleared by hardware automatically.
Unimplemented, read as "0"
96 of 226
May 15, 2013
Interrupts
Bit 6
6
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
IRCON2 Register
SFR Address: BFh
Bit
6
5
4
3
2
1
0
Name
—
—
—
—
LVDF
TBF
CMPF
IDAC
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 2
Bit 1
Bit 0
Unimplemented, read as "0"
LVDF: LVD interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
TBF: Time Base interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
CMPF: Comparator overall interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
IADC: ADC interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
97 of 226
Interrupts
Bit 7~4
Bit 3
Rev. 1.00
7
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
S0CON Register
SFR Address: 98h
Bit
7
6
5
4
3
2
Name
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
0
SM0~SM1: UART 0 mode select bits
Described elsewhere
SM20: Multiprocessor communication enable control
Described elsewhere
REN0: UART 0 serial data reception enable
Described elsewhere
TB80: UART 0 Ninth Transmit bit assignment
Described elsewhere
RB80: UART 0 Ninth Receive bit assignment
Described elsewhere
TI0: UART 0 transmit interrupt flag
0: No request
1: Interrupt request
This bit must be cleared using the application program.
RI0: UART 0 receive interrupt flag
0: No request
1: Interrupt request
This bit must be cleared using the application program.
98 of 226
Interrupts
Bit 5
1
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
S1CON Register
SFR Address: 9Bh
Bit
7
6
5
4
3
2
Name
SM
—
SM21
REN1
TB81
RB81
TI1
RI1
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
—
0
0
0
0
0
0
Bit 7
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
0
SM: UART 1 operating mode select bit
Described elsewhere
Unimplemented, read as "0"
SM21: Multiprocessor communication enable control
Described elsewhere
REN1: UART 1 serial data reception enable
Described elsewhere
TB81: UART 1 Ninth Transmit bit assignment
Described elsewhere
RB81: UART 1 Ninth Receive bit assignment
Described elsewhere
TI1: UART 1 transmit interrupt flag
0: No request
1: Interrupt request
This bit must be cleared using the application program.
RI1: UART 1 receive interrupt flag
0: No request
1: Interrupt request
This bit must be cleared using the application program.
99 of 226
Interrupts
Bit 6
Bit 5
1
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
TCON Register
SFR Address: 88h
Bit
6
5
4
3
2
1
0
Name
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TF1: Timer 1 interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
TR1: Timer 1 Run control
Described elsewhere
TF0: Timer 0 interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
TR0: Timer 0 Run control
Described elsewhere
IE1: External interrupt 1 request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
IT1: External interrupt 1 type control
0: Falling Edge
1: Low Level
IE0: External interrupt 0 request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
IT0: External interrupt 0 type control
0: Falling Edge
1: Low Level
100 of 226
Interrupts
Bit 6
Rev. 1.00
7
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
T2CON Register
SFR Address: C8h
Bit
7
6
5
4
3
2
1
0
Name
—
I3FR
I2FR
T2R1
T2R0
T2CM
T2I1
T2I0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 5
Bit 4~3
Bit 2
Bit 1~0
Unimplemented, read as "0"
I3FR: Active edge selection for external interrupt “INT3” and PCA module 0
Compare and Capture functions
0: Falling edge
1: Rising edge
This bit is used to select the external interrupt triggered edge for INT3, the PCA Module
0 Compare mode output interrupt triggered edge and the PCA Module 0 Capture mode
input triggered edge. Once the compare mode is enabled, the PCA interrupt will replace
the external interrupt. When Timer 2 is selected as compare mode 0, the I3FR bit is
recommended to be set high by firmware.
I2FR: Active edge selection for external interrupt “INT2”
0: Falling edge
1: Rising edge
T2R1, T2R0: Timer 2 reload mode selection
Described elsewhere
T2CM: Timer 2 Compare mode selection
Described elsewhere
T2I1, T2I0: Timer 2 input selection
Described elsewhere
T3CON Register
SFR Address: A1h
Bit
7
6
5
4
3
2
1
0
Name
GATE3
C/T3
T3M1
T3M0
—
—
TF3
TR3
R/W
R/W
R/W
R/W
R/W
—
—
R/W
R/W
POR
0
0
0
0
—
—
0
0
Bit 7
Bit 6
Bit 5~4
Bit 3~2
Bit 1
Bit 0
Rev. 1.00
GATE3: Timer 3 Gate Control
Described elsewhere
C/T3: Timer 3 Counter/Timer selection
Described elsewhere
T3M1, T3M0: Timer 3 mode selection
Described elsewhere
Unimplemented, read as "0"
TF3: Timer 3 interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
TR3: Timer 3 run flag
Described elsewhere
101 of 226
May 15, 2013
Interrupts
Bit 7
Bit 6
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
SPSTA Register
SFR Address: E1h
Bit
7
6
5
4
3
2
1
0
Name
SPIF
WCOL
SSERR
MODF
—
—
—
—
R/W
R/W
R/W
R/W
R/W
—
—
—
—
POR
0
0
0
0
—
—
—
—
Bit 7
Bit 5
Bit 4
Bit 3~0
Rev. 1.00
102 of 226
May 15, 2013
Interrupts
Bit 6
SPIF: SPI Transmit/Receive Complete flag
0: Data is being transferred
1: SPI data transmission completed
The SPIF bit is the Transmit/Receive Complete flag and is set high automatically when
an SPI data transmission is completed, it must be cleared using the application program.
The SPIF bit can be also cleared by hardware when the data transfer is in progress. It
can also be used to generate an interrupt.
WCOL: SPI Write Collision flag
0: No collision
1: Collision
The WCOL flag is used to detect if a data collision has occurred. If this bit is high it
means that data has been attempted to be written to the SPDAT register during a data
transfer operation. An SPI interrupt will occur if the SPI interrupt function is enabled.
This write operation will be ignored if data is being transferred. It must be cleared using
the application program.
SSERR: Synchronous Serial Slave Error Flag
0: No error
1: Error
This bit is set by hardware when the SSN pin input is selected to disable the Slave
device status while the receive sequence is incomplete. A SPI interrupt will occur if the
SPI interrupt function is enabled. This bit will be cleared by disabling the SPI module,
clearing the SPEN bit in the SPCON register.
MODF: SPI Master/Slave Mode Mismatch Flag
0: No Mismatch
1: Mismatch
This bit is set by hardware when the Slave Select SSN pin level conflicts with actual
Master/Slave mode of the SPI Master controller which is configured as a master while
externally selected as a slave. A SPI interrupt will occur if the SPI interrupt function is
enabled. It must be cleared using the application program.
Unimplemented, read as "0"
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
CPICR Register
SFR Address: BEh
Bit
7
6
5
4
3
2
1
0
Name
CP1IF
CP1IEN
CP1P1
CP1P0
CP0IF
CP0IEN
CP0P1
CP0P0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 5~4
Bit 3
Bit 2
Bit 1~0
Rev. 1.00
103 of 226
May 15, 2013
Interrupts
Bit 6
CP1IF: Comparator 1 Output Transition Interrupt Request Flag
0: No request
1: Interrupt request
This bit should be cleared using the application program.
CP1IEN: Comparator 1 Output Transition Interrupt Enable
0: Disable
1: Enable
CP1P1, CP1P0: Comparator 1 Output Transition Setting for interrupt request
00: Interrupt disabled
01: High to low
10: Low to high
11: High to low or low to high
CP0IF: Comparator 0 Output Transition Interrupt Request Flag
0: No request
1: Interrupt request
This bit should be cleared using the application program.
CP0IEN: Comparator 0 Output Transition Interrupt Enable
0: Disable
1: Enable
CP0P1, CP0P0: Comparator 0 Output Transition Setting for interrupt request
00: Interrupt disabled
01: High to low
10: Low to high
11: High to low or low to high
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I2CCON Register
SFR Address: D8h
Bit
7
6
5
4
3
2
1
0
Name
—
ENS1
STA
STO
SI
AA
—
—
R/W
—
R/W
R/W
R/W
R
R
—
—
POR
—
0
0
0
0
0
—
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1~0
Unimplemented, read as "0"
ENS1: I2C Enable Control
Described elsewhere
STA: I2C Start flag
Described elsewhere
STO: I2C Stop flag
Described elsewhere
SI: I2C Interrupt Request flag
0: No request
1: Interrupt request
The SI bit is set by hardware when one of the 25 possible I2C states takes place. This bit
must be cleared using the application program.
AA: I2C Acknowledge Indication flag
Described elsewhere
Unimplemented, read as "0"
Interrupt Operation
A Timer Counter overflow, an active edge or level on the external interrupt pin, a comparator
output changes state or A/D conversion completion etc, will all generate an interrupt request by
setting their corresponding request flag. When this happens, if the interrupt enable bit is set, then
the Program Counter, which stores the address of the next instruction to be executed, will be
transferred onto the stack. The Program Counter will then be loaded with a new address which
will be the value of the corresponding interrupt vector. The microcontroller will begin then fetch
its next instruction from this interrupt vector. The instruction at this vector will jump to another
section of program which is known as the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service routine must be terminated with a RETI
instruction, which retrieves the original Program Counter address from the stack and allows the
microcontroller to continue with normal execution at the point where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
following diagram with their order of priority. The interrupts are assigned into groups. Interrupts
with higher priority can stop lower priority ones. All interrupts are categorised into 19 groups and
4 priority levels, setup using the IP0 and IP1 registers.
Rev. 1.00
104 of 226
May 15, 2013
Interrupts
Bit 7
Bit 6
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Legend
Request Flag – no auto reset in ISR
xxx
Request Flag – auto reset in ISR
Exx
Enable Bit
Interrupt
Name
Request
Flags
Enable
Bits
Comparator 0 CP0IF
CP0IEN
Comparator 1 CP1IF
CP1IEN
Request
Flags
Enable
Bits
�aster
Enable
INT0 Pin
IE0
EX0
EAL
0�H
Timer 0
TF0
ET0
EAL
0BH
INT1 Pin
IE1
EX1
EAL
1�H
Timer 1
TF1
ET1
EAL
1BH
UART 0
RI0/TI0
ES0
EAL
��H
Timer �
TF�/EXF�
ET�/EXEN�
EAL
�BH
ESPI
EAL
��H
SPI
SPIF
SPI
WCOL
Vector
SPI
SSERR
SPI
�ODF
I�C
SI
EI�C
EAL
�BH
INT�/CCU0
IEX�
EX�
EAL
4�H
INT4/CCU1
IEX4
EX4
EAL
4BH
INT�/CCU�
IEX�
EX�
EAL
��H
INT6/CCU�
IEX6
EX6
EAL
�BH
EC�P
EAL
6�H
Comparator C�PF
Timer �
TF�
ET�
EAL
6BH
ADC
IADC
EADC
EAL
7�H
Time Base
TBF
ETB
EAL
7BH
INT� Pin
IEX�
EX�
EAL
8�H
LVD
LVDF
ELVD
EAL
8BH
UART 1
RI1/TI1
ES1
EAL
9�H
Priorit�
High
Interrupts
xxx
Interrupt
Name
Low
Interrupt Structure
Rev. 1.00
105 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
When an interrupt request is generated, it takes several instruction cycles before the program jumps
to the interrupt vector.
�ain
Program
Interrupt Request or
Interrupt Flag Set b� Instruction
N
Enable Bit Set ?
Y
Automaticall� Disable Interrupt
Clear EAL & Request Flag
�ain
Program
Wait for � s�stem clocks
ISR Entr�
…
…
RETI
(it will set EAL automaticall�)
Interrupt Flowchart
Rev. 1.00
106 of 226
May 15, 2013
Interrupts
Once an interrupt subroutine is serviced, all the other interrupts must be blocked by clearing
the EAL bit using the application program. This will prevent any further interrupt nesting from
occurring. However, if other interrupt requests occur during this interval, although the interrupt
will not be immediately serviced, the request flag will still be recorded. If an interrupt requires
immediate servicing while the program is already in another interrupt service routine, the EAL bit
should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack must be prevented from becoming full.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Interrupt Priority
If the priority level is the same for different groups, then an internal polling sequence determines
which interrupt request is serviced. The polling sequence is based on the vector address; an
interrupt with a lower vector address has higher priority than an interrupt with a higher vector
address. Note that the polling sequence is only used to resolve interrupt requests of the same
priority level.
Priority Levels
The accompanying table illustrates the interrupt priority level assigned by the corresponding
IPnH.x and IPn.x bits (n=0~3).
IPnH.x
IPn.x
Priority Level
Note
1
1
Level 3
Highest Priority
1
0
Level 2
↓
0
1
Level 1
↓
0
0
Level 0
Lowest Priority
If the interrupt levels are assigned the same priority level by the IPnH.x and IPn.x bits, the interrupt
priority is followed by the accompanying table.
Rev. 1.00
107 of 226
May 15, 2013
Interrupts
In case of simultaneous requests, the following table shows the priority that is applied. The
interrupts can be assigned into groups. Higher priority interrupts can stop the lower priority
interrupts. All interrupts are categorised into 19 groups with 4 priority levels. In cases where
both higher priority and lower priority interrupts are enabled and where a higher priority and
lower priority interrupt occurs simultaneously, the higher priority interrupt will always have
priority and will therefore be serviced first. Suitable masking of the individual interrupts using the
interrupt registers can prevent simultaneous occurrences. Each interrupt source can be individually
programmed to one of four priority levels by setting or clearing bits in the interrupt priority
registers: IP0, IP1, IP2, IP3, IP0H, IP1H, IP2H and IP3H. IP0, IP1, IP2 and IP3 hold the low order
priority bits and IP0H, IP1H, IP2H and IP3H hold the high priority bits for each interrupt.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Interrupt Source
Service
Priority
Priority Control
Group Priority
Reset
0000H
Top
External Interrupt 0 (INT0)
0003H
0
Timer 0 Overflow Interrupt
000BH
1
PT0H(IP0H.1)/PT0(IP0.1)
↓
External Interrupt 1 (INT1)
0013H
2
PX1H(IP0H.2)/PX1(IP0.2)
↓
Timer 1 Overflow Interrupt
001BH
3
PT1H(IP0H.3)/PT1(IP0.3)
↓
Serial Port 0 Interrupt
0023H
4
PS0H(IP0H.4)/PS0(IP0.4)
↓
Timer 2 Overflow Interrupt or Timer 2
External Reload Interrupt
002BH
5
PT2H(IP0H.5)/PT2(IP0.5)
↓
Serial Peripheral Interface Interrupt
0033H
6
PSPIH(IP3H.0)/PSPI(IP3.0)
↓
I2C Interrupt
003BH
7
PI2CH(IP3H.1)/PI2C(IP3.1)
↓
External Interrupt 3 (INT3) or CCU0
Interrupt
0043H
8
PX3H(IP1H.0)/PX3(IP1.0)
↓
External Interrupt 4 (INT4) or CCU1
Interrupt
004BH
9
PX4H(IP1H.1)/PX4(IP1.1)
↓
External Interrupt 5 (INT5) or CCU2
Interrupt
0053H
10
PX5H(IP1H.2)/PX5(IP1.2)
↓
External Interrupt 6 (INT6) or CCU3
Interrupt
005BH
11
PX6H(IP1H.3)/PX6(IP1.3)
↓
Comparator Interrupt (CMP0 & CMP1)
0063H
12
PCMPH(IP1H.4)/PCMP(IP1.4)
↓
Timer 3 Overflow Interrupt
006BH
13
PT3H(IP1H.5)/PT3(IP1.5)
↓
ADC End of Conversion Interrupt
0073H
14
PADCH(IP3H.2)/PADC(IP3.2)
↓
Time Base Overflow Interrupt
007BH
15
PTBH(IP3H.3)/PTB(IP3.3)
↓
External Interrupt 2 (INT2)
0083H
16
PX2H(IP2H.0)/PX2(IP2.0)
↓
LVD Interrupt
008BH
17
PLVDH(IP2H.1)/PLVD(IP2.1)
Serial Port 1 Interrupt
0093H
18
PS1H(IP2H.2)/PS1(IP2.2)
108 of 226
Always Highest
PX0H(IP0H.0)/PX0(IP0.0)
Highest Priority
↓
↓
Lowest Priority
May 15, 2013
Interrupts
Rev. 1.00
Interrupt
Vector
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Priority Control Registers
Low byte of Interrupt Priority Register 0: IP0
SFR Address: B8h
Bit
7
6
5
4
3
2
1
0
Name
—
WDTS
PT2
PS0
PT1
PX1
PT0
PX0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Interrupts
Bit 7
Bit 6
Unimplemented, read as “0”
WDTS: Watchdog timer reset indication flag
Described elsewhere
PT2: Timer 2 Interrupt priority low
Low order bit for Timer 2 interrupt priority level.
PS0: UART 0 Interrupt priority low
Low order bit for UART 0 interrupt priority level.
PT1: Timer 1 Interrupt priority low
Low order bit for Timer 1 interrupt priority level.
PX1: External interrupt 1 priority low
Low order bit for External Interupt 1 interrupt priority level.
PT0: Timer 0 Interrupt priority low
Low order bit for Timer 0 interrupt priority level.
PX0: External interrupt 0 priority low
Low order bit for External Interupt 0 interrupt priority level.
High byte of Interrupt Priority Register 0: IP0H
SFR Address: B9h
Bit
7
6
5
4
3
2
1
0
Name
—
—
PT2H
PS0H
PT1H
PX1H
PT0H
PX0H
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
Unimplemented, read as “0”
PT2H: Timer 2 Interrupt priority high
High order bit for Timer 2 interrupt priority level.
PS0H: UART 0 Interrupt priority high
High order bit for UART 0 interrupt priority level.
PT1H: Timer 1 Interrupt priority high
High order bit for Timer 1 interrupt priority level.
PX1H: External interrupt 1 priority high
High order bit for External Interupt 1 interrupt priority level.
PT0H: Timer 0 Interrupt priority high
High order bit for Timer 0 interrupt priority level.
PX0H: External interrupt 0 priority high
High order bit for External Interupt 0 interrupt priority level.
109 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Low byte of Interrupt Priority Register 1: IP1
SFR Address: E4h
Bit
7
6
5
4
3
2
1
0
Name
—
—
PT3
PCMP
PX6
PX5
PX4
PX3
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unimplemented, read as “0”
PT3: Timer 3 Interrupt priority low
Low order bit for Timer 3 interrupt priority level.
PCMP: Comparator Interrupt priority low
Low order bit for Comparator interrupt priority level.
PX6: External interrupt 6 Interrupt priority low
Low order bit for External interrupt 6 interrupt priority level.
PX5: External interrupt 5 priority low
Low order bit for External Interupt 5 interrupt priority level.
PX4: External interrupt 4 Interrupt priority low
Low order bit for External interrupt 4 interrupt priority level.
PX3: External interrupt 3 priority low
Low order bit for External Interupt 3 interrupt priority level.
Interrupts
Bit 7~6
Bit 5
High byte of Interrupt Priority Register 1: IP1H
SFR Address: E5h
Bit
6
5
4
3
2
1
0
Name
—
—
PT3H
PCMPH
PX6H
PX5H
PX4H
PX3H
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
7
Unimplemented, read as “0”
PT3H: Timer 3 Interrupt priority high
High order bit for Timer 3 interrupt priority level.
PCMPH: Comparator Interrupt priority high
High order bit for Comparator interrupt priority level.
PX6H: External interrupt 6 Interrupt priority high
High order bit for External interrupt 6 interrupt priority level.
PX5H: External interrupt 5 priority high
High order bit for External Interupt 5 interrupt priority level.
PX4H: External interrupt 4 Interrupt priority high
High order bit for External interrupt 4 interrupt priority level.
PX3H: External interrupt 3 priority high
High order bit for External Interupt 3 interrupt priority level.
110 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Low byte of Interrupt Priority Register 2: IP2
SFR Address: E6h
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
PS1
PLVD
PX2
R/W
—
—
—
—
—
R/W
R/W
R/W
POR
—
—
—
—
—
0
0
0
Bit 1
Bit 0
Unimplemented, read as “0”
PS1: UART 1 priority low
Low order bit for UART 1 interrupt priority level.
PLVD: LVD Interrupt priority low
Low order bit for LVD interrupt priority level.
PX2: External interrupt 2 priority low
Low order bit for External Interupt 2 interrupt priority level.
Interrupts
Bit 7~3
Bit 2
High byte of Interrupt Priority Register 2: IP2H
SFR Address: E7h
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
PS1H
PLVDH
PX2H
R/W
—
—
—
—
—
R/W
R/W
R/W
POR
—
—
—
—
—
0
0
0
Bit 7~3
Bit 2
Bit 1
Bit 0
Unimplemented, read as “0”
PS1H: UART 1 priority high
High order bit for UART 1 interrupt priority level.
PLVDH: LVD Interrupt priority high
High order bit for LVD interrupt priority level.
PX2H: External interrupt 2 priority high
High order bit for External Interupt 2 interrupt priority level.
Low byte of Interrupt Priority Register 3: IP3
SFR Address: CEh
Bit
6
5
4
3
2
1
0
Name
—
—
—
—
PTB
PADC
PI2C
PSPI
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 7~4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
7
Unimplemented, read as “0”
PTB: Time Base Interrupt Priority low
Low order bit for Time Base Interrupt Priority level.
PADC: ADC Interrupt priority low
Low order bit for ADC interrupt priority level.
PI2C: I2C Interrupt priority low
Low order bit for I2C interrupt priority level.
PSPI: SPI Interrupt priority low
Low order bit for SPI interrupt priority level.
111 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
How byte of Interrupt Priority Register 3: IP3H
SFR Address: CFh
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
PTBH
PADCH
PI2CH
PSPIH
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit 2
Bit 1
Bit 0
Unimplemented, read as “0”
PTBH: Time Base Interrupt Priority high
High order bit for Time Base Interrupt Priority level.
PADCH: ADC Interrupt priority high
High order bit for ADC interrupt priority level.
PI2CH: I2C Interrupt priority high
High order bit for I2C interrupt priority level.
PSPIH: SPI Interrupt priority high
High order bit for SPI interrupt priority level.
Interrupts
Bit 7~4
Bit 3
External Interrupt
The external interrupt pins are pin-shared with the I/O pins and can be configured as an external
interrupt pin if the corresponding external interrupt enable bits in the interrupt control registers
have been set. The pin must also be setup as an input by setting the corresponding bits in the
port mode register. Any pull-high resistor settings will also remain valid when the pin is used as
an external interrupt pin. When the interrupt is enabled, the stack is not full and a falling edge,
a rising edge or a high to low level transition appears on the external interrupt pin, a subroutine
call to the external interrupt vector, will take place. When the interrupt is serviced, the external
interrupt request flag will be automatically reset and the EAL bit must be cleared by the application
program to disable other interrupts.
The IT0, IT1, I2FR and I3FR bits are used to select the type of active edge that will trigger the
external interrupt for INT0, INT1, INT2 and INT3 respectively. The other external interrupts,
INT4, INT5 and INT6, are triggered with a rising edge signal.
External Interrupt Trigger Type
Ext Int
Rev. 1.00
Trigger Type
Register
Bit
IT0
INT0
Falling Edge or Low Level
TCON
INT1
Falling Edge or Low Level
TCON
IT1
INT2
Falling Edge or Rising Edge
T2CON
I2FR
INT3
Falling Edge or Rising Edge
T2CON
I3FR
INT4
Rising Edge
—
—
INT5
Rising Edge
—
—
INT6
Rising Edge
—
—
112 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Comparator Interrupt
CPICR Register
SFR Address: BEh
Bit
7
6
5
4
3
2
1
0
Name
CP1IF
CP1IEN
CP1P1
CP1P0
CP0IF
CP0IEN
CP0P1
CP0P0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5~4
Bit 3
Bit 2
Bit 1~0
Rev. 1.00
CP1IF: Comparator 1 Output Transition Interrupt Request Flag
0: No request
1: Interrupt request
This bit must be cleared using the application program.
CP1IEN: Comparator 1 Output Transition Interrupt Enable
0: Disable
1: Enable
CP1P1, CP1P0: Comparator 1 Output Transition Setting for interrupt request
00: Interrupt disabled
01: High to low
10: Low to high
11: High to low or low to high
CP0IF: Comparator 0 Output Transition Interrupt Request Flag
0: No request
1: Interrupt request
This bit must be cleared using the application program.
CP0IEN: Comparator 0 Output Transition Interrupt Enable
0: Disable
1: Enable
CP0P1, CP0P0: Comparator 0 Output Transition Setting for interrupt request
00: Interrupt disabled
01: High to low
10: Low to high
11: High to low or low to high
113 of 226
May 15, 2013
Interrupts
The comparator interrupts are controlled by the two internal comparators. A comparator interrupt
request will take place when the comparator interrupt request flag, CPnIF, is set, a situation
that will occur when one of the comparator output bits changes state. This will in turn cause the
comparator overall request flag, CMPF, to go high. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EAL, individual comparator enable bit,
CPnIEN, and overall comparator interrupt enable bit, ECMP, must first be set. When the interrupt
is enabled, the stack is not full and the comparator inputs generate a comparator output transition,
a subroutine call to the comparator interrupt vector, will take place. When the interrupt is serviced,
the CP0IF and CP1IF bits can be examined to determine whether the interrupt was generated by
Comparator 0 or Comparator 1. In addition, the comparator output transition interrupt can be set
up by the CPICR control register. Note that the comparator overall request flag, CMPF, will be
automatically cleared, however the individual comparator interrupt request flags, CPnIF, must be
cleared by the application program. The EAL bit must be cleared by the application program to
disable other interrupts when in the interrupt routine.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
A/D Converter Interrupt
Timer/Counter Interrupt
For a Timer Counter interrupt to occur, the global interrupt enable bit, EAL, and the corresponding
timer interrupt enable bit, ETn, must first be set. An actual Timer Counter interrupt will take place
when the Timer Counter request flag, TFn, is set, a situation that will occur when the relevant
Timer Counter overflows. When the interrupt is enabled, the stack is not full and a Timer Counter
n overflow occurs, a subroutine call to the relevant timer interrupt vector, will take place. When the
interrupt is serviced, the timer interrupt request flag, TFn (n=0, 1, 3), will be automatically reset,
while the TF2 bit must be cleared by the application program, and the EAL bit must also be cleared
using the application program to disable other interrupts.
Time Base Interrupts
The function of the Time Base Interrupt is to provide a regular time signal in the form of an
internal interrupt. It is basically a simple timer whose interrupt is generated when it overflows.
When this happen its respective interrupt request flag, TBF will be set. To allow the program to
branch to its respective interrupt vector address, the global interrupt enable bit, EAL and Time
Base enable bit, ETB, must first be set. When the interrupt is enabled, the stack is not full and the
Time Base overflows, a subroutine call to its respective vector locations will take place. When the
interrupt is serviced, the respective interrupt request flag, TBF, will be automatically reset but the
EAL bit must be cleared by the application program to disable other interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their
clock sources originate from the internal clock source f TBC. This f TBC input clock passes through a
divider, the division ratio of which is selected by programming the appropriate bits in the TBCR
register to obtain longer interrupt periods. The clock source that generates f TBC, which in turn controls
the Time Base interrupt period, can originate from the system clock, LIRC or LXT oscillator.
fSYS/4
fSYS/128
f32K
M
U
X
fTBC
TBCK[1:0]
÷28~215
Time Base Interrupt
TBS[2:0]
Time Base Clock Source Select
Rev. 1.00
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May 15, 2013
Interrupts
The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An
A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag,
IADC, is set, which occurs when the A/D conversion process finishes. To allow the program to
branch to its respective interrupt vector address, the global interrupt enable bit, EAL, and A/D
Interrupt enable bit, EADC, must first be set. When the interrupt is enabled, the stack is not full
and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector,
will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, IADC, will be
automatically cleared. The EAL bit must be cleared by the application program to disable other
interrupts.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
TBCR Register
SFR Address: B2h
Bit
7
Name
R/W
POR
Bit 7
Bit 3
Bit 2~0
5
4
3
2
1
0
TBEN
—
TBCK1
R/W
—
R/W
TBCK0
—
TBS2
TBS1
TBS0
R/W
—
R/W
R/W
0
—
0
R/W
0
—
1
1
1
TBEN: TB Control bit
0: Disable
1: Enable
Unimplemented, read as “0”
TBCK1~TBCK0: Select Time Base clock source, f TBC
00: f SYS/4
01: f SYS/128
1x: f 32K (f 32K is sourced from f LIRC or f LXT)
Unimplemented, read as “0”
TBS2~TBS0: Select Time Base Time-out Period
000: 256/f TBC
001: 512/f TBC
010: 1024/f TBC
011: 2048/f TBC
100: 4096/f TBC
101: 8192/f TBC
110: 16384/f TBC
111: 32768/f TBC (default setting)
Interrupts
Bit 6
Bit 5~4
6
I2C Interface Interrupt
An I2C Interrupt request will take place when the I2C Interrupt request flag, SI, is set, which occurs
when one of the 25 possible I2C states takes place. To allow the program to branch to its respective
interrupt vector address, the global interrupt enable bit, EAL, and the I2C Interface Interrupt enable
bit, EI2C, must first be set. When the interrupt is enabled, the stack is not full and a byte of data
has been compared match with the I2C states, a subroutine call to the respective Interrupt vector,
will take place. When the I2C Interface Interrupt is serviced, the EAL bit must be cleared by the
application program to disable other interrupts, and the SI flag also must be cleared using the
application program.
Rev. 1.00
115 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
SPI Interface Interrupt
UART Interface Interrupt
A UARTn Interrupt request will take place when the UARTn Interrupt request flags, RIn or TIn, is
set, which occurs when a byte of data has been received or transmitted by the UARTn interface. To
allow the program to branch to its respective interrupt vector address, the global interrupt enable
bit, EAL, and the UART Interrupt enable bit, ESn, must first be set. When the interrupt is enabled,
the stack is not full and a byte of data has been transmitted or received by the UARTn interface,
will take place. When the UARTn Interface Interrupt is serviced, the EAL bit must be cleared by
the application program to disable other interrupts, and the RIn or TIn flag also must be cleared
using the application program.
LVD Interrupt
A LVD Interrupt request will take place when the LVD Interrupt request flag, LVDF, is set, which
occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the
program to branch to its respective interrupt vector address, the global interrupt enable bit, EAL,
Low Voltage Interrupt enable bit, ELVD, must first be set. When the interrupt is enabled, the stack
is not full and a low voltage condition occurs, a subroutine call to the Interrupt vector, will take
place. When the Low Voltage Interrupt is serviced, the EAL bit will be automatically cleared to
disable other interrupts and the LVDF flag will be automatically cleared.
Rev. 1.00
116 of 226
May 15, 2013
Interrupts
A SPI Interrupt request will take place when one of the SPI Interrupt request flags, SPIF, WCOL,
SSERR or MODF, is set, which occurs when a byte of data has been received or when there is
a write collision or when there is a Serial Slave error or transmitted by the SPI interface or the
Master mode or Slave mode is mismatched with the mode selected input pin level. To allow the
program to branch to its respective interrupt vector address, the global interrupt enable bit, EAL,
and the Serial Interface Interrupt enable bit, ESPI, must first be set. When the interrupt is enabled,
the stack is not full and a byte of data has been transmitted or received by the SPI interface, or the
Mode mismatch, a subroutine call to the respective Interrupt vector, will take place. When the SPI
Interface Interrupt is serviced, the EAL bit must be cleared by the application program to disable
other interrupts, and the SPIF, WCOL, SSERR and MODF flags also must be cleared using the
application program.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Interrupt Wake-up Function
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the interrupt
register until the corresponding interrupt is serviced or until the request flag is cleared by the
application program.
It is recommended that programs do not use the “CALL subroutine” instruction within the interrupt
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately
in some applications. If only one stack is left and the interrupt is not well controlled, the original
control sequence will be damaged once a “CALL” subroutine is executed in the interrupt
subroutine.
All these interrupt functions have the capability of waking up the microcontroller when in
the IDLE mode, only INT0 and INT1 interrupts can wake up the microcontroller when in the
Power-down mode.
Only the Program Counter is pushed onto the stack. If the contents of the register or status register
are altered by the interrupt service program, which may corrupt the desired control sequence, then
the contents should be saved in advance.
Rev. 1.00
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May 15, 2013
Interrupts
Each of the interrupt functions has the capability of waking up the microcontroller when in the
IDLE mode, and only INT0 and INT1 interrupts can wake up the microcontroller when in the
Power-down mode. A wake-up is generated when an interrupt request flag changes from low
to high and is independent of whether the interrupt is enabled or not. Therefore, even though
the device is in the Power-Down or IDLE Mode and the CPU clock stopped, situations such as
external edge transitions on the external interrupt pins, a low power supply voltage or comparator
input change may cause their respective interrupt flag to be set high and consequently generate
an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an
interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be
set high before the device enters the Power-Down or IDLE Mode. The interrupt enable bits have no
effect on the interrupt wake-up function.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
26
Input/Output Ports
The devices offer a range of flexible options on their I/O ports. Many pins can be setup with a
choice of different register controlled modes as well as having pull-high wake up and slew rate
functions.
The devices are provided with a series bidirectional input/output ports labeled with port names
P0~P5. These I/O ports are mapped to the Special Function Registers with specific addresses as
shown in the Special Function Registers table. All of these I/O ports can be used for both input and
output operations, the data for which is stored in Port Data Registers. Ports P0~P3 can be setup
using Port Mode Registers to operate in a series of different modes. Ports 4 and 5 can only operate
in the traditional 8051 type quasi-bidirectional mode. The Port P0 provides register controlled wake
up function as well. Bit manipulation instructions can be used to control Ports P0~P3, while Ports
4 and 5 must be controlled using byte wide instructions.
I/O Port Function Summary
Function.
Rev. 1.00
Port Number
P0
P1
P2
P3
P4
P5
Push-Pull
√
√
√
√
—
—
CMOS Output
Open Drain
√
√
√
√
—
—
NMOS
Quasi Bi-direct
√
√
√
√
√
√
Traditional 8051 Port type
Input Only
√
√
√
√
—
—
High impedance
Bit Addressable
√
√
√
√
—
—
Slew Rate Control
√
√
√
√
√
√
118 of 226
Notes
—
Fast or Slow select
May 15, 2013
Input/Output Ports
Input/Output Port Overview
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Register Description
This section provides a description of all the registers associated with I/O setup and control. The
following table gives a summary of all associated I/O registers, which will be described in detail
later.
I/O Register List
Bit
7
6
5
4
3
2
1
0
P0WAKE
P07WU
P06WU
P05WU
P04WU
P03WU
P02WU
P01WU
P00WU
P0
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
P0M0
P0M0.7
P0M0.6
P0M0.5
P0M0.4
P0M0.3
P0M0.2
P0M0.1
P0M0.0
P0M1
P0M1.7
P0M1.6
P0M1.5
P0M1.4
P0M1.3
P0M1.2
P0M1.1
P0M1.0
P1
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
P1M0
P1M0.7
P1M0.6
P1M0.5
P1M0.4
P1M0.3
P1M0.2
P1M0.1
P1M0.0
P1M1
P1M1.7
P1M1.6
P1M1.5
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0
P2
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
P2M0
P2M0.7
P2M0.6
P2M0.5
P2M0.4
P2M0.3
P2M0.2
P2M0.1
P2M0.0
P2M1
P2M1.7
P2M1.6
P2M1.5
P2M1.4
P2M1.3
P2M1.2
P2M1.1
P2M1.0
P3
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
P3M0
P3M0.7
P3M0.6
P3M0.5
P3M0.4
P3M0.3
P3M0.2
P3M0.1
P3M0.0
P3M1
P3M1.7
P3M1.6
P3M1.5
P3M1.4
P3M1.3
P3M1.2
P3M1.1
P3M1.0
P4
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
P5
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
SRCR
—
—
SRCR.5
SRCR.4
SRCR.3
SRCR.2
SRCR.1
SRCR.0
Each Port has its own data register, known as P0, P1, P2, P3, P4 and P5 which are used to control
the input and output I/O pin data. These registers read input pin data or write output pin data on the
selected I/O pin. For I/O pins setup as outputs a read operation to these registers will setup either
a high or low level on the corresponding pin. For I/O pins setup as inputs a read operation to these
registers will read the actual logic level on the corresponding pin.
P0 Register
SFR Address: 80h
Bit
7
6
5
4
3
2
1
0
Name
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
P1 Register
SFR Address: 90h
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
119 of 226
May 15, 2013
Input/Output Ports
Register
Name
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
P2 Register
SFR Address: A0h
Bit
7
6
5
4
3
2
1
0
Name
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
Name
P3.7
P3.6
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
P4 Register
SFR Address: B1h
Bit
7
6
5
4
3
2
1
0
Name
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
P5 Register
SFR Address: D9h
Bit
7
6
5
4
3
2
1
0
Name
P5.7
P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit 7~0
Rev. 1.00
I/O Port bit 7~bit 0 Input/Output Data Control
During reading and writing of data to these registers, what actually happens is
dependent upon whether the corresponding pin is setup as an output or input.
Register Write Operations
A write operation is only effective when the corresponding pin is setup as an output. In
such cases a write operation will setup the logic level on the pin as follows:
0: Output low
1: Output high
Register Read Operations
A read operation will read the current logic level on the corresponding pin.
0: Read low level
1: Read high level
120 of 226
May 15, 2013
Input/Output Ports
P3 Register
SFR Address: B0h
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
PnM0/PnM1 Registers – Port Mode Registers
These registers only exist for Ports 0~3. They are used to setup the I/O operating mode of each pin.
As there are four different operating modes for the Port 0~3 pins, each pin has two bits to select
the mode, known as the PnM0 and PnM1 bits. As Ports 4 and 5 only have a single operating mode,
they do not have port mode registers.
Bit
7
6
5
4
3
2
1
0
Name
P0M0.7
P0M0.6
P0M0.5
P0M0.4
P0M0.3
P0M0.2
P0M0.1
P0M0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
P0M1 Register
SFR Address: 9Fh
Bit
7
6
5
4
3
2
1
0
Name
P0M1.7
P0M1.6
P0M1.5
P0M1.4
P0M1.3
P0M1.2
P0M1.1
P0M1.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Port 1 Mode Control
P1M0 Register
SFR Address: A6h
Bit
7
6
5
4
3
2
1
0
Name
P1M0.7
P1M0.6
P1M0.5
P1M0.4
P1M0.3
P1M0.2
P1M0.1
P1M0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
P1M1 Register
SFR Address: A7h
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
P1M1.7
P1M1.6
P1M1.5
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
121 of 226
May 15, 2013
Input/Output Ports
Port 0 Mode Control
P0M0 Register
SFR Address: 9Eh
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Port 2 Mode Control
P2M0 Register
SFR Address: AEh
Bit
7
6
5
4
3
2
1
0
Name
P2M0.7
P2M0.6
P2M0.5
P2M0.4
P2M0.3
P2M0.2
P2M0.1
P2M0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
P2M1.7
P2M1.6
P2M1.5
P2M1.4
P2M1.3
P2M1.2
P2M1.1
P2M1.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Port 3 Mode Control
P3M0 Register
SFR Address: B6h
Bit
7
6
5
4
3
2
1
0
Name
P3M0.7
P3M0.6
P3M0.5
P3M0.4
P3M0.3
P3M0.2
P3M0.1
P3M0.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
P3M1 Register
SFR Address: B7h
Bit
7
6
5
4
3
2
1
0
Name
P3M1.7
P3M1.6
P3M1.5
P3M1.4
P3M1.3
P3M1.2
P3M1.1
P3M1.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
These registers operate as pairs, for example P0M0 and P0M1, to select the operating mode for
each I/O pin. The following table shows how the PnM0 and PnM1 bits are used to select the I/O
operating mode.
PnM0.m
PnM1.m
Configuration of Port n.m
0
0
Quasi-bidirectional
0
1
Push-Pull Output
1
0
Input-Only – High Impedance Input
1
1
Open-Drain Output
Legend: n=0~3 which selects Port 0 to Port 3
m=0~7 which selects the port pin
Rev. 1.00
122 of 226
May 15, 2013
Input/Output Ports
P2M1 Register
SFR Address: AFh
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
P0WAKE Register – Port 0 Wake-up
P0WAKE Register
SFR Address: 91h
Bit
7
6
5
4
3
2
1
0
Name
P07WU
P06WU
P05WU
P04WU
P03WU
P02WU
P01WU
P00WU
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
SRCR Register – Slew Rate Control
SRCR Register
SFR Address: A4h
Bit
7
6
5
4
3
2
1
0
Label
—
—
SRCR.5
SRCR.4
SRCR.3
SRCR.2
SRCR.1
SRCR.0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit 7~6
Bit 5
Unimplemented, read as “0”
SRCR.5: P5 [7:0] Slew Control Enable
0: Fast
1: Slow
Bit 4
SRCR.4: P4 [7:0] Slew Control Enable
0: Fast
1: Slow
Bit 3
SRCR.3: P3 [7:0] Slew Control Enable
0: Fast
1: Slow
Bit 2
SRCR.2: P2 [7:0] Slew Control Enable
0: Fast
1: Slow
Bit 1
SRCR.1: P1 [7:0] Slew Control Enable
0: Fast
1: Slow
Bit 0
SRCR.0: P0 [7:0] Slew Control Enable
0: Fast
1: Slow
The port pins, when setup as outputs, can be selected to have either a fast or slow slew rate. To
minimise noise generation due to fast switching of the output drivers, it may be advisable to select
the slower slew rate. The slew rates are selected port wide, individual pins cannot be selected to
have either fast or slow slew rates.
Rev. 1.00
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Input/Output Ports
P0WAKE: Port 0 bit 7~bit 0 Wake-up Control
0: Disable
1: Enable
When the device enters the IDLE or Power-Down Mode, the system clock will stop resulting in
power being conserved, a feature that is important for battery and other low-power applications.
Various methods exist to wake-up the microcontroller, one of which is to change the logic condition
on one of the P0.0~P0.7 pins to a low level. Note that the Port 0 wake-up functions are triggered
by a low logic level and not by a falling edge. This Port 0 wake-up function is especially suitable
for applications that can be woken up via external switches. The P0 wake up pins can be selected
individually to have this wake-up feature using the P0WAKE, register.
Bit 7~0
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I/O Pin Structures
The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As
the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a
guide only to assist with the functional understanding of the I/O pins.
Quasi-bidirectional I/O – All Ports
A Very Weak pull high resistor will be turned on whenever the I/O port registers, associated with
the I/O pins, contain a high level.
When the I/O port registers has a high level and the corresponding I/O pins stay at high level as
well, the Weak pull high resistor will be turned on. However, if the I/O port registers are high and
the corresponding I/O pins are pulled low by the external devices, then the Weak pull high resistor
will be disabled by hardware. These weak pull-high resistor enable/disable function are dependant
on the voltage level after the I/O pin is connected to the external circuit.
The Strong pull high resistor is used to enhance the output response time. When the output state
changes from low to high, the Strong resistor will be turned on after two system clock delay times.
A Quasi-bidirectional pin also provides a Schmitt Trigger input.
VCC
Two System
Clock Delay
Strong
VCC
Very Weak
VCC
Weak
Port
Pin
Q
Port Register Data
Input
Data
Quasi-bidirectional I/O Structure
Rev. 1.00
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May 15, 2013
Input/Output Ports
This is the traditional 8051 type I/O port type, constructed from an NMOS FET transistor and
three pull high resistors, so called Strong, Weak, Very Weak pull high resistors. This structure can
be used to reduce the power consumption and the output switching state respond time.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Push-pull Output – Ports 0~3 Only
This I/O structure is a standard CMOS type structure with a single NMOS and PMOS complimentary
transistor pair. The input is a Schmitt Trigger type input.
VCC
Input/Output Ports
Strong
Port
Pin
Q
Port Register Data
Input
Data
Push-pull Output Structure
Open-drain Output – Ports 0~3 Only
This I/O structure is an open drain type structure with a Schmitt Trigger input. Usually, an external
pull high resistor is needed for such applications.
Port
Pin
Q
Port Register Data
Input
Data
Open-drain Output Structure
Input Only – Ports 0~3 Only
This Input Only structure is a Schmitt Trigger type input without any pull high resistors.
Input
Data
Port
Pin
Input Only Structure
Rev. 1.00
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May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Programming Considerations
The data registers, P0~P5, reflect the value of the corresponding I/O port, however, they do not
necessarily reflect the I/O pin logic state. During reading and writing of data to these registers,
what actually happens is dependent upon whether the corresponding pin is setup as an output or
input. A write operation is only effective when the corresponding pin is setup as an output. In such
cases a write operation will setup the logic level, low or high, on the pin. A read operation will read
the current logic level, low or high, on the corresponding pin.
If any pins are setup to be used as A/D input pins then it is important to ensure that the I/O Port
Mode registers setup the pins as inputs, which are essentially high impedance inputs. In this way
the I/O logic circuits will have a minimal influence on the A/D input impedance.
When using these bit control instructions, a read-modify-write operation takes place. The
microcontroller must first read in the data on the entire port, modify it to the required new bit
values and then rewrite this data back to the output ports, such as using CLR or SET bit write
instructions. Care should be taken that some instructions, the Read-Modify-Write instructions,
operate on the Pn register, such as “INC P0” or “ANL P2, A”, while others can operate directly
onto the external port input, such as “MOV A, P1”. Note that P4 and P5 cannot be modified by
bit manipulation instructions as their registers are not located in bit addressable space. In case of
reading, the state of P4 and P5 registers reflects the value of the corresponding I/O port.
The accompanying table illustrates the Read-Modify-Write related instructions.
Mnemonic
Rev. 1.00
Instruction
Example
Bit Manipulation
ANL
Logical AND
ANL P3, A
—
ORL
Logical OR
OR P3, A
—
XRL
Logical XOR
XRL P3, A
—
JBC
Jump if bit set and then clear bit
JBC P3.0, (LABEL)
—
CPL
Complement bit
CPL P3.0
—
INC
Increment
INC P3
—
DEC
Decrement
DEC P3
—
DJNZ
Decrement and jump if not zero
DJNZ P3, (LABEL)
—
MOV Px.y, C
Move carry flag to Bit y of Port x
MOV P3.0, C
V
CLR Px.y
Clear Bit y of Port x
CLR P3.0
V
SET Px.y
Set Bit y of Port x
SET P3.0
V
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May 15, 2013
Input/Output Ports
Within the user program, one of the first things to consider is port initialisation. After a reset, the
I/O data register will be set high and I/O port mode registers will be cleared to low. This means that
all I/O pins will default to a Quasi-bidirectional structure. The I/O pins can be re-assigned to some
other mode for each I/O using the control registers, PnM0 and PnM1. Ports P0~P3 provide four I/O
structure modes option while the P4 and P5 only provide a Quasi-bidirectional I/O structure mode.
Care should be taken to setup the correct I/O structure for each I/O pin, otherwise unexpected data
will be input or output on the I/O pins.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
27
Timer/Event Counters
Timer/Event Counter Summary
The devices contain four Timers, namely Timer 0, Timer 1, Timer 2 and Timer 3. Each individual
Timer is 16-bit wide which are composed of two 8-bit registers, TLn and THn. Timers 0, 1 and 3
have similar structures and similar operating modes. Timer 2 has a different structure and is also
known as a Programmable Counter Array, or PCA for short and has functions such as Compare,
Reload and Capture functions, so called CRC, as well a programmable clock output function. All
timers have a clock divider which provides additional range to the timers.
Various Timer control registers determine how each Timer is operated. The clock sources for the
Timers can come from an internal clock source or from an external timer pin. Note that if the
external timer input function is selected, the respective pin-shared I/O pins should be configured as
input pins.
As Timer 0, 1 and 3 have similar structures they will be described together in their own single
chapter, however as Timer 2 has a very different structure it will be described in a separate chapter.
The main features and differences among the Timers are summarised in the accompanying table.
Timer Function Summary
Function
Rev. 1.00
Timer 0
Timer 1
Timer 2
Timer 3
13-bit Timer/Counter
√
√
—
√
16-bit Timer/Counter
√
√
—
√
8-bit timer with auto-reload
√
√
—
√
Two 8-bit Timer/Counters
√
—
—
—
16-bit Timer/Counter with auto-reload
—
—
√
—
16-bit Timer/Counter with capture
—
—
√
—
Compare Match Output
—
—
√
—
Programmable Clock Output
—
—
√
—
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May 15, 2013
Timer/Event Counters
One of the most fundamental functions in any microcontroller device is the ability to control and
measure time. To implement time related functions each device includes several Timer/Counters.
The Timers are multi-purpose timing units and serve to provide operations such as Timer/Counter,
Input Capture, Compare Match Output and Programmable Clock Output. Each of the Timers has
one individual interrupt. The addition of input and output pins for each Timer ensures that users
are provided with timing units with a wide and flexible range of features.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
28
Timer/Event Counters 0, 1, 3
These three timers provide have a similar type and structure and operate with a choice of three
modes for Timers 1 and 3 and four modes for Timer 0. They provide basic timing and event
counting operations.
The different operating modes of the timers are selected using the TnM1 and TnM0 bits in the
TMOD or T3CON register.
Timer Mode
TnM1, TnM0 bits
0
00
13-bit Timer-Counter
Mode Name
Application Timer
Timer 0, 1, 3
1
01
16-bit Counter
Timer 0, 1, 3
2
10
8-bit Counter Auto Reload
Timer 0, 1, 3
3
11
Two 8-bit Counters
Timer 0 only
The registers, THn and TLn, are special function registers located in the Special Function Registers
and is the place where the actual timer value is stored. This register pair, are each 8-bit wide, and
can be cascaded into 13-bit or 16-bit wide using mode options. The value in the timer registers
increases by one each time an internal clock pulse is received or an external transition occurs on
the external timer pin. The timer will count from the initial value loaded by the preload register to
their full count at which point the timer overflows and an internal interrupt signal is generated. If
the timer auto-reload mode is selected, the timer value will then be reset with the initial preload
register value and continue counting, otherwise the timer value will be reset to zero. Note that to
achieve a maximum full range count, the preload register must first be cleared to all zeros.
Rev. 1.00
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May 15, 2013
Timer/Event Counters 0, 1, 3
Introduction
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Timer 0/Timer 1/Timer 3 Register Description
Overall operation of the Timer 0, Timer 1 and Timer 3 are controlled using the registers listed in
the accompanying table. A register pair, TLn and THn, exist to store the internal counter 13-bit or
16-bit value. The TCON, IRCON, IEN0, IEN1 registers include the TIMERn interrupt control and
interrupt request flags, which are described in the Interrupt section. The remaining registers are
control registers which setup the different operating and control modes as well as the clock source
control bits.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IEN0
EAL
WDT
ET2
ES0
ET1
EX1
ET0
EX0
EX3
IEN1
EXEN2
SWDT
ET3
ECMP
EX6
EX5
EX4
IRCON
EXF2
TF2
IEX6
IEX5
IEX4
IEX3
IEX2
—
TMOD
GATE1
C/T1
T1M1
T1M0
GATE0
C/T0
T0M1
T0M0
TCON
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
T3CON
GATE3
C/T3
T3M1
T3M0
—
—
TF3
TR3
TLn
D7
D6
D5
D4
D3
D2
D1
D0
THn
D15
D14
D13
D12
D11
D10
D9
D8
TMPRE
T3PRE1
T3PRE0
T2PRE1
T2PRE0
T1PRE1
T1PRE0
T0PRE1
T0PRE0
Note: n=0, 1, 3
TL0 Register
SFR Address: 8Ah
●● 16-bit
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
TL0: TIMER0 Counter Low Byte Register bit 7~bit 0
●● 13-bit
Bit
6
5
4
3
Name
—
—
—
D4
D3
D2
D1
D0
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
0
0
0
0
0
Bit 7~5
Bit 4~0
Rev. 1.00
7
Unimplemented, read as “0”
TL0: TIMER0 Counter Low Byte Register bit 4~bit 0
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May 15, 2013
Timer/Event Counters 0, 1, 3
Timer0/Timer1/Timer3 Register List
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
TH0 Register
SFR Address: 8Ch
●● 16-bit
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
TH0: TIMER0 Counter High Byte Register bit 15~bit 8
●● 13-bit
Bit
7
6
5
4
3
2
1
0
Name
D12
D11
D10
D9
D8
D7
D6
D5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
TH0: TIMER0 Counter High Byte Register bit 12~bit 5
TL1 Register
SFR Address: 8Bh
●● 16-bit
Bit
7
6
5
4
3
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
TL1: TIMER1 Counter Low Byte Register bit 7~bit 0
●● 13-bit
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
D4
D3
D2
D1
D0
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
0
0
0
0
0
Bit 7~5
Bit 4~0
Rev. 1.00
Unimplemented, read as “0”
TL1: TIMER1 Counter Low Byte Register bit 4~bit 0
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May 15, 2013
Timer/Event Counters 0, 1, 3
Bit 7~0
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
TH1 Register
SFR Address: 8Dh
●● 16-bit
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
TH1: TIMER1 Counter High Byte Register bit 15~bit 8
●● 13-bit
Bit
7
6
5
4
3
2
1
0
Name
D12
D11
D10
D9
D8
D7
D6
D5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
TH1: TIMER1 Counter High Byte Register bit 12~bit 5
TL3 Register
SFR Address: A2h
●● 16-bit
Bit
7
6
5
4
3
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
2
1
0
Bit 7~0
TL3: TIMER3 Counter Low Byte Register bit 7~bit 0
●● 13-bit
Bit
6
5
4
3
Name
—
—
—
D4
D3
D2
D1
D0
R/W
—
—
—
R/W
R/W
R/W
R/W
R/W
POR
—
—
—
0
0
0
0
0
Bit 7~5
Bit 4~0
Rev. 1.00
7
Unimplemented, read as “0”
TL3: TIMER3 Counter Low Byte Register bit 4~bit 0
131 of 226
May 15, 2013
Timer/Event Counters 0, 1, 3
Bit 7~0
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
TH3 Register
SFR Address: A3h
●● 16-bit
Bit
7
6
5
4
3
2
1
0
Name
D15
D14
D13
D12
D11
D10
D9
D8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
TH3: TIMER3 Counter High Byte Register bit 15~bit 8
●● 13-bit
Bit
7
6
5
4
3
2
1
0
Name
D12
D11
D10
D9
D8
D7
D6
D5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
TH3: TIMER3 Counter High Byte Register bit 12~bit 5
TMOD Register
SFR Address: 89h
Bit
7
6
5
4
3
2
1
0
Name
GATE1
C/T1
T1M1
T1M0
GATE0
C/T0
T0M1
T0M0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5~4
Bit 3
Rev. 1.00
GATE1: Timer 1 Gate Control
0: Disable
1: Enable
This bit is used to enable the Timer 1 Gate function. When the GATE1 bit is set high
and Timer 1 is enabled to run using the TR1 bit and when the INT1 pin is input high,
then the Timer 1 Counter will increment one on every falling edge on the T1 input pin.
C/T1: Timer 1 Counter/Timer selection
0: Timer
1: Counter
T1M1, T1M0: Timer 1 mode selection
00: Mode 0 – 13-bit Timer/Counter
01: Mode 1 – 16-bit Timer/Counter
10: Mode 2 – 8-bit Auto Reload Timer/Counter
11: Mode 3 – Timer Stopped
GATE0: Timer 0 Gate Control
0: Disable
1: Enable
This bit is used to enable the Timer 0 Gate function. When the GATE0 bit is set high
and Timer 0 is enabled to run using the TR0 bit and when the INT0 pin is input high,
then the Timer 0 Counter will increment one on every falling edge on the T0 input pin.
132 of 226
May 15, 2013
Timer/Event Counters 0, 1, 3
Bit 7~0
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Bit 2
Bit 1~0
C/T0: Timer 0 Counter/Timer selection
0: Timer
1: Counter
T0M1, T0M0: Timer 0 mode selection
00: Mode 0 – 13-bit Timer/Counter
01: Mode 1 – 16-bit Timer/Counter
10: Mode 2 – 8-bit Auto Reload Timer/Counter
11: Mode 3 – Two independent 8-bit Timer/Counters
Bit
6
5
4
3
2
1
0
Name
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
7
TF1: Timer 1 interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
TR1: Timer 1 Run control
0: Stop
1: Run
TF0: Timer 0 interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
TR0: Timer 0 Run control
0: Stop
1: Run
IE1: External interrupt 1 request flag
Described elsewhere
IT1: External interrupt 1 type control
Described elsewhere
IE0: External interrupt 0 request flag
Described elsewhere
IT0: External interrupt 0 type control
Described elsewhere
133 of 226
May 15, 2013
Timer/Event Counters 0, 1, 3
TCON Register
SFR Address: 88h
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
T3CON Register
SFR Address: A1h
Bit
7
6
5
4
3
2
Name
GATE3
C/T3
T3M1
T3M0
—
—
TF3
TR3
R/W
R/W
R/W
R/W
R/W
—
—
R/W
R/W
POR
0
0
0
0
—
—
0
0
Bit 7
Bit 5~4
Bit 3~2
Bit 1
Bit 0
Rev. 1.00
0
GATE3: Timer 3 Gate Control
0: Disable
1: Enable
This bit is used to enable the Timer 3 Gate function. When the GATE3 bit is set high
and Timer 3 is enabled to run using the TR3 bit and when the INT3 pin is input high,
then the Timer 3 Counter will increment one on every falling edge on the T3 input pin.
C/T3: Timer 3 Counter/Timer selection
0: Timer
1: Counter
T3M1, T3M0: Timer 3 mode selection
00: Mode 0 – 13-bit Timer/Counter
01: Mode 1 – 16-bit Timer/Counter
10: Mode 2 – 8-bit Auto Reload Timer/Counter
11: Mode 3 – Timer Stopped
Unimplemented, read as "0"
TF3: Timer 3 interrupt request flag
0: No request
1: Interrupt request
This bit will be cleared by hardware automatically.
TR3: Timer 3 run flag
0: Stop
1: Run
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May 15, 2013
Timer/Event Counters 0, 1, 3
Bit 6
1
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
TMPRE Register
SFR Address: 8Fh
Bit
7
6
5
4
3
2
1
0
Name
T3PRE1
T3PRE0
T2PRE1
T2PRE0
T1PRE1
T1PRE0
T0PRE1
T0PRE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 3~2
Bit 1~0
Rev. 1.00
135 of 226
Timer/Event Counters 0, 1, 3
Bit 5~4
T3PRE1, T3PRE0: Timer 3 Clock Frequency selection
00: f SYS/12
01: f SYS/6
10: f SYS/4
11: f SYS
T2PRE1, T2PRE0: Timer 2 Clock Frequency selection
00: f SYS/12
01: f SYS/6
10: f SYS/4
11: f SYS
T1PRE1, T1PRE0: Timer 1 Clock Frequency selection
00: f SYS/12
01: f SYS/6
10: f SYS/4
11: f SYS
T0PRE1, T0PRE0: Timer 0 Clock Frequency selection
00: f SYS/12
01: f SYS/6
10: f SYS/4
11: f SYS
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Mode 0 – 13-bit Counter/Timer Mode Operation
13-bit Counter Data
Bit
Register
7
6
5
4
3
THn
D12
D11
D10
D9
D8
TLn
—
—
—
D4
D3
2
1
0
D7
D6
D5
D2
D1
D0
Note: n=1, 2, 3
Mode 1 – 16-bit Counter/Timer Mode Operation
To select this mode, bits TnM1 and TnM0, should be set to “01” respectively. The 16 bits of data are
stored in the TLn and THn registers. The C/Tn bit is used to select the timer or counter function.
The Counter/Timer Run or Stop is controlled by TRn bit. If the Counter function is selected, the
TRn and GATEn bits can be used to manage the external INTn input to count edge transitions
or measure pulse widths. The timer/counter clock source is decided by the TnPRE0 and TnPRE1
bits in the TMPRE register. Note that the TRn bit is used to control the Timer/Counter run or
stop function. Clearing this bit will not clear the TLn and THn registers, the registers should
be initialised by the application program. When an overflow occurs, the TFn interrupt request
flags will be set and an interrupt will take place if the interrupt is enabled. The following block
illustrates the 13-bit and 16-bit Timer/Counter basic operational blocks.
fSYS
fSYS/4
Prescaler
fSYS
fSYS/6
�UX
C/Tn=0
fSYS/1�
�ode 0
/
TnPRE[1:0]
Tn
C/Tn=1
�ode 1
Tn�1/Tn�0 = 00
THn
D1�
D11
TLn
-
D10
-
D9
D4
D8
D�
D7
D�
D6
D1
D�
D0
Tn�1/Tn�0 = 01
THn
D1�
D14
TLn
D7
D6
D1�
D�
D1�
D4
D11
D�
D10
D�
D9
D1
D8
D0
Interrupt
TFn flag
TRn
GATEn
INTn
Mode 0 and Mode 1 Block Diagram – Timer 0, 1, 3
Rev. 1.00
136 of 226
May 15, 2013
Timer/Event Counters 0, 1, 3
To select this mode, bits TnM1 and TnM0, should be set to “00”. The 13 bits of data are comprised
of 5 low bits in the TLn register and 8 high bits in the THn register. The C/Tn bit is used to select
the timer or counter function. The Counter/Timer Run or Stop operation is controlled using the TRn
bit. If the Counter function is selected, the TRn and GATEn bits can be used to manage the external
INTn input to count edge transitions or measure pulse widths. The timer/counter clock source is
decided by the TnPRE0 and TnPRE1 bits in the TMPRE register. Note that the TRn bit is used to
control the Timer/Counter run or stop function. Clearing this bit will not clear the TLn and THn
registers, the registers should be initialised by the application program. When an overflow occurs,
the TFn interrupt request flag will be set and an interrupt will take place if the interrupt is enabled.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Mode 2 – 8-bit Auto-reload Counter/Timer Mode Operation
fSYS
fSYS/4
Prescaler
fSYS
fSYS/6
�UX
C/Tn=0
fSYS/1�
/
TLn Register
TnPRE[1:0]
Interrupt
TFn flag
C/Tn=1
Tn
TRn
Auto-reload
GATEn
INTn
THn Register
Mode 2 Block Diagram – Timer 0, 1, 3
Rev. 1.00
137 of 226
May 15, 2013
Timer/Event Counters 0, 1, 3
To select this mode, bits TnM1 and TnM0, should be set to “10” respectively. This function is
implemented by the 8-bit TLn and THn registers. The C/Tn bit is used to select the timer or counter
function. The Counter/Timer Run or Stop is controlled by the TRn bit. If the Counter function is
selected, the TRn and GATEn bits can be used to manage the external INTn input to count edge
transitions or measure pulse widths. The timer/counter clock source is decided by the TnPRE0 and
TnPRE1 registers in the TMPRE register. When the values in the TLn register overflows, the TLn
value will be auto-reloaded with the data in the THn register and an interrupt will take place if the
interrupt is enabled. Note that the value of THn register should be initialised by the application
program. The accompanying block diagram illustrates the 8-bit Auto-Reload Timer/Counter basic
operational blocks.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Mode 3 – Two 8-Bit Timers/Counters Mode Operation – Timer 0 Only
In addition to TL0, the other 8-bit timer, TH0, can use the TR1 bit to enable the Timer. If the TH0
counter overflows, an interrupt will be generated and the interrupt request flag, TF1, will be set
high. The timer clock source is decided by the T0PRE0 and T0PRE1 bits in the TMPRE register.
The following block illustrates the two 8-bit Timer/Counters basic operational blocks.
TR1
fSYS
fSYS/4
Prescaler
fSYS
fSYS/6
�UX
TH0
Interrupt TF1 flag
C/T0=0
fSYS/1�
/
TL0
T0PRE[1:0]
T0
Interrupt TF0 flag
C/T0=1
TR0
GATE0
INT0
Mode 3 Block Diagram – Timer 0
Rev. 1.00
138 of 226
May 15, 2013
Timer/Event Counters 0, 1, 3
To select this mode, bits T0M1 and T0M0, should be set to “11” respectively. This mode is only
available for Timer 0. For Timer 1 and Timer 3, this mode is not available and if selected will stop
the timer function. The two 8-bit Timer/Counter function is implemented by the two individual 8-bit
TL0 and TH0 registers. TL0 can have both Timer and Counter functions while TH0 can only have
a Timer function. The C/T0 bit is used to select the timer or counter function for TL0. The TL0
Run or Stop is controlled by the TR0 bit. If the Counter function is selected, the TR0 and GATE0
bits can be used to manage the external INT0 input to count external edge transitions or to measure
input pulse widths. If the TL0 counter overflows, an interrupt will be generated and the interrupt
request flag, TF0, will be set high. The timer/counter clock source is decided by the T0PRE0 and
T0PRE1 bits in the TMPRE register.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
29
Timer 2 with Additional 4-channel PCA
The structure of Timer 2 is very different from that of Timers 0, 1 and 3 and is therefore described
in its own chapter.
Introduction
Timer 2 with PCA Modules Operating Modes Summary
Module
Compare
Capture
Reload
0
√
√
√
Clock Output
√
1
√
√
—
—
2
√
√
—
—
3
√
√
—
—
Note: Module 0 only provides the reload value from the Timer 2 capture registers CRCH and CRCL for
the Clock Output Mode. It is important to note that the actual Clock Output pin is T2 and not CC0.
Timer 2 with PCA Modules I/O Pins
Function
Compare
Reload trigger
Capture
Rev. 1.00
Input Pins
Output Pins
—
CC0, CC1, CC2, CC3
T2EX
—
CC0, CC1, CC2, CC3
—
Event Counter or Gated input
T2
—
Clock Output
—
T2
139 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
The Timer 2 provides the Timer, Event Counter, Gated timer functions and also cooperates with
a 4-channel Programmable Counter Array, known as PCA, to implement the Compare, Reload,
Capture and Programmable Clock Output functions. Each channel has a module, so there are four
modules, named Module 0~Module 3. Each module can be operated as a Compare and Capture
function while Module 0 can also be operated as a Compare, Reload, Capture, known as CRC, and
Programmable Clock Output functions. The accompanying tables and diagram illustrate the PCA
modules functional compare table, timer I/O pin list and basic operational block diagram.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
EXF�
Interrupt
Request
EXEN�
Transition
Detector
Reload
Module 0
Reload
Capture
CRCL/CRCH
TF�
Interrupt
Request
Comparator
T2
�atch
Timer 2
CC1/P1.1
Comparator
TH2/TL2
fSYS
CC0/P1.0
�atch
Overflow
Capture
Prescaler
& �ux
I/O
Control
Module 1
T�I[1:0]
CCL1/CCH1
T�PRE[1:0]
Comparator
�atch
CC2/P1.2
Capture
Module 2
CCL2/CCH2
Comparator
�atch
CC3/P1.3
Capture
Module 3
CCL3/CCH3
: Latch
Timer 2 with PCA Modules Block Diagram
Rev. 1.00
140 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
T2EX
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Timer 2
Timer 2 is a 16-bit wide count-up counter which is driven by a user selectable internal or external
clock source. The counter is composed of two registers, TL2 and TH2, to implement the Timer,
event counter and gated timer functions. The clock source is decided by the bits T2I1 and T2I0 in
the T2CON register.
To select this function, bits T2I1 and T2I0 in the T2CON register, should be set to “01” respectively.
The value in the Timer 2 registers, TL2 and TH2, increases by one each time an internal clock
pulse is received. The count rate is derived from the “f SYS”. The prescaler can be managed by
the T2PRE1 and T2PRE0 bits in the TMPRE register. When the timer counter is overflowed, an
interrupt will take place and the interrupt request flag, TF2, will be set to high.
Event Counter function
To select this function, bits T2I1 and T2I0 in the T2CON register, should be set to “10” respectively.
The value in the Timer 2 registers, TL2 and TH2, increases by one each time a falling edge occurs
on the external timer pin, T2. When the timer counter is overflowed, an interrupt will take place
and the interrupt request flag, TF2, will be set to high. The maximum count rate is 1/4 of the
system clock frequency.
Gated Timer function
To select this function, bits T2I1 and T2I0 in the T2CON register, should be set to “11” respectively.
The value in the Timer 2 registers, TL2 and TH2, increases by one each time an internal clock
pulse is received. The count rate is derived from the “f SYS” and the prescaler can be managed by
the T2PRE1 and T2PRE0 bits in the TMPRE register. The external timer pin, T2, can be a gate to
the Timer 2 input. When the T2 pin is set high, the Timer 2 keeps counting and when the Timer 2
is cleared to low, the Timer 2 will be stopped. The T2 input signal will be sampled once by every
internal system clock. When the timer counter is overflowed, an interrupt will take place and the
interrupt request flag, TF2, will be set to high.
Rev. 1.00
141 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
Timer function
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Timer 2 with PCA
Time 2 and 4-channel PCA modules provide the Compare, Reload, Capture and programmable
clock output functions. Each of the four Timer 2 Modules contains a pair of registers, CRCL/CRCH
for Module 0 and CCLn/CCHn for Modules 1, 2 and 3. These registers are compared with the
Timer 2 TL2/TH2 register pair and when a compare match occurs, an interrupt signal can be
generated. The value in the Timer 2 registers increases by one each time an internal clock pulse is
received or an external transition occurs on the external timer pin.
There are two modes for the Capture function, Mode 0 and Mode 1, which are used to select
different trigger methods. In Mode 0, the Capture function is triggered by the external I/O pins,
CCn. In Mode 1, the Capture function is triggered by writing data to the CCLn or CRCL registers.
Once the Capture function is enabled and triggered, the Timer 2 data in the TL2 and TH2 registers
will be captured into the respective CCLn/CCHn or CRCL/CRCH registers. Refer Capture modes
for details.
In the Reload mode, the timer counter registers, TH2 and TL2, are located in the Special Function
Registers and is the place where the actual timer value is stored. The value in the timer registers
increases by one each time an internal clock pulse is received or an external transition occurs on
the external timer pin. The timer will count from the initial value loaded by the preload register to
the full count of FFFFH for the 16-bit Timer/Event Counters, at which point the timer overflows
and an internal interrupt signal is generated. There are two modes to reload the CRC register data,
one is the counter overflow and the other is triggered by the falling edge on the T2EX pin. Refer
Reload mode for details.
In the Programmable Clock Output mode, the clock output frequency depends on the system
clock and the reload value of the Timer 2 capture registers, CRCH and CRCL. The output clock
is generated by programming the T2CON control bit, and output via T2 pin. Refer Programmable
Clock Output mode for details.
Rev. 1.00
142 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
The Compare function provides two modes, Mode 0 and Mode 1. When a compare match takes
place, the compare results will output to the respective output pins, according to the selected mode.
Refer Compare mode section for details.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Timer 2 Register Description
The Timer 2 value is stored in a register pair, TL2/TH2. Each of the internal PCA modules has
a register pair, known as CRCL/CRCH for Module 0 and CCLn/CCHn for modules 1, 2 and 3.
The T2CON register is related to the interrupt control register which is described in the Interrupt
section. The remaining two registers, CCEN and T2CON1, are control registers which setup the
different operating and control modes. The following table provides a register summary list for
Timer 2.
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TL2
D7
D6
D5
D4
D3
D2
D1
D0
TH2
D15
D14
D13
D12
D11
D10
D9
D8
CRCL
D7
D6
D5
D4
D3
D2
D1
D0
CRCH
D15
D14
D13
D12
D11
D10
D9
D8
CCLn
D7
D6
D5
D4
D3
D2
D1
D0
CCHn
D15
D14
D13
D12
D11
D10
D9
D8
T2CON
—
I3FR
I2FR
T2R1
T2R0
T2CM
T2I1
T2I0
T2CON1
—
—
—
MCD
T2OI
T2OE
—
—
CCEN
COCAH3
COCAL3
COCAH2
COCAL2
COCAH1
COCAL1
COCAH0
COCAL0
CCEN Register
SFR Address: C1h
Bit
7
6
5
4
3
2
1
0
Name
COCAH3
COCAL3
COCAH2
COCAL2
COCAH1
COCAL1
COCAH0
COCAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 5~4
Bit 3~2
Bit 1~0
Rev. 1.00
COCAH3, COCAL3: Compare/Capture mode select for Module 3 CC3 register
00: Disable
01: Capture on rising edge at the CC3 pin
10: Compare mode
11: Capture on write data into register CCL3
COCAH2, COCAL2: Compare/Capture mode select for Module 2 CC2 register
00: Disable
01: Capture on rising edge at the CC2 pin
10: Compare mode
11: Capture on write data into register CCL2
COCAH1, COCAL1: Compare/Capture mode select for Module 1 CC1 register
00: Disable
01: Capture on rising edge at the CC1 pin
10: Compare mode
11: Capture on write data into register CCL1
COCAH0, COCAL0: Compare/Capture mode select for Module 0 CRC register
00: Disable
01: Capture on rising or falling edge at the CC0 pin
10: Compare mode
11: Capture on write data into register CRCL
143 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
Timer 2 Register List
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
T2CON Register
SFR Address: C8h
Bit
7
6
5
4
3
2
1
0
Name
—
I3FR
I2FR
T2R1
T2R0
T2CM
T2I1
T2I0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit 5
Bit 4~3
Bit 2
Bit 1~0
Rev. 1.00
Unimplemented, read as “0”
I3FR: Active edge selection for external interrupt “INT3” and PCA module 0
Compare and Capture functions
0: Falling edge
1: Rising edge
This bit is used to select the external interrupt triggered edge for INT3, the PCA Module
0 Compare mode output interrupt triggered edge and the PCA Module 0 Capture mode
input triggered edge. Once the compare mode is enabled, the PCA interrupt will replace
the external interrupt. When Timer 2 is selected as compare mode 0, the I3FR bit is
recommended to be set high by firmware.
I2FR: Active edge selection for external interrupt “INT2”
Described elsewhere
T2R1, T2R0: Timer 2 reload mode selection
00: Reload function disabled
01: Reload function disabled
10: Mode 0
11: Mode 1
T2CM: Timer 2 Compare mode selection
0: Mode 0
1: Mode 1
T2I1, T2I0: Timer 2 clock source select
00: Timer 2 stopped
01: Internal clock source, decided by the T2PRE1 and T2PRE0 bits in the TMPRE
register
10: External T2 pin falling edge clock source
11: Internal clock source, decided by the T2PRE1 and T2PRE0 bits, gated by the
external T2 pin
144 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
Bit 7
Bit 6
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
T2CON1 Register
SFR Address: FEh
Bit
6
5
4
3
2
1
0
Name
—
—
—
MCD
T2OI
T2OE
—
—
R/W
—
—
—
R/W
R/W
R/W
—
—
POR
—
—
—
0
1
0
—
—
Bit 3
Bit 2
Bit 1~0
Unimplemented, read as “0”
MCD: Missing Clock Detection Reset control
Described elsewhere
T2OI: Timer 2 output initial state control
0: T2 pin initial output Low
1: T2 pin initial output High
The Timer 2 output initial state can be selected by the T2OI bit before enable the Timer
2 programmable clock output function.
T2OE: Timer 2 output enable bit
0: Disable
1: Enable
The Timer 2 output is enabled by setting the T2OE bit high.
When the Timer 2 output is disabled, this pin can be used as the other pin shared
functions.
Unimplemented, read as “0”
145 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
Bit 7~5
Bit 4
Rev. 1.00
7
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Capture Modes
Timer 2 has two capture modes, the Capture on Edge Mode, known as Capture Mode 0, and the
Capture on Write Mode, known as Capture Mode 1. The required mode is selected using the
COCAHn and COCALn bits in the CCEN register. The accompanying diagram illustrates the basic
operational blocks.
Capture �ode 1
Capture �ode 0
CCn
CRCH
CRCL
11
01
COCAHn
COCALn
I�FR bit
TL�
Note: 1. n=0~3
2. CC1~CC3 capture input by rising edge
3. CC0 capture input by rising or falling edge selected by the I3FR bit
4. Write to CCLn is for CC1~CC3 and Write to CRCL is for CC0
Capture Modes Block Diagram
Capture On Edge Mode
To select this mode, bits COCAHn and COCALn in the CCEN register, should be set to “01”
respectively. In this mode, Modules 1~3 will capture the Timer 2 counter on the rising edge of an
external signal applied on the CC1~CC3 pins. Module 0 will capture the Timer 2 counter contents
on a rising or falling edge applied on the CC0 pin. The rising or falling edge trigger is controlled by
the I3FR bit in the T2CON register.
Capture On Write Mode
To select this mode, bits COCAHn and COCALn in the CCEN register, should be set to “11”
respectively. In this mode a Timer 2 Capture is generated by any write operation into the capture
register low byte. The value written to capture register is irrelevant for this function. The Timer 2
contents will be latched into the appropriate capture registers.
Rev. 1.00
146 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
Write to CCLn(CRCL)
TH�
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Compare Modes
Timer 2 has two compare modes, known as Mode 0 and Mode 1. The required mode is selected
using the T2CM bit in the T2CON register. Setting counter data in the Compare modes can
implement the PWM function for various control applications.
Compare Mode 0
Interrupt
CCHn
CCLn
Compare �atch
“1”
CCn
Comparator
“0”
TH�
TL�
Overflow
Interrupt
Note: n=1~�
Compare Mode 0 – Module 1, Module 2, Module 3
Rev. 1.00
147 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
In Mode 0, if the Timer 2 counter data is the same as the Compare registers, the compare output
will be set from low to high and the Timer 2 counter overflow will clear the respective output pins,
CCn, to low. In addition, the Module 0 can select the output rising or falling edge interrupt trigger
by the I3FR bit in the T2CON register. The accompanying diagrams illustrate the Basic application
blocks.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Interrupt
CRCL
I3FR
Compare Match
“1”
CC0
Comparator
“0”
TH2
TL2
Overflow
Interrupt
Compare Mode 0 – Module 0
Figure below illustrates the operation of compare mode 0.
Contents of
Timer 2
CRC / CCn
Reload value
CCn Output
Compare interrupt
Overflow interrupt
Compare Mode 0 Timing Diagram
Rev. 1.00
148 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
CRCH
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Compare Mode 1
In Mode 1, the compare output can be decided by the software setting of the I/O pins control
register, P1. When the compare match takes place, the control register value will be outputted to
I/O pins, CCn, and the Timer 2 counter overflow will not affect the Compare output. In addition,
the Module 0 can select the output rising or falling edge interrupt trigger by the I3FR bit in the
T2CON register. The accompanying diagrams illustrate the Basic application blocks.
CCHn
CCLn
Compare Match
Comparator
TH2
TL2
I/O
Control
Register
Overflow
CCn
Interrupt
Note: n=1~3
Compare Mode 1 – Module1, Module2, Module 3
Interrupt
CRCH
CRCL
I3FR
Compare Match
Comparator
TH2
TL2
Overflow
I/O
Control
Register
CC0
Interrupt
Compare Mode 1 – Module 0
Rev. 1.00
149 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
Interrupt
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Figure below illustrates the operation of compare mode 1.
Contents of
Timer 2
Timer 2 with Additional 4-channel PCA
CRC or CCn
Reload value
CCn Output
Output register
P1 I/O Control register
CCn Output
Compare Match
Compare Mode 1 Timing Diagram
Rev. 1.00
150 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Reload Mode
EXF2
Count Enable
EXEN2
Interrupt
ET2
T2EX
TH2/TL2
Transition
Detector
Reload Mode 1
Reload Mode 0
CRCH/CRCL
Reload Mode – Module 0
Rev. 1.00
151 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
Module 0 provides a Reload Mode function. In the reload function, preset values in the CRCL and
CRCH registers are loaded into the TL2 and TH2 registers. There are two kinds of Reload modes,
Mode 0 and Mode 1, which are selected by the T2R1 and T2R0 bits in the T2CON register. In
Reload Mode 0, the Reload enable is controlled by the Timer 2 overflow which is an auto reload
and a Timer 2 interrupt will take place. In Reload Mode 1, a falling edge at the T2EX input pin
will reload the data from CRCH/CRCL registers to TH2/TL2 registers. When the external reload
interrupt control bit, EXEN2, and the Timer 2 interrupt control bit, ET2, are both set high, a
Timer 2 interrupt will be generated .The following diagram illustrates the basic operation.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Programmable Clock Output Mode
The clock-out frequency depends on the system frequency and the reload value of Timer 2 capture
registers (CRCH, CRCL) as shown in this equation:
Clock Out Frequency =
Timer 2 Clock Frequency
2 * (65536 - [CRCH, CRCL])
The Timer 2 Clock frequency is dependent on the T2PRE0 and T2PRE1 bits. The accompanying
diagram illustrates the Timer2 Clock output basic operation block diagram.
fSYS
TH2/TL2
Prescaler
TF2
/2
Interrupt
T2PRE[1:0]
P1.6/T2
T2OE
CRCH/CRCL
Timer2 Clock Output Block Diagram
If the Timer 2 Programmable Clock Output Mode is selected, it is essential for the Port 1 control
registers, P1M1 and P1M0, to setup the P1.6 pin as an output. The accompanying diagram
illustrates the Timer2 programmable clock output timing diagram.
Timer 2 Clock
Timer 2
FFFE FFFF 0000
FFFE FFFF 0000
FFFE FFFF 0000
FFFE FFFF 0000
Timer 2 Overflow
P1.6/T2
Programmable Clock Output Timing Diagram – Module 0
Rev. 1.00
152 of 226
May 15, 2013
Timer 2 with Additional 4-channel PCA
The Programmable Clock Output mode is related to Module 0. With this function, Timer 2 can
generate various clock outputs. This function is enabled by the T2OE bit in the T2CON1 register.
The output initial state is decided by the T2OI bit in the T2CON1 register. The Timer 2 enable
control or clock source is selected by the T2I1 and T2I0 bits in the T2CON register. The clock
source is further decided by the T2PRE1 and T2PRE0 bits in the TMPRE register. The data in
the TL2 and TH2 registers decides the clock duty cycle. If the counter overflows, then the CRCL
and CRCH registers will be auto-reloaded to the TL2 and TH2 registers. There are two ways
to implement a 50% duty cycle clock output on the T2 pin. One method is to input the external
clock for Timer/Counter 2 and the other is to output a 50% duty cycle clock ranging from 61HZ to
4MHz when the system clock is selected as 16MHz. To configure the Timer/Counter 2 as a clock
generator, the T2I1 and T2I0 bits in the T2CON register must be set as 0 and 1 respectively to start
the timer and the T2OE bit in the T2CON1 register must be set as well.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
30
Analog to Digital Converter – ADC
The devices include a multi-channel 12-bit fully integrated Analog to Digital Converter or ADC.
A range of programmable features allow flexible and fast analog to digital conversion for a wide
range of input signals.
The Analog to Digital Converter contains a range of features which include:
■■ Multiplexed Multi-channel Inputs
■■ Programmable Gain Amplifier
■■ Temperature Sensor Input
■■ Internal Voltage Reference Source
■■ External Reference Voltage Input
■■ Programmable Clock Speed
■■ A/D Converter Interrupt
All functions are controlled using dedicated ADC control registers for setup and dynamic control.
The following block diagram shows the overall structure of the converter together with its relative
control bits.
ACE7~ACE0
VCCA3
fSYS
P4.0/AIN.0
P4.1/AIN.1
ADCK2~ADCK0
Internal Voltage Reference
÷ 2N
(N=0~6)
A/D Clock
P4.7/AIN.7
ADOFF
Temperature Sensor
MUX
PGA
VREFAS
VREFIS
ADRL
A/D Converter
1
ADRH
A/D Data
Registers
VSS
ADGN2~ADGN0
TSEN
MUX
A/D Reference Voltage
0
ACS3~ACS0
VREF
ADRFS
ACS4
START EOCB
A/D Converter Structure
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Analog to Digital Converter – ADC
A/D Overview
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
A/D Converter Register Description
A read only register pair exists to store the ADC data 12-bit value. The remaining registers are
control registers which setup the operating and control function of the A/D converter.
A/D Converter Register List
Bit
Name
7
6
5
4
3
2
1
0
D3
D2
D1
D0
—
—
—
—
ADRL(ADRFS=1)
D7
D6
D5
D4
D3
D2
D1
D0
ADRH(ADRFS=0)
D11
D10
D9
D8
D7
D6
D5
D4
ADRH(ADRFS=1)
—
—
—
—
D11
D10
D9
D8
ADCR0
START
EOCB
ADOFF
ADRFS
ACS3
ACS2
ACS1
ACS0
ADCR1
ACS4
TSEN
—
VREFAS
VREFIS
ADCK2
ADCK1
ADCK0
ADCR2
ACE7
ACE6
ACE5
ACE4
ACE3
ACE2
ACE1
ACE0
ADPGA
—
—
—
—
—
ADGN2
ADGN1
ADGN0
A/D Converter Data Registers – ADRL, ADRH
As the devices contain an internal 12-bit A/D converter, they require two data registers to store the
converted value. These are a high byte register, known as ADRH, and a low byte register, known
as ADRL. After the conversion process takes place, these registers can be directly read by the
microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space
is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0
register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any
unused bits will be read as zero.
A/D Data Registers
ADRFS
ADRH
ADRL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
0
0
0
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A/D Converter Control Registers – ADCR0, ADCR1, ADCR2, ADPGA
To control the function and operation of the A/D converter, four control registers known as
ADCR0, ADCR1, ADCR2 and ADPGA are provided. These 8-bit registers define functions such
as analog channel selection, converted data format, PGA gain, clock source as well as the start
bit and end of conversion flag. As the device contains only one actual analog to digital converter
hardware circuit, each of the individual 8 analog inputs must be routed to the converter. It is the
function of the ACS4~ACS0 bits to determine which analog channel input pin, reference voltage or
internal temperature sensor is actually connected to the internal A/D converter.
The ADCR2 control register bits determine whether the pins on Port 4 are to be used as A/D
converter analog inputs or used as logic I/O pins. Setting the corresponding bit high will select the
A/D input function, clearing the bit to zero will select the I/O function. When the pin is selected
to be an A/D input, its logic I/O function will be removed and any internal pull-high resistors
connected to these pins will be automatically removed.
The ADPGA register determines the gain of the Programmable Gain Amplifier which is used to
amplify the analog input signal before conversion by the A/D Converter.
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Analog to Digital Converter – ADC
ADRL(ADRFS=0)
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
ADCR0 Register
SFR Address: F1h
Bit
7
6
5
4
3
2
1
0
Name
START
EOCB
ADOFF
ADRFS
ACS3
ACS2
ACS1
ACS0
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
1
0
0
0
0
0
Bit 7
Bit 5
Bit 4
Bit 3~0
Rev. 1.00
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Analog to Digital Converter – ADC
Bit 6
START: Starts the A/D conversion
0→1→0: Start
0→1: Reset the A/D converter and set EOCB to “1”
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
When the bit is set high the A/D converter will be reset.
EOCB: End of A/D conversion flag
0: A/D conversion ended
1: A/D conversion in progress
This read only flag is used to indicate when an A/D conversion process has completed.
When the conversion process is running the bit will be high.
ADOFF : ADC power on/off control bit
0: ADC power on
1: ADC power off
This bit controls the power to the A/D internal function. This bit should be cleared
to zero to enable the A/D converter. If the bit is set high then the A/D converter will
be switched off reducing the device power consumption. As the A/D converter will
consume a limited amount of power, even when not executing a conversion, this may be
an important consideration in power sensitive battery powered applications.
ADRFS: ADC Data Format Control
0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4
1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers.
ACS3~ACS0: Select A/D channel (when ACS4 is “0”)
0000: AIN.0
0001: AIN.1
0010: AIN.2
0011: AIN.3
0100: AIN.4
0101: AIN.5
0110: AIN.6
0111: AIN.7
1xxx: Undefined, must not be used
These are the A/D channel select control bits. As there is only one internal hardware
A/D converter each of the eight A/D inputs must be routed to the internal converter
using these bits. If bit ACS4 in the ADCR1 register is set high then the internal
temperature sensor will be routed to the A/D Converter and these ADC input channels
disconnected.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
ADCR1 Register
SFR Address: F2h
Bit
7
6
Name
ACS4
R/W
R/W
POR
0
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2~0
Rev. 1.00
4
3
2
1
0
TSEN
—
VREFAS
VREFIS
ADCK2
ADCK1
ADCK0
R/W
—
R/W
R/W
R/W
R/W
R/W
0
—
0
0
0
0
0
ACS4: Internal temperature sensor ADC input control
0: Disable
1: Enable
This bit enables the temperature sensor to the A/D converter. The TSEN bit must first
have been set to enable the temperature sensor circuit. When the ACS4 bit is set high,
the temperature sensor will be routed to the A/D converter and the other A/D input
channels disconnected.
TSEN: Internal temperature sensor control
0: Disable
1: Enable
This bit controls the internal temperature sensor function to the A/D converter. When
the bit is set high the temperature sensor can be used by the A/D converter.
Unimplemented, read as "0"
VREFAS: ADC reference voltage select
0: VCCA3 pin
1: Externally supplied on VREF pin or internal voltage reference generator
This bit is used to select the reference voltage for the A/D converter. If the bit is high
then the A/D converter reference voltage is supplied on the external VREF pin or the
internal reference voltage, the choice being made using the VREFIS bit. If the pin is
low then the internal reference is used which is sourced from the power supply pin
VCCA3.
VREFIS: A/D and DAC reference voltage select
0: Externally supplied on VREF pin
1: Internal Voltage Reference
ADCK2~ADCK0: Select ADC clock source
000: f SYS
001: f SYS/2
010: f SYS/4
011: f SYS/8
100: f SYS/16
101: f SYS/32
110: f SYS/64
111: f SYS
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Analog to Digital Converter – ADC
Bit 6
5
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
ADCR2 Register
SFR Address: F3h
Bit
7
6
5
4
3
2
1
0
Name
ACE7
ACE6
ACE5
ACE4
ACE3
ACE2
ACE1
ACE0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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Analog to Digital Converter – ADC
Bit 6
ACE7: P4.7 A/D input select
0: Logic I/O
1: A/D input, AIN.7
ACE6: P4.6 A/D input select
0: Logic I/O
1: A/D input, AIN.6
ACE5: P4.5 A/D input select
0: Logic I/O
1: A/D input, AIN.5
ACE4: P4.4 A/D input select
0: Logic I/O
1: A/D input, AIN.4
ACE3: P4.3 A/D input select
0: Logic I/O
1: A/D input, AIN.3
ACE2: P4.2 A/D input select
0: Logic I/O
1: A/D input, AIN.2
ACE1: P4.1 A/D input select
0: Logic I/O
1: A/D input, AIN.1
ACE0: P4.0 A/D input select
0: Logic I/O
1: A/D input, AIN.0
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
ADPGA Register
SFR Address: F4h
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
ADGN2
ADGN1
ADGN0
R/W
—
—
—
—
—
R/W
R/W
R/W
POR
—
—
—
—
—
0
0
0
Unimplemented, read as “0”
ADGN2~ADGN0: PGA gain select
000: PGA off
001: 0.5
010: 1
011: 2
100: 4
101: 8
110: 12
111: 16
These three bits are used to select the PGA internal gain setting to allow greater A/D
Converter input voltage dynamic range.
A/D Operation
Controlling the power on/off function of the A/D converter circuitry is implemented using the
ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the
ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as
indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no
pins are selected for use as A/D inputs by clearing the ACE7~ACE0 bits in the ADCR2 register, if
the ADOFF bit is zero then some power will still be consumed. In power conscious applications it
is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D
converter function is not being used.
The reference voltage supply to the A/D Converter can be supplied from either the positive power
supply pin, VCCA3, internal voltage reference or from an external reference sources supplied on
pin VREF. The desired selection is made using the VREFAS and VREFIS bits.
The START bit in the ADCR0 register is used to start and reset the A/D converter. When the
microcontroller sets this bit from low to high and then low again, an analog to digital conversion
cycle will be initiated. When the START bit is brought from low to high but not low again, the
EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset.
It is the START bit that is used to control the overall start operation of the internal analog to digital
converter.
The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion
process is complete. This bit will be automatically set to “0” by the microcontroller after a
conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set
in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt
signal will be generated. This A/D internal interrupt signal will direct the program flow to the
associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled,
the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has
been cleared as an alternative method of detecting the end of an A/D conversion cycle.
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Analog to Digital Converter – ADC
Bit 7~3
Bit 2~0
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
A/D Converter Clock Source
The clock source for the A/D converter, which originates from the system clock f SYS, can be chosen
to be either f SYS or a subdivided version of f SYS. The division ratio value is determined by the
ADCK2~ADCK0 bits in the ADCR1 register.
A/D Clock Period Examples
A/D Clock Period (tADCK)
fSYS
1MHz
ADCK2,
ADCK1,
ADCK0
=000
(fSYS)
ADCK2,
ADCK1,
ADCK0
=001
(fSYS/2)
ADCK2,
ADCK1,
ADCK0
=010
(fSYS/4)
ADCK2,
ADCK1,
ADCK0
=011
(fSYS/8)
ADCK2,
ADCK1,
ADCK0
=100
(fSYS/16)
ADCK2,
ADCK1,
ADCK0
=101
(fSYS/32)
ADCK2,
ADCK1,
ADCK0
=110
(fSYS/64)
ADCK2,
ADCK1,
ADCK0
=111
1μs
2μs
4μs
8μs
16μs
32μs
64μs
Undefined
2MHz
500ns
1μs
2μs
4μs
8μs
16μs
32μs
Undefined
4MHz
250ns*
500ns
1μs
2μs
4μs
8μs
16μs
Undefined
8MHz
125ns*
250ns*
500ns
1μs
2μs
4μs
8μs
Undefined
12MHz
83ns*
167ns*
333ns*
667ns
1.33μs
2.67μs
5.33μs
Undefined
16MHz
62.5ns*
125ns*
250ns*
500ns
1μs
2μs
4μs
Undefined
32MHz
31.25ns*
62.5ns*
125ns*
250ns*
500ns
1μs
2μs
Undefined
A/D Input Pins
All of the A/D analog input pins are pin-shared with the I/O pins on Port 4 function. The
ACE7~ACE0 bits in the ADCR2 registers, determine whether the input pins are setup as A/D
converter analog inputs or I/O function. If the ACE7~ACE0 bits for its corresponding pin is set
high then the pin will be setup to be an A/D converter input and the original pin functions disabled.
In this way, pins can be changed under program control to change their function between A/D
inputs and I/O function. All pull-high resistors, which are setup through register programming,
will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary
to first setup the A/D pin as an input in the P4 port control register to enable the A/D input as when
the ACE7~ACE0 bits enable an A/D input, the status of the port control register will be overridden.
The A/D converter has its own reference voltage pin, VREF, however the reference voltage can
also be supplied from the power supply pin or internal voltage reference, a choice which is made
through the VREFAS and VREFIS bits in the ADCR1 register. The analog input values must not
be allowed to exceed the value of VREF.
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Analog to Digital Converter – ADC
Although the A/D clock source is determined by the system clock f SYS, and by bits ADCK2~ADCK0,
there are some limitations on the maximum A/D clock source speed that can be selected. As the
minimum value of permissible A/D clock period, t ADCK, is 0.5μs, care must be taken for system
clock frequencies equal to or greater than 4MHz. For example, if the system clock operates at a
frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to “000”. Doing so will give A/D
clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D
conversion values. Refer to the following table for examples, where values marked with an asterisk
* show where, depending upon the device, special care must be taken, as the values may be less
than the specified minimum A/D Clock Period.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Temperature Sensor
A temperature sensor circuit is provided to measure the temperature which the designer can use
to adjust some measured parameters. The temperature sensor output voltage is proportional to the
temperature increment and can be amplified by the PGA. The accompanying diagram illustrates the
basic relationship between the measured temperature and the voltage output. However, the designer
should consider that the temperature sensor output voltage might be affected by the manufacturing
process.
A/D Reference Voltage Source
The A/D can obtain its reference voltage from three different sources, the VCCA3 power supply
pin, an externally supplied reference voltage supplied on pin VREF or from the internal voltage
reference generator. Two bits control which reference source is selected, these are the VREFIS and
VREFAS bits.
A/D Converter Voltage Reference Select
Rev. 1.00
VREFIS
VREFAS
0
0
VCCA3 pin
Reference Source
0
1
Externally supplied on VREF pin
1
0
VCCA3 pin
1
1
Internal Voltage Reference Generator
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Analog to Digital Converter – ADC
The ADC temperature sensor input channel is selected by the ACS4 bit. The TSEN bit in the
ADCR1 register controls the temperature sensor enable/disable function. When the function is
disabled, the temperature sensor defaults to an unknown state and any A/D conversion performed
on the sensor will generate undefined data.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Summary of A/D Conversion Steps
The following summarises the individual steps that should be executed in order to implement an
A/D conversion process.
■■ Step 1
Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the
ADCR1 register and select the converted data storage format using the ADRFS bit.
■■ Step 3
Select which channel is to be connected to the internal A/D converter by correctly programming
the ACS4~ACS0 bits which are also contained in the ADCR1 and ADCR0 register.
■■ Step 4
Select which pins are to be used as A/D inputs and configure them by correctly programming the
ACE7~ACE0 bits in the ADCR2 register.
■■ Step 5
If the interrupts are to be used, the interrupt control registers must be correctly configured to
ensure the A/D converter interrupt function is active. The master interrupt control bit, EAL, and
the A/D converter interrupt bit, EADC, must both be set high to do this.
■■ Step 6
The analog to digital conversion process can now be initialised by setting the START bit in
the ADCR0 register from low to high and then low again. Note that this bit should have been
originally cleared to zero.
■■ Step 7
To check when the analog to digital conversion process is complete, the EOCB bit in the
ADCR0 register can be polled. The conversion process is complete when this bit changes from
high to low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the
conversion value. As an alternative method, if the interrupts are enabled and the stack is not full,
the program can wait for an A/D interrupt to occur.
Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in
the ADCR0 register is used, the interrupt enable step above can be omitted.
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Analog to Digital Converter – ADC
■■ Step 2
Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero and select the PGA
gain using the ADPGA register according to the dynamic range of the analog input signal.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
A/D Conversion Timing
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing. After an A/D conversion process has been initiated
by the application program, the microcontroller internal hardware will begin to carry out the
conversion, during which time the program can continue with other functions. The time taken for
the A/D conversion is 16 tADCK where tADCK is equal to the A/D clock period.
Analog to Digital Converter – ADC
A/D Conversion Timing
Rev. 1.00
162 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Programming Considerations
A/D Transfer Function
As the converted data is 12-bit wide, its full-scale converted digitised value is equal to FFFH.
Since the full-scale analog input value is equal to the VCCA3 or V REF voltage, this gives a single bit
analog input value of VCCA3 or VREF divided by 4096.
1 LSB=(VCCA3 or VREF)/4096
The A/D Converter input voltage value can be calculated using the following equation:
A/D input voltage=PGA Gain×A/D digital value×(VCCA3 or VREF)/4096
The diagram shows the ideal transfer function between the analog input value and the digitised
output value for the A/D converter. Except for the digitised zero value, the subsequent digitised
values will change at a point 0.5 LSB below where they would change without the offset, and the
last full scale digitised value will change at a point 1.5 LSB below the VCCA3 or V REF level.

   
   
Ideal A/D Transfer Function (PGA=1)
Rev. 1.00
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Analog to Digital Converter – ADC
During microcontroller operations where the A/D converter is not being used, the A/D internal
circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the
ADCR0 register. When this happens, the internal A/D converter circuits will not consume power
irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines
are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level,
then this may lead to some increase in power consumption.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
31
Digital to Analog Converter – DAC
All devices include a Digital to Analog Converter permitting the conversion of a 12-bit digital
value into an analog voltage. An additional programmable attenuation control function provides
further flexibility over the overall input/output transfer function.
A pair of data register, DAL and DAH, store the 12-bit digital value which is to be converted, while
an additional control register, DACTRL, controls the attenuation level, reference voltage select and
enable/disable control.
DAH Register
SFR Address: B5h
Bit
7
6
5
4
3
2
1
0
Name
D11
D10
D9
D8
D7
D6
D5
D4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
0
0
0
0
0
0
0
Bit 7~0
D11~D4: DAC output data bit 11~4
DAL Register
SFR Address: B4h
Bit
7
6
5
4
3
2
1
0
Name
D3
D2
D1
D0
—
—
—
—
R/W
R/W
R/W
R/W
R/W
—
—
—
—
POR
0
0
0
0
—
—
—
—
Bit 7~4
Bit 3~0
D3~D0: DAC output data bit 3~0
Unimplemented, read as “0”
DACTRL Register
SFR Address: B3h
Bit
7
6
5
4
3
2
1
0
Name
VOL2
VOL1
VOL0
—
—
—
VREFDS
DACEN
R/W
R/W
R/W
R/W
—
—
—
R/W
R/W
POR
0
0
0
—
—
—
0
0
Bit 7~5
Rev. 1.00
VOL2~VOL0: DAC attenuation control
There are 8 levels of DAC attenuation selected using these three bits. The accompanying
table illustrates the relationship between the DAC attenuation control bits and the DAC
data output.
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Digital to Analog Converter – DAC
DAC Register Description
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
DACOUT
VOL
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
D11
D11B
D11B
D11B
D11B
D11B
D11B
D11B
D10
D9
D8
D7
001
D11
D11B
D11B
D11B
D11B
D11B
D11B
D10
D9
D8
D7
D6
010
D11
D11B
D11B
D11B
D11B
D11B
D10
D9
D8
D7
D6
D5
011
D11
D11B
D11B
D11B
D11B
D10
D9
D8
D7
D6
D5
D4
100
D11
D11B
D11B
D11B
D10
D9
D8
D7
D6
D5
D4
D3
101
D11
D11B
D11B
D10
D9
D8
D7
D6
D5
D4
D3
D2
110
D11
D11B
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
111
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Unimplemented, read as “0”
VREFDS: DAC reference voltage select bit
0: VCCA2 external power supply pin
1: Externally supplied on VREF pin or internal voltage reference generator
DACEN: DAC enable control bit
0: Disable
1: Enable
165 of 226
May 15, 2013
Digital to Analog Converter – DAC
Rev. 1.00
Bit 9
000
Bit 4~2
Bit 1
Bit 0
Bit 11 Bit 10
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
DAC Operation
The accompanying diagram illustrates the DAC basic operational block diagram.
VCCA2
VREF
MUX
Reference Voltage
Internal Voltage Reference
VREFDS VREFIS
Data Bus
DACEN
Low Byte Buffer
12-bit D/A
Converter
/
DAL
DAH
DAC
/
Attenuation
Control
VOL[2:0]
DAC Basic Operational Block Diagram
Rev. 1.00
166 of 226
May 15, 2013
Digital to Analog Converter – DAC
The DAL and DAH registers contain the digital value to be converted. The DACEN bit in the
DACTRL register provides overall enable/disable control. When set high, the DAC output pin will
be enabled and the original I/O pin shared function disabled. Clearing this bit to zero will disable
the DAC and reduce any associated power consumption. The DAC attenuation control is provided
by the VOL0~VOL2 bits in the DACTRL register providing an 8-level attenuation control. These
bits rotate the digital DAC value thus providing a divide or multiply by two functions for each shift
left or right. If the DAC circuit is not enabled, any DAH/DAL values will be invalid. The VREFDS
and VREFIS bits select if the DAC reference is to be sourced from VCCA2, VREF pin or the
internal reference voltage. Bits 0~3 of the DAL register are always read as zero.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
DAC Reference Voltage Source
The DAC can obtain its reference voltage from three different sources, the VCCA2 power supply
pin, an externally supplied reference voltage supplied on pin VREF or from the internal voltage
reference generator. Two bits control which reference source is selected, these are the VREFIS and
VREFDS bits.
DAC Converter Voltage Reference Select
VREFDS
0
0
VCCA2 pin
Reference Source
0
1
Externally supplied on VREF pin
1
0
VCCA2 pin
1
1
Internal Voltage Reference Generator
Programming Considerations
Note that data written to the two DAC registers must be implemented in a specific way. Any
data written into the DAH register will load both the data into the DAL and DAH registers
simultaneously and influence the DAC output at the same time. However writing data to the DAL
register will only place the data into a low byte buffer and not directly into the DAL register. For
this reason, writing data to the DAL register should be followed by a write instruction to the DAH
register.
Rev. 1.00
167 of 226
May 15, 2013
Digital to Analog Converter – DAC
VREFIS
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
32
Voltage Reference Generator
All devices include a bandgap circuit based internal voltage reference generator which can supply a
temperature stable reference voltage for use by the internal A/D converter and DAC.
Voltage Reference Generator Operation
Internal Voltage Reference Enable/Disable Control
ADC
DAC
Voltage Reference
Disabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
The internal Voltage Reference Generator output is pin VREF and can be used as a reference
source for other circuits if loaded lightly. A suitable capacitor should be connected to this pin to
enhance voltage stability. If the internal Voltage Reference Generator is enabled then the VREF pin
will act as an output pin and must be treated accordingly. However if the internal Voltage Reference
Generator is disabled, then the VREF pin will act as an input pin to enable an externally supplied
reference voltage to be provided if required.
Rev. 1.00
168 of 226
May 15, 2013
Voltage Reference Generator
The voltage reference circuit will be automatically enabled when either the A/D converter or DAC
is enabled. If both the A/D converter and DAC are disabled then the generator will be disabled thus
conserving power.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
VCCA3
0
M
U
X
1
ADC Voltage
Reference
VREFI
VREF
0
1
VREFIS
M
U
X
DAC Voltage
Reference
VREFDS
Internal Voltage
Reference Generator
Enable/Disable
Control
OR
A/D
Enable
D/A
Enable
VCCA2
Voltage Reference Generator Block Diagram
The A/D converter and DAC reference voltage is selected by the VREFIS, VREFAS and VREFDS
control bits. When the VREFIS bit is enabled the internal voltage reference will be routed to pin
VREF and can be selected for use by the A/D converter or DAC, using the VREFAS and VREFDS
bits.
Rev. 1.00
169 of 226
May 15, 2013
Voltage Reference Generator
VREFAS
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
33
Comparators
Comparator Operation
Each device contains two comparator functions which are used to compare two analog voltages
and provide an output based on their difference. Full control over the two internal comparators is
provided via four control registers, CP0CR, CP1CR, CPHCR and CPICR. The comparator output
is recorded via a bit in their respective control register, but can also be transferred out onto a
shared I/O pin. Additional comparator functions include, output polarity, hysteresis functions and
power-down control.
Any pull-high resistors connected to the shared comparator input pins will be automatically
disconnected when the comparator is enabled. As the comparator inputs approach their switching
level, some spurious output signals may be generated on the comparator output due to the slow
rising or falling nature of the input signals. This can be minimised by selecting the hysteresis
function will apply a small amount of positive feedback to the comparator. Ideally the comparator
should switch at the point where the positive and negative inputs signals are at the same voltage
level, however, unavoidable input offsets introduce some uncertainties here. The hysteresis function,
if enabled, also increases the switching offset value. The Comparator Hysteresis control function
is selected by the CPHCR register. In addition, the comparator 0 provides the Comparator Output
Reset MCU function which is decided by the CP0RST and CP0RSTL bits in the CP0CR register.
CP0ON
CP0POL
CP0+
+
CP0-
-
CP0HP[1:0]
CP0HN[1:0]
CP0OUT
C0OUT
Interrupt
CP0OS
CP0RST
1
Reset MCU
MUX
0
Reset MCU
CP0RSTL
Comparator 0
Rev. 1.00
170 of 226
May 15, 2013
Comparators
Two independent analog comparators are contained within these devices. These functions offer
flexibility via their register controlled features such as power-down, polarity select, hysteresis,
interrupt, wake-up, output path selection etc. In sharing their pins with normal I/O pins the
comparators do not waste precious I/O pins if there functions are unused. One comparator also has
the ability to reset the MCU.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
CP1ON
CP1POL
CP1+
+
CP1-
-
CP1OUT
C1OUT
CP1OS
Comparators
Interrupt
CP1HP[1:0]
CP1HN[1:0]
Comparator 1
Comparator Registers
There are four registers for overall comparator operation. The CP0CR and CP1CR registers are
used to control the respective comparators settings for the Comparator 0 and Comparator 1 while
the CPHCR register is used to manage the hysteresis selection for these two comparators. In
addition, the CPICR register control the comparators interrupt settings. The accompanying register
table illustrates the control registers list.
Comparator Registers List
Rev. 1.00
Bit
Register
Name
7
6
5
4
3
2
1
0
CP0CR
—
CP0ON
CP0POL
CP0OUT
CP0OS
CP0RSTL
CP0RST
—
CP1CR
—
CP1ON
CP1POL
CP1OUT
CP1OS
—
—
—
CPHCR
CP1HP1
CP1HP0
CP1HN1
CP1HN0
CP0HP1
CP0HP0
CP0HN1
CP0HN0
CPICR
CP1IF
CP1IEN
CP1P1
CP1P0
CP0IF
CP0IEN
CP0P1
CP0P0
171 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
CP0CR Register
SFR Address: DEh
Bit
7
6
5
4
3
2
1
0
Name
—
CP0ON
CP0POL
CP0OUT
CP0OS
CP0RSTL
CP0RST
—
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
—
POR
—
0
0
0
1
0
0
—
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
Unimplemented, read as “0”
CP0ON: Comparator 0 On/Off control
0: Off
1: On
This is the Comparator 0 on/off control bit. If the bit is zero the comparator will be
switched off and no power consumed even if analog voltages are applied to its inputs.
For power sensitive applications this bit should be cleared to zero if the comparator is
not used or before the device enters the Power-Down or IDLE mode.
CP0POL: Comparator 0 output polarity
0: Output not inverted
1: Output inverted
This is the comparator 0 polarity bit. If the bit is zero then the CP0OUT bit will reflect
the non-inverted output condition of the comparator. If the bit is high the comparator
CP0OUT bit will be inverted.
CP0OUT: Comparator 0 output bit
CP0POL=0
0: CP0+ < CP01: CP0+ > CP0CP0POL=1
0: CP0+ > CP01: CP0+ < CP0This bit stores the comparator 0 output bit. The polarity of the bit is determined by the
voltages on the comparator 0 inputs and by the condition of the CP0POL bit.
CP0OS: Comparator 0 output path select
0: C0OUT pin
1: Internal use
This is the comparator 0 output path select control bit. If the bit is set to “0” and the
CP0ON bit is “1” the comparator 0 output is connected to an external C0OUT pin. If
the bit is set to “1” or the CP0ON bit is “1” the comparator 0 output signal is only used
internally by the device allowing the shared comparator output pin to retain its normal
I/O operation.
CP0RSTL: Output reset signal select
0: CP0OUT=0 will reset the MCU
1: CP0OUT=1 will reset the MCU
The CP0RST bit should be set high first to enable this function.
CP0RST: Comparator 0 output to reset MCU function control
0: Disable
1: Enable
Unimplemented, read as “0”
172 of 226
May 15, 2013
Comparators
Bit 7
Bit 6
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
CP1CR Register
SFR Address: DFh
Bit
7
6
5
4
3
2
1
0
Name
—
CP1ON
CP1POL
CP1OUT
CP1OS
—
—
—
R/W
—
R/W
R/W
R/W
R/W
—
—
—
POR
—
0
0
0
1
—
—
—
Bit 5
Bit 4
Bit 3
Bit 2~0
Rev. 1.00
Unimplemented, read as “0”
CP1ON: Comparator 1 On/Off control
0: Off
1: On
This is the Comparator 1 on/off control bit. If the bit is zero the comparator will be
switched off and no power consumed even if analog voltages are applied to its inputs.
For power sensitive applications this bit should be cleared to zero if the comparator is
not used or before the device enters the Power-Down or IDLE mode.
CP1POL: Comparator 1 output polarity
0: Output not inverted
1: Output inverted
This is the comparator 1 polarity bit. If the bit is zero then the CP1OUT bit will reflect
the non-inverted output condition of the comparator. If the bit is high the comparator
CP1OUT bit will be inverted.
CP1OUT: Comparator 1 output bit
CP1POL=0
0: CP1+ < CP11: CP1+ > CP1CP1POL=1
0: CP1+ > CP11: CP1+ < CP1This bit stores the comparator 1 output bit. The polarity of the bit is determined by the
voltages on the comparator 0 inputs and by the condition of the CP1POL bit.
CP1OS: Comparator 1 output path select
0: C1OUT pin
1: Internal use
This is the comparator 0 output path select control bit. If the bit is set to “0” and the
CP1ON bit is “1” the comparator 0 output is connected to an external C1OUT pin. If
the bit is set to “1” or the CP1ON bit is “1” the comparator 0 output signal is only used
internally by the device allowing the shared comparator output pin to retain its normal
I/O operation.
Unimplemented, read as “0”
173 of 226
May 15, 2013
Comparators
Bit 7
Bit 6
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
CPHCR Register
SFR Address: BDh
Bit
7
6
5
4
3
2
1
0
Name
CP1HP1
CP1HP0
CP1HN1
CP1HN0
CP0HP1
CP0HP0
CP0HN1
CP0HN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 3~2
Bit 1~0
Rev. 1.00
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May 15, 2013
Comparators
Bit 5~4
CP1HP1, CP1HP0: Comparator 1 Positive Hysteresis voltage level Control bits
00: Disabled
01: 3mV
10: 6mV
11: 12mV
CP1HN1, CP1HN0: Comparator 1 Negative Hysteresis voltage level Control bits
00: Disabled
01: 3mV
10: 6mV
11: 12mV
CP0HP1, CP0HP0: Comparator 0 Positive Hysteresis voltage level Control bits
00: Disabled
01: 3mV
10: 6mV
11: 12mV
CP0HN1, CP0HN0: Comparator 0 Negative Hysteresis voltage level Control bits
00: Disabled
01: 3mV
10: 6mV
11: 12mV
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
CPICR Register
SFR Address: BEh
Bit
7
6
5
4
3
2
1
0
Name
CP1IF
CP1IEN
CP1P1
CP1P0
CP0IF
CP0IEN
CP0P1
CP0P0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7
Bit 5~4
Bit 3
Bit 2
Bit 1~0
Rev. 1.00
175 of 226
May 15, 2013
Comparators
Bit 6
CP1IF: Comparator 1 Output Transition Interrupt Request Flag
0: No request
1: Interrupt request
Note that this flag should be cleared using the application program.
CP1IEN: Comparator 1 Output Transition Interrupt enable control
0: Disable
1: Enable
CP1P1, CP1P0: Comparator 1 Output Transition Interrupt settings for interrupt
00: Interrupt disabled
01: Comparator transition output from high to low will cause an interrupt
10: Comparator transition output from low to high will generate an interrupt
11: Comparator transition output from low to high or high to low will generate an
interrupt
CP0IF: Comparator 0 Output Transition Interrupt Request Flag
0: Not request
1: Interrupt request
Note that this flag should be cleared using the application program.
CP0IEN: Comparator 0 Output Transition Interrupt enable control
0: Disable
1: Enable
CP0P1, CP0P0: Comparator 0 Output Transition Interrupt settings for interrupt
00: Interrupt disabled
01: Comparator transition output from high to low will generate an interrupt
10: Comparator transition output from low to high will generate an interrupt
11: Comparator transition output from low to high or high to low will generate an
interrupt
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Comparator Interrupt
Comparator Reset Function
Comparator 0 has the ability to reset the device. The reset function of Comparator 0 can be enabled
or disabled by the CP0RST bit in the CP0CR register after which the comparator polarity which
will reset the device can be selected using the CP0RSTL bit.
Programming Considerations
If the comparator is enabled, it will remain active when the microcontroller enters the PowerDown or IDLE Mode, however as it will consume a certain amount of power, the user may wish
to consider disabling it before the Power-Down or IDLE Mode is entered. As comparator pins
are shared with normal I/O pins the I/O registers for these pins will be read as zero (port control
register is “1”) or read as port data register value (port control register is “0”) if the comparator
function is enabled.
Rev. 1.00
176 of 226
May 15, 2013
Comparators
Each also possesses its own interrupt function. When any one of the changes state, its relevant
interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its
relevant interrupt vector will be executed. Note that it is the changing state of the CP0OUT or
CP1OUT bit and not the output pin which generates an interrupt. If the microcontroller is in the
Power-Down or IDLE Mode and the Comparator is enabled, then if the external input lines cause
the Comparator output to change state, the resulting generated interrupt flag will also generate a
wake-up. If it is required to disable a wake-up from occurring, then the interrupt function should
be disabled before entering the Power-Down or IDLE Mode. Each of the comparators has the
compare output transition settings to decide the interrupt request conditions. There are three
options, compare output rising, falling or both rising and falling conditions, decided by the CPnP1
and CPnP0 bits in the CPICR register.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
34
I2C Serial Interface
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface
for synchronous serial data transfer. The advantage of only two lines for communication, relatively
simple communication protocol and the ability to accommodate multiple devices on the same bus
has made it an extremely popular interface type for many applications.
I2C Serial Interface
I2C Master Slave Bus Connection
I2C Interface Operation
The I2C serial interface is a two line serial interface. These lines are a serial data line, SDA, and
serial clock line, SCL. As many devices may be connected together on the same bus, their outputs
are both open drain types. For this reason it is necessary that external pull-high resistors are
connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is
identified by a unique address which will be transmitted and received on the I2C bus.
When two devices communicate with each other on the bidirectional I2C bus, one is known as the
master device and one as the slave device. Both master and slave can transmit and receive data,
however, it is the master device that has overall control of the bus. The I2C meets the Philips I2C
bus specification and supports all transfer modes from and to the I2C bus.
When the I 2C is in the master mode, a variable baud rate setup is available using the I2C clock
generator. The clock source is sourced from the system clock. The clock generator can be controlled
using the I2CLK register. The clock generator is suppressed when the I2C is in the slave mode.
I2C Interface Operation Flow
Rev. 1.00
177 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I2C Registers
I2C Register List
Bit
Register
Name
7
6
5
4
3
2
1
0
I2CCON
—
ENS1
STA
STO
SI
AA
—
—
I2CLK.0
I2CLK
I2CLK.7
I2CLK.6
I2CLK.5
I2CLK.4
I2CLK.3
I2CLK.2
I2CLK.1
I2CSTA
IICS7
IICS6
IICS5
IICS4
IICS3
—
—
—
I2CDAT
D7
D6
D5
D4
D3
D2
D1
D0
I2CADR
IICA6
IICA5
IICA4
IICA3
IICA2
IICA1
IICA0
GC
I2CCON Register
SFR Address: D8h
Bit
7
6
5
4
3
2
1
0
Name
—
ENS1
STA
STO
SI
AA
—
—
R/W
—
R/W
R/W
R/W
R/W
R/W
—
—
POR
—
0
0
0
0
0
—
—
Bit 7
Bit 6
Bit 5
Bit 4
Rev. 1.00
Unimplemented, read as “0”
ENS1: I2C Enable Control
0: Disable
1: Enable
When the ENS1 bit is cleared to zero, the I2C interface will be disabled and will become
high impedance and not affect the original pin-shared I/O pin function. When the ENS1
bit is set high, the I2C function is enabled and care should be taken regarding the related
pin-shared I/O structure settings, such as disabling any internal pull up functions and
any other circuits connected to these pins.
STA: I2C Start flag
0: No START condition on the I2C bus
1: START condition
When the STA bit is set high, the master device will check the I2C bus status first and if
the bus is free a START condition will be generated.
STO: I2C Stop flag
0: No STOP condition on the I2C bus
1: Set STOP condition
When the STO bit is set high, the master device will transmit a STOP condition to the
I2C bus.
178 of 226
May 15, 2013
I2C Serial Interface
There are three control registers associated with the I2C bus, I2CCON, I2CADR and I2CSTA and
one data register, I2CDAT. The I2CDAT register is used to store the data being transmitted and
received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be
transmitted must be placed in the I2CDAT register. After the data is received from the I2C bus, the
microcontroller can read it from the I2CDAT register. Any transmission or reception of data from
the I2C bus must be made via the I2CDAT register. The I2CADR register holds the address of the
device slave interface. This address is used by an external device when attempting to access it via
I2C bus. The complete I2C interface operation is controlled by the I2CCON register. The I2CLK
register controls the I 2C clock frequency. In addition, the I 2C Bus status can be reflected by the
I2CSTA register.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Bit 3
Bit 1~0
I2CLK Register
SFR Address: E9h
Bit
7
6
5
4
3
2
1
0
Name
I2CLK.7
I2CLK.6
I2CLK.5
I2CLK.4
I2CLK.3
I2CLK.2
I2CLK.1
I2CLK.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
1
1
0
0
1
Bit 7~0
I2C clock rate bit 7~0
The I2C baud rate calculation is described as follow:
I2C_Baud_Rate =
f SYS
4*(I2CLK[7:0]+5)
Here fSYS is the system clock frequency.
For example, if the system clock is 12MHZ and I2CLK [7:0]=19h(25), then
I2C_baud_rate=12MHz/(4*(25+5))=100Kbit/Sec
Rev. 1.00
179 of 226
May 15, 2013
I2C Serial Interface
Bit 2
SI: Serial Interrupt Request flag
0: No Interrupt request
1: Interrupt request
The SI bit will be set by hardware when one of the 25 out of 26 possible I2C statuses is
entered. The only state that does not set the SI bit is the state F8H, which indicates that
no relevant state information is available. This bit must be cleared by the application
program.
AA: I2C Acknowledge Indication flag
0: No Acknowledge
1: Acknowledge
This bit indicates the type of acknowledge returned during the acknowledge cycle on
the SCL pin. If this bit is cleared to low, a “no acknowledge” (high level on SDA) is
returned during the acknowledge cycle. If the bit is set to high, an “acknowledge” (low
level on SDA) is returned during the acknowledge cycle.
When AA=1, an “acknowledge” will be returned under the following conditions:
- The “own slave address” has been received
- The general call address has been received while the GC bit in the I2CADR register
was set
- A data byte has been received while the I2C was in the master receiver mode
- A data byte has been received while the I2C was in the slave receiver mode
When AA= 0, a “not acknowledge” will be returned under the following conditions:
- A data byte has been received while the I2C was in the master receiver mode
- A data byte has been received while the I2C was in the slave receiver mode
Unimplemented, read as “0”
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I2CSTA Register
SFR Address: DDh
Bit
7
6
5
4
3
2
1
0
Name
IICS7
IICS6
IICS5
IICS4
IICS3
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
POR
1
1
1
1
1
—
—
—
Bit 7~3
I2CDAT Register
SFR Address: DAh
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
0
Note: The I2CDAT register is used as the I2C transmitted or received data register.
I2CADR Register
SFR Address: DBh
Bit
7
6
5
4
3
2
1
Name
IICA6
IICA5
IICA4
IICA3
IICA2
IICA1
IICA0
GC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
IICA6~IICA0: I2C slave address
IICA6~IICA0 is the I2C slave address bit 6~bit 0.
When a master device, which is connected to the I2C bus, sends out an address, which
matches the slave address in the I2CADR register, the slave device will be selected.
Bit 0
GC: General Call Address Acknowledge control bit
0: General Call Address is ignored
1: General Call Address is recognised
This bit is used to enable the General Call Address (00H) recognition function.
The I2CADR register contains the slave address for the I 2C interface. In the Slave mode, the
IICA6~IICA0 bits represent a 7-bit slave address. The GC bit is used to enable the recognition
of the general call address (0x00). If the GC bit is set to “1”, the general call address recognition
function will be enabled. Otherwise, the general call address will be ignored. In the master mode,
the contents of this I2CADR register will be ignored.
Bit 7~1
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I2C Serial Interface
Bit 2~0
IICS7~IICS3: I2C Status Code
These Read-only bits are used to indicate the I2C Status code. Refer to the I2C Status
Code section for details. The contents of the I2CSTA register is only defined when the
SI bit is set high.
Unimplemented, read as “0”
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Data Bus
I2CADR
Address Register
Address Comparator
ACK
Input Filter
Output
Arbitration And
Synchronization Logic
SDA
N
Input Filter
Serial Clock Generator
Output
Open drain
SCL
N
Open drain
Timer1
Overflow
I2CCON
Control Register
I2C Interrupt
I2CSTA
Status Register
I2C Block Diagram
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I2C Serial Interface
I2CDAT
Shift Register
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I2C Bus Communication
During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit,
which is the 8th bit, is the read/write bit. This bit will be checked by the slave device to determine
whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the
microcontroller must initialise the bus. The following are the steps to achieve this:
■■ Step 1
Set the ENS1 bit in the I2CCON register high to enable the I2C bus.
■■ Step 2
Write the slave address of the device to the I2C bus address register I2CADR.
■■ Step 3
Set the EI2C interrupt enable bit of the interrupt control register to enable the I2C interrupt.
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    
I2C Bus Initialisation Flow Chart
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I2C Serial Interface
Communication on the I2C bus requires four separate steps, a START signal, a slave device address
transmission, a data transmission and finally a STOP signal. When a START signal is placed on
the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of
data on the bus. The first seven bits of the data will be the slave address with the first bit being the
MSB. If the address of the slave device matches that of the transmitted address, which means one
of the I2C states is matched, the SI bit in the I2CCON register will be set and an I2C interrupt will
be generated. After entering the interrupt service routine, the devices must first check the status
of the I2CSTA register to determine the interrupt source originating condition. The SI bit is set by
hardware when one of 25 out of 26 possible I2C states is entered. The only state that does not set
the SI bit is the state F8H, which indicates that no relevant state information is available The SI bit
must be cleared by the application program.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I2C Bus Start Signal
The START signal can only be generated by the master device connected to the I2C bus and not by
the slave device. This START signal will be detected by all devices connected to the I2C bus. When
detected, this indicates that the I2C bus is busy and therefore the STA bit will be set. A START
condition occurs when a high to low transition on the SDA line takes place when the SCL line
remains high.
The transmission of a START signal by the master will be detected by all devices on the I2C bus.
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out
by the master matches the internal address of the microcontroller slave device, or if the general
call address, 00H, is received when the GC bit in the I2CADR register is set high, then an internal
I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit,
defines the read/write status. The slave device will then transmit an acknowledge bit, which is a
low level, as the 9th bit. The slave device will also set the flag SI when the addresses match.
As an I 2C bus interrupt will take place if one of the possible I 2C states is matched when the
program enters the interrupt subroutine, the I2CSTA register should be examined to see, for
example, whether the interrupt source has come from a matching slave address or from the
completion of a data byte transfer. When a slave address is matched, the device must be placed
in either the transmit mode and then data written to the I2CDAT register, or in the receive mode
where it must implement a dummy read from the I2CDAT register to release the SCL line. Refer to
the I2C Status Code section for details.
I2C Bus Read/Write Signal
The Read/Write bit, so called as R/W bit, is located in the 8th bit of the address data in the I2CDAT
register. The R/W bit is set high to indicate a read operation and cleared low to indicate a write
operation. The direction bit defines whether the slave device wishes to read data from the I2C bus
or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a
transmitter or a receiver. If the R/W bit is “1” then this indicates that the master device wishes to
read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a
transmitter. If the R/W bit is “0” then this indicates that the master wishes to send data to the I 2C
bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.
I2C Bus Slave Address Acknowledge Signal
After the master has transmitted a calling address, any slave device on the I 2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal. The
acknowledge signal will inform the master that a slave device has accepted its calling address. If no
acknowledge signal is received by the master then a STOP signal must be transmitted by the master
to end the communication. When the SI flag is high, the addresses have matched and the slave
device must check the R/W bit, to determine if it is to be a transmitter or a receiver. If the R/W
bit is high, the slave device should be setup to be a transmitter, and then the microcontroller slave
device should be setup as a receiver.
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I2C Serial Interface
Slave Address
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I2C Bus Data and Acknowledge Signal
The AA bit in the I2CCON register bit indicates the type of acknowledge returned during the
acknowledge cycle on the SCL pin. If this bit is cleared to zero, a "not acknowledge" (high level
on SDA) is returned during the acknowledge cycle. If the bit is set to high, an "acknowledge" (low
level on SDA) is returned during the acknowledge cycle. The slave device, which is setup as a
transmitter will check the AA bit in the I2CCON register to determine if it is to send another data
byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master.
Note: * When a slave address is matched, the device must be placed in either the transmit mode
and then write data to the I2CDAT register, or in the receive mode where it must implement a
dummy read from the I2CDAT register to release the SCL line.
I2C Communication Timing Diagram
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I2C Serial Interface
The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged
receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last.
After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, a low level, before
it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal
from the master receiver, then the slave transmitter will release the SDA line to allow the master to
send a STOP signal to release the I2C Bus. The corresponding data will be stored in the I2CDAT
register. If setup as a transmitter, the slave device must first write the data to be transmitted into
the I2CDAT register. If setup as a receiver, the slave device must read the transmitted data from the
I2CDAT register.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I2C Status Codes
I2C Status in Master Transmitter Mode
Application software response
Status
Code
Status of the I2C
08H
START condition has been
transmitted
10H
Repeated START condition
has been transmitted
18H
20H
28H
30H
38H
to/from
I2CDAT
to I2CCON
STA STO SI AA
Next action taken by
the I2C hardware
Load SLA+W
X
0
0
X
SLA+W will be transmitted; ACK will be received
Load SLA+W
X
0
0
X
SLA+W will be transmitted; ACK will be received
Load SLA+W
X
0
0
X
SLA+R will be transmitted;
I2C will be switched to “Master receiver” mode
Load data byte
0
0
0
X
Data byte will be transmitted; ACK will be received
No action
1
0
0
X
Repeated START will be transmitted;
SLA+W has been transmitted;
No action
ACK has been received
0
1
0
X
STOP condition will be transmitted;
the “STO” flag will be reset
No action
1
1
0
X
STOP condition followed by a START condition
will be transmitted; the “STO” flag will be reset
Load data byte
0
0
0
X
Data byte will be transmitted; ACK will be received
No action
1
0
0
X
Repeated START will be transmitted
SLA+W has been transmitted;
“not ACK” has been received No action
0
1
0
X
STOP condition will be transmitted;
the “STO” flag will be reset
No action
1
1
0
X
STOP condition followed by a START condition
will be transmitted; the “STO” flag will be reset
Load data byte
0
0
0
X
Data byte will be transmitted;
ACK bit will be received
Data byte in I2CDAT has been No action
transmitted;
No action
ACK has been received
1
0
0
X
Repeated START will be transmitted
0
1
0
X
STOP condition will be transmitted;
the “STO” flag will be reset
No action
1
1
0
X
STOP condition followed by a START condition
will be transmitted; STO flag will be reset
data byte
0
0
0
X
Data byte will be transmitted; ACK will be received
No action
1
0
0
X
Repeated START will be transmitted;
Data byte in I2CDAT has been
No action
transmitted
0
1
0
X
STOP condition will be transmitted;
STO flag will be reset
No action
1
1
0
X
STOP condition followed by a START condition
will be transmitted; STO flag will be reset
No action
0
0
0
X
I2C bus will be released;
the “not addressed slave” state will be entered
No action
1
0
0
X
A START condition will be transmitted when the
bus becomes free
Arbitration lost in SLA+R/W or
data bytes
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I2C Serial Interface
The I2CSTA register reflects the current status of the I2C interface. The three least significant bits
of this register are always zero. There are 26 possible status codes, presented in the accompanying
tables. When any one of 25 out of a total of 26 possible I 2C states is entered, an interrupt is
requested. The only state that does not generate an interrupt is the F8h state. The contents of the
I2CDAT register is only available when an I2C interrupt takes place and the SI bit is set high. This
register is read-only and should not be written to by the application program. In the table below, the
term “SLA” means the slave address, “R” means the R/W bit=1 which are transferred together with
the slave address, “W” means the R/W bit=0 transferred together with the slave address.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I2C Status in Master Receiver Mode
Application software response
Status
Code
Status of the I C
2
START condition has been
transmitted
10H
Repeated START condition
has been transmitted
38H
40H
48H
50H
58H
to I2CCON
STA STO SI AA
Next action taken by
the I2C hardware
Load SLA+R
X
0
0
X
SLA+R will be transmitted; ACK will be received
Load SLA+R
X
0
0
X
SLA+R will be transmitted; ACK will be received
Load SLA+W
X
0
0
X
SLA+W will be transmitted;
I2C will be switched to “master transmitter” mode
No action
0
0
0
X
I2C bus will be released;
I2C will enter a “slave” mode
No action
1
0
0
X
A start condition will be transmitted when the bus
becomes free
SLA+R has been transmitted; No action
ACK has been received
No action
0
0
0
0
Data byte will be received;
“not ACK” will be returned
0
0
0
1
Data byte will be received; ACK will be returned
No action
1
0
0
X
Repeated START condition will be transmitted
SLA+R has been transmitted; No action
“not ACK” has been received
0
1
0
X
STOP condition will be transmitted;
the “STO” flag will be reset
No action
1
1
0
X
STOP condition followed by START condition will
be transmitted; the “STO” flag will be reset
Data byte has been received; Read data byte
ACK has been returned
Read data byte
0
0
0
0
Data byte will be received;
“not ACK” will be returned
0
0
0
1
Data byte will be received; ACK will be returned
Read data byte
1
0
0
X
Repeated START condition will be transmitted
Data byte has been received; Read data byte
“not ACK” has been returned
0
1
0
X
STOP condition will be transmitted;
the “STO” flag will be reset
Read data byte
1
1
0
X
STOP condition followed by START condition will
be transmitted; the “STO” flag will be reset
Arbitration lost in “not ACK” bit
Rev. 1.00
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I2C Serial Interface
08H
to/from
I2CDAT
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
I2C Status in Slave Receiver Mode
Application software response
Status
Code
Status of the I C
2
to/from
I2CDAT
0
0
0
Data byte will be received and “not ACK” will be
returned
No action
X
0
0
1
Data byte will be received and ACK will be returned
X
0
0
0
Data byte will be received and “not ACK” will be
returned
X
0
0
1
Data byte will be received and ACK will be returned
No action
X
0
0
0
Data byte will be received and “not ACK” will be
returned
No action
X
0
0
1
Data byte will be received and ACK will be returned
X
0
0
0
Data byte will be received and “not ACK” will be
returned
X
0
0
1
Data byte will be received and ACK will be returned
read data byte
X
0
0
0
Data byte will be received and “not ACK” will be
returned
read data byte
X
0
0
1
Data byte will be received and ACK will be returned
Read data byte
0
0
0
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address
Read data byte
0
0
0
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address;
START condition will be transmitted when the bus
becomes free
68H
Arbitration lost in SLA+R/W
No action
as master;
own SLA+W has been
No action
received, ACK returned
70H
General call address (00H)
has been received;
ACK has been returned
78H
Arbitration lost in SLA+R/W
No action
as master; general call
address has been received,
No action
ACK returned
88H
90H
98H
Previously addressed with
own SLA;
DATA byte has been
received;
“not ACK” returned
Previously addressed with
general call address;
DATA has been received;
ACK returned
Previously addressed with
general call address;
DATA has been received;
not ACK returned
Read data byte
0
0
Read data byte
1
0
0
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized;
START condition will be transmitted when the bus
becomes free
Read data byte
X
0
0
0
Data byte will be received and “not ACK” will be
returned
Read data byte
X
0
0
1
Data byte will be received and ACK will be returned
Read data byte
0
0
0
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address
Read data byte
0
0
0
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address;
START condition will be transmitted when the bus
becomes free
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized;
START condition will be transmitted when the bus
becomes free
Read data byte
Read data byte
Rev. 1.00
1
1
1
0
0
0
0
187 of 226
May 15, 2013
I2C Serial Interface
X
Own SLA+W has been
received;
ACK has been returned
Previously addressed with
own SLV address;
DATA has been received;
ACK returned
STA STO SI AA
Next action taken by
the I2C hardware
No action
60H
80H
to I2CCON
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Application software response
Status
Code
to/from
I2CDAT
to I2CCON
STA STO SI AA
Next action taken by
the I2C hardware
No action
0
0
0
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address
No action
0
0
0
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address;
START condition will be transmitted when the bus
becomes free
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized;
START condition will be transmitted when the bus
becomes free
STOP condition or repeated
S TA R T c o n d i t i o n h a s
been received while still
addressed as SLV/REC or No action
SLV/TRX
No action
1
1
0
0
0
0
I2C Status in Slave Transmitter Mode
Application software response
Status
Code
A8H
B0H
B8H
C0H
Status of the I2C
to/from
I2CDAT
to I2CCON
STA STO SI AA
Next action taken by
the I2C hardware
Load data byte
X
0
0
0
Last data byte will be transmitted and ACK will be
received
Load data byte
X
0
0
1
Data byte will be transmitted;
ACK will be received
Arbitration lost in SLA+R/W Load data byte
as master own SLA+R has
been received;
Load data byte
ACK has been returned
X
0
0
0
Last data byte will be transmitted and ACK will be
received
X
0
0
1
Data byte will be transmitted;
ACK will be received
Data byte has been
transmitted;
ACK has been received
Load data byte
X
0
0
0
Last data byte will be transmitted and ACK will be
received
Load data byte
X
0
0
1
Data byte will be transmitted; ACK will be received
No action
0
0
0
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address
No action
0
0
0
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address;
START condition will be transmitted when the bus
becomes free
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized;
START condition will be transmitted when the bus
becomes free
Own SLA+R has been
received;
ACK has been returned
Data byte has been
transmitted;
not ACK has been received No action
No action
Rev. 1.00
1
1
0
0
0
0
188 of 226
May 15, 2013
I2C Serial Interface
A0H
Status of the I C
2
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Application software response
Status
Code
Last data byte has been
transmitted;
ACK has been received
to/from
I2CDAT
to I2CCON
STA STO SI AA
Next action taken by
the I2C hardware
No action
0
0
0
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address
No action
0
0
0
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized
0
Switched to “not addressed slave” mode;
no recognition of own slave address or general call
address;
START condition will be transmitted when the bus
becomes free
1
Switched to “not addressed slave” mode;
own slave address or general call address will be
recognized;
START condition will be transmitted when the bus
becomes free
No action
1
No action
0
1
0
0
0
I2C Status: Miscellaneous States
Status
Code
Status of the I2C
Application software
response
to/from
I2CDAT
F8H
No relevant state information
No action
available SI=0
00H
Bus error during MST or
selected slave modes
Rev. 1.00
No action
Next action taken by
the I2C hardware
to I2CCON
STA STO SI AA
No action
0
1
0
Wait or proceed current transfer
X
189 of 226
Only the internal hardware is affected in the “master”
or “addressed slave” modes.
In all cases, the bus is released and I2C is switched to
the “not addressed slave” mode.
The “STO” flag is reset.
May 15, 2013
I2C Serial Interface
C8H
Status of the I C
2
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
35
Serial Interface – SPI
SPI Interface Operation
The SPI interface is a full duplex synchronous serial data link. The SPI interface is disabled or
enabled using the SPEN bit in the SPCON register which configures the functionally shared pins as
SPI pins and disables their logic I/O function. The SPI interface is a slave/master type, where the
device can be either master or slave decided by the MSTR bit in the SPCON register. It is a four line
interface with pin names, MOSI, MISO, SCK and SSN. Pins MOSI and MISO are the Serial Data
Input and Serial Data Output lines, SCK is the Serial Clock line and SSN is the Slave Select line.
Communication between devices connected to the SPI interface is carried out in a slave/master
mode with all data transfer initiations being implemented by the master. The Master also controls
the clock signal.
Single SPI Master and single Slave Connection
Rev. 1.00
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May 15, 2013
Serial Interface – SPI
The SPI interface is often used to communicate with external peripheral devices such as sensors,
Flash Memory or EEPROM memory devices etc. Originally developed by Motorola, the four line
SPI interface is a synchronous serial data interface that has a relatively simple communication
protocol simplifying the programming requirements when communicating with external hardware
devices.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Data Bus
SPDAT
Clock
Level/Edge
Setup
Clock Active
Edge Select
CHPA bit
�OSI pin
WCOL
SPI Control
SCK pin
Status
Flags
Clock
Source
Select
SPR0
�ISO pin
Tx/Rx Shift Register
SPIF
SSERR
�ODF
Clock
Division
Select
SPR1
SPR�
�STR bit
�aster/Slave
Control
SSN pin
SSDIS bit
fs�s
�STR bit
SPI Interface Block Diagram
SPI Features
The SPI function in the devices have the following features:
■■ Full duplex synchronous data transfer
■■ Three wire synchronous transfers
■■ Dual Master and Slave modes
■■ Seven SPI Master baud rates
■■ Slave Clock rate up to fSYS/8
■■ Serial clock with programmable polarity and phase
■■ Master Mode fault error flag with MCU interrupt capability
■■ Write collision flag protection
■■ Data transmitted by MSB First, LSB Last mode
Rev. 1.00
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May 15, 2013
Serial Interface – SPI
Clock Base
Level Select
CPOL bit
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
SPI Registers
There are three internal registers which control the overall operation of the SPI interface. These
are the SPDAT data register, where the received data or transmitted data is stored and two control
registers SPCON and SPSTA.
SPI Register List
Bit
7
6
5
4
3
2
1
0
SPCON
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
SPSTA
SPIF
WCOL
SSERR
MODF
—
—
—
—
SPDAT
D7
D6
D5
D4
D3
D2
D1
D0
The SPDAT register is used to store the data being transmitted and received. Before the device
writes data to the SPI bus, the actual data to be transmitted must be placed in the SPDAT register.
After the data is received from the SPI bus, the device can read the data from the SPDAT register.
Any transmission or reception of data from the SPI bus must be made via the SPDAT register.
SPDAT Register
SFR Address: E3h
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
There are also two control registers for the SPI interface, SPCON and SPSTA. Register SPCON
is used to control the enable/disable function, to assign the clock Polarity/Edge types, to
enable/disable the SPI function and to set the data transmission clock frequency. Register SPSTA
is used to indicate the SPI operational status, such as data transferred complete flag, write collision
flag, Synchronous Serial Slave Error flag and SPI mode Fault detection flag etc. When any one of
the SPIF, WCOL, SSERR and MODF flags in the SPSTA register is set high, an SPI interrupt will
occur if the SPI interrupt function is enabled.
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Serial Interface – SPI
Register
Name
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
SPCON Register
SFR Address: E8h
Bit
7
6
5
4
3
2
1
0
Name
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
1
0
1
0
0
Bit 7, 1, 0
Bit 5
Bit 4
Bit 3
Bit 2
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Serial Interface – SPI
Bit 6
SPR2, SPR1, SPR0: Master Clock Select
000: Reserved
001: f SYS/4
010: f SYS/8
011: f SYS/16
100: f SYS/32
101: f SYS/64
110: f SYS/128
111: Master clock not generated
SPEN: SPI enable or disable
0: Disable
1: Enable
When set high, the SPI interface internal circuits will be enabled. All the relevant
functionally shared pins will be enabled to have SPI functions and their original logical
I/O functions will be disabled. When cleared to zero, the SPI interface will be disabled,
and all the functionally shared pins will have a logical I/O function.
SSDIS: SSN pin disable control
0: Enable
1: Disable, SSN pin floating
When this bit is cleared to zero, the “SSN” input is enabled in both Master and Slave
modes. When set high, the “SSN” input is disabled in both Master and Slave modes. In
the Slave mode, this bit has no effect if “CPHA”=0. When the bit is high, no “MODF”
interrupt request will be generated.
MSTR: SPI Master or Slave
0: Slave
1: Master
CPOL: SPI Clock Polarity
0: SCK low when clock is inactive
1: SCK high when clock is inactive
The CPOL bit determines the SPI clock polarity when not active.
CPHA: SPI Active Clock Edge Select
0: Data sampled on first clock edge
1: Data sampled on second clock edge
The CPHA and CPOL bits are used to setup the way that the clock signal transmits data
on the SPI bus. These two bits must be configured before a data transfer is executed.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
SPSTA Register
SFR Address: E1h
Bit
7
6
5
4
3
2
1
0
Name
SPIF
WCOL
SSERR
MODF
—
—
—
—
R/W
R/W
R/W
R/W
R/W
—
—
—
—
POR
0
0
0
0
—
—
—
—
Bit 7
Bit 5
Bit 4
Bit 3~0
Rev. 1.00
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Serial Interface – SPI
Bit 6
SPIF: SPI Transmit/Receive Complete Flag
0: Data is being transferred
1: SPI data transmission completed
The SPIF bit is the Transmit/Receive Complete flag and is set high automatically when
an SPI data transmission is completed, it must be cleared using the application program.
The SPIF bit can be also cleared by hardware when the data transfer is in progress. It
can also be used to generate an interrupt.
WCOL: SPI Write Collision Flag
0: No collision
1: Collision
The WCOL flag is used to detect if a data collision has occurred. If this bit is high it
means that data has been attempted to be written to the SPDAT register during a data
transfer operation. A SPI interrupt will occur if the SPI interrupt function is enabled.
This writing operation will be ignored if data is being transferred. It must be cleared
using the application program.
SSERR: Synchronous Serial Slave Error Flag
0: No error
1: Error
This bit is set by hardware when the SSN pin input is selected to disable the Slave
device status while the receive sequence is incomplete. A SPI interrupt will occur if the
SPI interrupt function is enabled. This bit will be cleared by disabling the SPI module,
clearing the SPEN bit in the SPCON register.
MODF: SPI Master/Slave Mode Mismatch Flag
0: No Mismatch
1: Mismatch
This bit is set by hardware when the Slave Select SSN pin level conflicts with actual
Master/Slave mode of the SPI Master controller which is configured as a master while
externally selected as a slave. A SPI interrupt will occur if the SPI interrupt function is
enabled. It must be cleared using the application program.
Unimplemented, read as “0”
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
SPI Communication
The master should output an SSN signal to enable the slave device before a clock signal is provided.
The slave data to be transferred should be well prepared at the appropriate moment relative to the
SSN signal depending upon the configurations of the CPOL bit and CPHA bit. The accompanying
timing diagram shows the relationship between the slave data and SSN signal for various
configurations of the CPOL and CPHA bits.
SPI Master Mode Timing
Rev. 1.00
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Serial Interface – SPI
The SPI interface is first enabled by setting the SPEN bit high. This enables the internal SPI
circuitry and also enables all the SPI pins which also disabled all of the logical I/O functions. In
the Master Mode, when data is written to the SPDAT register, transmission/reception will begin
simultaneously. When the data transfer is complete, the SPIF flag will be set automatically, but
must be cleared using the application program. In the Slave Mode, when the clock signal from the
master has been received, any data in the SPDAT register will be transmitted and any data on the
MISO pin will be shifted into the SPDAT register.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Serial Interface – SPI
SPI Slave Mode Timing – CPHA=0
SPI Slave Mode Timing – CPHA=1
Rev. 1.00
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May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
    ‡
 Serial Interface – SPI
­ € ‚ ƒ ‚
 „ †‡ ˆ
 
  
   SPI Transfer Control Flowchart
Rev. 1.00
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May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
36
UART Serial Interfaces – UART0 and UART1
UART Overview
UART0 provides a flexible full-duplex synchronous/asynchronous receiver/transmitter and has four
operating modes while UART1 provides a flexible full-duplex asynchronous receiver/transmitter
with two operating modes. Both of them have programmable Baud Rates. The UART functions
have many features and can transmit and receive data serially by transferring a frame of data with
eight or nine data bits per transmission. The UART functions possesses their own internal interrupt
which can be used to indicate when a data reception operation has occurred or when a data
transmission operation has terminated.
UART0 Features
The integrated UART0 function contains the following features:
■■ Full-duplex, synchronous and asynchronous communication
■■ Four operating modes
■■ 8 or 9 bits character length
■■ Programmable Baud rate generator
■■ Separately enabled transmitter and receiver
■■ 2-byte Deep FIFO Receive Data Buffer
■■ Transmission and reception of interrupts
■■ Fully compatible with the standard 8051 serial channel
UART1 Features
The integrated UART1 function contains the following features:
■■ Full-duplex, asynchronous communication
■■ Two operating modes
■■ 8 or 9 bits character length
■■ Programmable Baud rate generator
■■ Separately enabled transmitter and receiver
■■ 2-byte Deep FIFO Receive Data Buffer
■■ Transmission and reception of interrupts
■■ Fully compatible with the standard 8051 serial channel
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
Two fully integrated serial communications UART interfaces, namely UART0 and UART1, enable
the communication with external devices that contain a similar serial interface. The UART1 is
only available on the HT85F2270/2280. Although what is known as a UART function essentially
provides only asynchronous data transfer operations, UART0 also provides extended synchronous
data transfer operations.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Basic UART Data Transfer Scheme
The block diagram shows the overall UART data transfer structure arrangement. For data
transmission, the actual data to be transmitted from the MCU is first transferred to the transmitted
register by the application program. The data will then be transferred to the Transmit Shift Register
from where it will be shifted out, LSB first, onto the transmitter pin, TXDn, at a rate controlled by
the Baud Rate Generator. Only the transmitted register is mapped onto the MCU Data Memory, the
Transmit Shift Register is not mapped and is therefore inaccessible to the application program.
It should be noted that the actual register for data transmission and reception, only exists as a single
shared register in the Data Memory, known as the S0BUF register in the UART0 or the S1BUF
register in the UART1, and is used for both data transmission and data reception.
T r a n s m itte r S h ift R e g is te r
M S B
T r a n s m it
T X D n P in
L S B
R e c e iv e r S h ift R e g is te r
R e c e iv e
R X D n P in
C L K
M S B
L S B
C L K
T r a n s m it R e g is te r
B a u d R a te
G e n e ra to r
R e c e iv e R e g is te r
B u ffe r
M C U D a ta B u s
Basic UART Data Transfer Diagram
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
For data reception, data to be received by the UART is accepted on the external receive pin,
RXDn, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled
by the Baud Rate Generator. When the shift register is full, the data will then be transferred from
the shift register to the internal received register, where it is buffered and can be manipulated by
the application program. Only the received register is mapped onto the MCU Data Memory, the
Receiver Shift Register is not mapped and is therefore inaccessible to the application program.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
UART0 Operating Description
This section provides a more detailed description of the UART0 structure and operation. The
following shows the overall UART0 block diagram.
Transmit Shift Register
UART0 Baud Rate
Control Unit
TXD0
RXD0
RI0
TI0
Receive Shift Register
Input
Latch
RXD0
S0BUF
UART 0 Block Diagram
UART0 External Pin Interfacing
To communicate with an external serial interface, the UART0 has two external pins known as
TXD0 and RXD0. The UART0 provides four operating modes which can be categorised into
two transmitter/receiver methods, so called Synchronous and Asynchronous. In Synchronous
communication, the MCU must be the master device and the TXD0 pin is used to provide the
shift clock while the RXD0 pin is used as the data transmitter/receiver pin. In Asynchronous
communication, which does require a clock signal, the TXD0 pin is used to transmit data while the
RXD0 pin is used as the data receive pin. The TXD0 and RXD0 pins are pin shared with I/O pins.
When the UART0 function is disabled, controlled by the REN0 bit in the S0CON register, these
two pins can be used as general purpose I/O pins.
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
MCU Data Bus
Output
Latch
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
UART0 Register Description
There are several control registers associated with the UART0 function. The S0CON register
controls the overall function of the UART0, while the SBRCON, SPPRE, S0RELL and S0RELH
registers control the Baud rate. The actual data to be transmitted and received on the serial
interface is managed through the S0BUF data register. The SMOD bit in the PCON register is used
to double the baud rate clock.
Register
Name
Bit
7
6
5
4
3
2
1
0
S0CON
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
S0RELL
S0REL.7
S0REL.6
S0REL.5
S0REL.4
S0REL.3
S0REL.2
S0REL.1
S0REL.0
S0REL.8
S0RELH
—
—
—
—
—
—
S0REL.9
S0BUF
D7
D6
D5
D4
D3
D2
D1
D0
SPPRE
—
—
—
—
S1PRE1
S1PRE0
S0PRE1
S0PRE0
SBRCON
BD
BD1
—
—
—
—
—
—
PCON
SMOD
—
—
—
—
GF0
PD
IDL
S0BUF Register – UART0 Data register
SFR Address: 99h
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
UART0 data buffer
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UART Serial Interfaces – UART0 and UART1
UART0 Register List
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
S0CON Register – UART0 Control register
SFR Address: 98h
Bit
7
6
5
4
3
2
Name
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~6
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
0
SM0, SM1: UART0 Operating mode select bits
00: Mode 0
01: Mode 1
10: Mode 2
11: Mode 3
The following table illustrates the corresponding mode descriptions and baud rates. In
mode1 and mode 3, the variable baud rate is dependent on the system clock, the baud
rate clock source and the prescaler selections. Operating mode details are described
elsewhere.
Mode
Mode Name
Baud Rate
Synchronisation
Mode 0
8-bit shift register
fSYS/12
Synchronous
Mode 1
8-bit UART
Variable
Asynchronous
Mode 2
9-bit UART
SP0CLK/32 or
SP0CLK/64
Asynchronous
Mode 3
9-bit UART
Variable
Asynchronous
Note that the SP0CLK is described in the UART0 Baud Rate Setup section.
SM20: Multiprocessor communication enable control
0: Disable
1: Enable
Refer to the UART0 Multiprocessor Communication section for details.
REN0: UART0 serial data reception enable control
0: Disable
1: Enable
TB80: Ninth Transmit bit assignment
0: Low
1: High
This bit is only available in Mode 2 and Mode 3. It is not effective in Mode 0 and Mode
1. The bit is assigned using the application program.
RB80: Ninth Receive bit assignment
0: Low
1: High
This bit is used to assign the level of the ninth bit in Mode 2 and Mode 3. In mode 1, if
the SM20 bit is zero, the RB80 bit is assigned as the level of the received stop bit. It is
not available in Mode 0.
TI0: UART0 transmit interrupt flag
0: No interrupt request
1: Interrupt request
This bit must be cleared using the application program.
RI0: UART0 receive interrupt flag
0: No interrupt request
1: Interrupt request
This bit must be cleared using the application program.
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UART Serial Interfaces – UART0 and UART1
Bit 5
1
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
S0RELL Register – UART0 Reload Low Register
SFR Address: AAh
7
6
5
4
3
2
1
0
Name
S0REL.7
S0REL.6
S0REL.5
S0REL.4
S0REL.3
S0REL.2
S0REL.1
S0REL.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
0
1
1
0
0
1
3
2
1
0
S0RELH Register – UART0 Reload High Register
SFR Address: BAh
Bit
7
6
5
4
Name
—
—
—
—
—
—
S0REL.9
S0REL.8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
1
1
The UART0 Reload registers, S0RELL and S0RELH, are used to setup the UART0 baud rate
generation. The UART0 baud rate setup range is 10-bit wide, consisting of 8 bits in S0RELL and 2
bits in S0RELH.
SPPRE Register – UART Clock Prescaler Register
SFR Address: A5h
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
S1PRE1
S1PRE0
S0PRE1
S0PRE0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
1
1
1
1
Bit 7~4
Bit 3~2
Bit 1~0
Rev. 1.00
Unimplemented, read as “0”
S1PRE1, S1PRE0: UART 1 Reload Counter Clock Select
00: f SYS/12
01: f SYS/6
10: f SYS/4
11: f SYS
S0PRE1, S0PRE0: UART 0 Reload Counter Clock Select
00: f SYS/12
01: f SYS/6
10: f SYS/4
11: f SYS
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UART Serial Interfaces – UART0 and UART1
Bit
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
SBRCON Register
SFR Address: DCh
Bit
7
6
5
4
3
2
1
0
Name
BD
BD1
—
—
—
—
—
—
R/W
R/W
R/W
—
—
—
—
—
—
POR
0
0
—
—
—
—
—
—
Bit 7
Bit 5~0
PCON Register
SFR Address: 87h
Bit
7
6
5
4
3
2
1
0
Name
SMOD
—
—
—
—
GF0
PD
IDL
R/W
R/W
—
—
—
R
R/W
R/W
R/W
POR
0
—
—
—
1
0
0
0
Bit 7
Bit 6~3
Bit 2
Bit 1
Bit 0
Rev. 1.00
SMOD: UART0 double baud rate select
0: Not double
1: Double
Unimplemented
GF0: General Purpose Flag
PD: Power-Down Mode control bit
Described elsewhere
IDL: IDLE Mode control bit
Described elsewhere
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UART Serial Interfaces – UART0 and UART1
Bit 6
BD: UART0 Baud rate select for mode 1 and mode 3
0: Timer 1 overflow baud rate generator
1: SRELL and SRELH register controlled baud rate generator
The SRELL and SRELH registers combine to form a 10-bit reload register pair for the
Baud rate generator.
BD1: UART1 internal Baud rate generator enable control (only available on HT85F2280/2270)
0: Disable
1: Enable
Unimplemented, read as “0”
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
UART0 Operating Modes
UART0 provides four operation modes, selected by the SM1 and SM0 bits in the S0CON register.
There are one synchronous and three asynchronous modes, offering different baud rates and
functional options. The following table illustrates the different operational mode list. When a
transmit/receive data transfer operation has completed, a transmit/receive interrupt will take place
and the interrupt request bit, TI0 or RI0, will be set high.
Mode
Mode Name
Baud Rate
Synchronisation
Mode 0
8-bit shift register
fSYS/12
Synchronous
Start/Stop Bits
None
Mode 1
8-bit UART
Variable
Asynchronous
1 Start, 1 Stop
Mode 2
9-bit UART
SP0CLK/32 or SP0CLK/64
Asynchronous
1 Start, 1 Stop
Mode 3
9-bit UART
Variable
Asynchronous
1 Start, 1 Stop
Mode 0
Mode 0 is an integrated half-duplex synchronous serial communication interface. The 8 bits of
data are communicated via the RXD0 pin while the TXD0 pin provides the shift clock for this
communication. The data will then be transferred to the Transmit Shift Register from where it will
be shifted out, LSB first, onto the RXD0 pin at a fixed Baud rate of f SYS/12. The Transmission is
started by writing a data into the S0BUF register.
Data to be received by the UART is accepted on the external RXD0 pin, from where it is shifted in,
LSB first, to the Receiver Shift Register at a fixed Baud rate of f SYS/12. The reception is started by
setting the REN0 bit in the S0CON register to “1”. When the shift register is full, the data will then
be transferred from the shift register to the internal S0BUF register, where it is buffered and can be
manipulated by the application program.
UART0 Mode 0 Timing Diagram
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
UART0 Operating Modes
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Data transmission is started by writing to the S0BUF register. The TXD0 pin outputs the serial
data. The first bit transmitted is a start bit, always “0”, then 8 bits of data, after which a stop bit,
always “1”, is transmitted.
Data to be received by the UART is accepted on the external RXD0 pin. When reception starts, the
UART0 synchronises with the falling edge detected by the RXD0 pin. Input data is available after
one byte of data is complete in the S0BUF register and the value of the STOP bit is available as the
RB80 flag in the S0CON register. During the reception process, the S0BUF data and the RB80 bit
will remain unchanged until the process is complete.
 UART0 Mode 1 Timing Diagram
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
Mode 1
Mode 1 is an integrated full-duplex asynchronous serial communication interface with a variable
baud rate. The 8 bits of data are received via the RXD0 pin while the TXD0 pin is the data transmit
pin for this communication mode. For data reception, data received on the RXD0 pin will be
shifted into the Receive Shift Register by the Baud rate generator. For data transmission, data in
the Transmit Shift Register will be shifted out onto the TXD0 pin by the Baud rate generator. The
Baud rate frequency is selected by the BD bit in the SBRCON register to be either sourced from the
Timer1 overflow or to be setup by the S0RELL/S0RELH registers. In addition, the Baud rate can
be doubled using the SMOD bit in the PCON register.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Data transmission is started by writing to the S0BUF register. The TXD0 pin outputs the serial
data. The first bit transmitted is a start bit, always “0”, then 9 bits of data where the 9th bit is taken
from the TB80 bit of the S0CON register, after which a stop bit, always “1”, is transmitted.
Data to be received by the UART0 is accepted on the external RXD0 pin. When reception starts,
the UART0 synchronises with the falling edge detected by the RXD0 pin. Input data is available
after one byte of data is complete in the S0BUF register, and the 9th bit is available as the RB80 bit
in the S0CON register. During the reception process, the S0BUF data and the RB80 bit will remain
unchanged until the process is complete.
   UART0 Mode 2 Timing Diagram
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
Mode 2
Mode 2 is an integrated full-duplex asynchronous serial communication interface. The 9 bits
of data are received via the RXD0 pin while the TXD0 pin is the data transmit pin for this
communication mode. For data reception, data received on the RXD0 pin will be shifted into the
Receive Shift Register by the Baud rate generator. For data transmission, data in the Transmit Shift
Register will be will be shifted out onto the TXD0 pin by the Baud rate generator. The Baud rate
is fixed at a value of SP0CLK/32 or SP0CLK/64, depending on the setting of the SMOD bit in the
PCON register.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Data transmission is started by writing to the S0BUF register. The TXD0 pin outputs the serial
data. The first bit transmitted is a start bit, always “0”, then 9 bits of data where the 9th bit is taken
from the TB80 bit of the S0CON register, after which a stop bit, always “1”, is transmitted.
Data to be received by the UART is accepted on the external RXD0 pin. When reception starts, the
UART0 synchronizes with the falling edge detected by the RXD0 pin. Input data is available after
one byte of data is complete in the S0BUF register, and the 9th bit is available as the RB80 bit in
the S0CON register. During the reception process, the S0BUF data and the RB80 bit will remain
unchanged until the process is complete.
   UART0 Mode 3 Timing Diagram
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
Mode 3
The only difference between Mode 2 and Mode 3 is that the internal Baud rate is variable in
Mode 3, whereas it is fixed in Mode 2. Mode 3 is an integrated full-duplex asynchronous serial
communication interface. The 9 bits of data are received via the RXD0 pin while the TXD0 pin
is the data transmit pin for this communication mode. For data reception, data received on the
RXD0 pin will be shifted into the Receive Shift Register by the Baud rate generator. For data
transmission, data in the Transmit Shift Register will be will be shifted out onto the TXD0 pin by
the Baud rate generator. The Baud rate frequency is selected by the BD bit in the SBRCON register
to be either sourced from the Timer1 overflow or to be setup by the S0RELL/S0RELH registers. In
addition, the Baud rate can be doubled using the SMOD bit in the PCON register.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
UART0 Multiprocessor Communication
As UART0 can receive 9 bits in Modes 2 and 3, it can be used for multiprocessor communication.
When the SM20 bit in the S0CON register is set, the received interrupt is generated only when the
9th received bit, the RB80 bit in the S0CON register, is high. Otherwise, no interrupt is generated
upon reception.
UART0 Baud Rate Setup
The UART0 operating Modes1 and 3, have a variable baud rate setup using the UART0 Baud rate
generator. The clock source can be selected to be either the Timer 1 overflow or the system clock,
decided by the BD bit in the SBRCON register. The baud rate generator can be controlled by the
S0RELH and S0RELL registers and the clock is the output of the prescaler, defined by the S0PRE0
and S0PRE1 bits. Operating Mode 0 has a fixed baud rate of f SYS/12 and operating Mode 2, has two
baud rates, SP0CLK/64 and SP0CLK/32, selected by the SMOD bit in the PCON register.
S0RELH[1:0] S0RELL[7:0]
fSYS
Prescaler
fSYS
fSYS/4
fSYS/6
fSYS/12
M
U
X
SP0CLK
÷2
SP0CLK/2
10-bit Timer
Timer 1
Overflow 0
MUX
1
÷2
÷16
SMOD
Variable
fSYS/12
/
BD
÷2
S0PRE0
S0PRE1
÷16
MUX
00
UART0
Baud Rate
10
/
SMOD
SP0CLK/64
or
SP0CLK/32
01, 11
SM[1:0]
UART0 Baud Rate Generator
The Variable baud rate, which is provided for Mode 1 and Mode 3, can be derived using the
following two equations, depending upon the BD bit condition.
BD=0 – Timer1 overflow clock source.
Baud _ Rate =
2 SMOD
* (Timer1 _ Overflow _ Rate)
32
BD=1 – Register select clock Source.
Baud _ Rate =
Rev. 1.00
2 SMOD
* ( Freq _ of _ SP 0CLK )
64 * (2 − S 0 REL[9 : 0])
10
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UART Serial Interfaces – UART0 and UART1
To utilise this feature for multiprocessor communication, the slave processors have their SM20 bit
set high. The master processor transmits the slave’s address, with the 9th bit set high, generating a
reception interrupt in all of the slaves. The slave processors’ software compares the received byte
with their network address. If there is a match, the addressed slave clears its SM20 flag and the rest
of the message is transmitted from the master with the 9th bit cleared to zero. The other slaves keep
their SM20 set high so that they ignore the rest of the message sent by the master. In this way, there
are reduced program overheads to distinguish the target slave MCU.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
UART1 Operating Description
This section provides a more detailed description of the UART1 structure and operation. The
following shows the overall UART1 block diagram.
MCU Data Bus
Output
Latch
Control Unit
TXD1
RI1
TI1
Receive Shift Register
Input
Latch
RXD1
S1BUF
UART1 Block Diagram
UART1 External Pin Interfacing
To communicate with an external serial interface, the internal UART1 each has two external
pins known as TXD1 and RXD1. The UART1 provides two operating modes both of which use
Asynchronous communication. The TXD1 pin is used to transmit data while the RXD1 pin is
used as the data reception pin. The TXD1 and RXD1 pins are pin shared with I/O pins. When the
UART1 function is disabled, controlled by the REN1 bit in the S1CON register, these two pins can
be used as general purpose I/O pins.
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
Transmit Shift Register
UART1 Baud Rate
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
UART1 Register Description
There are several control registers associated with the UART1 function. The S1CON register
controls the overall function of the UART1, while the SPPRE, S1RELL and S1RELH registers
control the Baud rate. The actual data to be transmitted and received on the serial interface is
managed through the S1BUF data register.
UART1 Register List
Bit
7
6
5
4
3
2
1
0
S1CON
SM
—
SM21
REN1
TB81
RB81
TI1
RI1
S1RELL
S1REL.7
S1REL.6
S1REL.5
S1REL.4
S1REL.3
S1REL.2
S1REL.1
S1REL.0
S1REL.8
S1RELH
—
—
—
—
—
—
S1REL.9
S1BUF
D7
D6
D5
D4
D3
D2
D1
D0
SPPRE
—
—
—
—
S1PRE1
S1PRE0
S0PRE1
S0PRE0
S1BUF Register – UART1 Data register
SFR Address: 9Ch
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
Rev. 1.00
UART1 data buffer
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UART Serial Interfaces – UART0 and UART1
Register
Name
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
S1CON Register – UART1 Control register
SFR Address: 9Bh
Bit
7
6
5
4
3
2
Name
SM
—
SM21
REN1
TB81
RB81
TI1
RI1
R/W
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
—
0
0
0
0
0
0
Bit 7
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Rev. 1.00
0
SM: UART1 Operating mode select bit
0: Mode A
1: Mode B
The following table illustrates the corresponding mode descriptions and baud rates.
Operating mode details are described elsewhere.
SM bit
Mode
Mode Name
Baud Rate
Synchronisation
0
Mode A
9-bit UART
Variable
Asynchronous
1
Mode B
8-bit UART
Variable
Asynchronous
Unimplemented, read as “0”
SM21: Multiprocessor communication enable control
0: Disable
1: Enable
Refer to the UART1 Multiprocessor Communication section for details.
REN1: UART1 serial data reception enable control
0: Disable
1: Enable
TB81: Ninth Transmit bit assignment
0: Low
1: High
This bit is only available in Mode A. It is not effective in Mode B. The bit is assigned
using the application program.
RB81: Ninth Receive bit assignment
0: Low
1: High
This bit is used to assign the level of the ninth bit in Mode A. In mode A, if the SM21
bit is zero, the RB81 bit is assigned as the level of the received stop bit. It is not
available in Mode B.
TI1: UART1 transmit interrupt flag
0: No interrupt request
1: Interrupt request
This bit must be cleared using the application program.
RI1: UART1 receive interrupt flag
0: No interrupt request
1: Interrupt request
This bit must be cleared using the application program.
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UART Serial Interfaces – UART0 and UART1
Bit 6
Bit 5
1
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
S1RELL Register – UART1 Reload Low Register
SFR Address: 9Dh
Bit
7
6
5
4
3
2
1
0
Name
S1REL.7
S1REL.6
S1REL.5
S1REL.4
S1REL.3
S1REL.2
S1REL.1
S1REL.0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
S1REL.9
S1REL.8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
1
1
The UART1 Reload registers, S1RELL and S1RELH, are used to setup the UART1 baud rate
generation. The UART1 baud rate setup range is 10-bit wide, consisting of 8 bits in S1RELL and 2
bits in S1RELH.
SPPRE Register – UART Clock Prescaler Register
SFR Address: A5h
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
S1PRE1
S1PRE0
S0PRE1
S0PRE0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
1
1
1
1
Bit 7~4
Bit 3~2
Bit 1~0
Rev. 1.00
Unimplemented, read as “0”
S1PRE1, S1PRE0: UART 1 Reload Counter Clock Select
00: f SYS/12
01: f SYS/6
10: f SYS/4
11: f SYS
S0PRE1, S0PRE0: UART 0 Reload Counter Clock Select
00: f SYS/12
01: f SYS/6
10: f SYS/4
11: f SYS
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UART Serial Interfaces – UART0 and UART1
S1RELH Register – UART1 Reload High Register
SFR Address: BBh
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
UART1 Operating Modes
UART1 provides two operational modes, selected by the SM bit in the S1CON register. There are
two asynchronous modes, offering different baud rates and functional options. The following table
illustrates the different operational mode list. When the transmit/receive data process is complete,
the transmit/receive interrupt will take place and the interrupt request bit, TI1 or RI1, will be set
high.
SM bit
Mode
Mode Name
Baud Rate
Synchronisation
Start/Stop Bits
1
Mode B
8-bit UART
Variable
Asynchronous
1 Start, 1 Stop
0
Mode A
9-bit UART
Variable
Asynchronous
1 Start, 1 Stop
Mode A
Mode A is an integrated full-duplex asynchronous serial communication interface. The 9 bits
of data are received via the RXD1 pin while the TXD1 pin provides the data transmit for this
communication. The data will then be transferred to the Transmit Shift Register from where it
will be shifted out onto the TXD1 pin by the UART1 Baud rate generator. The internal Baud rate
generator is enabled/disabled by the BD1 bit of the SBRCON register. The S1RELL/S1RELH
registers must be used to setup the Baud rate generator.
Data transmission is started by writing to the S1BUF register. The TXD1 pin outputs the serial
data. The first bit transmitted is a start bit, always “0”, and then 9 bits of data where the 9th bit is
taken from the TB81 bit of the S1CON register, after which a stop bit, always “1”, is transmitted.
Data to be received by the UART1 is accepted on the external RXD1 pin. When reception starts,
the UART1 synchronises with the falling edge detected by the RXD1 pin. Input data is available
after one byte of data is complete in the S1BUF register, and the ninth bit is available as the RB81
bit in the S1CON register. During the reception process, the S1BUF data and the RB81 bit will
remain unchanged until the process is complete.
   UART1 Mode A Timing Diagram
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
UART1 Operating Modes
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Mode B
Mode B is an integrated full-duplex asynchronous serial communication interface. The 8 bits
of data are received via the RXD1 pin while the TXD1 pin provides the data transmit for this
communication. The data will then be transferred to the Transmit Shift Register from where it
will be shifted out onto the TXD1 pin by the UART1 Baud rate generator. The internal Baud rate
generator is enabled/disabled by the BD1 bit of the SBRCON register. The S1RELL/S1RELH
registers must be used to setup the Baud rate generator.
Data to be received by the UART1 is accepted on the external RXD1 pin. When reception starts,
UART1 synchronises with the falling edge detected by the RXD1 pin. Input data is available after
one byte of data is complete in the S1BUF register and the value of the STOP bit is available as the
RB81 flag in the S1CON register. During the reception process, the S1BUF data and the RB81 bit
will remain unchanged until the process is complete.
 UART1 Mode B Timing Diagram
Rev. 1.00
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UART Serial Interfaces – UART0 and UART1
Data transmission is started by writing data to the S1BUF register. The TXD1 pin outputs data.
The first bit transmitted is a start bit, always “0”, then 8 bits of data, after which a stop bit, always “1”,
is transmitted.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
UART1 Multiprocessor Communication
As UART1 can receive 9 bits in Mode A, it can be used for multiprocessor communication. When
the SM21 bit in the S1CON register is set, the receive interrupt is generated only when the 9th
received bit, the RB81 bit in the S1CON register, is high. Otherwise, no interrupt is generated upon
reception.
UART1 Baud Rate Setup
The UART1 operating Modes A and B, have a variable baud rate setup using the UART1 Baud
rate generator. The clock source is sourced from the system clock. The baud rate generator can be
controlled using the S1RELH and S1RELL registers and the clock is selected using the S1PRE0 and
S1PRE1 bits.
S1RELH[1:0]
S1RELL[7:0]
fSYS
fSYS/4
Prescaler
fSYS
M
U
X
fSYS/6
fSYS/12
SP1CLK
÷2
10-bit Timer
÷16
UART1
Baud Rate
/
S1PRE0
S1PRE1
UART1 Baud Rate Generator
The Variable baud rate can be derived using the following equation:
Baud _ Rate =
Rev. 1.00
1
* ( Freq _ of _ SP1CLK )
32 * (2 − S1REL[9 : 0])
10
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UART Serial Interfaces – UART0 and UART1
To utilise this feature for multiprocessor communication, the slave processors have their SM21 bit
set to high. The master processor transmits the slave’s address, with the 9th bit set high, generating
a reception interrupt in all of the slaves. The slave processors’ software compares the received byte
with their network address. If there is a match, the addressed slave clears its SM21 flag and the rest
of the message is transmitted from the master with the 9th bit set to low. The other slaves keep their
SM21 set high so that they ignore the rest of the message sent by the master. In this way, there are
reduced program overheads to distinguish the target slave MCU.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
37
Instruction Set
Introduction
The following two tables contain notes on mnemonics used in Instruction set.
Notes on Data Addressing Modes
Symbol
Description
Rn
Working register R0~R7.
direct
One of 128 internal RAM locations or any Special Function Register.
@Ri
Indirect internal or external RAM location addressed by register R0 or R1.
#data
8-bit constant included in instruction (immediate operand).
#data 16
16-bit constant included as bytes 2 and 3 of instruction (immediate operand).
bit
One of 128 software flags located in internal RAM, or any flag of bit-addressable Special Function
Registers, including I/O pins and status word.
A
Accumulator.
Notes on Program Addressing Modes
Symbol
Description
addr16
Destination address for LCALL or LJMP, can be anywhere within the 64-Kbyte page of program
memory address space.
addr11
Destination address for ACALL or AJMP, within the same 2-Kbyte page of program memory as the
first byte of the following instruction.
rel
SJMP and all conditional jumps include an 8-bit offset byte. Its range is +127/-128 bytes relative to
the first byte of the following instruction.
The following tables show instruction hexadecimal codes, number of bytes and machine cycles that
each instruction takes to be executed. Note the number of cycles is given for no program memory
wait states.
Rev. 1.00
217 of 226
May 15, 2013
Instruction Set
All instructions are binary code compatible and perform the same functions as they do within
the industry standard 8051. The following tables give a summary of instruction cycles of the
HT85XXX microcontroller core.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Arithmetic Operations
Mnemonic
Code
Bytes Cycles
ADD A,Rn
Add register to Accumulator
0X28-0X2F
1
1
ADD A,direct
Add directly addressed data to Accumulator
0X25
2
2
ADD A,@Ri
Add indirectly addressed data to Accumulator
0X26-0X27
1
2
ADD A,#data
Add immediate data to Accumulator
0X24
2
2
ADDC A,Rn
Add register to Accumulator with carry flag
0X38-0X3F
1
1
ADDC A,direct
Add directly addressed data to Accumulator with carry flag
0X35
2
2
ADDC A,@Ri
Add indirectly addresses data to Accumulator with carry flag
0X36-0X37
1
2
ADDC A,#data
Add immediate data to Accumulator with carry flag
0X34
2
2
SUBB A,Rn
Subtract register from Accumulator with borrow
0X98-0X9F
1
1
SUBB A,direct
Subtract directly addressed data from Accumulator with borrow
0X95
2
2
SUBB A,@Ri
Subtract indirectly addressed data from Accumulator with borrow 0X96-0X97
1
2
SUBB A,#data
Subtract immediate data from Accumulator with borrow
0X94
2
2
INC A
Increment Accumulator
0X04
1
1
INC Rn
Increment register
0X08-0X0F
1
1
INC direct
Increment directly addressed location
0X05
2
3
INC @Ri
Increment indirectly addressed location
0X06-0X07
1
3
INC DPTR
Increment data pointer
0XA3
1
1
DEC A
Decrement Accumulator
0X14
1
1
DEC Rn
Decrement register
0X18-0X1F
1
1
DEC direct
Decrement directly addressed location.
0X15
2
3
DEC @Ri
Decrement indirectly addressed location
0X16-0X17
1
3
MUL AB
Multiply A and B
0XA4
1
4
DIV AB
Divide A by B
0X84
1
4
DA A
Decimal adjust Accumulator
0XD4
1
1
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May 15, 2013
Instruction Set
Rev. 1.00
Description
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Logic Operations
Mnemonic
Code
Bytes Cycles
ANL A,Rn
AND register to Accumulator
0X58-0X5F
1
1
ANL A,direct
AND directly addressed data to Accumulator
0X55
2
2
ANL A,@Ri
AND indirectly addressed data to Accumulator
0X56-0X57
1
2
ANL A,#data
AND immediate data to Accumulator
0X54
2
2
ANL direct,A
AND Accumulator to directly addressed location
0X52
2
3
ANL direct,#data
AND immediate data to directly addressed location
0X53
3
4
ORL A,Rn
OR register to Accumulator
0X48-0X4F
1
1
ORL A,direct
OR directly addressed data to Accumulator
0X45
2
2
ORL A,@Ri
OR indirectly addressed data to Accumulator
0X46-0X47
1
2
ORL A,#data
OR immediate data to Accumulator
0X44
2
2
ORL direct,A
OR Accumulator to directly addressed location
0X42
2
3
ORL direct,#data
OR immediate data to directly addressed location
0X43
3
4
XRL A,Rn
Exclusive OR register to Accumulator
0X68-0X6F
1
1
XRL A,direct
Exclusive OR directly addressed data to Accumulator
0X65
2
2
XRL A,@Ri
Exclusive OR indirectly addressed data to Accumulator
0X66-0X67
1
2
XRL A,#data
Exclusive OR immediate data to Accumulator
0X64
2
2
XRL direct,A
Exclusive OR Accumulator to directly addressed location
0X62
2
3
XRL direct,#data
Exclusive OR immediate data to directly addressed location 0X63
3
4
CLR A
Clear Accumulator
0XE4
1
1
CPL A
Complement Accumulator
0XF4
1
1
RL A
Rotate Accumulator left
0X23
1
1
RLC A
Rotate Accumulator left through carry
0X33
1
1
RR A
Rotate Accumulator right
0X03
1
1
RRC A
Rotate Accumulator right through carry
0X13
1
1
SWAP A
Swap nibbles within the Accumulator
0XC4
1
1
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May 15, 2013
Instruction Set
Rev. 1.00
Description
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Data transfer Operations
Mnemonic
Description
Bytes Cycles
Move register to Accumulator
0XE8-0XEF
1
1
MOV A,direct
Move directly addressed data to Accumulator
0XE5
2
2
MOV A,@Ri
Move indirectly addressed data to Accumulator
0XE6-0XE7
1
2
MOV A,#data
Move immediate data to Accumulator
0X74
2
2
MOV Rn,A
Move Accumulator to register
0XF8-0XFF
1
1
MOV Rn,direct
Move directly addressed data to register
0XA8-0XAF
2
2
MOV Rn,#data
Move immediate data to register
0X78-0X7F
2
2
MOV direct,A
Move Accumulator to direct byte
0XF5
2
2
MOV direct,Rn
Move register to direct byte
0X88-0X8F
2
2
0X85
3
3
MOV direct,@Ri
Move indirectly addressed data to directly addressed location 0X86-0X87
2
2
MOV direct,#data
Move immediate data to directly addressed location
0X75
3
3
MOV @Ri,A
Move Accumulator to indirectly addressed location
0XF6-0XF7
1
1
MOV @Ri,direct
Move directly addressed data to indirectly addressed location 0XA6-0XA7
2
2
MOV @Ri,#data
Move immediate data to indirectly addressed location
0X76-0X77
2
2
MOV DPTR,#data16 Load data pointer with a 16-bit immediate
0X90
3
3
MOVC A,@A+DPTR Load Accumulator with a code byte relative to DPTR
0X93
1
4
MOVC A,@A+PC
Load Accumulator with a code byte relative to PC
0X83
1
4
MOVX A,@Ri
Move external RAM (8-bit addr.) to Accumulator
0XE2-0XE3
1
3
MOVX A,@DPTR
Move external RAM (16-bit addr.) to Accumulator
0XE0
1
3
MOVX @Ri,A
Move Accumulator to external RAM (8-bit addr.)
0XF2-0XF3
1
3
MOVX @DPTR,A
Move Accumulator to external RAM (16-bit addr.)
0XF0
1
3
PUSH direct
Push directly addressed data onto stack
0XC0
2
2
POP direct
Pop directly addressed location from stack
0XD0
2
3
XCH A,Rn
Exchange register with Accumulator
0XC8-0XCF
1
1
XCH A,direct
Exchange directly addressed location with Accumulator
0XC5
2
3
XCH A,@Ri
Exchange indirect RAM with Accumulator
0XC6-0XC7
1
2
XCHD A,@Ri
Exchange low-order nibbles of indirect and Accumulator
0XD6-0XD7
1
2
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May 15, 2013
Instruction Set
MOV A,Rn
MOV direct1,direct2 Move directly addressed data to directly addressed location
Rev. 1.00
Code
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Program Branches
Mnemonic
Description
Code
Bytes Cycles
ACALL addr11
Absolute subroutine call
xxx10001b
2
2(*2)/3
LCALL addr16
Long subroutine call
0X12
3
3(*2)/4
5
Return from subroutine
0X22
1
Return from interrupt
0X32
1
5
AJMP addr11
Absolute jump
xxx00001
2
2(*2)/3
LJMP addr16
Long jump
0X02
3
3(*2)/4
SJMP rel
Short jump (relative addr.)
0X80
2
3(*2)/4
JMP @A+DPTR
Jump indirect relative to the DPTR
0X73
1
3
JZ rel
Jump if Accumulator is zero
0X60
2
3/4(*1)
JNZ rel
Jump if Accumulator is not zero
0X70
2
3/4(*1)
JC rel
Jump if carry flag is set
0X40
2
3/4(*1)
JNC rel
Jump if carry flag is not set
0X50
2
3/4(*1)
JB bit, rel
Jump if directly addressed bit is set
0X20
3
4/5(*1)
JNB bit, rel
Jump if directly addressed bit is not set
0X30
3
4/5(*1)
JBC bit, direct rel
Jump if directly addressed bit is set and clear bit
0X10
3
4/5(*1)
CJNE A, direct rel
Compare directly addressed data to Accumulator and jump
if not equal
0XB5
3
4/5(*1)
CJNE A, #data rel
Compare immediate data to Accumulator and jump if not
equal
0XB4
3
4/5(*1)
CJNE Rn, #data rel
Compare immediate data to register and jump if not equal
0XB8-0XBF
3
4/5(*1)
CJNE @Ri, #data rel Compare immediate to indirect and jump if not equal
0XB6-0XB7
3
5/6(*1)
DJNZ Rn, rel
Decrement register and jump if not zero
0XD8-0XDF
2
3/4(*1)
DJNZ direct, rel
Decrement directly addressed location and jump if not zero
0XD5
3
4/5(*1)
NOP
No operation
0X00
1
1
Note: (*1) If the condition is true, the machine cycle will add 1.
(*2) If program execute ACALL/LCALL/AJMP/LJMP/SJMP and jump to the next address, the
machine cycle will decrease 1.
Rev. 1.00
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Instruction Set
RET
RETI
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Boolean Manipulation
Mnemonic
Description
Code
Bytes Cycles
CLR C
Clear carry flag
0XC3
1
CLR bit
Clear directly addressed bit
0XC2
2
1
3
SETB C
Set carry flag
0XD3
1
1
SETB bit
Set directly addressed bit
0XD2
2
3
CPL C
Complement carry flag
0XB3
1
1
Complement directly addressed bit
0XB2
2
3
AND directly addressed bit to carry flag
0X82
2
2
ANL C,/bit
AND complement of directly addressed bit to carry
0XB0
2
2
ORL C, bit
OR directly addressed bit to carry flag
0X72
2
2
ORL C,/bit
OR complement of directly addressed bit to carry
0XA0
2
2
MOV C, bit
Move directly addressed bit to carry flag
0XA2
2
2
MOV bit, C
Move carry flag to directly addressed bit
0X92
2
3
Read-Modify-Write Instruction
Instructions that read a byte from SFR or internal RAM, modify it and rewrite it back, are called
“Read-Modify-Write” instructions. When the destination is an I/O port (P0-P3), or a Port bit, these
instructions read the output latch rather than the pin. Below table is RMW instruction set.
Mnemonic
ANL direct, A
Description
AND accumulator to direct
Code
Bytes Cycles
0x52
2
3
ANL direct, #data AND immediate data to direct
0x53
3
4
ORL direct, A
0x42
2
3
ORL direct, #data OR immediate data to direct
0x43
3
4
XRL direct, A
0x62
2
3
XRL direct, #data Exclusive OR immediate data to direct
0x63
3
4
JBC bit, rel
Jump if bit is set and clear bit
0x10
3
4/5(*)
CPL bit
Complement bit
0xB2
2
3
INC direct
Increment direct
0x05
2
3
INC @Ri
Increment indirect
0x06-0x07
1
3
DEC direct
Decrement direct
0x15
2
3
DEC @Ri
Decrement indirect
0x16-0x17
1
3
DJNZ direct, rel
Decrement and jump if not zero
0xD5
3
4/5(*)
MOV bit, C
Move carry flag and direct bit
0x92
2
3
CLR bit
Clear bit
0xC2
2
3
SETB bit
Set bit
0xD2
2
3
OR accumulator to direct
Exclusive OR accumulator to direct
Note: (*) If the condition is true, the machine cycle will add 1.
Rev. 1.00
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May 15, 2013
Instruction Set
CPL bit
ANL C, bit
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
38
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website
for the latest version of the package information.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
• PB FREE Products
• Green Packages Products
Rev. 1.00
223 of 226
May 15, 2013
Package Information
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
48-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.350
—
0.358
B
0.272
—
0.280
C
0.350
D
0.272
—
E
—
0.020
—
F
—
0.008
—
G
0.053
—
0.057
H
—
—
0.063
I
—
0.004
—
J
0.018
—
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
0.358
0.280
Dimensions in mm
Min.
Nom.
A
8.90
—
9.10
B
6.90
—
7.10
C
8.90
—
9.10
D
6.90
—
7.10
E
—
0.50
—
F
—
0.20
—
G
1.35
—
1.45
H
—
—
1.60
I
—
0.10
—
J
0.45
—
0.75
K
0.10
—
0.20
α
0°
—
7°
Rev. 1.00
224 of 226
Max.
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
64-pin LQFP (7mm×7mm) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.350
—
0.358
B
0.272
—
0.280
C
0.350
D
0.272
—
E
—
0.016
—
F
0.005
—
0.009
G
0.053
—
0.057
H
—
—
0.063
I
0.002
—
0.006
0.358
0.280
J
0.018
—
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Dimensions in mm
Min.
Nom.
A
8.90
—
9.10
B
6.90
—
7.10
C
8.90
D
6.90
—
E
—
0.40
—
F
0.13
—
0.23
G
1.35
—
1.45
H
—
—
1.60
Rev. 1.00
Max.
9.10
7.10
I
0.05
—
0.15
J
0.45
—
0.75
K
0.09
—
0.20
α
0°
—
7°
225 of 226
May 15, 2013
Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
Package Information
Copyright© 2013 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely for
the purpose of illustration and Holtek makes no warranty or representation that such
applications will be suitable without further modification, nor recommends the use of
its products for application that may present a risk to human life due to malfunction or
otherwise. Holtek's products are not authorized for use as critical components in life
support devices or systems. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.
holtek.com.tw.
Rev. 1.00
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May 15, 2013