NCP392C Adjustable Front End Overvoltage Protection Controller with Protected Vbus Output www.onsemi.com The NCP392C is an overvoltage front end protection controller and is able to disconnect the systems from its output pin in case wrong input operating conditions are detected, up to +28 V. Thanks to this device using internal NMOS, no external device is necessary, reducing the system cost and the PCB area of the application board. Internal OVLO threshold is available, or can be adjusted if an external resistor bridge is used. At power up (EN pin = low level), the Vout turns on tstart time after internal timer elapsed. The NCP392C features an ACOK pin that indicates faulty condition. MARKING DIAGRAM 392Cx = Specific Device Number 392Cx = (x = R or S) A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package Features • • • • • • • • • • • • Over−voltage Protection Up to + 28 V On−chip Low RDS(on) NMOS Transistors: Typical 34 mW Over−voltage Lockout (OVLO) Externally Adjustable OVLO Internal 15 ms Startup Delay Shutdown EN Input ACOK Status Pin + 100 V Surge Capability, in Compliance with IEC61000−4−5 Standard Compliance to IEC61000−4−2 (Level 4) Standard 8 kV (Contact) 15 kV (Air) ESD Ratings: Machine Model = B (200 V) Human Body Model = 2 (2 kV) CSP−12 Package 1.3 x 2.0 mm, 0.4 mm Pitch This is a Pb−Free Device PIN CONNECTION 1 2 3 4 EN OUT OUT PGND B ACOK OUT IN PGND C OVLO IN IN PGND A (Top View) ORDERING INFORMATION See detailed ordering, marking and shipping information on page 9 of this data sheet. Typical Applications • • • • • 392Cx AYWW G WLCSP 12 FCC SUFFIX CASE 567JM Cell Phones Tablets Camera Phones Digital Still Cameras Personal Digital Applications © Semiconductor Components Industries, LLC, 2015 September, 2015 − Rev. 3 1 Publication Order Number: NCP392C/D NCP392C NCP392C B3 IN 0.1 μF OUT A2 C2 IN OUT A3 C3 IN OUT B2 OUTPUT CHARGER B+ PMIC C1 OVLO GND GND GND EN A4 B4 C4 A1 / ACOK B1 /Flag /EN Figure 1. Typical Application Circuit FUNCTIONAL BLOCK DIAGRAM INPUT Gate driver VREF OVLO Charge Pump OVLO TSD R1 C1 External OVLO selected GND Control logic and Timer SEL Internal OVLO selected R2 C2 OVLO EN Fault & EN ACOK Figure 2. Functional Block Diagram www.onsemi.com 2 EN NCP392C PIN FUNCTION DESCRIPTION 1 2 3 4 EN OUT OUT PGND B ACOK OUT IN PGND C OVLO IN IN PGND A (Top View) Figure 3. Pinout Table 1. NCP392 PIN DESCRIPTION Pin Pin Name Type A1 EN I/O A2, A3, B2 OUT OUTPUT Output voltage pins. These pins follow IN pins, with debounce time, when “no fault” are detected. The outputs are disconnected from the Vin power supply when the input voltage is below UVLO, above OVLO threshold or internal thermal protection is exceeded. The three OUT pins must be hardwired together and used for power dissipation. A4, B4, C4 PGND POWER Ground. The three GND pins must be hardwired together and connect to the system GND. B1 ACOK OUTPUT ACOK pin: fault indication pin. Open drain. This pied in tied low if Vin is within UVLO and OVLO range. B3, C2, C3 IN POWER C1 OVLO INPUT Description Enable pin bar. The device enters in shutdown mode when this pin is tied to a high level. In this case the output is disconnected from the input. 1 VIN < VUVLO or VIN ≥ VOVLO 0 Voltage stable Input voltage pins. These pins are connected to the power supply. The three IN pins must be hardwired together. External OVLO Adjustment. Connect external resistor bridge to OVLO pin to select a different OVLO threshold. Connect OVLO pin to GND if not used. In this case internal OVLO will be selected. www.onsemi.com 3 NCP392C Table 2. MAXIMUM RATINGS Symbol Value Unit Minimum Voltage (IN, OVLO to GND) Rating VminIN −0.3 V Minimum Voltage (All others to GND) Vmin −0.3 V VmaxIN 29 V Maximum Voltage (OVLO to GND) VmaxOVLO 14 V Maximum Voltage (OUT to GND) VmaxOUT 22 V Vmax 7 V Maximum DC current Imax 4.5 A Peak input current Ipeak 8 A Thermal Resistance, Junction−to−Air RqJA 70 °C/W Operating Ambient Temperature Range TA −40 to +85 °C Storage Temperature Range Tstg −65 to +150 °C Junction Operating temperature TJ + 125 °C ESD Withstand Voltage (IEC 61000−4−2) Human Body Model (HBM), model = 2 (Note 1) Machine Model (MM) model = B (Note 2) Vesd 15 kV air, 8 kV contact 2000 V 200 V kV V V Moisture Sensitivity MSL Level 1 Maximum Voltage (IN to GND) Maximum Voltage (All others to GND) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114. 2. Machine Model, 200 pF discharged through all pins following specification JESD22/A115 www.onsemi.com 4 NCP392C Table 3. ELECTRICAL CHARACTERISTICS Min / Max limits values (−40°C < TA < +85°C) and Vin = +5 V (Unless otherwise noted). Typical values are TA = +25°C. Characteristics Input Voltage Range Symbols Conditions Vin, VOVLO UVLO Vin rising Under voltage Lockout hysteresis UVLOhyst Vin falling OVLO Internal Over voltage Lockout hysteresis OVLOhyst External OVLO Reference OVLO_EXT Vin rising (Note 3) OVLO pin tied to GND − 25°C OVLOEXThyst External OVLO select threshold OVLOSEL RDSon Unit 28 V 2.8 V 60 − mV NCP392CR 13.4 13.8 14.2 V NCP392CS 15 15.5 16 Vin falling (Note 3) OVLO pin tied to GND − 25°C 1.5 2.5 % V NCP392CR 1.12 1.20 1.24 NCP392CS 1.18 1.221 1.26 4 Over−Voltage Lockout Hysteresis Max − External Adjustable OVLO Vin versus Vout Resistance Typ 2.8 Under voltage Lockout Internal Over voltage Lockout threshold Min Vin falling 20 2 0.2 V % 0.3 V Vin = 5 V, EN = GND, –40°C < TJ < 125°C 34 50 mW 58 100 mA 6 mA 100 mA 100 nA Supply Quiescent Current IDD No load, EN = 0.4 V Standby Current ISTB No load, EN = 1.2 V, OVLO Supply current IIN_OVLO VOVLO = 3 V, VIN = 5 V, VOUT = 0 V OVLO select leakage IOVLO 60 LOGIC EN Voltage High VIH 1.2 V EN Voltage Low VIL ACOK Output Low Voltage VOL ISINK = 1 mA 0.4 0.4 V V Start up time tSTART From Vin > 2.8 V to 10% Vout, EN low 15 ms Enable time tEN Vin present, From EN high to low, 10% Vout 15 ms tRISE From 10% to 90% of Vout, C load 100 mF, Rload, 100 W, EN low 1 ms tSTART2 From Vin Valid to ACOK tied low, EN low or high 30 ms Turn off time tOFF Surge off time 100 ns Disable time tDIS From EN >1.2 V to 90% Vout. No load 20 ms tOVLO Vin rising 2 V/ms 1.5 ms TSD 140 °C TSD rearm 115 °C TIMINGS Soft Start ACOK Start up time OVLO Turn off time TSD Thermal shutdown Thermal shutdown rearming Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Please contact your ON Semiconductor representative for additional OVLO threshold. Electrical parameters are guaranteed by correlation across the full range of temperature. www.onsemi.com 5 NCP392C Operation Under−voltage Lockout (UVLO) The NCP392C provides over−voltage protection for positive voltage surge, up to + 28 V. An additional clamp, between IN and GND, protects the part against surge test, in compliance with IEC 61000−4−5 standard. A ACOK open drain fault indicator is provided. This signal indicates whether input voltage is within the valid range. To ensure proper operation under any conditions, the device has a built−in under−voltage lock out (UVLO) circuit. This circuit has a built−in hysteresis to provide noise immunity to transient conditions. Over−voltage Lockout (OVLO) To protect connected systems on Vout pin from over−voltage, the device has a built−in over−voltage lock out (OVLO) circuit. During over−voltage condition, the output remains disabled until the input voltage is above OVLO – hysteresis. VIN OVLO UVLO VOUT / EN tVBUS tOFF t START tSTART tRISE tRISE tSOFT tSOFT Figure 4. UVLO, OVLO and EN Functionality www.onsemi.com 6 tOFF NCP392C INPUT NEW_OVLO TH + ǒR 1 ) R 2Ǔ OVLO EXT R2 (eq. 1) With: OVLOEXT = 1.221 V Typical (OVLO External Reference) Example: NEW_OVLOTH target 12 V. VREF GND R1 + R2 ǒ Ǔ OVLO * 1 + R2 1.221 ǒ Ǔ (eq. 2) 12 * 1 + 8.828 1.221 R2 Taking into account external input bridge doesn’t have excessive current consumption, and 1% is recommended: R2 arbitrarilly fixed at 1.05 MW. R1 = 9.269 MW (9.31 MW standard value) Obtained typical OVLO = 12.04 V C1 and C2 should be selected in such a way that the time constant R1C1 = R2C2. OVLO Internal OVLO selected SEL EN Input To enable normal operation, the EN pin has to be at low level. There is neither internal pull up, nor internal pull down connected to EN pin. If not externally driven, this pin and so NCP392C switch are undefined state. A high level on the pin, disconnects OUT pin from IN pin. Fault & EN ACOK Figure 5. External Connection to GND of OVLO Table 4. CONTROL LOGIC MODES If OVLO pin is not grounded, and by adding external bridge resistor on OVLO pin, between IN and GND, overvoltage protection can be adjusted as following: EN INPUT R1 GND Internal OVLO selected OVLO R2 C1 External OVLO selected VREF C2 OVLO EXT OVP State NCP392Cx SEL Fault & EN ACOK Figure 6. External Connection to Resistor Bridge of OVLO www.onsemi.com 7 Low High Low ON Tstart 15 ms OFF High OFF OFF NCP392C VIN OVLO UVLO ACOK High−Z VOUT EN tSTART tOFF tSTART tRISE tRISE tSTART2 tSTART2 Figure 7. EN and ACOK Associated Timers ACOK Pin The NCP392C is declined in a CSP package. So power dissipation can be decreased on each pin connection but main thermal area must be as large as possible around IN and OUT pins. Taking into account and respectively, four IN and OUT pins must be hardwired together on the PCB. Maximum power dissipation can be calculated with the following formula: The NCP392C version integrates a ACOK status indicator. This is a drain pin tied low when no fault is present (no TSd, no under voltage, no over voltage). When disabled, the ACOK feature is disabled too and the output pin is in high impedance mode. Thermal Shutdown Protection T J * T A + R qJA In case of internal overheating, the integrated thermal shutdown (TSD) protection allows to open the internal MOSFET in order to instantaneously decrease the device temperature. Embedded hysteresis allows to reengage the MOSFET when the junction temperature decreases. If the fault event is still present, the temperature increases again and engages the thermal shutdown one more time until fault event disappeared. Pd (eq. 3) TJ: junction temperature TA: ambient temperature RqJA: thermal resistance of the junction to air through the case and board. Pd: power dissipation = RDS(on) x I2 ESD Tests The NCP392C fully supports the IEC61000−4−2, level 4 (Input pin, 1 mF mounted on board). That means, in Air condition, Vin has a ±15 kV ESD protected input. In Contact condition, Vin has ±8 kV ESD protected input. Please refer to Figure 8 to see the IEC 61000−4−2 electrostatic discharge waveform. PCB Recommendations To limit internal power dissipation, PCB routing must be carefully done to improve current capability. www.onsemi.com 8 NCP392C USB OTG Support When used in an application that has to supply voltage to an external accessory (i.e. USB OTG), the part is able to supply 1.8 A to the accessory. If VIN = 0 V when +5.0 V OTG is applied to the OUT pin, current will flow through the MOSFET body diode and, as soon as the output voltage will be higher than the VUVLO voltage (2.8 V) plus Body diode forward voltage, the part will turn fully ON and current will be supplied to the accessory with minimum drop. In that case, the ACOK pin will keep High−Z state. Figure 8. Ipeak = f(t) / IEC61000−4−2 ORDERING INFORMATION Device Marking Option Package Shipping† NCP392CRFCCT1G 392CR OVLO 13.8 V 3000 / Tape & Reel NCP392CSFCCT1G 392CS OVLO 15.5 V WLCSP (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 9 NCP392C PACKAGE DIMENSIONS WLCSP12, 1.3x2.0 CASE 567JM ISSUE A PIN A1 REFERENCE 0.10 C 2X ÈÈ ÈÈ E NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. A B DIE COAT (OPTIONAL) A3 D DIM A A1 A2 A3 b D E e DETAIL A 0.10 C 2X TOP VIEW A2 DETAIL A MILLIMETERS MIN MAX −−− 0.60 0.17 0.23 0.36 REF 0.04 REF 0.24 0.30 1.26 1.31 2.01 2.04 0.40 BSC A 0.10 C RECOMMENDED SOLDERING FOOTPRINT* 0.08 C SIDE VIEW NOTE 3 A1 C SEATING PLANE PACKAGE OUTLINE A1 e/2 e 12X b 0.05 C A B 0.03 C 12X 0.40 PITCH e C B 0.25 0.40 PITCH DIMENSIONS: MILLIMETERS A 1 2 3 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 4 BOTTOM VIEW ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. 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