AD ADG708 Cmos, 3 ohm low voltage 4-/8-channel multiplexer Datasheet

a
FEATURES
1.8 V to 5.5 V Single Supply
ⴞ3 V Dual Supply
3 ⍀ On-Resistance
0.75 ⍀ On-Resistance Flatness
100 pA Leakage Currents
14 ns Switching Times
Single 8-to-1 Multiplexer ADG708
Differential 4-to-1 Multiplexer ADG709
16-Lead TSSOP Package
Low Power Consumption
TTL/CMOS-Compatible Inputs
APPLICATIONS
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
CMOS, 3 ⍀ Low Voltage
4-/8-Channel Multiplexers
ADG708/ADG709
FUNCTIONAL BLOCK DIAGRAMS
ADG708
ADG709
S1
S1A
DA
S4A
D
S1B
DB
S4B
S8
1 OF 8
DECODER
A0 A1
A2 EN
1 OF 4
DECODER
A0
A1
EN
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG708 and ADG709 are low voltage, CMOS analog
multiplexers comprising eight single channels and four differential
channels respectively. The ADG708 switches one of eight inputs
(S1–S8) to a common output, D, as determined by the 3-bit
binary address lines A0, A1, and A2. The ADG709 switches one
of four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An EN
input on both devices is used to enable or disable the device. When
disabled, all channels are switched OFF.
1. Single/Dual Supply Operation. The ADG708 and ADG709
are fully specified and guaranteed with 3 V and 5 V single
supply and ± 3 V dual supply rails.
2. Low RON (3 Ω Typical).
3. Low Power Consumption (<0.01 µW).
4. Guaranteed Break-Before-Make Switching Action.
5. Small 16-Lead TSSOP Package.
Low power consumption and operating supply range of 1.8 V to
5.5 V make the ADG708 and ADG709 ideal for battery-powered,
portable instruments. All channels exhibit break-before-make
switching action preventing momentary shorting when switching channels.
These switches are designed on an enhanced submicron process
that provides low power dissipation yet gives high switching
speed, very low on-resistance and leakage currents. On-resistance
is in the region of a few ohms and is closely matched between
switches and very flat over the full signal range. These parts can
operate equally well as either Multiplexers or Demultiplexers,
and have an input signal range that extends to the supplies.
The ADG708 and ADG709 are available in a 16-lead TSSOP
package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
ADG708/ADG709–SPECIFICATIONS1 (V
B Version
–40ⴗC
+25ⴗC to +85ⴗC
Parameter
ANALOG SWITCH
Analog Signal Range
On-Resistance (RON)
On-Resistance Match Between
Channels (∆R ON)
On-Resistance Flatness (RFLAT(ON))
5
0.4
0.8
0.75
0 V to VDD
3
4.5
5
0.4
0.8
0.75
1.2
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
± 0.01
Drain OFF Leakage ID (OFF)
± 0.01
Channel ON Leakage I D, I S (ON)
± 0.01
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
± 20
± 20
1.2
± 0.01
± 0.1 ± 0.3
± 0.01
± 0.1 ± 0.75
± 0.01
± 0.1 ± 0.75
2.4
0.8
0.005
2
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 0 V to VDD, I DS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, I DS = 10 mA
VS = 0 V to VDD, I DS = 10 mA
VDD = 5.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 3
VD = VS = 1 V, or 4.5 V, Test Circuit 4
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or V INH
RL = 300 Ω, CL = 35 pF, Test Circuit 5
VS1 = 3 V/0 V, VS8 = 0 V/3 V
RL = 300 Ω, CL = 35 pF
VS = 3 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF
VS = 3 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS = 3 V, Test Circuit 7
VS = 2.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
RL = 50 Ω, CL = 5 pF, Test Circuit 9
2
2
14
14
tON(EN)
14
tOFF(EN)
7
Charge Injection
±3
±3
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
Off Isolation
–60
–80
–60
–80
dB typ
dB typ
Channel-to-Channel Crosstalk
–60
–80
–60
–80
dB typ
dB typ
–3 dB Bandwidth
CS (OFF)
CD (OFF)
ADG708
ADG709
CD , CS (ON)
ADG708
ADG709
55
13
55
13
MHz typ
pF typ
85
42
85
42
pF typ
pF typ
96
48
96
48
pF typ
pF typ
0.001
0.001
µA typ
µA max
25
Break-Before-Make Time Delay, t D
8
25
8
1
1
14
25
25
7
12
POWER REQUIREMENTS
IDD
Test Conditions/Comments
2.4
0.8
0.005
± 0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
tTRANSITION
± 20
= 5 V ⴞ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
C Version
–40ⴗC
+25ⴗC to +85ⴗC
0 V to VDD
3
4.5
DD
1.0
12
1.0
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
NOTES
1
Temperature range is as follows: B and C Versions: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG708/ADG709
SPECIFICATIONS1 (V
DD
= 3 V ⴞ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted)
B Version
–40ⴗC
+25ⴗC to +85ⴗC
Parameter
ANALOG SWITCH
Analog Signal Range
On-Resistance (RON)
0 V to VDD
8
11
On-Resistance Match Between
Channels (∆RON)
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
± 0.01
Drain OFF Leakage ID (OFF)
± 0.01
Channel ON Leakage ID, IS (ON)
± 0.01
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or I INH
12
0.4
1.2
± 20
± 20
± 20
C Version
–40ⴗC
+25ⴗC to +85ⴗC
0 V to VDD V
Ω typ
12
Ω max
0.4
Ω typ
1.2
Ω max
8
11
± 0.01
± 0.1 ± 0.3
± 0.01
± 0.1 ± 0.75
± 0.01
± 0.1 ± 0.75
2.0
0.4
0.005
CIN, Digital Input Capacitance
± 0.1
2
Unit
0.005
nA typ
nA max
nA typ
nA max
nA typ
nA max
Test Conditions/Comments
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD , IDS = 10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 3
VS = VD = 1 V or 3 V, Test Circuit 4
2.0
0.4
V min
V max
± 0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF, Test Circuit 5
VS1 = 2 V/0 V, V S2 = 0 V/2 V
RL = 300 Ω, CL = 35 pF
VS = 2 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF
VS = 2 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS = 2 V, Test Circuit 7
VS = 1.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
RL = 50 Ω, CL = 5 pF, f = 10 MHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
2
2
DYNAMIC CHARACTERISTICS
tTRANSITION
18
18
30
Break-Before-Make Time Delay, tD
8
30
8
1
1
tON(EN)
18
18
tOFF(EN)
8
Charge Injection
±3
Off Isolation
–60
–80
–60
–80
dB typ
dB typ
Channel-to-Channel Crosstalk
–60
–80
–60
–80
dB typ
dB typ
–3 dB Bandwidth
CS (OFF)
CD (OFF)
ADG708
ADG709
CD, CS (ON)
ADG708
ADG709
55
13
55
13
MHz typ
pF typ
85
42
85
42
pF typ
pF typ
96
48
96
48
pF typ
pF typ
0.001
0.001
µA typ
µA max
30
POWER REQUIREMENTS
IDD
30
8
15
1.0
15
±3
1.0
NOTES
1
Temperature ranges are as follows: B and C Versions: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
RL = 50 Ω, CL = 5 pF, Test Circuit 9
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
ADG708/ADG709–SPECIFICATIONS1
DUAL SUPPLY (V
DD
= +3 V ⴞ 10%, VSS = –3 V ⴞ 10%, GND = 0 V)
B Version
–40ⴗC
+25ⴗC to +85ⴗC
Parameter
ANALOG SWITCH
Analog Signal Range
On-Resistance (RON)
C Version
–40ⴗC
+25ⴗC to +85ⴗC
VSS to VDD
2.5
4.5
On-Resistance Match Between
Channels (∆R ON)
On-Resistance Flatness (RFLAT(ON))
5
0.4
0.8
0.6
VSS to VDD
2.5
4.5
0.6
1.0
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
± 0.01
Drain OFF Leakage ID (OFF)
± 0.01
Channel ON Leakage I D, I S (ON)
± 0.01
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
tTRANSITION
± 20
± 20
± 20
1.0
± 0.01
± 0.1 ± 0.3
± 0.01
± 0.1 ± 0.75
± 0.01
± 0.1 ± 0.75
2.0
0.4
0.005
5
0.4
0.8
± 0.1
2
0.005
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
2.0
0.4
V min
V max
± 0.1
µA typ
µA max
pF typ
2
Test Conditions/Comments
VS = VSS to V DD, IDS = 10 mA;
Test Circuit 1
VS = VSS to V DD, IDS = 10 mA
VS = VSS to V DD, IDS = 10 mA
VDD = +3.3 V, V SS = –3.3 V
VS = +2.25 V/–1.25 V, V D = –1.25 V/+2.25 V;
Test Circuit 2
VS = +2.25 V/–1.25 V, V D = –1.25 V/+2.25 V;
Test Circuit 3
VS = VD = +2.25 V/–1.25 V, Test Circuit 4
VIN = VINL or V INH
2
tON(EN)
14
tOFF(EN)
8
Charge Injection
±3
Off Isolation
–60
–80
–60
–80
Channel-to-Channel Crosstalk
–60
–80
–60
–80
–3 dB Bandwidth
CS (OFF)
CD (OFF)
ADG708
ADG709
CD , CS (ON)
ADG708
ADG709
55
13
55
13
RL = 300 Ω, CL = 35 pF, Test Circuit 5
VS = 1.5 V/0 V, Test Circuit 5
RL = 300 Ω, CL = 35 pF
VS = 1.5 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF
VS = 1.5 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF
VS = 1.5 V, Test Circuit 7
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 8
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
dB typ
RL = 50 Ω, CL = 5 pF, f = 10 MHz
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 9
pF typ
85
42
85
42
pF typ
pF typ
96
48
96
48
0.001
0.001
14
14
25
Break-Before-Make Time Delay, tD
8
25
8
1
1
14
25
POWER REQUIREMENTS
IDD
25
8
15
±3
1.0
ISS
0.001
15
`
1.0
0.001
1.0
1.0
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
pF typ
pF typ
µA typ
µA max
µA typ
µA max
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
VSS = –3.3 V
Digital Inputs = 0 V or 3.3 V
NOTES
1
Temperature range is as follows: B and C Versions: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. 0
ADG708/ADG709
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C unless otherwise noted)
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –3.5 V
Analog Inputs2 . . . . . . . . . . . . . . VSS – 0.3 V to VDD +0.3 V or
30 mA, Whichever Occurs First
Digital Inputs2 . . . . . . . . . . . . . . . . . . –0.3 V to V DD +0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
. . . . . . . . . . . . . . . . . (Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 432 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG708/ADG709 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Table I. ADG708 Truth Table
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
A2
A1
A0
EN
Switch Condition
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
8
TSSOP
A0 1
16 A1
EN 2
15 A2
VSS 3
S1 4
S2 5
ADG708
14 GND
13 VDD
TOP VIEW
(Not to Scale)
12 S5
S3 6
11 S6
S4 7
10 S7
D 8
9 S8
ON Switch Pair
A0 1
16 A1
NONE
1
2
3
4
EN 2
15 GND
X = Don’t Care
Table II. ADG709 Truth Table
A1
X
0
0
1
1
A0
X
0
1
0
1
EN
0
1
1
1
1
VSS 3
S1A 4
S2A 5
X = Don’t Care.
ADG709
14 VDD
13 S1B
TOP VIEW
(Not to Scale)
12 S2B
S3A 6
11 S3B
S4A 7
10 S4B
DA 8
9 DB
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
ADG708BRU
ADG709BRU
ADG708CRU
ADG709CRU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
RU-16
RU-16
RU-16
RU-16
REV. 0
–5–
ADG708/ADG709
TERMINOLOGY
VDD
Most positive power supply potential.
tON (EN)
VSS
Most negative power supply in a dual supply
application. In single supply applications, this
should be tied to ground at the device.
Delay time between the 50% and 90% points
of the EN digital input and the switch “ON”
condition.
tOFF (EN)
Delay time between the 50% and 90% points
of the EN digital input and the switch “OFF”
condition.
tOPEN
“OFF” time measured between the 80% points
of both switches when switching from one address
state to another.
GND
Ground (0 V) Reference.
S
Source Terminal. May be an input or output.
D
Drain Terminal. May be an input or output.
IN
Logic Control Input.
RON
Ohmic resistance between D and S.
Off Isolation
RFLAT(ON)
Flatness is defined as the difference between the
maximum and minimum value of on-resistance
as measured over the specified analog signal range.
A measure of unwanted signal coupling through
an “OFF” switch.
Crosstalk
A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Charge
Injection
A measure of the glitch impulse transferred from
the digital input to the analog output during
switching.
The frequency at which the output is attenuated
by 3 dBs.
IS (OFF)
Source leakage current with the switch “OFF.”
ID (OFF)
Drain leakage current with the switch “OFF.”
ID, IS (ON)
Channel leakage current with the switch “ON.”
VD (VS)
Analog voltage on terminals D, S.
Bandwidth
CS (OFF)
“OFF” switch source capacitance. Measured
with reference to ground.
On Response The frequency response of the “ON” switch.
CD (OFF)
“OFF” switch drain capacitance. Measured
with reference to ground.
CD, CS (ON) “ON” switch capacitance. Measured with
reference to ground.
On Loss
The loss due to the ON resistance of the switch.
VINL
Maximum input voltage for Logic “0.”
VINH
Minimum input voltage for Logic “1.”
Input current of the digital input.
CIN
Digital Input Capacitance.
IINL (IINH)
tTRANSITION
Delay time measured between the 50% and 90%
points of the digital inputs and the switch “ON”
condition when switching from one address state
to another.
IDD
Positive Supply Current.
ISS
Negative Supply Current.
–6–
REV. 0
Typical Performance Characteristics– ADG708/ADG709
8
8
TA = 258C
VSS = 0V
7
6
6
VDD = 2.7V
ON RESISTANCE – V
ON RESISTANCE – V
VDD = 3V
VSS = 0V
7
5
VDD = 3.3V
4
VDD = 4.5V
VDD = 5.5V
3
+858C
5
4
–408C
3
2
2
1
1
+258C
0
0
0
1
2
3
4
VD, VS, DRAIN OR SOURCE VOLTAGE – V
0
5
Figure 1. On Resistance as a Function of VD (VS) for Single
Supply
1.0
1.5
2.0
2.5
0.5
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
Figure 4. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
8
8
7
7
6
6
ON RESISTANCE – V
ON RESISTANCE – V
TA = 258C
5
4
VDD = +2.25V
VSS = –2.25V
3
2
1
3.0
VDD = +3.0V
VSS = –3.0V
5
4
+258C
3
+858C
2
VDD = +3.0V
VSS = –3.0V
VDD = +2.75V
VSS = –2.75V
0
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5
0
0.5
1.0
1.5
–408C
1
2.0
2.5
0
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5
3.0
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
Figure 2. On Resistance as a Function of VD (VS) for Dual
Supply
8
0.5 1.0
1.5
2.0
2.5 3.0
Figure 5. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply
0.12
VDD = 5V
VSS = 0V
7
0
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
VDD = 5V
VSS = 0V
TA = 258C
0.08
CURRENT – nA
ON RESISTANCE – V
6
5
4
+258C
3
+858C
ID (ON)
0.04
0.00
IS (OFF)
–0.04
2
–408C
ID (OFF)
–0.08
1
0
–0.12
0
1
2
3
4
VD OR VS – DRAIN OR SOURCE VOLTAGE – V
5
0
Figure 3. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
REV. 0
1
2
3
VD (VS) – Volts
4
5
Figure 6. Leakage Currents as a Function of V D (V S)
–7–
ADG708/ADG709
0.12
0.08
VDD = 3V
VSS = 0V
TA = 258C
0.04
ID (ON)
0.35
VDD = 3V
VSS = 0V
0.30
CURRENT – nA
CURRENT – nA
0.25
0.00
IS (OFF)
–0.04
ID (OFF)
0.20
0.15
0.10
ID (OFF)
0.05
–0.08
0.00
–0.05
15
–0.12
0
0.5
1.0
1.5
2.0
VD (VS) – Volts
3.0
2.5
Figure 7. Leakage Currents as a Function of V D (V S)
25
35
45
55
65
TEMPERATURE – 8C
75
85
Figure 10. Leakage Currents as a Function of Temperature
10m
0.12
TA = 258C
VDD = +3.0V
VSS = –3.0V
TA = 258C
0.08
1m
VDD = +3.0V
VSS = –3.0V
100m
ID (ON)
0.04
CURRENT – A
CURRENT – nA
ID (ON)
IS (OFF)
0.00
10m
VDD = +5V
1m
VDD = +3V
IS (OFF)
–0.04
100n
–0.08
10n
ID (OFF)
–0.12
0.5 1.0
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0
VD (VS) – Volts
1.5
2.0
2.5
1n
10
3.0
Figure 8. Leakage Currents as a Function of V D (V S)
0.35
1M
10M
VDD = 5V
TA = 258C
–20
0.20
0.15
ID (OFF)
0.10
10k
100k
FREQUENCY – Hz
0
ATTENUATION – dB
CURRENT – nA
0.25
1k
Figure 11. Supply Current vs. Input Switching Frequency
VDD = 5V
VSS = 0V
AND
VDD = +3V
VSS = –3V
0.30
100
–40
–60
–80
ID (ON)
0.05
–100
0.00
IS (OFF)
–0.05
15
25
35
45
55
65
TEMPERATURE – 8C
75
–120
30k
85
Figure 9. Leakage Currents as a Function of Temperature
100k
1M
FREQUENCY – Hz
10M
100M
Figure 12. Off Isolation vs. Frequency
–8–
REV. 0
ADG708/ADG709
0
0
VDD = 5V
TA = 258C
VDD = 5V
TA = 258C
–20
ATTENUATION – dB
ATTENUATION – dB
–5
–40
–60
–80
–10
–15
–100
–120
30k
100k
1M
FREQUENCY – Hz
10M
–20
30k
100M
Figure 13. Crosstalk vs. Frequency
100k
1M
FREQUENCY – Hz
Figure 14. On Response vs. Frequency
20
TA = 258C
10
VDD = 5V
VSS = 0V
QINJ – pC
0
VDD = 3V
VSS = 0V
–10
–20
VDD = +3V
VSS = –3V
–30
–40
–3
–2
–1
2
0
1
VOLTAGE – Volts
3
4
5
Figure 15. Charge Injection vs. Source Voltage
REV. 0
10M
–9–
100M
ADG708/ADG709
Test Circuits
IDS
VDD
VSS
VDD
VSS
V1
S1
S
ID (OFF)
S2
D
D
S8
VS
VS
EN
GND
A
VD
0.8V
RON = V1/IDS
Test Circuit 3. I D (OFF)
Test Circuit 1. On Resistance
VDD
VSS
VDD
VSS
IS(OFF)
VDD
VD
EN
GND
VS
0.8V
GND
VSS
VDD
A2
VSS
A0
S1
ADDRESS
DRIVE (VIN)
VS1
2.4V
S8
VS8
50%
VS1
90%
VOUT
CL
35pF
RL
300V
GND
50%
VOUT
D
EN
VD
2.4V
0V
S2 THRU S7
ADG708*
EN
3V
A1
50V
A
Test Circuit 4. I D (ON)
Test Circuit 2. IS (OFF)
VDD
D
S8
D
S8
VIN
ID (ON)
S1
S2
VS
VSS
VDD
S1
A
VSS
90%
VS8
tTRANSITION
tTRANSITION
* SIMILAR CONNECTION FOR ADG709
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
VSS
3V
VSS
ADDRESS
DRIVE (VIN)
VDD
VDD
A2
VIN
A1
50V
VS
S1
0V
S2 THRU S7
A0
ADG708*
2.4V
S8
VOUT
D
EN
GND
RL
300V
VOUT
CL
35pF
80%
80%
tOPEN
* SIMILAR CONNECTION FOR ADG709
Test Circuit 6. Break-Before-Make Delay, tOPEN
–10–
REV. 0
ADG708/ADG709
VSS
3V
VSS
ENABLE
DRIVE (VIN)
VDD
VDD
A2
VS
S1
S2 THRU S8
tOFF (EN)
V0
ADG708*
D
EN
VIN
50%
0V
A1
A0
50%
VOUT
RL
300V
GND
50V
0.9V0
0.9V0
OUTPUT
CL
35pF
0V
tON (EN)
* SIMILAR CONNECTION FOR ADG709
Test Circuit 7. Enable Delay, tON (EN), tOFF (EN)
VDD
A2 VDD
VSS
3V
VSS
LOGIC INPUT
(VIN)
0V
A1
A0
RS
ADG708*
D
S
VS
CL
1nF
EN
VIN
VOUT
DVOUT
VOUT
QINJ = CL 3 DVOUT
GND
*SIMILAR CONNECTION FOR ADG709
Test Circuit 8. Charge Injection
VSS
VDD
VDD
A1
A0
A2
S1
S8
A2
50V
VOUT
VSS
2.4V
D
S1
RL VOUT
50V
S2
D
VS
RL
50V
S8
GND
VSS
VSS
VSS
OFF ISOLATION = 20LOG10
INSERTION LOSS = 20LOG10
EN
A0 ADG708*
VS
ADG708*
EN**
GND
VDD
A1
(
VOUT
VS
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG10
* SIMILAR CONNECTION FOR ADG709
)
VOUT
VS
* SIMILAR CONNECTION FOR ADG709
** CONNECT TO 2.4V FOR BANDWIDTH MEASUREMENTS
Test Circuit 9. OFF Isolation and Bandwidth
Test Circuit 10. Channel-to-Channel Crosstalk
Power-Supply Sequencing
When using CMOS devices, care must be taken to ensure correct
power-supply sequencing. Incorrect power-supply sequencing
can result in the device being subjected to stresses beyond the
maximum ratings listed in the data sheet. Digital and analog
inputs should always be applied after power supplies and ground.
For single supply operation, VSS should be tied to GND as close
to the device as possible.
REV. 0
–11–
ADG708/ADG709
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3712–8–1/00 (rev. 0)
16-Lead TSSOP
(RU-16)
0.201 (5.10)
0.193 (4.90)
9
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
16
1
8
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
8°
0°
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
0.0256
SEATING (0.65)
PLANE BSC
0.0433
(1.10)
MAX
–12–
REV. 0