ISSI IS61LV2568-10K 256k x 8 high-speed cmos static ram Datasheet

ISSI
IS61LV2568
256K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access times:
8, 10, 12 and 15 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
• CE power-down
• Low power: 540 mW @ 10 ns
36 mW standby mode
• TTL compatible inputs and outputs
• Single 3.3V ±10% power supply
• Packages available:
– 36-pin 400-mil SOJ
– 44-pin TSOP (Type II)
®
DECEMBER 2000
DESCRIPTION
The ISSI IS61LV2568 is a very high-speed, low power,
262,144-word by 8-bit CMOS static RAM. The IS61LV2568
is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 36mW (max.) with CMOS input levels.
The IS61LV2568 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
The IS61LV2568 is available in 36-pin 400-mil SOJ, and
44-pin TSOP (Type II) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K X 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE
OE
CONTROL
CIRCUIT
WE
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
1
ISSI
IS61LV2568
®
PIN CONFIGURATION
36-Pin SOJ
44-Pin TSOP (Type II)
A4
1
36
NC
A3
2
35
A5
A2
3
34
A6
A1
4
33
A7
A0
5
32
A8
CE
6
31
OE
I/O0
7
30
I/O7
I/O1
8
29
I/O6
Vcc
9
28
GND
GND
10
27
Vcc
I/O2
11
26
I/O5
I/O3
12
25
I/O4
WE
13
24
A9
A17
14
23
A10
A16
15
22
A11
A15
16
21
A12
A14
17
20
NC
A13
18
19
NC
PIN DESCRIPTIONS
NC
NC
A4
A3
A2
A1
A0
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A17
A16
A15
A14
A13
NC
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
NC
NC
A5
A6
A7
A8
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A9
A10
A11
A12
NC
NC
NC
NC
TRUTH TABLE
WE
A0-A17
Address Inputs
Mode
CE
Chip Enable Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Bidirectional Ports
Not Selected
X
(Power-down)
Output Disabled H
Read
H
Write
L
Vcc
Power
GND
Ground
NC
No Connection
CE
OE
H
X
High-Z
ISB1, ISB2
L
L
L
H
L
X
High-Z
DOUT
DIN
ICC
ICC
ICC
I/O Operation Vcc Current
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VCC
VTERM
TBIAS
TSTG
PD
Parameter
Supply voltage with Respect to GND
Terminal Voltage with Respect to GND
Temperature Under Bias
Com.
Ind.
Storage Temperature
Power Dissipation
Value
–0.5 to +4.6
–0.5 to Vcc + 0.5
–10 to +85
–45 to +90
–65 to +150
1.0
Unit
V
V
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI
IS61LV2568
®
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
3.3V ± 10%
3.3V ± 10%
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
Min.
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
2.4
—
V
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
—
0.4
V
VIH
Input HIGH Voltage(1)
2.0
VCC + 0.3
V
VIL
Input LOW Voltage(1)
–0.3
0.8
V
ILI
Input Leakage
GND - VIN - VCC
Com.
Ind.
–1
–5
1
5
µA
ILO
Output Leakage
GND - VOUT - VCC, Outputs Disabled
Com.
Ind.
–1
–5
1
5
µA
Note:
1. VIL(min) = –0.3V (DC); VIL(min) = –2.0V (pulse width - 2.0 ns).
VIH(max) = VCC + 0.3V (DC); VIH(max) = Vcc + 2.0V (pulse width - 2.0 ns).
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol
-8 ns
Min. Max.
-10 ns
Min. Max.
-12 ns
Min. Max.
-15 ns
Min. Max.
Parameter
Test Conditions
Unit
ICC
Vcc Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = Max.
Com.
Ind.
—
—
150
160
—
—
125
135
—
—
110
120
—
—
90
100
mA
ISB1
TTL Standby
Current
(TTL Inputs)
VCC = Max.,
VIN = VIH or VIL
CE • VIH, f = max
Com.
Ind.
—
—
50
60
—
—
40
50
—
—
35
45
—
—
30
40
mA
ISB2
CMOS Standby
Current
(CMOS Inputs)
VCC = Max.,
CE - VCC – 0.2V,
VIN > VCC – 0.2V, or
VIN - 0.2V, f = 0
Com.
Ind.
—
—
10
20
—
—
10
20
—
—
10
20
—
—
10
20
mA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
CI/O
Input/Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
3
ISSI
IS61LV2568
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
- 8 ns
Min. Max
Parameter
-10 ns
Min. Max.
-12 ns
Min.
Max.
-15 ns
Min.
Max.
Unit
tRC
Read Cycle Time
8
—
10
—
12
—
15
—
ns
tAA
Address Access Time
—
8
—
10
—
12
—
15
ns
tOHA
Output Hold Time
3
—
3
—
3
—
3
—
ns
tACE
CE Access Time
—
8
—
10
—
12
—
15
ns
tDOE
OE Access Time
—
3
—
4
—
5
—
6
ns
tLZOE(2) OE to Low-Z Output
0
—
0
—
0
—
0
—
ns
tHZOE(2) OE to High-Z Output
0
3
0
4
0
5
0
6
ns
CE to Low-Z Output
3
—
3
—
3
—
3
—
ns
CE to High-Z Output
0
3
0
4
0
5
0
6
ns
tLZCE
(2)
tHZCE
(2)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
319 Ω
319 Ω
3.3V
3.3V
OUTPUT
OUTPUT
30 pF
Including
jig and
scope
Figure 1
4
353 Ω
5 pF
Including
jig and
scope
353 Ω
Figure 2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI
IS61LV2568
®
AC WAVEFORMS
READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL)
t RC
ADDRESS
t AA
t OHA
t OHA
DOUT
DATA VALID
PREVIOUS DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3) (CE and OE Controlled)
t RC
ADDRESS
t AA
t OHA
OE
t HZOE
t DOE
t LZOE
CE
t ACE
t HZCE
t LZCE
DOUT
HIGH-Z
DATA VALID
CE_RD2.eps
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
5
ISSI
IS61LV2568
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol
- 8 ns
Min. Max
Parameter
-10 ns
Min. Max.
-12 ns
Min.
Max.
-15 ns
Min.
Max.
Unit
tWC
Write Cycle Time
8
—
10
—
12
—
15
—
ns
tSCE
CE to Write End
6.5
—
8
—
9
—
10
—
ns
tAW
Address Setup Time to
Write End
6.5
—
8
—
9
—
10
—
ns
tHA
Address Hold from
Write End
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
0
—
ns
tPWE1
WE Pulse Width (OE = HIGH)
5
—
7
—
8
—
10
—
ns
tPWE2
WE Pulse Width (OE = LOW)
6.5
—
8
—
10
—
11
—
ns
tSD
Data Setup to Write End
4
—
5
—
6
—
7
—
ns
tHD
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
tHZWE(3) WE LOW to High-Z Output
—
3
—
4
—
5
—
6
ns
WE HIGH to Low-Z Output
0
—
0
—
0
—
0
—
ns
tLZWE
(3)
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
VALID ADDRESS
ADDRESS
t SA
t SCE
t HA
CE
t AW
t PWE1
t PWE2
WE
t HZWE
DOUT
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR1.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
ISSI
IS61LV2568
®
AC WAVEFORMS
WRITE CYCLE NO. 2(1) (WE Controlled, OE = HIGH during Write Cycle)
t WC
ADDRESS
VALID ADDRESS
t HA
OE
CE
LOW
t AW
t PWE1
WE
t SA
DOUT
t HZWE
t LZWE
HIGH-Z
DATA UNDEFINED
t SD
t HD
DATAIN VALID
DIN
CE_WR2.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
t WC
ADDRESS
VALID ADDRESS
OE
LOW
CE
LOW
t HA
t AW
t PWE2
WE
t SA
DOUT
t HZWE
DATA UNDEFINED
t LZWE
HIGH-Z
t SD
DIN
t HD
DATAIN VALID
CE_WR3.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
7
ISSI
IS61LV2568
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
Speed (ns)
Order Part No.
Package
8
IS61LV2568-8K
IS61LV2568-8T
400-mil Plastic SOJ
TSOP (Type II)
8
IS61LV2568-8KI
IS61LV2568-8TI
400-mil Plastic SOJ
TSOP (Type II)
10
IS61LV2568-10K
IS61LV2568-10T
400-mil Plastic SOJ
TSOP (Type II)
10
IS61LV2568-10KI
IS61LV2568-10TI
400-mil Plastic SOJ
TSOP (Type II)
12
IS61LV2568-12K
IS61LV2568-12T
400-mil Plastic SOJ
TSOP (Type II)
12
IS61LV2568-12KI
IS61LV2568-12TI
400-mil Plastic SOJ
TSOP (Type II)
15
IS61LV2568-15K
IS61LV2568-15T
400-mil Plastic SOJ
TSOP (Type II)
15
IS61LV2568-15KI
IS61LV2568-15TI
400-mil Plastic SOJ
TSOP (Type II)
ISSI
®
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
12/19/00
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