Catalyst CAT24C05YI-GT3 2-kb and 4-kb i2c serial eeprom with partial array write protection Datasheet

CAT24C03/05
2-Kb and 4-Kb I2C Serial EEPROM with Partial Array Write Protection
FEATURES
DEVICE DESCRIPTION
■ Supports Standard and Fast I2C Protocol
The CAT24C03/CAT24C05 is a 2-kb/4-kb CMOS Serial
EEPROM device organized internally as 16/32 pages
of 16 bytes each, for a total of 256x8/512x8 bits. These
devices support both Standard (100kHz) as well as Fast
(400kHz) I2C protocol.
■ 1.8 V to 5.5 V Supply Voltage Range
■ 16-Byte Page Write Buffer
■ Hardware Write Protection for upper half of
memory
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
■ Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 100 year data retention
Write operations can be inhibited for upper half of memory
by taking the WP pin High.
■ Industrial temperature range
■ RoHS-compliant 8-lead PDIP, SOIC, and TSSOP,
External address pins make it possible to address
up to eight CAT24C03 or four CAT24C05 devices on the
same bus.
8-pad TDFN and 5-lead TSOT-23 packages.
For Ordering Information details, see page 17.
PIN CONFIGURATION
FUNCTIONAL SYMBOL
PDIP (L)
SOIC (W)
TSSOP (Y)
TDFN (VP2)
VCC
TSOT-23 (TD)
CAT24C05 / 03
NC / A0
1
8
VCC
A1 / A1
A2 / A2
2
7
WP
3
6
SCL
VSS
4
5
SDA
SCL
1
VSS
2
SDA
3
5
WP
4
VCC
SCL
A2, A1, A0
CAT24C03
CAT24C05
SDA
WP
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A0, A1, A2
Device Address Inputs
SDA
Serial Data Input/Output
SCL
Serial Clock Input
WP
Write Protect Input
VCC
Power Supply
VSS
Ground
NC
No Connect
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
VSS
* Catalyst carries the I2C protocol under a license from the Philips Corporation.
1
Doc. No. 1116, Rev. B
CAT24C03/05
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature
-65°C to +150°C
Voltage on Any Pin with Respect to Ground(2)
-0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS(3)
Symbol
Parameter
Min
Units
NEND(4)
Endurance
1,000,000
Program/ Erase Cycles
100
Years
TDR
Data Retention
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICCR
Read Current
ICCW
Min
Max
Units
Read, fSCL = 400 kHz
1
mA
Write Current
Write, fSCL = 400 kHz
1
mA
ISB
Standby Current
All I/O Pins at GND or VCC
1
μA
IL
I/O Pin Leakage
Pin at GND or VCC
1
μA
VIL
Input Low Voltage
VCC x 0.3
V
VIH
Input High Voltage
VCC x 0.7 VCC + 0.5
V
VOL1
Output Low Voltage
VCC ≥ 2.5 V, IOL = 3.0 mA
0.4
V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2
V
Max
Units
-0.5
PIN IMPEDANCE CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol
Parameter
Conditions
CIN(3)
SDA I/O Pin Capacitance
VIN = 0 V
8
pF
CIN(3)
Input Capacitance (other pins)
VIN = 0 V
6
pF
IWP(5)
WP Input Current
VIN < VIH, VCC = 5.5 V
200
VIN < VIH, VCC = 3.3 V
150
VIN < VIH, VCC = 1.8 V
100
VIN > VIH
μA
1
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
Doc. No. 1116, Rev. B
2
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03/05
A.C. CHARACTERISTICS(1)
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C.
Standard
Symbol
FSCL
tHD:STA
Parameter
Min
Max
Clock Frequency
Fast
Min
100
START Condition Hold Time
Max
Units
400
kHz
4
0.6
μs
tLOW
Low Period of SCL Clock
4.7
1.3
μs
tHIGH
High Period of SCL Clock
4
0.6
μs
4.7
0.6
μs
tSU:STA
START Condition Setup Time
tHD:DAT
Data In Hold Time
0
0
μs
tSU:DAT
Data In Setup Time
250
100
ns
tR
SDA and SCL Rise Time
1000
300
ns
tF(2)
SDA and SCL Fall Time
300
300
ns
tSU:STO
STOP Condition Setup Time
tBUF
Bus Free Time Between STOP and START
tAA
SCL Low to Data Out Valid
tDH
Data Out Hold Time
Ti(2)
Noise Pulse Filtered at SCL and SDA Inputs
4
0.6
μs
4.7
1.3
μs
3.5
100
0.9
μs
100
100
ns
100
ns
tSU:WP
WP Setup Time
0
0
μs
tHD:WP
WP Hold Time
2.5
2.5
μs
tWR
tPU(2, 3)
Write Cycle Time
5
5
ms
Power-up to Ready Mode
1
1
ms
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times
≤ 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Levels
0.5 x VCC
Output Load
Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc No. 1116, Rev. B
CAT24C03/05
POWER-ON RESET (POR)
I2C BUS PROTOCOL
The CAT24C03/05 incorporates Power-On Reset
(POR) circuitry which protects the internal logic against
powering up in the wrong state.
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
The CAT24C03/05 device will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. For normal Read/Write operations, the first 4 bits of the Slave address are fixed at
1010 (Ah). The next 3 bits are used as programmable
address bits when cascading multiple devices and/or as
internal address bits. The last bit of the slave address,
R/W, specifies whether a Read (1) or Write (0) operation is to be performed. The 3 address space extension
bits are assigned as illustrated in Figure 2. A2, A1 and
A0 must match the state of the external address pins,
and a8 (CAT24C05) is internal address bit.
A0, A1 and A2: The Address inputs set the device address when cascading multiple devices. When not driven,
these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits the write operations for upper half of memory, when pulled HIGH. When
not driven, this pin is pulled LOW internally.
Acknowledge
FUNCTIONAL DESCRIPTION
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge the address byte and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9th clock cycle. As long as the Master acknowledges
the data, the Slave will continue transmitting. The Master
terminates the session by not acknowledging the last
data byte (NoACK) and by issuing a STOP condition.
Bus timing is illustrated in Figure 4.
The CAT24C03/05 supports the Inter-Integrated Circuit
(I2C) Bus data transmission protocol, which defines a
device that sends data to the bus as a transmitter and a
device receiving data as a receiver. Data flow is controlled
by a Master device, which generates the serial clock and
all START and STOP conditions. The CAT24C03/05 acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver.
Doc. No. 1116, Rev. B
4
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03/05
Figure 1. START/STOP Conditions
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Slave Address Bits
1
0
1
0
A2
A1
A0
R/W
CAT24C03
1
0
1
0
A2
A1
a8
R/W
CAT24C05
Figure 3. Acknowledge Timing
BUS RELEASE DELAY (RECEIVER)
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 4. Bus Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc No. 1116, Rev. B
CAT24C03/05
WRITE OPERATIONS
Byte Write
Hardware Write Protection
In Byte Write mode, the Master sends the START condition and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge,
the Master sends the byte address that is to be written
into the address pointer of the CAT24C03/05. After receiving another acknowledge from the Slave, the Master
transmits the data byte to be written into the addressed
memory location. The CAT24C03/05 device will acknowledge the data byte and the Master generates the STOP
condition, at which time the device begins its internal
Write cycle to nonvolatile memory (Figure 5). While this
internal cycle is in progress (tWR), the SDA output will be
tri-stated and the CAT24C03/05 will not respond to any
request from the Master device (Figure 6).
With the WP pin held HIGH, the upper half of memory
is protected against Write operations. If the WP pin is
left floating or is grounded, it has no impact on the operation of the CAT24C03/05. The state of the WP pin
is strobed on the last falling edge of SCL immediately
preceding the first data byte (Figure 8). If the WP pin is
HIGH during the strobe interval, the CAT24C03/05 will
not acknowledge the data byte and the Write request
will be rejected.
Delivery State
The CAT24C03/05 is shipped erased, i.e., all bytes are
FFh.
Page Write
The CAT24C03/05 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation (Figure 7). The Page Write operation is initiated in the same
manner as the Byte Write operation, however instead of
terminating after the data byte is transmitted, the Master
is allowed to send up to fifteen additional bytes. After
each byte has been transmitted the CAT24C03/05 will
respond with an acknowledge and internally increments
the four low order address bits. The high order bits that
define the page address remain unchanged. If the Master
transmits more than sixteen bytes prior to sending the
STOP condition, the address counter ‘wraps around’ to
the beginning of page and previously transmitted data
will be overwritten. Once all sixteen bytes are received
and the STOP condition has been sent by the Master, the
internal Write cycle begins. At this point all received data
is written to the CAT24C03/05 in a single write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once
the stop condition is issued to indicate the end of the
host’s write operation, the CAT24C03/05 initiates the
internal write cycle. The ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation.
If the CAT24C03/05 is still busy with the write operation, NoACK will be returned. If the CAT24C03/05 has
completed the internal write operation, an ACK will be
returned and the host can then proceed with the next
read or write operation.
Doc. No. 1116, Rev. B
6
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03/05
Figure 5. Byte Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
a7 ÷ a 0
d7 ÷ d0
S
T
O
P
S
P
A
C
K
SLAVE
A
C
K
A
C
K
Figure 6. Write Cycle Timing
SCL
8th Bit
Byte n
SDA
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Page Write Sequence
S
T
A
R
T
BUS ACTIVITY:
MASTER
DATA
BYTE
n
ADDRESS
BYTE
SLAVE
ADDRESS
DATA
BYTE
n+1
DATA
BYTE
n+P
S
T
O
P
S
P
A
C
K
SLAVE
A
C
K
A
C
K
A
C
K
A
C
K
n=1
P ≤ 15
Figure 8. WP Timing
ADDRESS
BYTE
DATA
BYTE
1
8
a7
a0
9
1
8
d7
d0
SCL
SDA
tSU:WP
WP
tHD:WP
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc No. 1116, Rev. B
CAT24C03/05
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set to
‘1’, the CAT24C03/05 will interpret this as a request for
data residing at the current byte address in memory.
The CAT24C03/05 will acknowledge the Slave address,
will immediately shift out the data residing at the current
address, and will then wait for the Master to respond.
If the Master does not acknowledge the data (NoACK)
and then follows up with a STOP condition (Figure 9),
the CAT24C03/05 returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read operation. The Master device first performs a ‘dummy’ write
operation by sending the START condition, slave address
and byte address of the location it wishes to read. After
the CAT24C03/05 acknowledges the byte address, the
Master device resends the START condition and the
slave address, this time with the R/W bit set to one. The
CAT24C03/05 then responds with its acknowledge and
sends the requested data byte. The Master device does
not acknowledge the data (NoACK) but will generate a
STOP condition (Figure 10).
Sequential Read
If during a Read session, the Master acknowledges
the 1st data byte, then the CAT24C03/05 will continue
transmitting data residing at subsequent locations until
the Master responds with a NoACK, followed by a STOP
(Figure 11). In contrast to Page Write, during Sequential
Read the address count will automatically increment to
and then wrap-around at end of memory (rather than
end of page).
Doc. No. 1116, Rev. B
8
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03/05
Figure 9. Immediate Read Sequence and Timing
BUS ACTIVITY:
MASTER
N
O
S
T
A
R
T
S
AT
CO
KP
SLAVE
ADDRESS
S
P
A
C
K
SLAVE
SCL
8
DATA
BYTE
9
8th Bit
SDA
DATA OUT
NO ACK
STOP
Figure 10. Selective Read Sequence
BUS ACTIVITY:
MASTER
S
T
A
R
T
S
T
A
R
T
ADDRESS
BYTE
SLAVE
ADDRESS
N
O
S
AT
CO
KP
SLAVE
ADDRESS
S
S
A
C
K
A
C
K
SLAVE
P
A
C
K
DATA
BYTE
Figure 11. Sequential Read Sequence
N
O
BUS ACTIVITY:
MASTER
A
C
K
SLAVE
ADDRESS
A
C
K
S
AT
CO
KP
A
C
K
P
SLAVE
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
9
DATA
BYTE
n+2
DATA
BYTE
n+x
Doc No. 1116, Rev. B
CAT24C03/05
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
A1
L
e
eB
b2
b
SYMBOL
A
A1
A2
b
b2
D
E
E1
e
eB
L
MIN
NOM
MAX
4.57
0.38
3.05
0.36
1.14
9.02
7.62
6.09
7.87
0.115
0.46
7.87
6.35
2.54 BSC
0.130
3.81
0.56
1.77
10.16
8.25
7.11
9.65
0.150
24C16_8-LEAD_DIP_(300P).eps
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC Standard MS001.
3. Dimensioning and tolerancing per ANSI Y14.5M-1982
Doc. No. 1116, Rev. B
10
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03/05
8-LEAD 150 MIL WIDE SOIC (W)
E1
E
h x 45
D
C
A
θ1
e
A1
L
b
SYMBOL
MIN
A1
A
b
C
D
E
E1
e
h
L
θ1
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
1.27 BSC
0.25
0.40
0°
0.50
1.27
8°
24C16_8-LEAD_SOIC.eps
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MS-012 dimensions.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc No. 1116, Rev. B
CAT24C03/05
8-LEAD TSSOP (Y)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
4
1
PIN #1 IDENT.
0.25
θ1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
θ1
MIN
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.50
0.00
NOM
0.90
3.00
6.4
4.40
0.65 BSC
0.60
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.75
8.00
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MO-153.
Doc. No. 1116, Rev. B
12
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03/05
8-PAD TDFN 2X3 PACKAGE (VP2)
A
E
PIN 1 INDEX AREA
A1
D
D2
A2
A3
SYMBOL
MIN
NOM
MAX
A
A1
A2
A3
b
D
D2
E
E2
e
L
0.70
0.00
0.45
0.75
0.02
0.55
0.20 REF
0.25
2.00
1.40
3.00
1.30
0.50 TYP
0.30
0.80
0.05
0.65
0.20
1.90
1.30
2.90
1.20
0.20
E2
0.30
2.10
1.50
3.10
1.40
PIN 1 ID
L
0.40
b
e
3xe
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
TDFN2X3 (03).eps
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MO-229.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc No. 1116, Rev. B
CAT24C03/05
5 LEAD TSOT-23 PACKAGE
5-Lead TSOT-23 (TD)
e
e
E
E1
E1
e1
D
A2
GAUGE
PLANE
c
A
L2
L
θ
A1
b
L1
SYMBOL
A
A1
A2
b
c
D
E
E1
e
e1
L
L1
L2
θ
MIN
—
0.01
0.80
0.30
0.12
0.30
NOM
—
0.05
0.87
—
0.15
2.90 BSC
2.80 BSC
1.60 BSC
0.95 BSC
1.90 BSC
0.40
0.60 REF
0.25 BSC
0°
MAX
1.0
0.1
0.9
0.45
0.20
0.50
8°
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
1. All dimensions are in millimeters.
2. Complies with JEDEC specification MO-193.
Doc. No. 1116, Rev. B
14
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03/05
PACKAGE MARKING
8-Lead PDIP
8-Lead SOIC
24CXXLI
FYYWWR
CSI
XX
I
YY
WW
R
F
=
=
=
=
=
=
=
24CXXWI
FYYWWR
CSI
XX
I
YY
WW
R
F
Catalyst Semiconductor, Inc.
Device Code (see Marking Code table below)
Temperature Range
Production Year
Production Week
Product Revision (see Marking Code table below)
Lead Finish
4 = NiPdAu
3 = Matte-Tin
=
=
=
=
=
=
=
Catalyst Semiconductor, Inc.
Device Code (see Marking Code table below)
Temperature Range
Production Year
Production Week
Product Revision (see Marking Code table below)
Lead Finish
4 = NiPdAu
3 = Matte-Tin
8-Lead TSSOP
YMRF
24CXXI
Marking Codes
Y
M
R
XX
I
WW
F
=
=
=
=
=
=
=
Production Year
Production Month
Die Revision (see Marking Code table below)
Device Code (see Marking Code table below)
Temperature Range
Production Week
Lead Finish
4 = NiPdAu
3 = Matte-Tin
Device Code
XX
Product Revision
R
24C03
03
G
24C05
05
J
Note:
(1) The circle on the package marking indicates the location of Pin 1.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc No. 1116, Rev. B
CAT24C03/05
PACKAGE MARKING
8-Pad TDFN
5-Lead TSOT
XXN
NNN
XXYM
YM
XX = XX
Device
CodeCode
= Device
Matte-Tin
Matte-Tin
NiPdAu NiPdAu
24C01
EP
EM
24C03 Rev. G
FA EE
24C02
ER
EB
FB
EN
24C05 Rev. J
24C04
ES
EC
N = Traceable
Code ET
24C08
ED
24C16
DZ
Y = Production
Year EU
N = Traceability Code
M = Production Month
Y = Production Year
M = Production Month
XX = Device Code
XX = Device Code
NiPdAu
Matte-Tin NiPdAu
Matte-Tin
24C01
RA
MM
RK
RH
24C03 Rev. G
24C02
RB
MN
RL
RJ
24C05 Rev. J
24C04
RC
MP
Y = Production
Year
24C08
RD
MR
24C16
ML
M = Production
Month RE
Y = Production Year
M = Production Month
Notes:
(1) The circle on the package marking indicates the location of Pin 1.
(2) For TDFN and TSOT packages, the Product Revision marking is included in the Device Code (XX).
Doc. No. 1116, Rev. B
16
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT24C03/05
EXAMPLE OF ORDERING INFORMATION
Prefix
CAT
Company ID
Device #
Suffix
24C03
Y
Product Number
24C03
24C05
L:
W:
Y:
VP2:
TD:
I
–
Temperature Range
I = Industrial (-40°C to +85°C)
Package
PDIP
SOIC, JEDEC
TSSOP
TDFN
TSOT
G
T3
T: Tape & Reel
3: 3000/Reel
Lead Finish
G: NiPdAu
Blank: Matte-Tin
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu pre-plated (PPF) lead frames.
(3) The device used in the above example is a CAT24C03YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
17
Doc No. 1116, Rev. B
REVISION HISTORY
Date
Document Revision
03/08/06
Doc# 1113 Rev. A
Doc# 1114 Rev. A
07/24/06
Doc# 1116 Rev. A
08/01/06
Doc# 1116 Rev. B
Comments
CAT24CAT03 Data Sheet initial issue
CAT24CAT05 Data Sheet initial issue
Combine CAT24C03 and CAT24C05 data sheets into one data sheet.
Update marking and ordering information.
Update Package Marking
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Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
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Publication #:
Revison:
Issue date:
1116
B
08/01/06