LTC2360/LTC2361/LTC2362 100ksps/250ksps/500ksps, 12-Bit Serial ADCs in TSOT-23 DESCRIPTION FEATURES n n n n n n n n n n n n 12-Bit Resolution Low Noise: 73dB SNR Low Power Dissipation: 1.5mW @ 100ksps 100ksps/250ksps/500ksps Sampling Rates Single Supply 2.35V to 3.6V Operation No Data Latency Sleep Mode with 0.1μA Typical Supply Current Dedicated External Reference (TSOT23-8) 1V to 3.6V Digital Output Supply (TSOT23-8) SPI/MICROWIRE™ Compatible Serial I/O Guaranteed Operation from –40°C to 125°C Tiny 6- and 8-Lead TSOT-23 Packages APPLICATIONS n n n n n n The LTC®2360/LTC2361/LTC2362 are 100ksps/250ksps/ 500ksps, 12-bit, sampling A/D converters that draw only 0.5mA, 0.75mA and 1.1mA, respectively, from a single 3V supply. The supply current drops at lower sampling rates because these devices automatically power down after conversions. The full-scale input of the LTC2360/ LTC2361/LTC2362 is 0V to VDD or VREF. These ADCs are available in tiny 6- and 8-lead TSOT-23 packages. The serial interface, tiny TSOT-23 package and extremely high sample rate-to-power ratio make the LTC2360/ LTC2361/LTC2362 ideal for compact, low power, high speed systems. The high impedance single-ended analog input and the ability to operate with reduced spans (down to 1.4V full scale) allow direct connection to sensors and transducers in many applications, eliminating the need for gain stages. Communication Systems Data Acquisition Systems Handheld Portable Devices Uninterrupted Power Supplies Battery-Operated Systems Automotive L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. TYPICAL APPLICATION 12-Bit TSOT23-6/-8 ADC Family DATA OUTPUT RATE 3Msps 1Msps 500ksps 250ksps 100ksps Part Number LTC2366 LTC2365 LTC2362 LTC2361 LTC2360 Single 3V Supply, 500ksps, 12-Bit Sampling ADC Supply Current vs Sample Rate 1200 3V LTC2362 VDD CONV VREF SCK GND SDO AIN OVDD SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTORS DIGITAL OUTPUT SUPPLY 1V TO 3.6V 2.2μF 236012 TA01a SUPPLY CURRENT (μA) 1000 2.2μF ANALOG INPUT 0V TO 3V VDD = 3.6V TA = 25°C 800 LTC2361 600 LTC2362 400 LTC2360 200 0 1 10 100 SAMPLE RATE (ksps) 1000 236012 TA01b 236012f 1 LTC2360/LTC2361/LTC2362 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) Supply Voltage (VDD, OVDD)........................................4V VREF and Analog Input Voltage (Note 3).........................................–0.3V to (VDD + 0.3V) Digital Input Voltage......................–0.3V to (VDD + 0.3V) Digital Output Voltage ...................–0.3V to (VDD + 0.3V) Power Dissipation ...............................................100mW Operating Temperature Range LTC2360C/LTC2361C/LTC2362C .............. 0°C to 70°C LTC2360I/LTC2361I/LTC2362I.............. –40°C to 85°C LTC2360H/LTC2361H/LTC2362H (Note 12).. –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) .................. 300°C PIN CONFIGURATION TOP VIEW VDD 1 VREF 2 GND 3 AIN 4 TOP VIEW 8 CONV 7 SCK 6 SDO 5 OVDD VDD 1 6 CONV GND 2 5 SDO AIN 3 4 SCK TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 S6 PACKAGE 6-LEAD PLASTIC TSOT-23 TJMAX = 150°C, θJA = 250°C/W TJMAX = 150°C, θJA = 250°C/W ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2362CTS8#TRMPBF LTC2362CTS8#TRPBF LTDBV 8-Lead Plastic TSOT23 0°C to 70°C LTC2362ITS8#TRMPBF LTC2362ITS8#TRPBF LTDBV 8-Lead Plastic TSOT23 -40°C to 85°C LTC2362HTS8#TRMPBF LTC2362HTS8#TRPBF LTDBV 8-Lead Plastic TSOT23 -40°C to 125°C LTC2362CS6#TRMPBF LTC2362CS6#TRPBF LTDGP 6-Lead Plastic TSOT23 0°C to 70°C LTC2362IS6#TRMPBF LTC2362IS6#TRPBF LTDGP 6-Lead Plastic TSOT23 -40°C to 85°C LTC2362HS6#TRMPBF LTC2362HS6#TRPBF LTDGP 6-Lead Plastic TSOT23 -40°C to 125°C LTC2361CTS8#TRMPBF LTC2361CTS8#TRPBF LTDGM 8-Lead Plastic TSOT23 0°C to 70°C LTC2361ITS8#TRMPBF LTC2361ITS8#TRPBF LTDGM 8-Lead Plastic TSOT23 -40°C to 85°C LTC2361HTS8#TRMPBF LTC2361HTS8#TRPBF LTDGM 8-Lead Plastic TSOT23 -40°C to 125°C LTC2361CS6#TRMPBF LTC2361CS6#TRPBF LTDGN 6-Lead Plastic TSOT23 0°C to 70°C LTC2361IS6#TRMPBF LTC2361IS6#TRPBF LTDGN 6-Lead Plastic TSOT23 -40°C to 85°C LTC2361HS6#TRMPBF LTC2361HS6#TRPBF LTDGN 6-Lead Plastic TSOT23 -40°C to 125°C LTC2360CTS8#TRMPBF LTC2360CTS8#TRPBF LTDGJ 8-Lead Plastic TSOT23 0°C to 70°C LTC2360ITS8#TRMPBF LTC2360ITS8#TRPBF LTDGJ 8-Lead Plastic TSOT23 -40°C to 85°C LTC2360HTS8#TRMPBF LTC2360HTS8#TRPBF LTDGJ 8-Lead Plastic TSOT23 -40°C to 125°C LTC2360CS6#TRMPBF LTC2360CS6#TRPBF LTDGK 6-Lead Plastic TSOT23 0°C to 70°C LTC2360IS6#TRMPBF LTC2360IS6#TRPBF LTDGK 6-Lead Plastic TSOT23 -40°C to 85°C LTC2360HS6#TRMPBF LTC2360HS6#TRPBF LTDGK 6-Lead Plastic TSOT23 TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ -40°C to 125°C 236012f 2 LTC2360/LTC2361/LTC2362 CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) PARAMETER CONDITIONS MIN l Resolution (No Missing Codes) TYP MAX UNITS 12 Bits (Notes 5, 6) l ±0.25 ±1 Differential Linearity Error (Note 6) l ±0.25 ±1 Transition Noise (Note 7) Offset Error (Note 6) l 1 ±3.5 LSB Gain Error (Note 6) l 0.1 ±2 LSB Total Unadjusted Error (Note 6) l 1.1 ±3.5 LSB Integral Linearity Error 0.25 LSB LSB LSBRMS ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN VIN Analog Input Voltage S6 Package TS8 Package l l IIN Analog Input Leakage Current CONV = High l CIN Analog Input Capacitance Between Conversions During Conversions VREF Reference Input Voltage TS8 Package l IREF Reference Input Leakage Current TS8 Package l CREF Reference Input Capacitance TS8 Package tAP Sample-and-Hold Aperture Delay Time tJITTER Sample-and-Hold Aperture Delay Time Jitter TYP MAX –0.05 –0.05 UNITS VDD + 0.05 VREF + 0.05 V ±1 μA 20 4 pF pF 1.4 VDD + 0.05 V ±1 μA 20 pF 1 ns 0.3 ns DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS SINAD Signal-to-(Noise + Distortion) Ratio fIN = 49kHz for LTC2360/LTC2361, fIN = 100kHz for LTC2362 72 dB SNR Signal-to-Noise Ratio fIN = 49kHz for LTC2360/LTC2361, fIN = 100kHz for LTC2362 73 dB THD Total Harmonic Distortion fIN = 49kHz for LTC2360/LTC2361, fIN = 100kHz for LTC2362 –85 dB SFDR Spurious Free Dynamic Range fIN = 49kHz for LTC2360/LTC2361, fIN = 100kHz for LTC2362 86 dB IMD Intermodulation Distortion fIN1 = 97kHz, fIN2 = 100kHz for LTC2362 fIN1 = 47kHz, fIN2 = 49kHz for LTC2360/LTC2361 –75 dB Full-Power Bandwidth at 3dB at 0.1dB 10 2 MHz MHz Full-Linear Bandwidth SINAD ≥ 68dB 1 MHz 236012f 3 LTC2360/LTC2361/LTC2362 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS VIH High Level Input Voltage 2.7V < VDD ≤ 3.6V 2.35V ≤ VDD ≤ 2.7V l l MIN TYP MAX VIL Low Level Input Voltage 2.7V < VDD ≤ 3.6V 2.35V ≤ VDD ≤ 2.7V l l 0.8 0.7 V V IIH High Level Input Current VIN = VDD l 2.5 μA VIN = 0V l –2.5 μA 2 1.7 UNITS V V IIL Low Level Input Current CIN Digital Input Capacitance VOH High Level Output Voltage VDD = 2.35V to 3.6V, ISOURCE = 200μA l VOL Low Level Output Voltage VDD = 2.35V to 3.6V, ISINK = 200μA l 0.2 V IOZ Hi-Z Output Leakage CONV = VDD l ±3 μA 2 pF VDD – 0.2 V COZ Hi-Z Output Capacitance CONV = VDD 4 pF ISOURCE Output Source Current VOUT = 0V –10 mA ISINK Output Sink Current VOUT = VDD 10 mA POWER REQUIREMENT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) SYMBOL PARAMETER VDD Supply Voltage OVDD Digital Output Supply Voltage IDD Supply Current Operational Mode, LTC2362 Operational Mode, LTC2361 Operational Mode, LTC2360 Sleep Mode Sleep Mode Sleep Mode fSMPL = 500ksps fSMPL = 250ksps fSMPL = 100ksps 0°C to 70°C –40°C to 85°C –40°C to 125°C l l l l l l Power Dissipation Operational Mode, LTC2362 Operational Mode, LTC2361 Operational Mode, LTC2360 Sleep Mode Sleep Mode Sleep Mode fSMPL = 500ksps fSMPL = 250ksps fSMPL = 100ksps 0°C to 70°C –40°C to 85°C –40°C to 125°C l l l l l l PD CONDITIONS MIN TYP MAX UNITS l 2.35 3.0 3.6 V l 1.0V 3.6 V 1.1 0.75 0.5 0.1 0.1 0.1 2 1.5 1 2 2 5 mA mA mA μA μA μA 3.3 2.25 1.5 0.3 0.3 0.3 7.2 5.4 3.6 7.2 7.2 18 mW mW mW μW μW μW 236012f 4 LTC2360/LTC2361/LTC2362 TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4) LTC2360 SYMBOL PARAMETER CONDITIONS fSMPL(MAX) Maximum Sampling Frequency (Notes 8, 9) l fSCK Shift Clock Frequency (Notes 8, 9) l tSCK MIN l Shift Clock Period TYP 100 MIN TYP LTC2362 MAX 250 100 MIN TYP MAX 500 10 50 MHz 2 μs 20 10 UNITS kHz 25 40 l tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV LTC2361 MAX ns 4 tACQ Acquisition Time l 2 1 0.5 μs tCONV Conversion Time l 8 3 1.5 μs t1 Minimum Positive CONV Pulse Width (Note 8) l 8 3 1.5 μs 16 t2 SCK↑ Setup Time After CONV↓ (Note 8) l t3 SDO Enabled Time After CONV↓ (Notes 8, 9) l 16 16 16 ns t4 SDO Data Valid Access Time After SCK↓ (Notes 8, 9, 10) l 8 8 8 ns t5 SCK Low Time (Note 11) l 40% 40% 40% tSCK t6 SCK High Time (Note 11) l 40% 40% 40% tSCK t7 SDO Data Valid Hold Time After SCK↓ (Notes 8, 9, 10) l t8 SDO Into Hi-Z State Time After CONV↑ (Notes 8, 9) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When pins AIN and VREF are taken below GND or above VDD, they will be clamped by internal diodes. These products can handle input currents greater than 100mA below GND or above VDD without latch-up. Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and fSCK = fSCK(MAX) unless otherwise specified. Note 5: Integral linearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. 16 4 16 4 6 ns 4 6 ns 6 ns Note 6: Linearity, offset and gain specifications apply for a single-ended AIN input with respect to GND. Note 7: Typical RMS noise at code transitions. Note 8: Guaranteed by characterization. All input signals are specified with tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V. Note 9: All timing specifications given are with a 10pF capacitance load. With a capacitance load greater than this value, a digital buffer or latch must be used. Note 10: The time required for the output to cross the VIH or VIL voltage. Note 11: Guaranteed by design, not subject to test. Note 12: High temperatures degrade operating lifetimes. Operating lifetime is derated at temperatures greater than 105°C. 236012f 5 LTC2360/LTC2361/LTC2362 TYPICAL PERFORMANCE CHARACTERISTICS Differential Nonlinearity vs Output Code Integral Nonlinearity vs Output Code 0.6 0.6 0.4 0.4 0.2 0.2 0 –0.2 –0.2 –0.4 –0.6 –0.6 –0.8 –0.8 –1 –1 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 0 0.2 MAX INL 0 MIN DNL –0.4 –0.6 –1 0.8 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 20.0 VDD = 3.6V SUPPLY CURRENT (μA) REFERENCE CURRENT (μA) 400 8000 300 200 100 2000 0 2046 2047 2048 CODE 2049 2050 0 16.0 12.0 8.0 4.0 0.0 10 20 30 40 50 60 70 80 90 100 SAMPLING FREQUENCY (ksps) 0 10 20 30 40 50 60 70 80 90 100 SAMPLE RATE (ksps) 236012 G05 236012 G04 236012 G06 THD vs Input Frequency SINAD vs Input Frequency 74 3.6 1.6 2 2.4 2.8 3.2 REFERENCE VOLTAGE (V) Reference Current vs Sample Rate (TS8 Package) VDD = 3.6V 4000 1.2 236012 G03 500 VDD = 3V 6000 MIN INL –0.2 Supply Current vs Sample Rate 10000 2045 MAX DNL 0.4 236012 G02 Histogram for 16384 Conversions COUNT 0.6 –0.8 236012 G01 0 VDD = 3.6V 0.8 0 –0.4 0 1 VDD = 3V 0.8 DNL (LSB) INL (LSB) 1 VDD = 3V 0.8 Integral and Differential Nonlinearity vs Reference Voltage (TS8 Package) NONLINEARITY ERROR (LSB) 1 TA = 25°C, VDD = OVDD = VREF (LTC2360, Note 4) 48kHz Sine Wave 8192 FFT Plot –78 0 –80 –20 VDD = 3.6V VDD = 3V fSMPL = 100ksps 73 –82 72 71 VDD = 2.35V MAGNITUDE (dB) VDD = 2.35V THD (dB) SINAD (dB) VDD = 3.0V –84 VDD = 3.6V –86 –88 –40 –60 –80 –100 70 –90 –120 VDD = 3.0V 69 –92 1 10 INPUT FREQUENCY (kHz) 100 236012 G07 1 10 INPUT FREQUENCY (kHz) 100 236012 G08 –140 0 10 30 20 40 INPUT FREQUENCY (kHz) 50 2306012 G09 236012f 6 LTC2360/LTC2361/LTC2362 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity vs Output Code 1 VDD = 3V 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0 –0.2 1 0 –0.4 –0.6 –0.6 –0.8 –0.8 –1 –1 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 0 MAX INL –0.4 –0.6 –1 0.8 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 4000 2047 2048 CODE 2049 50.0 VDD = 3.6V 600 400 200 0 2050 0 50 150 100 200 SAMPLE RATE (ksps) 40.0 30.0 20.0 10.0 0.0 250 0 50 150 200 100 SAMPLE RATE (ksps) 236012 G14 236012 G13 124kHz Sine Wave 8192 FFT Plot 0 –71 VDD = 3.6V –73 73 250 236012 G15 THD vs Input Frequency SINAD vs Input Frequency 74 3.6 Reference Current vs Sample Rate (TS8 Package) 2000 2046 1.6 2 2.4 2.8 3.2 REFERENCE VOLTAGE (V) 1.2 236012 G12 REFERENCE CURRENT (μA) SUPPLY CURRENT (μA) 6000 MIN INL MIN DNL VDD = 3.6V 8000 VDD = 3V fSMPL = 250ksps –20 –75 –77 THD (dB) VDD = 3.0V 72 VDD = 2.35V 71 VDD = 2.35V –79 –81 –83 –85 70 MAGNITUDE (dB) COUNT 0 –0.2 800 VDD = 3V SINAD (dB) 0.2 Supply Current vs Sample Rate 10000 2045 MAX DNL 0.4 236012 G11 Histogram for 16384 Conversions –40 –60 –80 –100 VDD = 3.6V –87 –120 –89 69 0.6 –0.8 236012 G10 0 VDD = 3.6V 0.8 –0.2 –0.4 0 Integral and Differential Nonlinearity vs Reference Voltage (TS8 Package) VDD = 3V 0.8 DNL (LSB) INL (LSB) Differential Nonlinearity vs Output Code NONLINEARITY ERROR (LSB) 1 TA = 25°C, VDD = OVDD = VREF (LTC2361, Note 4) 1 10 100 INPUT FREQUENCY (kHz) 1000 2306012 G16 VDD = 3.0V –91 1 10 100 INPUT FREQUENCY (kHz) –140 1000 236012 G17 0 25 75 50 100 INPUT FREQUENCY (kHz) 125 2306012 G18 236012f 7 LTC2360/LTC2361/LTC2362 TYPICAL PERFORMANCE CHARACTERISTICS Integral Nonlinearity vs Output Code 1 VDD = 3V 0.8 0.6 0.6 0.4 0.4 0.2 0.2 DNL (LSB) INL (LSB) 1 VDD = 3V 0 –0.2 0 –0.4 –0.6 –0.6 –0.8 –0.8 –1 –1 0.2 0 MIN INL MIN DNL –0.4 –0.6 –1 0.8 3.6 1.6 2 2.4 2.8 3.2 REFERENCE VOLTAGE (V) 1.2 236012 G21 Reference Current vs Sample Rate (TS8 Package) Supply Current vs Sample Rate 1200 10000 80.0 VDD = 3V VDD = 3.6V VDD = 3.6V SUPPLY CURRENT (μA) 6000 4000 2000 REFERENCE CURRENT (μA) 1000 8000 800 600 400 60.0 40.0 20.0 200 0 2045 2046 2047 2048 CODE 2049 0 2050 0 100 300 200 400 SAMPLE RATE (ksps) 0.0 500 248kHz Sine Wave 8192 FFT Plot –67 0 VDD = 3V –20 fSMPL = 500ksps VDD = 3.6V MAGNITUDE (dB) –71 VDD = 3.0V –75 THD (dB) VDD = 2.35V 72 71 VDD = 2.35V –79 –83 70 VDD = 3.0V VDD = 3.6V –87 –91 1 10 100 INPUT FREQUENCY (kHz) 1000 2306012 G25 50 100 150 200 250 300 350 400 450 500 SAMPLE RATE (ksps) 236012 G24 THD vs Input Frequency SINAD vs Input Frequency 74 73 0 236012 G23 236012 G22 SINAD (dB) MAX INL –0.2 236012 G20 Histogram for 16384 Conversions 69 MAX DNL 0.4 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE 236012 G19 COUNT 0.6 –0.8 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE VDD = 3.6V 0.8 –0.2 –0.4 0 Integral and Differential Nonlinearity vs Reference Voltage (TS8 Package) Differential Nonlinearity vs Output Code NONLINEARITY ERROR (LSB) 1 0.8 TA = 25°C, VDD = OVDD = VREF (LTC2362, Note 4) –40 –60 –80 –100 –120 1 10 100 INPUT FREQUENCY (kHz) 1000 2306012 G26 –140 0 50 150 100 200 INPUT FREQUENCY (kHz) 250 2306012 G27 236012f 8 LTC2360/LTC2361/LTC2362 PIN FUNCTIONS S6 Package TS8 Package VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. VDD also defines the input span of the ADC, 0V to VDD. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). VDD (Pin 1): Positive Supply. The VDD range is 2.35V to 3.6V. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). GND (Pin 2): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 3): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VDD. SCK (Pin 4): Shift Clock Input. The SCK serial clock synchronizes the serial data transfer. SDO data transitions on the falling edge of SCK. SDO (Pin 5): Three-State Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with MSB first. The data stream consists of 12 bits of conversion data followed by trailing zeros. CONV (Pin 6): Convert Input. This active high signal starts a conversion on the rising edge. The device automatically powers down after conversion. A logic low on this input enables the SDO pin, allowing the data to be shifted out. VREF (Pin 2): Reference Input. VREF defines the input span of the ADC, 0V to VREF. The VREF range is 1.4V to VDD. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). GND (Pin 3): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 4): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VREF. OVDD (Pin 5): Output Driver Supply for SDO. The OVDD range is 1V to 3.6V. Bypass to GND and to a solid ground plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in parallel with 0.1μF ceramic). OVDD can be driven separately from VDD and OVDD can be higher than VDD. SDO (Pin 6): Three-State Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with MSB first. The data stream consists of 12 bits of conversion data followed by trailing zeros. SCK (Pin 7): Shift Clock Input. The SCK serial clock synchronizes the serial data transfer. SDO data transitions on the falling edge of SCK. CONV (Pin 8): Convert Input. This active high signal starts a conversion on the rising edge. The device automatically powers down after conversion. A logic low on this input enables the SDO pin, allowing the data to be shifted out. 236012f 9 LTC2360/LTC2361/LTC2362 BLOCK DIAGRAM 2.2μF 2.2μF + + 1 ANALOG INPUT RANGE 0V TO VREF 5 VDD OVDD AIN 4 S AND H THREE-STATE SERIAL OUTPUT PORT 12-BIT ADC SDO 6 VREF 2 2.2μF SCK TIMING LOGIC GND 3 CONV 7 8 TS8 PACKAGE 236012 BD TIMING DIAGRAMS t8 CONV SDO t7 1.6V SCK Hi-Z SDO 236012 F01 1.6V VIH VIL 236012 F02 Figure 1. SDO Into Hi-Z State After CONV Rising Edge Figure 2. SDO Data Valid Hold Time After SCK Falling Edge t4 SCK 1.6V VIH SDO VIL 236012 F03 Figure 3. SDO Data Valid Acess Time After SCK Falling Edge 236012f 10 LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION DC PERFORMANCE DYNAMIC PERFORMANCE The noise of an ADC can be evaluated in two ways: signal-to-noise ratio (SNR) in the frequency domain and histogram in the time domain. The LTC2360/LTC2361/ LTC2362 excel in both. Figure 5 demonstrates that the LTC2360/LTC2361/LTC2362 have an SNR of over 73dB. The noise in the time domain histogram is the transition noise associated with a 12-bit resolution ADC which can be measured with a fixed DC signal applied to the input of the ADC. The resulting output codes are collected over a large number of conversions. The shape of the distribution of codes will give an indication of the magnitude of the transition noise. In Figure 4, the distribution of output codes is shown for a DC input that has been digitized 16384 times. The distribution is Gaussian and the RMS code transition is about 0.32LSB. This corresponds to a noise level of 73dB relative to a full scale of 3V. The LTC2360/LTC2361/LTC2362 have excellent high speed sampling capability. Fast fourier transform (FFT) test techniques are used to test the ADCs’ frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADCs’ spectral content can be examined for frequencies outside the fundamental. Figures 5 and 6 show typical LTC2361 and LTC2362 FFT plots respectively. 10000 VDD = 3V COUNT 8000 6000 4000 2000 0 2045 2046 2047 2048 CODE 2049 2050 236012 F04 Figure 4. Histogram for 16384 Conversions 0 –40 –60 –80 –40 –60 –80 –100 –100 –120 –120 –140 0 25 VDD = 3V fSMPL = 500ksps fIN = 248kHz SINAD = 73dB THD = –81dB –20 MAGNITUDE (dB) –20 MAGNITUDE (dB) 0 VDD = 3V fSMPL = 250ksps fIN = 124kHz SINAD = 73dB THD = –84dB 75 50 100 INPUT FREQUENCY (kHz) 125 236012 F05 Figure 5. LTC2361 FFT Plot –140 0 50 150 100 200 INPUT FREQUENCY (kHz) 250 236012 F06 Figure 6. LTC2362 FFT Plot 236012f 11 LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION Signal-to-Noise plus Distortion Ratio The signal-to-noise plus distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 6 shows a typical FFT with a 500kHz sampling rate and a 248kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist frequency of 250kHz. Effective Number of Bits The effective number of bits (ENOB) is a measurement of the resolution of an ADC and is directly related to SINAD by the equation: ENOB = SINAD – 1.76 6.02 where ENOB is the effective number of bits of resolution and SINAD is expressed in dB. At the maximum sampling 74 rate of 500kHz, the LTC2362 maintains ENOB above 11 bits up to the Nyquist input frequency of 250kHz (refer to Figure 7). Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD = 20log V2 2 + V3 2 + V4 2 + ...Vn 2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs. Input Frequency is shown in Figure 8. The LTC2362 has excellent distortion performance up to the Nyquist frequency and beyond. –67 12 VDD = 3.6V 73 11.67 71 70 11.34 –75 ENOB VDD = 2.35V VDD = 2.35V –79 –83 69 68 67 THD (dB) 72 SINAD (dB) –71 VDD = 3.0V 11 1 10 100 INPUT FREQUENCY (kHz) 1000 2306012 F07 Figure 7. LTC2362 ENOB and SINAD vs Input Frequency VDD = 3.0V VDD = 3.6V –87 –91 1 10 100 INPUT FREQUENCY (kHz) 1000 2306012 F08 Figure 8. LTC2362 THD vs Input Frequency 236012f 12 LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION Intermodulation Distortion Peak Harmonic or Spurious Noise If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermoduation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa ± fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: The full-power bandwidth is that input frequency at which the amplitude of reconstructed fundamental is reduced by 3dB for full-scale input signal. Amplitude at ( fa ± fb ) Amplitude at fa The full-linear bandwidth is the input frequency at which the SINAD has dropped to 68dB (11 effective bits). The LTC2362 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter’s Nyquist frequency. The noise floor stays very low at high frequencies; SINAD becomes dominated by distortion at frequencies far beyond Nyquist. 0 VDD = 3.6V fSMPL = 500ksps fa = 99kHz fb = 101kHz IMD = –76.5dB –20 MAGNITUDE (dB) IMD ( fa ± fb ) = 20log Full-Power and Full-Linear Bandwidth –40 –60 –80 –100 –120 0 50 100 200 150 INPUT FREQUENCY (kHz) 250 236012 F09 Figure 9. LTC2362 Intermodulation Distortion Plot 236012f 13 LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION OVERVIEW Data Transfer The LTC2360/LTC2361/LTC2362 use a successive approximation algorithm and internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output. All devices operate from a single 2.35V to 3.6V supply. The conversion time of the devices is controlled by an internal oscillator, which allows the LTC2360/LTC2361/LTC2362 to sample at a rate of 100ksps, 250ksps and 500ksps respectively. A rising CONV edge starts a conversion and disables SDO. After the conversion, the ADC automatically goes into sleep mode, drawing only leakage current. The LTC2360/LTC2361/LTC2362 contain a 12-bit, switchedcapacitor ADC, a sample-and-hold, a serial interface(see Block Diagram) and are available in tiny 6- or 8-lead TSOT-23 packages. The S6 package of the LTC2360/LTC2361/LTC2362 uses VDD as the reference and has an analog input range of 0V to VDD. The ADC samples the analog input with respect to GND and outputs the result through the serial interface. The TS8 package provides two additional pins: a reference pin, VREF, and an output supply pin, OVDD. The ADC can operate with reduced spans down to 1.4V and achieve 342μV resolution. OVDD controls the output swing of the digital output pin, SDO, and allows the device to communicate with 1.8V, 2.5V or 3V digital systems. SERIAL INTERFACE The LTC2360/LTC2361/LTC2362 communicate with microcontrollers, DSPs and other external circuitry via a 3-wire interface. Figure 10 shows the operating sequence of the serial interface. CONV going low enables SDO and clocks out the MSB bit, B11. SCK then synchronizes the data transfer with each bit being transmitted on the falling SCK edge and can be captured on the rising SCK edge. After completing the data transfer, if further SCK clocks are applied with CONV low, SDO will output zeros indefinitely (see Figure 10). For example, 16-clocks at SCK will produce the 12-bit data and four trailing zeros on SDO. SLEEP MODE The LTC2360/LTC2361/LTC2362 enter sleep mode to save power after each conversion if CONV remains high. In sleep mode, all bias currents are shut down and only leakage currents remain (about 0.1μA). The sample-and-hold is in hold mode while the ADC is in sleep mode. The ADC returns to sample mode after the falling edge of CONV during power-up (see Figure 10). Exiting Sleep Mode and Power-Up Time By taking CONV low, the ADC powers up and acquires an input signal completely after the aquisition time (tACQ). After tACQ, the ADC can perform a conversion as described in the Serial Interface section (see Figure 10). BY TAKING CONV LOW, THE DEVICE POWERS UP AND ACQUIRES AN INPUT ACCURATELY AFTER tACQ CONV tCONV SCK SDO SLEEP MODE RECOMMENDED HIGH OR LOW Hi-Z STATE t2 t6 1 t3 B11 2 3 4 t4 B10 9 10 t5 B9 12 t7 B3 B2 t8 B1 B0* 236012 F10 (MSB) t1 11 tACQ tTHROUGHPUT *AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY Figure 10. LTC2360/LTC2361/LTC2362 Serial Interface Timing Diagram 236012f 14 LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION ACHIEVING MICROPOWER PERFORMANCE With typical operating currents of 0.5mA, 0.75mA and 1.1mA for the LTC2360/LTC2361/LTC2362 and automatically entering sleep mode right after a conversion, these devices achieve extremely low power consumption over a wide range of sample rates (see Figure 11). The sleep mode allows the supply current to drop with reduced sample rate. Several things must be taken into account to achieve such low power consumption. Minimize Power Consumption in Sleep Mode The LTC2360/LTC2361/LTC2362 enter sleep mode after each conversion if CONV remains high and draw only leakage current (see Figure 10). If the CONV input is not running rail-to-rail, the input logic buffer will draw current. This current may be large compared to the typical supply 1200 VDD = OVDD = VREF = 3.6V TA = 25°C current. To obtain the lowest supply current, bring the CONV pin to GND when it is low and to VDD when it is high. After the conversion with CONV staying high, the converter is in sleep mode and draws only leakage current. The status of the SCK input has no effect on supply current during this time. For the best performance, hold SCK either high or low while the ADC is converting. Minimize the Device Active Time In systems that have significant time between conversions, the ADC draws a minimal amount of power. Figures 12 and 13 show two ways to minimize the amount of time the ADC draws power. In Figure 12, the ADC draws power during tACQ and tCONV and is in sleep mode for the rest of the time. The conversion results are available at the next CONV falling edge. In Figure 13, the ADC draws twice the power than that in Figure 12, but the conversion results are available during tDATA. The user can use the fastest SCK available in the system to shorten data transfer time, tDATA as long as t4 and t7 are not violated. SUPPLY CURRENT (μA) 1000 SDO Loading 800 Capacitive loading on the digital output can increase power consumption. A 100pF capacitor on the SDO pin can add more than 50μA to the supply current at a 200kHz clock frequency. An extra 50μA or so of current goes into charging and discharging the load capacitor. The same goes for digital lines driven at a high frequency by any logic. The C • V • f currents must be evaluated with the troublesome ones minimized. LTC2361 600 LTC2362 400 LTC2360 200 0 1 10 100 SAMPLE RATE (ksps) 1000 236012 TA01b Figure 11. Supply Current vs Sample Rate EXECUTING A CONVERSION AND PUTTING THE DEVICE INTO SLEEP MODE SAMPLING INPUT AND TRANSFERRING DATA CONV tACQ tCONV RECOMMENDED HIGH OR LOW SCK SDO SLEEP MODE 1 2 B11 B10 3 B9 4 9 B3 10 B2 11 B1 12 B0 Hi-Z STATE tTHROUGHPUT = tACQ + tCONV + tSLEEPMODE 236012 F12 Figure 12. Minimize the Time When the Device Draws Power, While the Conversion Results are Available After the Device Wakes Up 236012f 15 LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION CONV EXECUTE CONVERSION DATA TRANSFER ACQUIRE INPUT tACQ SCK tCONV EXECUTING A DUMMY CONVERSION AND PUT THE DEVICE INTO SLEEP MODE tDATA tCONV RECOMMENDED HIGH OR LOW SDO SLEEP MODE RECOMMENDED HIGH OR LOW 1 2 B11 B10 3 B9 4 9 B3 10 B2 11 B1 12 B0 tTHROUGHPUT = tACQ + 2 • tCONV + tDATA + tSLEEPMODE Hi-Z STATE 236012 F13 Figure 13. Minimize the Time When the Device Draws Power, While the Conversion Results are Available Right After Conversion SINGLE-ENDED ANALOG INPUT Driving the Analog Input The analog input of the LTC2360/LTC2361/LTC2362 is easy to drive. The input draws only one small current spike while charging the sample-and-hold capacitor with the ADC going into track mode. During the conversion, the analog input draws only a small leakage current. If the source impedance of the driving circuit is low, then the input of the LTC2360/LTC2361/LTC2362 can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier should be used. The main requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts (settling time must be less than tACQ for full throughput rate). While choosing an input amplifier, also keep in mind the amount of noise and harmonic distortion the amplifier contributes. Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100Ω) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 10MHz, then the output impedance at 10MHz must be less than 100Ω. The second requirement is that the closed-loop bandwidth must be greater than 8MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC2360/LTC2361/LTC2362 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC2360/LTC2361/LTC2362. (More detailed information is available on the Linear Technology website at www.linear.com.) LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass Filter. LT®1630: Dual 30MHz Rail-to-Rail Voltage FB Amplifier. 2.7V to ±15V supplies. Very high AVOL, 500μV offset and 520ns settling to 0.5LSB for a 4V swing. THD and noise are –93dB to 40kHz and below 1LSB to 320kHz (AV = 1, 2VP-P into 1k, VS = 5V), making the part excellent for AC applications (to 1/3 Nyquist) where rail-to-rail performance is desired. Quad version is available as LT1631. LTC6241: Dual 18MHz, Low Noise, Rail-to-Rail, CMOS Voltage FB Amplifier. 2.8V to 6V supplies. Very high AVOL and 125μV offset. It is suitable for applications with a single 5V supply. Quad version is available as LTC6242. LT1797: Unity-Gain Stable 10MHz, Rail-to-Rail Voltage Feedback Amplifier. LT1801: 180MHz GBWP, –75dBc at 500kHz, 2mA/Amplifier, 8.5nV/√Hz. LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz, UnityGain Stable, R-R In and Out, 3mA/Amplifier, 1.9nV/√Hz. 236012f 16 LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION Input Filtering and Source Impedance Reference Input The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC2360/LTC2361/LTC2362 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 10MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 14 shows a 220pF capacitor from AIN to ground and a 51Ω source resistor to limit the input bandwidth to 10MHz. The 220pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling-glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silvermica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. High external source resistance, combined with the 20pF of input capacitance, will reduce the rated 10MHz bandwidth and increase acquisition time beyond 500ns. On the TS8 package of the LTC2360/LTC2361/LTC2362, the voltage on the VREF pin defines the full-scale range of the ADC. The reference voltage can range from VDD down to 1.4V. Input Range The analog input of the LTC2360/LTC2361/LTC2362 is driven single-ended with respect to GND from a single supply. The input may swing up to VDD for the S6 package and to VREF for the TS8 package. The 0V to 2.5V range is also ideally suited for single-ended input use with VDD or VREF = 2.5V for single supply applications. If the difference between the AIN input and GND exceeds VDD for the S6 package or VREF for the TS8 package, the output code will stay fixed at all ones, and if this difference goes below 0V, the output code will stay fixed at all zeros. Figure 15 shows the ideal input/output characteristics for the LTC2360/LTC2361/LTC2362. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, …, FS – 1.5LSB). The output code is straight binary with 1LSB = VDD/4096 for the S6 package and 1LSB = VREF /4096 for the TS8 package. 111...111 LTC2362 1 2.2μF 220pF 51Ω 2 3 VDD CONV GND SDO AIN SCK 6 5 4 236012 F14 UNIPOLAR OUTPUT CODE 111...110 000...001 000...000 Figure 14. RC Input Filter 0 1LSB INPUT VOLTAGE (V) FS – 1LSB 236012 F15 Figure 15. Transfer Characteristics 236012f 17 LTC2360/LTC2361/LTC2362 APPLICATIONS INFORMATION BOARD LAYOUT AND BYPASSING connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Wire wrap boards are not recommended for high resolution and/or high speed A/D converters. To obtain the best performance from the LTC2360/LTC2361/LTC2362, a printed circuit board with ground plane is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by the ground plane. Figure 16 shows the recommended system ground connections. All analog circuitry grounds should be terminated at the LTC2360/LTC2361/LTC2362. The ground return from the LTC2360/LTC2361/LTC2362 to the power supply should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a wait state during conversion or by using three-state buffers to isolate the ADC data bus. High quality tantalum and ceramic bypass capacitors should be used at the VDD pin as shown in the Block Diagram on the first page of this data sheet. For optimum performance, a 2.2μF surface mount AVX capacitor with a 0.1μF ceramic is recommended for the VDD and VREF pins. Alternatively, 2.2μF ceramic chip capacitors such as Murata GRM235Y5V106Z016 may be used. The capacitors must be located as close to the pins as possible. The traces CVDD + 2.2μF PIN 1 CAIN VDD CONV GND SDO AIN SCK VIAS TO GROUND PLANE 236012 F16 Figure 16. Power Supply Ground Practice 236012f 18 LTC2360/LTC2361/LTC2362 PACKAGE DESCRIPTION S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 2.80 BSC 1.4 MIN 3.85 MAX 2.62 REF 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 1.90 BSC 0.09 – 0.20 (NOTE 3) S6 TSOT-23 0302 REV B 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637) 0.52 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 – 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 0.09 – 0.20 (NOTE 3) 1.95 BSC TS8 TSOT-23 0802 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 236012f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC2360/LTC2361/LTC2362 TYPICAL APPLICATION Recommended AC Test Circuitry for the LTC2362 3V + + 4.7μF 2.2μF 1k 1% ±1.5V AC INPUT VDD 50Ω 5% 4.7μF CONV AIN LTC2362 220pF 2200pF SCK TO MCU SDO GND 1k 1% 236012 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial Sampling ADC 3V, Differential Input, 12mW, MSOP Package LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package LTC1860 12-Bit, 250ksps Serial ADC 5V Supply, 1-Channel, 4.3mW, MSOP-8 Package LTC1860L 12-Bit, 150ksps Serial ADC 3V Supply, 1-Channel, 1.3mW, MSOP-8 Package LTC1861 12-Bit, 250ksps Serial ADC 5V Supply, 2-Channel, 4.3mW, MSOP-8 Package LTC1861L 12-Bit, 150ksps Serial ADC 3V Supply, 2-Channel, 1.3mW, MSOP-8 Package LTC1863 12-Bit, 200ksps Serial ADC 8-Channel ADC 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867 LTC1863L 12-Bit, 250ksps Serial ADC 8-Channel ADC 5V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L LTC1864/LTC1865 16-Bit, 250ksps Serial ADC 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package LTC1867 16-Bit, 200ksps Serial ADC 8-Channel ADC 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L LTC1867L 16-Bit, 175ksps Serial ADC 8-Channel ADC 3V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867 LTC2355/LTC2356 12-/14-Bit, 3.5Msps Serial ADCs 3.3V Supply, Differential Input, 18mW, MSOP Package LTC2365/LTC2366 12-Bit, 1/3 Msps Serial ADCs in TSOT23 2.35V to 3.6V Supply, Pin and Software Compatible to LTC2360/LTC2361/LTC2362 16-Bit, Serial SoftSpan™ IOUT DAC ±1LSB INL/DNL, Software Selectable Spans ADCs DACs LTC1592 LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs 87dB SFDR, 20ns Settling Time 12-/10-/8-Bit Single VOUT DACs SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits) LT1460-2.5 Micropower Series Voltage Reference 0.1% Initial Accuracy, 10ppm Drift LT1461-2.5 Precision Voltage Reference 0.05% Initial Accuracy, 3ppm Drift LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift LT6660 Ultra-Tiny Micropower Series Reference 2mm × 2mm DFN Package, 0.2% Initial Accuracy, 10ppm Drift LTC2630 References SoftSpan is a trademark of Linear Technology Corporation. 236012f 20 Linear Technology Corporation LT 0408 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008