EL5102, EL5103, EL5202, EL5203, EL5302 ® October 3, 2005 Data Sheet 400MHz Slew Enhanced VFAs Features The EL5x02 and EL5x03 families represent high-speed VFAs based on a CFA amplifier architecture. This gives the typical high slew rate benefits of a CFA family along with the stability and ease of use associated with the VFA type architecture. With slew rates of 3500V/µs this family of devices enables the use of voltage feedback amplifiers in a space where the only alternative has been current feedback amplifiers. This family will also be available in single, dual, and triple versions, with 200MHz, 400MHz, and 750MHz versions. These are all available in single, dual, and triple versions. • Operates off 3V, 5V, or ±5V applications Both families operate on single 5V or ±5V supplies from minimum supply current. EL5x02 also features an output enable function, which can be used to put the output in to a high-impedance mode. This enables the outputs of multiple amplifiers to be tied together for use in multiplexing applications. • AVOL = 2000 Typical applications for these families will include cable driving, filtering, A-to-D and D-to-A buffering, multiplexing and summing within video, communications, and instrumentation designs. FN7331.4 • Power-down to 0µA (EL5x02) • -3dB bandwidth = 400MHz • ±0.1dB bandwidth = 50MHz • Low supply current = 5mA • Slew rate = 3500V/µs • Low offset voltage = 5mV max • Output current = 140mA • Diff gain/phase = 0.01%/0.01° • Pb-Free plus anneal available (RoHS compliant) Applications • Video amplifiers • PCMCIA applications • A/D drivers • Line drivers • Portable computers • High speed communications • RGB applications • Broadcast equipment • Active filtering 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL5102, EL5103, EL5202, EL5203, EL5302 Ordering Information (Continued) Ordering Information PART PART NUMBER MARKING PACKAGE TAPE & REEL PKG. DWG. # TAPE & REEL PKG. DWG. # 8 Ld SO (Pb-free) 7” MDP0027 EL5203ISZ-T13 5203ISZ (See Note) 8 Ld SO (Pb-free) 13” MDP0027 MDP0027 - MDP0027 EL5203IY BSAAA 8 Ld MSOP - MDP0043 EL5203IY-T7 BSAAA 8 Ld MSOP 7” MDP0043 8 Ld SO (Pb-free) 7” MDP0027 EL5203IY-T13 BSAAA 8 Ld MSOP 13” MDP0043 8 Ld SO (Pb-free) 13” EL5203IYZ (See Note) BAAAE 8 Ld MSOP (Pb-free) - MDP0043 5102IS 8 Ld SO - MDP0027 EL5102IS-T7 5102IS 8 Ld SO 7” MDP0027 EL5102IS-T13 5102IS 8 Ld SO 13” EL5102ISZ (See Note) 5102ISZ 8 Ld SO (Pb-free) EL5102ISZ-T7 (See Note) 5102ISZ MDP0027 EL5203ISZ-T7 (See Note) PACKAGE 5203ISZ EL5102IS EL5102ISZ-T13 5102ISZ (See Note) PART PART NUMBER MARKING EL5102IW-T7 q 6 Ld SOT-23 7” MDP0038 (3K pcs) EL5203IYZ-T7 (See Note) BAAAE 8 Ld MSOP (Pb-free) 7” MDP0043 EL5102IW-T7A q 6 Ld SOT-23 7” MDP0038 (250 pcs) EL5203IYZ-T13 BAAAE (See Note) 8 Ld MSOP (Pb-free) 13” MDP0043 EL5103IC-T7 B 5 Ld SC-70 7” (3K pcs) P5.049 EL5302IU 5302IU 16 Ld QSOP - MDP0040 EL5302IU-T7 5302IU 16 Ld QSOP 7” MDP0040 EL5103IC-T7A B 5 Ld SC-70 7” (250 pcs) P5.049 EL5302IU-T13 5302IU 16 Ld QSOP 13” MDP0040 EL5103IW-T7 g 5 Ld SOT-23 MDP0038 7” (3K pcs) EL5302IUZ (See Note) 5302IUZ 16 Ld QSOP (Pb-free) - MDP0040 EL5103IW-T7A g 5 Ld SOT-23 7” MDP0038 (250 pcs) EL5302IUZ-T7 (See Note) 5302IUZ 16 Ld QSOP (Pb-free) 7” MDP0040 EL5202IY BRAAA 10 Ld MSOP - MDP0043 EL5302IUZ-T13 5302IUZ (See Note) 16 Ld QSOP (Pb-free) 13” MDP0040 EL5202IY-T7 BRAAA 10 Ld MSOP 7” MDP0043 EL5202IY-T13 BRAAA 10 Ld MSOP 13” MDP0043 EL5202IYZ (See Note) BAAAD 10 Ld MSOP (Pb-free) - MDP0043 EL5202IYZ-T7 (See Note) BAAAD 10 Ld MSOP (Pb-free) 7” MDP0043 EL5202IYZ-T13 BAAAD (See Note) 10 Ld MSOP (Pb-free) 13” MDP0043 EL5203IS 5203IS 8 Ld SO - MDP0027 EL5203IS-T7 5203IS 8 Ld SO 7” MDP0027 EL5203IS-T13 5203IS 8 Ld SO 13” MDP0027 EL5203ISZ (See Note) 5203ISZ 8 Ld SO (Pb-free) - MDP0027 2 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 Pinouts EL5103 (5 LD SOT-23) TOP VIEW EL5102 (6 LD SOT-23) TOP VIEW OUT 1 VS- 2 + - IN+ 3 6 VS+ OUT 1 5 CE VS- 2 4 IN- IN+ 3 8 CE IN- 2 + IN+ 3 VS- 4 INA- 2 6 OUT INA+ 3 IN+ 3 9 OUT + VS- 4 CE 5 7 OUTB + 6 INB+ 8 IN- INA+ 1 CEA 2 16 INA+ 7 IN+ CEB 4 6 CE INB+ 5 CEC 7 INC+ 8 15 OUTA 14 VS+ VS- 3 + - 13 OUTB 12 INB- NC 6 3 5 INB+ EL5302 (16 LD QSOP) TOP VIEW 10 VS+ + 8 VS+ VS- 4 EL5202 (10 LD MSOP) TOP VIEW IN- 2 4 IN- OUTA 1 7 VS+ 5 NC OUT 1 + - EL5203 (8 LD SO, MSOP) TOP VIEW EL5102 (8 LD SO) TOP VIEW NC 1 5 VS+ 11 NC + - 10 OUTC 9 INC- FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VS+ and GND . . . . . . . . . . . . . . . . . 13.2V Maximum Supply Slewrate between VS+ and VS- . . . . . . . . . 1V/µs Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±4V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 80mA Maximum Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . ±5mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature Range . . . . . . . . . .-40°C to +85°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, TA = 25°C, RL = 500Ω, VENABLE = +5V, unless otherwise specified. TYP MAX UNIT EL5102, EL5103, EL5202, EL5203 1 5 mV EL5302 2 8 mV Offset Voltage Temperature Coefficient Measured from TMIN to TMAX 10 Input Bias Current VIN = 0V -12 2 12 µA Input Offset Current VIN = 0V -8 1 8 µA TCIOS Input Bias Current Temperature Coefficient Measured from TMIN to TMAX PSRR Power Supply Rejection Ratio VS = ±4.75V to ±5.25V CMRR Common Mode Rejection Ratio CMIR VOS TCVOS IB IOS DESCRIPTION Offset Voltage CONDITIONS MIN µV/°C 50 nA/°C -70 -80 dB VCM = -3V to 3.0V -60 -80 dB Common Mode Input Range Guaranteed by CMRR test -3 ±3.3 RIN Input Resistance Common mode 200 400 kΩ CIN Input Capacitance SO package 1 pF 3 V IS,ON Supply Current - Enabled per amplifier 4.6 5.2 5.8 mA IS,OFF Supply Current - Shut-down per amplifier VS+ +1 0 +25 µA VS- -25 7 -1 µA VOUT = ±2.5V, RL = 1kΩ to GND 58 66 dB 60 dB AVOL Open Loop Gain VOUT = ±2.5V, RL = 150Ω to GND VOUT IOUT Output Voltage Swing Output Current RL = 1kΩ to GND ±3.5 ±3.9 V RL = 150Ω to GND ±3.4 ±3.7 V AV = 1, RL = 10Ω to 0V ±80 ±150 mA VCE-ON CE Pin Voltage for Power-up (VS+)-5 (VS+)-3 V VCE-OFF CE Pin Voltage for Shut-down (VS+)-1 VS+ V IEN-ON Pin Current - Enabled CE = 0V -1 0 +1 µA IEN-OFF Pin Current - Disabled CE = +5V 1 14 25 µA 4 FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 Closed Loop AC Electrical Specifications VS+ = +5V, VS- = -5V, TA = 25°C, VENABLE = +5V, AV = +1, RF = 0Ω, RL = 150Ω to GND pin, unless otherwise specified. (Note 1) PARAMETER DESCRIPTION CONDITIONS BW -3dB Bandwidth (VOUT = 400mVP-P) AV = 1, RF = 0Ω SR Slew Rate AV = +2, RL = 100Ω, VOUT = -3V to +3V MIN TYP MAX 400 1100 RL = 500Ω, VOUT = -3V to +3V 2200 UNIT MHz 5000 V/µs 4000 V/µs tR,tF Rise Time, Fall Time ±0.1V step 2.8 ns OS Overshoot ±0.1V step 10 % tS 0.1% Settling Time VS = ±5V, RL = 500Ω, AV = 1, VOUT = ±3V 20 ns dG Differential Gain (Note 2) AV = 2, RF = 1kΩ 0.01 % dP Differential Phase (Note 2) AV = 2, RF = 1kΩ 0.01 ° eN Input Noise Voltage f = 10kHz 12 nV/√Hz iN Input Noise Current f = 10kHz 11 pA/√Hz tDIS Disable Time (Note 3) 50 ns tEN Enable Time (Note 3) 25 ns NOTES: 1. All AC tests are performed on a “warmed up” part, except slew rate, which is pulse tested. 2. Standard NTSC signal = 286mVP-P, f = 3.58MHz, as VIN is swept from 0.6V to 1.314V.RL is DC coupled. 3. Disable/Enable time is defined as the time from when the logic signal is applied to the ENABLE pin to when the supply current has reached half its final value. 5 FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves 5 3 2 VS=±5V AV=+1 RF=0 RL=500Ω CL=+3.3pF 180 120 60 PHASE (°) NORMALIZED GAIN (dB) 240 VS=±5V AV=+1 RF=0 RL=500Ω CL=+3.3pF 4 1 0 -1 -2 0 -60 -120 -3 -4 -180 -3dB BW @ 438MHz -240 -5 0.1 1 10 100 FREQUENCY (MHz) 0.1 1000 FIGURE 1. GAIN vs FREQUENCY (-3dB BANDWIDTH) 70 0.3 0.2 0.1 GAIN=40dB or 100 FREQ.=1.64 MHz GAIN BW PRODUCT=1.64x100=164MHz 0.1dB BW @ 35MHz 0 -0.1 1000 VS=±5V RL=500Ω 60 GAIN (dB) NORMALIZED GAIN (dB) 0.4 10 100 FREQUENCY (MHz) FIGURE 2. PHASE vs FREQUENCY 0.5 VS=±5V AV=+1 RF=0 RL=500Ω CL=+3.3pF 1 50 40 -0.2 30 -0.3 -0.4 20 -0.5 1 10 FREQUENCY (MHz) 100 1 10 FREQUENCY (MHz) 100 FIGURE 4. GAIN BANDWIDTH PRODUCT 300 5 VS=±5V RL=500Ω 4 NORMALIZED GAIN (dB) GAIN-BANDWIDTH PRODUCT (MHz) FIGURE 3. 0.1dB BANDWIDTH 0 250 200 150 100 3 VS=±5V RL=500Ω CL=+3.3pF AV=+2 RF=RG=400Ω 2 AV=+1 RF=0 1 0 -1 -2 AV=+5 RF=1.6K, RG=400 -3 -4 50 -5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGES (±V) FIGURE 5. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGES 6 0.1 1 10 100 1000 FREQUENCY (MHz) FIGURE 6. GAIN vs FREQUENCY FOR VARIOUS +AV FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves (Continued) 5 3 2 5 AV=+1 RF=0 RL=500Ω CL=+3.3pF 1 0 -1 VS=±6 -2 VS=±5V VS=±4V -3 VS=±3V -4 -5 1 10 3 2 100 1 0 -1 -2 RL=150Ω -3 RL=75Ω -5 1000 RL=50Ω 0.1 1 FREQUENCY (MHz) 4 RL=500Ω RL=1kΩ 1 0 -1 RL=50Ω -2 RL=70Ω -3 RL=150Ω -4 1 10 100 FREQUENCY (MHz) 3 2 CL=15pF CL=27pF -1 0 -1 CL=3.3pF -2 -3 CL=0pF -4 RL=50Ω -2 -3 4 CL=8.2pF 1 RL=1kΩ 0 5 VS=±5V AV=+1 RF=0 RL=500Ω RL=500Ω 1 RL=75Ω RL=150Ω 0.1 1 10 FREQUENCY (MHz) 100 FIGURE 10. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +5) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 2 -5 1000 FIGURE 9. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +2) 5 3 VS=±5V AV=+5 RF=402Ω CL=+3.9pF -4 -5 0.1 1000 5 VS=±5V AV=+2 RF=402Ω CL=+3.9pF NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 100 FIGURE 8. GAIN vs FREQUENCY FOR VARIOUS RLOAD (AV = +1) 5 3 10 FREQUENCY (MHz) FIGURE 7. GAIN vs FREQUENCY FOR VARIOUS ±VS 4 RL=1kΩ RL=500Ω -4 VS=±2.5V 0.1 VS=±5V AV=+1 RF=0 CL=+3.3pF 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 3 2 VS=±5V AV=+2 RF=400Ω RL=500Ω CL=33pF CL=18pF 1 0 -1 CL=8.2pF -2 -3 CL=0pF -4 -5 CL=47pF -5 0.1 1 10 100 FREQUENCY (MHz) FIGURE 11. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV =+1) 7 1000 0.1 1 10 100 FREQUENCY (MHz) 1000 FIGURE 12. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV = +2) FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves (Continued) 5 3 2 5 VS=±5V AV=+5 RF=400Ω RL=500Ω CL=220pF CL=150pF 4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 CL=100pF 1 0 -1 CL=56pF -2 -3 -4 3 2 VS=±5V AV=+1 RL=500Ω CL=+3pF 1 0 -1 RF=50Ω -2 RF=25Ω -3 RF=0Ω -4 CL=0pF -5 -5 0.1 1 10 0.1 100 1 FREQUENCY (MHz) 3 2 5 VS=±5V AV=+2 RL=500Ω CL=+8pF RF=1.0kΩ 4 RF= 680Ω 1 0 -1 RF=402Ω -2 RF=274Ω -3 -4 -5 1 10 3 2 VS=±5V AV=+5 RL=500Ω CL=+12pF 1000 RF=4kΩ RF=2kΩ 1 0 -1 RF=100Ω RF=1kΩ -2 -3 -4 RF=100Ω 0.1 100 FIGURE 14. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +1) NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 4 10 FREQUENCY (MHz) FIGURE 13. GAIN vs FREQUENCY FOR VARIOUS CLOAD (AV =+5) 5 RF=150Ω RF=100Ω 100 -5 1000 RF=402Ω 0.1 1 10 100 FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 15. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +2) FIGURE 16. GAIN vs FREQUENCY FOR VARIOUS RF (AV = +5) NORMALIZED GAIN (dB) 4 3 2 VS=±5V AV=+2 RF=RG=402Ω RL=500Ω CL=+8pF CIN=3.3pF 5 CIN=4.7pF 4 NORMALIZED GAIN (dB) 5 CIN=2.2pF 1 0 -1 -2 CIN=1pF -3 CIN=0pF -4 -5 0.1 1 10 100 FREQUENCY (MHz) 2 CIN=8.2pF CIN=10pF CIN=6.8pF 1 0 -1 -2 CIN=0pF CIN=4.7pF -3 -4 1000 FIGURE 17. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +2) 8 3 VS=±5V AV=+5 RG=402Ω RL=1600Ω CL=+12pF -5 0.1 1 10 FREQUENCY (MHz) 100 FIGURE 18. GAIN vs FREQUENCY FOR VARIOUS CIN(-) (AV = +5) FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 -45 70 0 45 PHASE 50 90 40 135 30 180 20 225 GAIN 10 270 0 315 -10 -20 10 VCC=+5V VEE=-5V 100 OUTPUT IMPEDANCE (Ω) 80 60 GAIN (dB) (Continued) PHASE (°) Typical Performance Curves 360 1K 10K 100K 1M AV=+2 VS=±5V 10 1 0.1 0.01 405 10M 100M 1G 10K 100K FREQUENCY (Hz) FIGURE 19. OPEN LOOP GAIN AND PHASE vs FREQUENCY -10 -10 -40 -20 -50 -60 -70 -30 -40 -50 -80 -60 -90 -70 -100 -80 10K 100K 1M 10M +PSRR -90 1K 100M 500M -PSRR 10K 9 RLOAD=1kΩ 8 GROUP DELAY (ns) MAX OUTPUT VOLTAGE SWING (Vp-p) 10 7 6 5 4 1 0 VS=±5V AV=+2 RF=RG=402Ω CL=8pF 0.1 1 RLOAD=150Ω 10 100 1000 FREQUENCY (MHz) FIGURE 23. MAX OUTPUT VOLTAGE SWING vs FREQUENCY 9 1M 10M 100M 500M FIGURE 22. PSRR vs FREQUENCY FIGURE 21. CMRR vs FREQUENCY 2 100K FREQUENCY (Hz) FREQUENCY (Hz) 3 100M AV=+1 VS=±5V 0 PSRR (dB) CMRR (dB) 10 -30 -110 1K 10M FIGURE 20. OUTPUT IMPEDANCE/PHASE vs FREQUENCY AV=+5 VS=±5V -20 1M FREQUENCY (Hz) 30 25 VS=±5V A =+1 20 RV=0 F 15 RL=500Ω 10 5 0 -5 -10 -15 -20 -25 -30 0.1 1 10 100 FREQUENCY (MHz) 1000 FIGURE 24. GROUP DELAY vs FREQUENCY FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves (Continued) -10 ISOLATION (dB) -30 VS=±5V AV=+1 RF=0 CHIP DISABLED OUTPUT to INPUT -40 -50 -60 INPUT to OUTPUT -70 -80 -90 -100 0.1 1 10 100 1000 GAIN (dB) -20 10 NOTE: 0 VS=±5V This was done on the -10 AV=+1 EL5203 (Dual Op-Amps) RF=0 -20 R =500Ω L -30 B in to A Out -40 -50 A in to B Out -60 -70 -80 -90 -100 -110 -120 0.1 1 10 100 FREQUENCY (MHz) FIGURE 25. INPUT AND OUTPUT ISOLATION FIGURE 26. CHANNEL TO CHANNEL ISOLATION -20 -30 -40 -50 -60 VS=±5V AV=+1 RF=0 RL=500Ω CL=3.3pF VOUT=2Vp-p VS=±5V AV=+5 RG=402Ω RF=1600Ω RL=500Ω CL=12pF -30 -40 THD (dBc) HARMONIC DISTORTION (dBc) 1000 FREQUENCY (MHz) T.H.D -70 2nd HD -80 -50 FIN=10MHz -60 -70 -80 -90 FIN=1MHz -90 3rd HD -100 0.1 -100 1 10 100 6 5 ENABLE SIGNAL AMPLITUDE (V) 4 3 VS=±5V AV=+1 RF=0 RL=500Ω VOUT=2Vp-p OUTPUT SIGNAL 2 1 0 VS=±5V 5 AV=+1 RF=0 4 R =500Ω L 3 VOUT=2Vp-p 2 -2 FIGURE 29. TURN-ON TIME 10 4 5 6 7 8 DISABLE SIGNAL OUTPUT SIGNAL 0 -1 TIME (ns) 3 1 -2 0 200 400 600 800 1000 1200 1400 1600 2 6 -1 -3 -600 -400 -200 1 FIGURE 28. TOTAL HARMONIC DISTORTION vs OUTPUT VOLTAGES AMPLITUDE (V) FIGURE 27. HARMONIC DISTORTION vs FREQUENCY 0 OUTPUT VOLTAGES (Vp-p) FUNDAMENTAL FREQUENCY (MHz) -3 -600 -400 -200 0 200 400 600 800 1000 1200 1400 1600 TIME (ns) FIGURE 30. TURN-OFF TIME FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves (Continued) 0.5 AMPLITUDE (V) NOISE VOLTAGE (nV/√Hz) RL=500Ω CL=3.3pF VOUT=400mV VS=±5V 0.4 AV=+1 RF=0 0.3 VS=±5V 100 10 0.2 TFALL=0.9ns 0.1 0.0 TRISE=0.923ns -0.1 -0.2 1 10 100 1K 10K -0.3 -20 100K 0 20 FREQUENCY (Hz) FIGURE 31. EQUIVALENT NOISE VOLTAGE vs FREQUENCY 6.0 AMPLITUDE (V) 3 2 1 TFALL=1.167ns 0 TRISE=1.243ns -1 -2 5.6 5.4 5.2 5.0 4.8 4.6 Please note that the curve showed positive Current. The negative current was almost the same. 4.4 4.2 4.0 2.5 -3 0 20 40 60 80 100 120 140 160 TIME (ns) FIGURE 33. LARGE SIGNAL STEP RESPONSE_RISE AND FALL TIME 10 0 -10 -20 -30 -40 -50 Delta IM=(1)-(-77)=78dB IP3=1+(78/2)=40dBm 40 35 2f2-f1=-77.0dBm @ 1.15MHz 2f1-f2=-76.8dBm -60 @ 0.85MHz -70 5.5 6.0 VS=±5V AV=+5 RF=1600Ω RL=100Ω CL=12pF 45 f2=1dBm @ 1.05MHz f1=1dBm @ 0.95MHz 30 25 20 15 -80 10 -90 5 0 0.9 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 50 VS=±5V AV=+5 RF=1600Ω RL=100Ω CL=12pF -100 0.8 3.0 FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE IP3 (dBm) -20 AMPLITUDE (dBm) AV=+1 RF=0 RL=500Ω CL=3.3pF 5.8 SUPPLY CURRENT (mA) 4 RL=500Ω CL=5pF VOUT=4.0V 60 80 100 120 140 160 TIME (ns) FIGURE 32. SMALL SIGNAL STEP RESPONSE_RISE AND FALL TIME 5 VS=±5V AV=+5 RG=25Ω 40 1.0 1.1 FREQUENCY (MHz) 1.2 FIGURE 35. THIRD ORDER IMD INTERCEPT (IP3) 11 1 10 FREQUENCY (MHz) 100 FIGURE 36. THIRD ORDER IMD INTERCEPT vs FREQUENCY FN7331.4 October 3, 2005 EL5102, EL5103, EL5202, EL5203, EL5302 Typical Performance Curves JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 1.087W M θ JA = 0.8 SO 11 5 P8 °C 0.6 543mW 0.4 θJ SO 0 0 /W T2 3 A =23 0.2 /1 1.4 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 (Continued) - 5/6 0° C /W 1.2 1.136W 25 75 85 100 50 125 0.8 QSOP16 θJA=112°C/W 0.6 0.4 0.2 150 0 25 FIGURE 37. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) POWER DISSIPATION (W) 1 607mW MSOP8/10 θJA=206°C/W 488mW 0.5 0.4 SOT23-5/6 θJA=256°C/W 0.3 0.2 0.1 0 0 25 75 85 100 50 125 75 85 100 150 125 FIGURE 38. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.6 50 AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) 0.7 SO8 θJA=110°C/W 1 1.116W 0 0 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 150 AMBIENT TEMPERATURE (°C) FIGURE 39. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 791mW 0.8 QSOP16 θJA=158°C/W 781mW 0.6 SO8 θJA=160°C/W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 40. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7331.4 October 3, 2005