[ /Title (CD74H C14, CD74H CT14) /Subject (High Speed CMOS Logic Hex Invert- CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Data sheet acquired from Harris Semiconductor SCHS129F High-Speed CMOS Logic Hex Inverting Schmitt Trigger January 1998 - Revised May 2005 Features Description • Unlimited Input Rise and Fall Times The ’HC14 and ’HCT14 each contain six inverting Schmitt triggers in one package. • Exceptionally High Noise Immunity Ordering Information • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads PART NUMBER TEMP. RANGE (oC) PACKAGE • Wide Operating Temperature Range . . . -55oC to 125oC CD54HC14F3A -55 to 125 14 Ld CERDIP • Balanced Propagation Delay and Transition Times CD54HCT14F3A -55 to 125 14 Ld CERDIP • Significant Power Reduction Compared to LSTTL Logic ICs CD74HC14E -55 to 125 14 Ld PDIP CD74HC14M -55 to 125 14 Ld SOIC • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD74HC14MT -55 to 125 14 Ld SOIC CD74HC14M96 -55 to 125 14 Ld SOIC CD74HC14PW -55 to 125 14 Ld TSSOP • HCT Types - 4.5V to 5.5V Operation - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HC14PWR -55 to 125 14 Ld TSSOP CD74HCT14E -55 to 125 14 Ld PDIP CD74HCT14M -55 to 125 14 Ld SOIC CD74HCT14MT -55 to 125 14 Ld SOIC CD74HCT14M96 -55 to 125 14 Ld SOIC CD74HCT14PW -55 to 125 14 Ld TSSOP CD74HCT14PWR -55 to 125 14 Ld TSSOP NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. The suffix T denotes a small-quantity reel of 250. Pinout CD54HC14, CD54HCT14 (CERDIP) CD74HC14, CD74HCT14 (PDIP, SOIC, TSSOP) TOP VIEW 1A 1 14 VCC 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 8 4Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2005, Texas Instruments Incorporated 1 CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Functional Diagram 1A 2A 3A 4A 5A 6A 1 2 3 4 5 6 9 8 11 10 13 12 1Y 2Y 3Y 4Y 5Y 6Y GND = 7 VCC = 14 TRUTH TABLE INPUT (A) OUTPUT (Y) L H H L H= High Level L= Low Level Logic Diagram nA nY VH VO VH = VT+ - VTVI VT- VT+ V T+ VT - VCC VH VI GND VCC VO GND FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP 2 CD54HC14, CD74HC14, CD54HCT, CD74HCT14 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 1) θJA (oC/W) E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VT+ - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 2 0.7 1.5 0.7 1.5 0.7 1.5 V 4.5 1.7 3.15 1.7 3.15 1.7 3.15 V 6 2.1 4.2 2.1 4.2 2.1 4.2 V 2 0.3 1.0 0.3 1.0 0.3 1.0 V 4.5 0.9 2.2 0.9 2.2 0.9 2.2 V 6 1.2 3.0 1.2 3.0 1.2 3.0 V 2 0.2 1.0 0.2 1.0 0.2 1.0 V 4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 6 0.6 1.6 0.6 1.6 0.6 1.6 V -0.02 2 1.9 - 1.9 - 1.9 - V -0.02 4.5 4.4 - 4.4 - 4.4 - V -0.02 6 5.9 - 5.9 - 5.9 - V - - - - - - - - V -4 4.5 3.98 - 3.84 - 3.7 - V -5.2 6 5.48 - 5.34 - 5.2 - V 0.02 2 - 0.1 - 0.1 - 0.1 V 0.02 4.5 - 0.1 - 0.1 - 0.1 V 0.02 6 - 0.1 - 0.1 - 0.1 V HC TYPES Input Switch Points VT- VH High Level Output Voltage CMOS Loads VOH - - V T- High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads VOL VT+ - - - - - - - - - - - V 4 4.5 - 0.26 - 0.33 - 0.4 V 5.2 6 - 0.26 - 0.33 - 0.4 V 3 CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current SYMBOL VI (V) II VCC or GND - ICC VCC or GND VT+ - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 6 - ±0.1 - ±1 - ±1 µA 0 6 - 2 - 20 - 40 µA - 4.5 1.2 1.9 1.2 1.9 1.2 1.9 V 5.5 1.4 2.1 1.4 2.1 1.4 2.1 V 4.5 0.5 1.2 0.5 1.2 0.5 1.2 V 5.5 0.6 1.4 0.6 1.4 0.6 1.4 V 4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 5.5 0.4 1.5 0.4 1.5 0.4 1.5 V -0.02 4.5 4.4 - 4.4 - 4.4 - V -4 4.5 3.98 - 3.84 - 3.7 - V 0.02 4.5 - 0.1 - 0.1 - 0.1 V 4 4.5 - 0.26 - 0.33 - 0.4 V HCT TYPES Input Switch Points VT- VH High Level Output Voltage CMOS Loads VOH V T- High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VT+ Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND - 5.5 - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - 2 - 20 - 40 µA ∆ICC (Note 2) VCC - 2.1 - 4.5 to 5.5 - 360 - 450 - 490 µA NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS nA 0.6 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 4 Switching Specifications Input tr, tf = 6ns PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 135 - 170 - 205 ns CL = 50pF 4.5 - - 27 - 34 - 41 ns CL = 15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 23 - 29 - 35 ns CL = 50pF 2 - - 75 - 95 18 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns HC TYPES Propagation Delay, A to Y Output Transition Times tTLH, tTHL Input Capacitance Power Dissipation Capacitance (Notes 3, 4) CI - - - - 10 - 10 - 10 pF CPD - 5 - 20 - - - - - pF CL = 50pF 4.5 - - 38 - 48 - 57 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 4.5 - - 15 - 19 - 22 ns HCT TYPES Propagation Delay, A to Y tPLH, tPHL Output Transition Times tTLH, tTHL Input Capacitance Power Dissipation Capacitance (Notes 3, 4) CI - - - - 10 - 10 - 10 pF CPD - 5 - 20 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per inverter. 4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL tPHL tf = 6ns tr = 6ns VCC tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 4. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 5 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) CD54HC14F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type CD54HC14F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type CD54HCT14F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type CD54HCT14F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type CD74HC14E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC14EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HC14M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14M96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14M96G4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14ME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14MG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14MT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14MTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14MTG4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HC14PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14E ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT14EE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type CD74HCT14M ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14M96 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14M96E4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14M96G4 ACTIVE SOIC D 14 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CD74HCT14ME4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14MG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14MT ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14MTE4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14MTG4 ACTIVE SOIC D 14 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14PW ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14PWR ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CD74HCT14PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC14M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC14M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC14MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC14PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HCT14M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT14MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT14PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC14M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC14M96 SOIC D 14 2500 333.2 345.9 28.6 CD74HC14MT SOIC D 14 250 367.0 367.0 38.0 CD74HC14PWR TSSOP PW 14 2000 367.0 367.0 35.0 CD74HCT14M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HCT14MT SOIC D 14 250 367.0 367.0 38.0 CD74HCT14PWR TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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