Freescale MCF51EM256CLK Coldfire microcontroller Datasheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MCF51EM256
Rev.2, 4/2010
MCF51EM256
MCF51EM256 Series
ColdFire Microcontroller
80 LQFP
14 mm × 14 mm
917A-03
100 LQFP
14 mm × 14 mm
983-02
Covers: MCF51EM256
MCF51EM128
The MCF51EM256/128 series microcontrollers are
a member of the ColdFire® family of reduced
instruction set computing (RISC) microprocessors.
This document provides an overview of these
32-bit microcontrollers, focusing on their highly
integrated and diverse feature set.
These microcontrollers are systems-on-chips
(SoCs) that are based on the V1 ColdFire core and
the following features:
• Operating at processor core speeds up to
50.33 MHz (peripherals operate at half of
this speed) at 3.6 V to 2.5 V and 20 MHz at
2.5 V to 1.8 V
• Up to 256 KB of flash memory
• Up to 16 KB of RAM
• Less than 1.3 μA of typical power
consumption in battery mode, with MCU
supply off
• Ultra-low power independent RTC with
calendar features, separate time base, power
domain, and 32 bytes of RAM
• A collection of communications
peripherals, including UART, IIC and SPI
• Integrated 16-bit SAR analog-to-digital
converter
• Programmable delay block (PDB)
• Two analog comparators with selectable
interrupt (PRACMP)
• LCD driver
•
•
•
•
•
Three serial communications interface
modules (SCI)
Three serial peripheral interfaces
Inter-integrated circuit (IIC)
Two 8-bit and one 16-bit modulo timers
(MTIM)
Two-channel timer/PWM module (TPM)
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2008-2010. All rights reserved.
Preliminary—Subject to Change Without Notice
Table of Contents
1
2
MCF51EM256 Series Configurations . . . . . . . . . . . . . . . . . . . .3
1.1 Device Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3.1 Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.4 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.5 Pinouts and Packaging . . . . . . . . . . . . . . . . . . . . . . . . .11
1.5.1 Pinout: 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . .11
1.5.2 Pinout: 100-Pin LQFP . . . . . . . . . . . . . . . . . . . .12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .16
2.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .17
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
2.4 Electrostatic Discharge (ESD) Protection Characteristics
19
2.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .24
2.7 Analog Comparator (PRACMP) Electricals. . . . . . . . . .27
2.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.9
2.10
2.11
2.12
3
4
External Oscillator (XOSC) Characteristics . . . . . . . . .
Internal Clock Source (ICS) Characteristics . . . . . . . .
LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
2.12.2 Timer (TPM/FTM) Module Timing . . . . . . . . . .
2.13 VREF Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . .
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . .
3.1 80-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 100-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
35
37
37
38
39
40
40
43
44
44
45
45
49
53
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
2
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51EM256 Series Configurations
1
MCF51EM256 Series Configurations
1.1
Device Comparison
The MCF51EM256 series is summarized in Table 1.
Table 1. MCF51EM256 Series Features by MCU and Package
Feature
MCF51EM256
MCF51EM128
Flash size (bytes)
262144
131072
RAM size (bytes)
16384
8192
Robust flash update
supported
Yes
Pin quantity
100
80
100
80
PRACMP1 inputs
5
3
5
3
PRACMP2 inputs
5
ADC modules
4
4
ADC differential
channels1
4
2
4
2
ADC single-ended
channels
16
12
16
12
DBG
Yes
ICS
Yes
IIC
Yes
IRQ
Yes
IRTC
Yes
VREF
Yes
LCD drivers
44
37
44
37
Rapid GPIO2
16
16
16
16
Port I/O3
47
40
47
40
Yes
No
Keyboard interface 1
8
Keyboard interface 2
8
SCI1
Yes
SCI2
Yes
SCI3
Yes
SPI1 (FIFO)
Yes
SPI2 (standard)
Yes
SPI3 (standard)
Yes
No
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
3
MCF51EM256 Series Configurations
Table 1. MCF51EM256 Series Features by MCU and Package (continued)
Feature
MCF51EM256
MCF51EM128
MTIM1 (8-bit)
Yes
MTIM2 (8-bit)
Yes
MTIM3 (16-it)
Yes
TPM channels
2
PDB
Yes
XOSC14
Yes
XOSC25
Yes
1
Each differential channel is comprised of 2 pin inputs
RGPIO is muxed with standard Port I/O
3 Port I/O count does not include the ouput only PTC2/BKGD/MS.
4 IRTC crystal input and possible crystal input to the ICS module
5 Main external crystal input for the ICS module
2
1.2
Block Diagram
Figure 1 shows the connections between the MCF51EM256 series pins and modules.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51EM256 Series Configurations
AD[20]
ADC 4
Port F:
AD[7], AD[19:17]
DADP/M[3]
AD[20]
ADC 3
PRACMP1*
ADC 2
Port F, B:
AD[6], AD[19:14]
DADP/M[2]
AD[20]
Port B, E:
RX2
TX2
Port A:
AD[5], AD[13:10]
ADC 1
SCI3
Port C,F:
RX3
TX3
IIC
Port B:
SDA
SCL
8-Bit MTIM1 Port B, D:
TMRCLK[n]
BDM
Port B, D:
TMRCLK[n]
8-Bit MTIM2 Port B, D:
INTC
RGPIO
Port A:
MOSI1 SS1
MISO1 SPSCK1
SPI2
LCD[9:6]:
MOSI2 SS2
MISO2 SPSCK2
SPI3
Port E, B:
MOSI3 SS3
MISO3 SPSCK3
LVD
FLASH1
128/64 KB
IRQ
Robust
Internal Clock Source
Update
FLASH2
Manager
128/64 KB
RAM
VREG
16/8 KB
VDD
1
2
REF CLK
IRCLK
Clock Check
& Select
XOSC2 Port C:
DADP/M[3,0]
AD[7,4]
EXTAL2
XTAL2
Port A0 or LCD25
CLKO
DADP/M[2:1]
AD[6:5]
XOSC1
LCD
VLL[3:1], VCAP[2:1]
SIM
LCD[24:21, 15:10]
RESET
SPI1
LCD[35] (CLKOUT)
LCD[26:25, 20:16]
V1 ColdFire Core
with MAC
COP
PTF7/LCD43/AD19
PTF6/LCD42/AD18
PTF5/LCD41/AD17
PTF4/LCD40/AD16
PTF3/LCD39/TX3
PTF2/LCD38/RX3
PTF1/LCD37/EXTRIG
PTF0/LCD36
Port B:
RGPIO[15:8]
Port A:
RGPIO[7:0]
PTA0/RPGPIO0/
IRQ/CLKOUT
PTE7/LCD5
PTE6/SS3/TX2
PTE5/SCLK3
PTE4/MISO3/MOSI3
PTE3/MOSI3/MISO3
PTE2/PRACMP1P1
PTE1/PRACMP1P3/AD9
PTE0/PRACMP1O/AD8
TMRCLK[n]
Port C:
BKGD/MS
control
BKGD/MS/PTC2
16-Bit MTIM3
Port E
TPMCLK
2 Channel TPM TPMCH[1:0]
Port F
Port A:
Port B/C & D:
KBI1P[7:0]
KBI2P[7:0]
KBI 1 & 2
Port D
DADP/M[1]
VREF
DBG
Port B
Port B:
RX1
TX1
SCI2
trig[A]
sel[A][1:0]
VDDA/VSSA
VREFH/VREFL
SCI1
Port C
AD[20]
COUT2
COUT1
VREFH/VREFL
Hardware CRC
PTA7/RGPIO7/TPMCLK/PRACMP1P2/AD13
PTA6/RGPIO6/TPMCH1/AD12
PTA5/RGPIO5/TPMCH0/AD11
PTA4/RGPIO4/SS1
PTA3/RGPIO3/SCLK1
PTA2/RGPIO2/MISO1/AD10
PTA1/RGPIO1/MOSI1
PTA0/RGPIO0/IRQ/CLKOUT
PTB7/RGPIO15/KBI1P5/TMRCLK2/AD15
PTB6/RGPIO14/KBI1P4/TMRCLK1/AD14
PTB5/RGPIO13/SDA/PRACMP2P3
PTB4/RGPIO12/SCL/PRACMP2P2
PTB3/RGPIO11/KBI1P3/PRACMP2P1/TX1
PTB2/RGPIO10/KBI1P2/PRACMP1P0/RX1
PTB1/RGPIO9/KBI1P1/SS3/TX2
PTB0/RGPIO8/KBI1P0/PRACMP2P0/RX2
PTC7/LCD4
PTC6/LCD3/PRACMP2P4
PTC5/LCD2/PRACMP1P4
PTC4/LCD1/PRACMP2O
PTC3/LCD0/PRACMP1O
BKGD/MS/PTC2
PTC1/KBI1P7/XTAL2/TX3
PTC0/KBI1P6/EXTAL2/RX3
PTD7/LCD34/KBI2P7
PTD6/LCD33/KBI2P6
PTD5/LCD32/KBI2P5/TMRCLK2
PTD4/LCD31/KBI2P4/TMRCLK1
PTD3/LCD30/KBI2P3
PTD2/LCD29/KBI2P2
PTD1/LCD28/KBI2P1
PTD0/LCD27/KBI2P0
PRACMP2
trig[B]
sel[B][1:0]
VDDA/VSSA
VREFO
Port F:
EXTRIG
COUT1
Port E, A:
AD[4], AD[13,9:8]
DADP/M[0]
VDDA/VSSA
VREFH/VREFL
PDB
trig[D:A]
sel[D:A][1:0]
trig[C]
sel[C][1:0]
VDDA/VSSA
VREFH/VREFL
trig[D]
sel[D][1:0]
COUT2
VREFH/VREFL
Port A
VDDA/VSSA
Port C,E:
LCD[5:0]
Port D:
LCD[34:27]
Port F:
LCD[43:36]
SPI2:
LCD[9:6]
VSS1 VSS2
EXTAL1
XTAL1
Port A0 or LCD25
CLKO
Independent
RTC
The IRTC is in a separate
power domain, as is the
LCD controller.
EXTAL1 XTAL1 VBAT TAMPER
Pins with • are not present on 80-pin devices.
PRACMP1 has two less available inputs on the 80-pin devices.
Figure 1. MCF51EM256 Series Block Diagram
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
5
MCF51EM256 Series Configurations
1.3
Features
Table 2 describes the functional units of the MCF51EM256 series.
Table 2. MCF51EM256 Series Functional Units
Unit
Function
ADC (analog-to-digital converter)
Measures analog voltages at up to 16 bits of resolution. Each ADC has
up to four differential and 24 single-ended inputs.
BDM (background debug module)
Provides single pin debugging interface (part of the V1 ColdFire core)
CF1 CORE (V1 ColdFire core) with MAC
unit
Executes programs, handles interrupts and containes
multiply-accumulate hardware (MAC).
PRACMP1, PRACMP2 (comparators)
Analog comparators for comparing external analog signals against
each other, or a variety of reference levels.
COP (computer operating poperly)
Software watchdog
IRQ (interrupt request)
Single pin high priority interrupt (part of the V1 ColdFire core)
CRC (cyclic Redundancy Check)
High-speed CRC calculation
DBG (debug)
Provides debugging and emulation capabilities (part of the V1 ColdFire
core)
FLASH (flash memory)
Provides storage for program code, constants and variables
IIC (inter-integrated circuits)
Supports standard IIC communications protocol and SMBus
INTC (interrupt controller)
Controls and prioritizes all device interrupts
KBI1 & KBI2
Keyboard Interfaces 1 and 2
LCD
Liquid crystal display driver
LVD (low voltage detect)
Provides an interrupt to the CF1CORE in the event that the supply
voltage drops below a critical value. The LVD can also be programmed
to reset the device upon a low voltage event
ICS (internal clock source)
Provides clocking options for the device, including a three
frequency-locked loops (FLLs) for multiplying slower reference clock
sources
IRTC (independent real-time clock)
The independent real time clock provides an independent time-base
with optional interrupt, battery backup and tamper protection
VREF (voltage reference)
The voltage reference output is available for both on and off-chip use
MTIM1, MTIM2 (modulo timers)
8-bit modulo timers with configurable clock inputs and interrupt
generation on overflow
MTIM3 (modulo timer)
16-bit modulo timer with configurable clock inputs and interrupt
generation on overflow
PDB (programmable delay block)
This timer is optimized for scheduling ADC conversions
RAM (random-access memory)
Provides stack and variable storage
RGPIO (rapid general-purpose
input/output)
Allows for I/O port access at CPU clock speeds and is used to
implement GPIO functionality for PTA and PTB.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
6
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51EM256 Series Configurations
Table 2. MCF51EM256 Series Functional Units (continued)
Unit
Function
SCI1, SCI2, SCI3(serial communications
interfaces)
Serial communications UARTs capable of supporting RS-232 and LIN
protocols
SIM (system integration unit)
SPI1 (FIFO), SPI2, SPI3 (serial peripheral SPI1 has full-complementary drive outputs. SPI2 may be configured
interfaces)
with full-complementary drive output via LCD control registers. SPI3
has open drain outputs on SCLK and (MISO or MOSI). These coupled
with off-chip pull-up resistors, allow interface to an external 5 V SPI.
TPM (Timer/PWM Module)
Timer/PWM module can be used for a variety of generic timer
operations as well as pulse-width modulation
VREG (voltage regulator)
Controls power management across the device
XOSC1 and XOSC2 (crystal oscillators)
These devices incorporate redundant crystal oscillators in separate
power domains.One is intended primarily for use by the IRTC, and the
other by the CPU and other peripherals.
1.3.1
•
•
•
Feature List
32-bit ColdFire V1 central processor unit (CPU)
— Up to 50.33 MHz ColdFire CPU from 3.6 V to 2.5 V and 20 MHz CPU at 2.5 V to 1.8 V across
temperature range of –40 °C to 85 °C
— ColdFire instruction set revision C (ISA_C) plus MAC
— 32-bit multiply and accumulate (MAC) optimized for 16×16±32 operations; supports signed or
unsigned integer or signed fractional inputs
On-chip memory
— MCF51EM256/128 series support two independent flash arrays; read/program/erase over full
operating voltage and temperature; allows interrupt processing while programming for robust
program updates
— Random-access memory (RAM)
— Security circuitry to prevent unathorized access to RAM and Flash contents
Power-saving modes
— Two ultra-low power stop modes
— New low-power run and low-power wait modes
— Reduced power wait mode
— Peripheral clock enable register can disable clocks to unused modules, thereby reducing
currents
— Ultra-low power independent real time clock with calendar features (IRTC); runs in all MCU
modes; external clock source with trim capabilities; independent voltage source runs IRTC
when MCU is powered-down; tamper detection and indicator; battery monitor output to ADC;
unaffected by MCU resets
— Ultra-low power external oscillator that can be used in stop modes to provide accurate clock
source to IRTC, ICS and LCD
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
7
MCF51EM256 Series Configurations
•
•
•
•
— 6 μs typical wakeup time from stop3 mode
Clock source options
— Two independent oscillators (XOSC1 and XOSC2) — loop-control Pierce oscillator;
32.768 kHz crystal or ceramic resonator. XOSC1 nominally supports the independent real time
clock, and can be powered by a separate battery backup. XOSC2 is the primary external clock
source for the ICS
— Internal clock source (ICS) — internal clock source module containing a
frequency-locked-loop (FLL) controlled by internal or external reference (XOSC1 or XOSC2);
precision trimming of internal reference allowing 0.2% resolution and typical 0.5% to –1%
deviation over temperature and voltage; supporting CPU frequencies from 4 kHz to 50 MHz
System protection
— Watchdog computer operating properly (COP) reset with option to run from dedicated 1 kHz
internal clock source or bus clock
— Low voltage detection with reset or interrupt; selectable trip points; seperate low voltage
warning with optional interrupt; selectable trip points
— Illegal opcode and illegal address detection with reset
— Flash block protection for each array to prevent accidental write/erasure
— Hardware CRC module to support fast cyclic redundancy checks
Development support
— Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM connection supports
same electrical interface used by the S08 family debug modules
— Real-time debug support with six hardware breakpoints (4 PC, 1 address and 1 data)
— On-chip trace buffer provides programmable start/stop recording conditions
Peripherals
— ADC16 — 4 analog-to-digital converters; the 100 pin version of the device has 1 dedicated
differential channel and 1 dedicated single-ended channel per ADC, along with 3 muxed
single-ended channels per ADC. The ADCs have 16-bit resolution, range compare function,
1.7 mV/°C temperature sensor, internal bandgap reference channel, operate in stop3 and are
fully functional from 3.6 V to 1.8 V
— PDB — Programmable delay block with 16-bit counter and modulus and 3-bit prescaler; 8
trigger outputs for ADC16 modules (2 per ADC); provides periodic coordination of ADC
sampling sequence with programmable sequence completion interrupt
— IRTC — Ultra-low power independent real time clock with calendar features (IRTC); runs in
all MCU modes; external clock source with trim capabilities (XOSC1); independent voltage
source runs IRTC when MCU is powered-down; tamper detection and indicator; battery
monitor output to ADC; unaffected by MCU resets
— PRACMPx — Two analog comparators with selectable interrupt on rising, falling, or either
edge of comparator output; compare option to programmable internal reference voltage;
operation in stop3
— LCD — up to 288 segments (8 × 36); 160 segments (4 × 40); internal charge pump and option
to provide internal reference voltage that can be trimmed for contrast control; flexible
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
8
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51EM256 Series Configurations
•
•
1.4
front-plane/backplane pin assignments; operation in all low power modes with blink
functionality
— SCIx — Three serial communications interface modules with optional 13-bit break; option to
connect Rx input to PRACMP output on SCI1 and SCI2; high current drive on Tx on SCI1 and
SCI2; wakeup from stop3 on Rx edge. SCI1 and SCI2 Tx pins can be modulated with timer
outputs for use with IR interfaces
— SPIx— Two serial peripheral interfaces (SPI2, SPI3) with full-duplex or single-wire
bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or
LSB-first shifting
— SPI16— Serial peripheral interface (SPI1) with 32-bit FIFO buffer; 16-bit or 8-bit data
transfers; full-duplex or single-wire bidirectional; double-buffered transmit and receive; master
or slave mode; MSB-first or LSB-first shifting
— IIC — Up to 100 kbps with maximum bus loading; multi-master operation; programmable
slave address; interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit
addressing
— MTIMx — Two 8-bit and one 16-bit modulo timers with 4-bit prescaler; overflow interrupt;
external clock input/pulse accumulator
— TPM — 2-channel Timer/PWM module; selectable input capture, output compare, or buffered
edge- or center-aligned PWM on each channel; external clock input/pulse accumulator; can be
used modulate SCI1 and SCI2 TX pins
Input/output
— up to 16 rapid GPIO and 48 standard GPIOs, including 1 output-only pin and 3 open-drain pins.
— up to 16 keyboard interrupts with selectable polarity
— Hysteresis and configurable pullup device on all input pins; configurable slew rate and drive
strength on all output pins
Package options
— 100-pin LQFP, 80-pin LQFP
Part Numbers
MCF 51 EM 256 C XX
Status
(MCF = Fully Qualified ColdFire)
(PCF = Product Engineering)
Core
Family
Package designator
Temperature range
(C= –40°C to 85°C )
Memory size designator
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
9
MCF51EM256 Series Configurations
Table 3. Orderable Part Number Summary
Freescale Part Number
Flash / SRAM (KB)
Package
Temperature
MCF51EM256CLL
256/16
100-Pin LQFP
–40°C to 85°C
MCF51EM256CLK
256/16
80-Pin LQFP
–40°C to 85°C
MCF51EM128CLL
128/16
100-Pin LQFP
–40°C to 85°C
MCF51EM128CLK
128/16
80-Pin LQFP
–40°C to 85°C
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
10
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51EM256 Series Configurations
1.5
1.5.1
Pinouts and Packaging
Pinout: 80-Pin LQFP
Pins not available on the 80-pin LQFP are automatically disabled for reduced current consumption. No
user interaction is needed. Software access to the functions on these pins will be ignored
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80 LQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTE7/LCD5
PTC7/LCD4
PTC6/LCD3/PRACMP2P5
PTC5/LCD2/PRACMP1P4
PTC4/LCD1/PRACMP2O
PTC3/LCD0/PRACMP1O
BKGD/MS/PTC2
PTC1/KBI1P7/XTAL2/TX3
PTC0/KBI1P6/EXTAL2/RX3
RESET
PTB7/RGPIO15/KBI1P5/TMRCLK2/AD15
PTB6/RGPIO14/KBI1P4/TMRCLK1/AD14
PTB5/RGPIO13/SDA/PRACMP2P3
PTB4/RGPIO12/SCL/PRACMP2P2
PTB3/RGPIO11/KBI1P3/PRACMP2P1/TX1
PTB2/RGPIO10/KBI1P2/PRACMP1P0/RX1
VSS
VDD
PTB1/RGPIO9/KBI1P1/SS3/TX2
PTB0/RGPIO8/KBI1P0/PRACMP2P0/RX2
DADM1
AD5
DADP2
DADM2
AD6
VREFO
VREFL
VSSA
EXTAL1
XTAL1
VBAT
TAMPER
PTA0/RGPIO0/IRQ/CLKOUT
PTA1/RGPIO1/MOSI1
PTA2/RGPIO2/MISO1/AD10
PTA3/RGPIO3/SCLK1
PTA4/RGPIO4/SS1
PTA5/RGPIO5/TPMCH0/AD11
PTA6/RGPIO6/TPMCH1/AD12
PTA7/RGPIO7/TPMCLK/PRACMP1P2/AD13
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PTD0/LCD27/KBI2P0
PTD1/LCD28/KBI2P1
PTD2/LCD29/KBI2P2
PTD3/LCD30/KBI2P3
PTD4/LCD31/KBI2P4/TMRCLK1
PTD5/LCD32/KBI2P5/TMRCLK2
PTD6/LCD33/KBI2P6
PTD7/LCD34/KBI2P7
LCD35/CLKOUT
PTF0/LCD36
PTF1/LCD37/EXTRIG
PTF2/LCD38/RX3
PTF3/LCD39/TX3
PTF4/LCD40/AD16
PTF5/LCD41/AD17
PTF6/LCD42/AD18
PTF7/LCD43/AD19
VDDA
VREFH
DADP1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
VCAP1
VCAP2
VLL1
VLL2
VLL3
VSS
LCD24
LCD23
LCD22
LCD21
LCD15
LCD14
LCD13
LCD12
LCD11
LCD10
LCD9/SS2
LCD8/SCLK2
LCD7/MISO2
LCD6/MOSI2
Figure 2 shows the pinout of the 80-pin LQFP.
Figure 2. 80-Pin LQFP Pinout
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
11
MCF51EM256 Series Configurations
1.5.2
Pinout: 100-Pin LQFP
VLL1
VLL2
VLL3
VSS
LCD24
LCD23
LCD22
LCD21
LCD20
LCD19
LCD18
LCD17
LCD16
LCD15
LCD14
LCD13
LCD12
LCD11
LCD10
LCD9/SS2
LCD8/SCLK2
LCD7/MISO2
LCD6/MOSI2
98
97
96
95
94
92
91
90
89
88
87
86
84
83
82
81
80
79
78
77
76
85
VCAP2
99
93
VCAP1
100
Figure 3 shows the pinout configuration for the 100-pin LQFP. Pins which are blacked out do not have an
equivalent pin on the 80-pin LQFP package.
LCD25
1
75
PTE7/LCD5
LCD26
2
74
PTC7/LCD4
PTD0/LCD27/KBI2P0
3
73
PTC6/LCD3/PRACMP2P4
PTD1/LCD28/KBI2P1
4
72
PTC5/LCD2/PRACMP1P4
PTD2/LCD29/KBI2P2
5
71
PTC4/LCD1/PRACMP2O
PTD3/LCD30/KBI2P3
6
70
PTC3/LCD0/PRACMP1O
PTD4/LCD31/KBI2P4/TMRCLK1
7
69
BKGD/MS/PTC2
PTD5/LCD32/KBI2P5/TMRCLK2
8
68
PTD6/LCD33/KBI2P6
9
67
PTC1/KBI1P7/XTAL2/TX3
PTC0/KBI1P6/EXTAL2/RX3
PTD7/LCD34/KBI2P7
10
66
RESET
LCD35/CLKOUT
11
65
PTF0/LCD36
12
64
PTB7/RGPIO15/KBI1P5/TMRCLK2/AD15
PTB6/RGPIO14/KBI1P4/TMRCLK1/AD14
PTF1/LCD37/EXTRIG
13
63
PTE6/SS3/TX2
PTF2/LCD38/RX3
14
PTF3/LCD39/TX3
100 LQFP
44
45
46
47
48
49
PTA1/RGPIO1/MOSI1
PTA2/RGPIO2/MISO1/AD10
PTA3/RGPIO3/SCLK1
PTA4/RGPIO4/SS1
PTA5/RGPIO5/TPMCH0/AD11
PTA6/RGPIO6/TPMCH1/AD12
50
43
PTA7/RGPIO7/TPMCLK/PRACMP1P2/AD13
42
PTE0/PRACMP1O/AD8
PTE1/PRACMP1P3/AD9
41
PTA0/RGPIO0/IRQ/CLKOUT
PTE2/PRACMP1P1
40
51
TAMPER
25
39
PTB0/RGPIO8/KBI1P0/PRACMP2P0RX2
DADP1
VBAT
PTB1/RGPIO9/KBI1P1/SS3/TX2
52
38
53
24
XTAL1
23
AD4
37
DADM0
EXTAL1
VDD
36
54
VSSA
22
35
VSS
DADP0
34
55
VREFL
21
VREFO
PTB2/RGPIO10/KBI1P2/PRACMP1P0/RX
VREFH
33
56
AD7
20
32
PTB3/RGPIO11/KBI1P3/PRACMP2P1/TX
VDDA
DADM3
PTB4/RGPIO12/SCL/PRACMP2P2
57
31
58
19
DADP3
18
PTF7/LCD43/AD19
30
PTF6/LCD42/AD18
AD6
PTE3/MOSI3/MISO3
PTB5/RGPIO13/SDA/PRACMP2P3
29
59
DADM2
60
17
28
16
PTF5/LCD41/AD17
DADP2
PTF4/LCD40/AD16
27
PTE4/MISO3/MOSI3
26
61
AD5
PTE5/SCLK3
15
DADM1
62
Figure 3. 100-Pin LQFP Pinout
Table 4 shows the package pin assignments.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
12
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51EM256 Series Configurations
Table 4. MCF51EM256 Series Package Pin Assignments
100
LQFP
80
LQFP
Default Function
1
—
LCD25
2
—
LCD26
3
1
4
ALT1
ALT2
ALT3
PTD0
LCD27
KBI2P0
2
PTD1
LCD28
KBI2P1
5
3
PTD2
LCD29
KBI2P2
6
4
PTD3
LCD30
KBI2P3
7
5
PTD4
LCD31
KBI2P4
TMRCLK1
8
6
PTD5
LCD32
KBI2P5
TMRCLK2
9
7
PTD6
LCD33
KBI2P6
10
8
PTD7
LCD34
KBI2P7
11
9
LCD35
CLKOUT
12
10
PTF0
LCD36
13
11
PTF1
LCD37
EXTRIG
14
12
PTF2
LCD38
RX3
15
13
PTF3
LCD39
TX3
16
14
PTF4
LCD40
AD16
17
15
PTF5
LCD41
AD17
18
16
PTF6
LCD42
AD18
19
17
PTF7
LCD43
AD19
20
18
VDDA
21
19
VREFH
22
—
DADP0
23
—
DADM0
24
—
AD4
25
20
DADP1
26
21
DADM1
27
22
AD5
28
23
DADP2
29
24
DADM2
30
25
AD6
31
—
DADP3
32
—
DADM3
Comment
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
13
MCF51EM256 Series Configurations
Table 4. MCF51EM256 Series Package Pin Assignments (continued)
100
LQFP
80
LQFP
Default Function
33
—
AD7
34
26
VREFO
35
27
VREFL
36
28
VSSA
37
29
EXTAL1
38
30
XTAL1
39
31
VBAT
40
32
TAMPER
41
33
PTA0/RGPIO0
42
—
PTE0
PRACMP1O
AD8
43
—
PTE1
PRACMP1P3
AD9
44
34
PTA1/RGPIO1
MOSI1
45
35
PTA2/RGPIO2
MISO1
46
36
PTA3/RGPIO3
SCLK1
47
37
PTA4/RGPIO4
SS1
48
38
PTA5/RGPIO5
TPMCH0
AD11
49
39
PTA6/RGPIO6
TPMCH1
AD12
50
40
PTA7/RGPIO7
TPMCLK
51
—
PTE2
52
41
PTB0/RGPIO8
ALT1
ALT2
IRQ
CLKOUT
ALT3
Comment
AD10
PRACMP1P2
RGPIO_ENB is used to select
between standard GPIO and
RGPIO
AD13
PRACMP1P1
KBI1P0
PRACMP2P0
RX2
RGPIO_ENB is used to select
between standard GPIO and
RGPIO
KBI1P1
SS3
TX2
2X Drive Output
RGPIO_ENB is used to select
between standard GPIO and
RGPIO
PTB2/RGPIO10
KBI1P2
PRACMP1P0
RX1
RGPIO_ENB is used to select
between standard GPIO and
RGPIO
PTB3/RGPIO11
KBI1P3
PRACMP2P1
TX1
2X drive output RGPIO_ENB is
used to select between standard
GPIO and RGPIO
53
42
PTB1/RGPIO9
54
43
VDD
55
44
VSS
56
45
57
46
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
14
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
MCF51EM256 Series Configurations
Table 4. MCF51EM256 Series Package Pin Assignments (continued)
100
LQFP
80
LQFP
Default Function
ALT1
ALT2
58
47
PTB4/RGPIO12
SCL
PRACMP2P2
59
48
PTB5/RGPIO13
SDA
PRACMP2P3
60
—
PTE3
MOSI3
MISO3
61
—
PTE4
MISO3
MOSI3
62
—
PTE5
SCLK3
63
—
PTE6
SS3
TX2
64
49
PTB6/RGPIO14
KBI1P4
TMRCLK1
AD14
65
50
PTB7/RGPIO15
KBI1P5
TMRCLK2
AD15
66
51
RESET
67
52
PTC0
KBI1P6
EXTAL2
RX3
68
53
PTC1
KBI1P7
XTAL2
TX3
69
54
BKGD/MS
PTC2
701
551
PTC3
LCD0
PRACMP1O
711
561
PTC4
LCD1
PRACMP2O
721
571
PTC5
LCD2
PRACMP1P4
731
581
PTC6
LCD3
PRACMP2P4
741
591
PTC7
LCD4
751
601
PTE7
LCD5
761
611
LCD6
MOSI2
771
621
LCD7
MISO2
781
631
LCD8
SCLK2
791
641
LCD9
SS2
80
65
LCD10
81
66
LCD11
82
67
LCD12
83
68
LCD13
84
69
LCD14
85
70
LCD15
86
—
LCD16
ALT3
Comment
RGPIO_ENB is used to select
between standard GPIO and
RGPIO
Open Drain
Open Drain
Open Drain
RGPIO_ENB is used to select
between standard GPIO and
RGPIO
This pin is an open drain device
and has an internal pullup. There is
no clamp diode to VDD.
This pin has an internal pullup.
PTC2 can only be programmed as
an output.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
15
Electrical Characteristics
Table 4. MCF51EM256 Series Package Pin Assignments (continued)
1
100
LQFP
80
LQFP
Default Function
87
—
LCD17
88
—
LCD18
89
—
LCD19
90
—
LCD20
91
71
LCD21
92
72
LCD22
93
73
LCD23
94
74
LCD24
95
75
VSS
96
76
VLL3
97
77
VLL2
98
78
VLL1
99
79
VCAP2
100
80
VCAP1
ALT1
ALT2
ALT3
Comment
These pins that are shared with the LCD are open-drain by default if not used as LCD pins. To configure this pins as full
complementary drive outputs, you must have the LCD modules bits configured as follow: FCDEN =1, VSUPPLY = 11 and RVEN
= 0. The Input levels and internal pullup resistors are referenced to VLL3. Referer to the LCD chapter for further information.
2
Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the
MCF51EM256/128 series microcontrollers, including detailed information on power considerations,
DC/AC electrical characteristics, and AC timing specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. These
specifications will, however, be met for production silicon. Finalized specifications will be published after
complete characterization and device qualifications have been completed.
NOTE
The parameters specified in this data sheet supersede any values found in
the module specifications.
2.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the
customer a better understanding the following classification is used and the parameters are tagged
accordingly in the tables where appropriate:
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
16
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 5. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter
tables where appropriate.
2.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the limits specified in Table 6 may affect device reliability or cause permanent
damage to the device. For functional operating conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD).
Table 6. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to 4.0
V
Input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins except PTB1
and PTB3)1, 2, 3
ID
±25
mA
Instantaneous maximum current
Single pin limit (applies to PTB1 and PTB3)4, 5, 6
ID
±50
mA
Maximum current into VDD
IDD
120
mA
Tstg
–55 to 150
°C
Storage temperature
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
17
Electrical Characteristics
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
4
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
5
All functional non-supply pins are internally clamped to VSS and VDD.
6
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
2.3
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package
thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in
on-chip logic and it is user-determined rather than being controlled by the MCU design. In order to take
PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or
VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy
loads), the difference between pin voltage and VSS or VDD will be very small.
Table 7. Thermal Characteristics
Rating
Operating temperature range (packaged)
Maximum junction temperature
Symbol
Value
Unit
TA
–40 to 85
°C
TJM
95
°C
θJA
54
42
°C/W
Thermal resistance 1,2,3,4
100-pin LQFP
1s
2s2p
80-pin LQFP
1s
2s2p
55
42
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance.
2 Junction to Ambient Natural Convection
3
1s — Single layer board, one signal layer
4 2s2p — Four layers board, two signal and two power layers
The average chip-junction temperature (TJ) in °C can be obtained from:
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
18
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ
(if PI/O is neglected) is:
PD = K ÷ (TJ + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of TA.
2.4
Electrostatic Discharge (ESD) Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS
circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification
tests are performed to ensure that these devices can withstand exposure to reasonable levels of static
without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade
Integrated Circuits. (http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the
device specification requirements. Complete dc parametric and functional testing is performed per the
applicable device specification at room temperature followed by hot temperature, unless specified
otherwise in the device specification.
Table 8. ESD and Latch-up Test Conditions
Model
Human Body
Machine
Latch-up
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ω
Storage Capacitance
C
100
pF
Number of Pulse per pin
—
3
Series Resistance
R1
0
Ω
Storage Capacitance
C
200
pF
Number of Pulse per pin
—
3
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
19
Electrical Characteristics
Table 9. ESD and Latch-Up Protection Characteristics
Num
2.5
Rating
Symbol
Min
Max
Unit
1
Human Body Model (HBM)
VHBM
±2000
—
V
2
Machine Model (MM)
VMM
±200
—
V
3
Charge Device Model (CDM)
VCDM
±500
—
V
4
Latch-up Current at TA = 85 °C
ILAT
±100
—
mA
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power
supply current in various operating modes.
Table 10. DC Characteristics
Num C
Symbol
Min
Typical1
Max
Digital supply — 50 MHz operation
VDD
2.5
—
3.6
Digital supply2 — 20 MHz maximum
operation
VDD
1.8
—
2.5
1.8
—
3.6
Parameter
Operating
voltage
Unit
1
P
2
P Analog supply
VDDA
3
D Battery supply
VBAT
2.2
3
3.3
V
4
P Bandgap voltage reference3
VBG
1.15
1.17
1.18
V
VOH
VDD – 0.5
—
—
V
VOH
VDD – 0.5
—
—
V
IOHT
—
—
100
mA
6
7
P
Output high
voltage
PTA[7:0], PTB[7:0], PTC[2:0], PTE[6:0],
high-drive strength.
VDD ≥ 2.7 V, ILoad = –10 mA
C
PTA[7:0], PTB[7:0], PTC[2:0], PTE[6:0],
high-drive strength.
VDD ≥ 1.8 V, ILoad = –3 mA
C
PTC[7:3], PTD[7:0], PTE7, PTF[7:0],
LCD35/CLKOUT, MOSI2, MISO2,
SCK2, SS2, low drive strength.
VDD ≥ 1.8 V, ILoad = –0.5 mA
Output high
P
voltage
PTC[7:3], PTD[7:0], PTE7, PTF[7:0],
LCD35/CLKOUT, MOSI2, MISO2,
SCK2, SS2, high-drive strength.
VDD ≥ 2.7 V, ILoad = –3 mA
C
PTC[7:3], PTD[7:0], PTE7, PTF[7:0],
LCD35/CLKOUT, MOSI2, MISO2,
SCK2, SS2, high-drive strength.
VDD ≥ 1.8 V, ILoad = –1 mA
D
V
PTA[7:0], PTB[7:0], PTC[2:0], PTE[6:0],
low-drive strength.
VDD ≥ 1.8 V, ILoad = –0.6 mA
C
5
V
Output high
current
Max total IOH for all ports
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
20
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 10. DC Characteristics (continued)
Symbol
Min
Typical1
Max
Unit
VOL
—
—
0.50
V
VOL
—
—
0.50
V
IOLT
—
—
100
mA
0.70 × VDD
—
—
0.85 × VDD
—
—
Tamper_in
1.5
—
—
All digital inputs except tamper_in,
VDD > 2.7 V
—
—
0.35 × VDD
—
—
0.3 × VDD
—
—
0.5
0.06 × VDD
—
—
Num C
Parameter
PTA[7:0], PTB[7:0], PTC[2:0], PTE[6:0],
low-drive strength.
VDD ≥ 1.8 V, ILoad = 2 mA
C
8
9
10
11
12
P
Output low
voltage
PTA[7:0], PTB[7:0], PTC[2:0], PTE[6:0],
high-drive strength.
VDD ≥ 2.7 V, ILoad = 10 mA
C
PTA[7:0], PTB[7:0], PTC[2:0], PTE[6:0],
high-drive strength.
VDD ≥ 1.8 V, ILoad = 3 mA
C
PTC[7:3], PTD[7:0], PTE7, PTF[7:0],
LCD35/CLKOUT, MOSI2, MISO2,
SCK2, SS2, low drive strength.
VDD ≥ 1.8 V, ILoad = 0.5 mA
Output low
P
voltage
PTC[7:3], PTD[7:0], PTE7, PTF[7:0],
LCD35/CLKOUT, MOSI2, MISO2,
SCK2, SS2, high-drive strength.
VDD ≥ 2.7 V, ILoad = 3 mA
C
PTC[7:3], PTD[7:0], PTE7, PTF[7:0],
LCD35/CLKOUT, MOSI2, MISO2,
SCK2, SS2, high-drive strength.
VDD ≥ 1.8 V, ILoad = 1 mA
D
P
Output low
current
Input high
voltage
Input low
P
voltage
Max total IOL for all ports
All digital inputs except tamper_in,
VDD > 2.7 V
All digital inputs except tamper_in,
2.7 V > VDD ≥ 1.8 V
all digital inputs except tamper_in,
2.7 V > VDD ≥ 1.8 V
VIH
VIL
Tamper_in
13
C Input hysteresis; all digital inputs
Vhys
V
V
mV
14
P Input leakage current; input only pins
|IIn|
—
0.1
1
μA
15
P High Impedance (off-state) leakage current4
|IOZ|
—
0.1
1
μA
16
P Internal pullup resistors5
RPU
17.5
—
52.5
kΩ
RPD
17.5
—
52.5
kΩ
4
6
17
P Internal pulldown resistors
18
C Input capacitance; all non-supply pins
CIn
—
—
8
pF
19
P POR rearm voltage
VPOR
0.9
1.4
2.0
V
20
D POR rearm time
tPOR
10
—
—
μs
Low-voltage
P detection
threshold
2.300
2.355
2.410
21
2.370
2.425
2.480
High range — VDD falling
High range — VDD rising
VLVDH
V
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
21
Electrical Characteristics
Table 10. DC Characteristics (continued)
Num C
Parameter
22
Low-voltage
C detection
threshold
Low-voltage
P warning
threshold
VDD falling, LVWV = 1
23
24
C
Low-voltage
warning
VDD falling, LVWV = 0
25
D RAM retention voltage
Low range — VDD falling
D
VLVDL
Low range — VDD rising
VLVWH
VDD rising, LVWV = 1
VLVWL
VDD rising, LVWV = 0
VRAM
7 8 9 10
26
Symbol
DC injection current
VIN > VDD, VIN < VSS
Min
Typical1
Max
Unit
1.800
1.845
1.890
V
1.870
1.915
1.960
V
2.590
2.655
2.720
2.580
2.645
2.710
2.300
2.355
2.410
2.360
2.425
2.490
—
0.6
1.0
–0.2
—
0.2
–5
—
5
V
V
V
(single pin limit),
IIC
DC injection current (Total MCU limit, includes sum of all
stressed pins), VIN > VDD, VIN < VSS
mA
mA
Typical values are based on characterization data at 25 °C unless otherwise stated.
Switch to lower frequency when the low-voltage interrupt asserts (VLVDH).
3 Factory trimmed at V
DD = 3.0 V, Temp = 25°C
4 Measured with V = V
In
DD or VSS.
5 Measured with V = V .
In
SS
6 Measured with V = V .
In
DD
7 Power supply must maintain regulation within operating V
DD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or
if clock rate is very low (which would reduce overall power consumption).
8 All functional non-supply pins are internally clamped to V
SS and VDD.
9 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
10 The RESET pin does not have a clamp diode to V . Do not drive this pin above V .
DD
DD
1
2
PullUp Resistor
43
41
25C
40.5
25C
40
-40C
-40C
42
41
40
39
85C
85C
Resistor (kOhm)
44
Resistor (kOhm)
PullDown Resistor
41.5
45
39.5
39
38.5
38
37.5
38
37
1.9
2.2
2.5
2.8
VDD(V)
3.1
3.4
1.9
2.2
2.5
2.8
VDD(V)
3.1
3.4
Figure 4. Pullup and Pulldown Typical Resistor Values
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
22
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Typical VOL vs VDD (IOL = 2mA)
VOL vs IOL (Low Drive)
1.60
0.39
85C
1.40
25C
0.34
1.20
-40C
25C
0.80
-40C
VOL(V)
VOL(V)
85C
1.00
0.60
0.29
0.24
0.40
0.19
0.20
0.00
0.14
0
1
3
5
7
9
IOL(mA)
11
13
15
17
19
1.8
2
2.2
2.4
2.6
2.8
VDD(V)
3
3.2
3.4
3.6
Figure 5. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0)
Typical VOL vs VDD
VOL vs IOL (High Drive)
1.00
0.8
0.90
0.7
0.6
0.70
85C
0.60
25C
0.50
-40C
0.40
-40 oC
0.5
VOL(V)
VOL(V)
85oC
25oC
0.80
0.4
IOL = 10mA
0.3
0.30
0.20
0.2
0.10
0.1
IOL = 6mA
IOL = 3mA
0.00
0
1
3
5
7
9
IOL(mA)
11
13
15
17
0.0
19
1.8
2
2.2
2.4
2.6
2.8
VDD(V)
3
3.2
3.4
3.6
Figure 6. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1)
Typical VDD - VOH vs VDD (IOH = -2mA)
VOH vs IOH (Low Drive)
1.80
0.84
1.60
0.74
85C
VOH(V)
1.20
25C
1.00
-40C
0.80
0.60
VDD - VOH(V)
1.40
85C
25C
-40C
0.64
0.54
0.44
0.34
0.40
0.24
0.20
0.14
0.00
0
-2
-4
-6
-8
-10
IOH(mA)
-12
-14
-16
-18
-20
1.8
2
2.2
2.4
2.6
2.8
VDD(V)
3
3.2
3.4
3.6
Figure 7. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0)
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
23
Electrical Characteristics
Typical VDD - VOH vs VDD
VOH vs IOH (High Drive)
1.0
1.40
0.9
85oC
0.8
1.00
Hot
0.80
Room
25oC
-40 oC
0.7
Cold
0.60
VDD - VOH(V)
VOH(V)
1.20
0.40
0.6
IOH = -10mA
0.5
0.4
0.3
IOH = -6mA
0.2
0.20
0.1
0.00
0
-2
-4
-6
-8
-10
-12
IOH(mA)
-14
-16
-18
IOH = -3mA
0.0
-20
1.8
2
2.2
2.4
2.6
2.8
VDD(V)
3
3.2
3.4
3.6
Figure 8. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1)
2.6
Supply Current Characteristics
90
80
IDD (mA)
70
FEI Off - Hot
FEI Off - Cold
FEI On - Room
FEI On
60
FEI Off - Room
FEI On - Hot
FEI On - Cold
50
FEI Off
40
30
1.8
2.1
2.4
2.7
VDD (V)
3.0
3.3
3.6
Figure 9. Typical Run IDD for FBE and FEI, IDD vs. VDD
(All Modules Enabled)
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
24
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 11. Supply Current Characteristics
Num
C
Parameter
P
1
2
T
T
Symbol
25.165 MHz
Run supply current
FEI mode, all
modules on
20 MHz
8 MHz
7
8
10
55.3
—
23.9
—
C
25.165 MHz
55.1
56
46.6
—
19.9
—
1 MHz
3.92
—
16 kHz FBILP
239
—
T
T
T
T
T
T
T
P
C
P
C
9
82
—
T
6
66.2
4.56
C
5
3
Max2
1 MHz
T
4
RIDD
Typical1
T
Run supply current
FEI mode, all
modules off
20 MHz
8 MHz
T
3
VDD (V)
T
T
Run supply current
LPS=0, all modules
off
16 kHz
FBELP
Run supply current
LPS = 1, all
modules off,
running from flash
Wait mode supply
current
FEI mode, all
modules off
16 kHz
FBELP
RIDD
3
RIDD
3
RIDD
3
25.165 MHz
20 MHz
8 MHz
WIDD
3
1
Wait mode supply current
LPRS = 1, all mods off
WIDD
3
Stop2 mode supply current
S2IDD
3
Stop3 mode supply current
S3IDD
LVD adder to stop3, stop2 (LVDE =
LVDSE = 1)
Voltage reference
adder to stop3
11
T
PRACMP adder to
stop3
12
T
13
14
2
S3IDDLVD
3
2
3
Low power
mode
Tight
regulation
mode
PRG disabled
Temp
(°C)
mA
–40 to
85°C
mA
–40 to
85°C
μA
–40 to
85°C
μA
–40 to
85°C
mA
–40 to
85°C
249
—
50
—
51.1
69
42.6
—
18.8
—
3.69
—
1
—
μA
–40 to
85°C
27
μA
–40 to
85°C
μA
–40 to
85°C
—
μA
–40 to
85°C
—
μA
–40 to
85°C
—
μA
–40 to
85°C
—
μA
–40 to
85°C
μA
–40 to
85°C
μA
–40 to
85°C
0.576
1.05
120
16
42
27
90
S3IDDLVD
3
270
13
S3IDDLVD
3
LCD adder to stop3, stop2
S3IDDLVD
3
TBD
C
Adder to stop3 for oscillator enabled3
(ERCLKEN =1 and EREFSTEN = 1)
S3IDDOSC
3
5
P
IRTC supply current4,5,6
PRG enabled
Unit
IDD-BAT
29
1.5
5
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
25
Electrical Characteristics
1
2
3
4
5
6
Typicals are measured at 25 °C.
Values given here are preliminary estimates prior to completing characterization.
Values given under the following conditions: low range operation (RANGE = 0), low power mode (HGO = 0).
This is the current consumed when the IRTC is being powered by the VBAT.
The IRTC power source depends on the MCU configuration and VDD voltage level. Refer to reference manual for further
information.
The IRTC current consumption includes the IRTC XOSC1.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
26
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
2.7
Analog Comparator (PRACMP) Electricals
Table 12. PRACMP Electrical Specifications
N
C
Symbol
Min
Typical
Max
Unit
1
—
Supply voltage
VPWR
1.8
—
3.6
V
2
C
Supply current (active) (PRG enabled)
IDDACT1
—
—
60
μA
3
C
Supply current (active) (PRG disabled)
IDDACT2
—
—
40
μA
4
D
Supply current (ACMP and PRG all
disabled)
IDDDIS
—
—
2
nA
5
—
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
6
T
Analog input offset voltage
VAIO
—
5
40
mV
7
T
Analog comparator hysteresis
VH
3.0
—
20.0
mV
8
D
Analog input leakage current
IALKG
—
—
1
nA
9
T
Analog comparator initialization delay
tAINIT
—
—
1.0
μs
10
—
Programmable reference generator input1
VIn1(VDD)
—
VDD
—
V
11
T
Programmable reference generator input2
VIn2(VDD25)
1.8
—
2.75
V
12
D
Programmable reference generator setup
delay
tPRGST
—
1
—
μs
13
D
Programmable reference generator step
size
Vstep
–0.25
0
0.25
LSB
14
P
Programmable reference generator voltage
range
Vprgout
VIn/32
—
Vin
V
2.8
Characteristic
ADC Characteristics
These specs all assume seperate VDDAD supply for ADC and isolated pad segment for ADC supplies and
differential inputs. Spec’s should be de-rated for VREFH = Vbg condition.
Table 13. 16-bit ADC Operating Conditions
Num
Charact
eristic
1
Conditions
Absolute
Supply
voltage
Delta to VDD (VDD–VDDA)2
3
Ground
voltage
Delta to VSS (VSS–VSSA)2
4
Ref
Voltage
High
2
Symb
Min
Typ1
Max
Unit
VDDA
1.8
—
3.6
V
ΔVDDA
–100
0
100
mV
ΔVSSA
–100
0
100
mV
VREFH
1.15
VDDA
VDDA
V
Comment
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
27
Electrical Characteristics
Table 13. 16-bit ADC Operating Conditions
Num
Charact
eristic
5
Symb
Min
Typ1
Max
Unit
Ref
Voltage
Low
VREFL
VSSA
VSSA
VSSA
V
6
Input
Voltage
VADIN
VREFL
—
VREFH
V
7
Input
Capacit
ance
CADIN
—
8
4
10
5
pF
8
Input
Resista
nce
RADIN
—
2
5
kΩ
9
16 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
0.5
1
2
10
13/12 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
1
2
5
Analog
Source
Resista
nce
Conditions
16-bit modes
8/10/12-bit modes
RAS
11
11/10 bit modes
fADCK > 8MHz
4MHz < fADCK < 8MHz
fADCK < 4MHz
—
—
—
—
—
—
2
5
10
12
9/8 bit modes
fADCK > 8MHz
fADCK < 8MHz
—
—
—
—
5
10
1.0
—
8
1.0
—
5
1.0
—
2.5
13
14
15
ADC
Convers
ion
Clock
Freq.
ADLPC = 0, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 1, ADHSC = 0
fADCK
Comment
External to MCU
kΩ
Assumes
ADLSMP=0
MHz
Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2 DC potential difference.
1
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
28
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ADC SAR
ENGINE
RADIN
+
VADIN
VAS
CAS
+
–
–
RADIN
INPUT PIN
For Differential Mode, this figure
applies to both inputs
RADIN
INPUT PIN
RADIN
INPUT PIN
CADIN
Figure 10. ADC Input Impedance Equivalency Diagram
Table 14. 16-bit ADC Characteristics full operating range(VREFH = VDDAD > 1.8, VREFL = VSSAD, FADCK < 8MHz)
Conditions1
Characteristic
Supply Current
C
Symb
ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
T
IDDA
ADLPC=0, ADHSC=1
Supply Current
Stop, Reset, Module Off
ADC
Asynchronous
Clock Source
ADLPC = 1, ADHSC = 0
ADLPC = 0, ADHSC = 0
C
P
IDDA
fADACK
ADLPC = 0, ADHSC = 1
Sample Time
See reference manual for sample times
Conversion
Time
See reference manual for conversion times
Min
Typ2
Max
—
215
—
—
470
—
—
610
—
—
0.01
—
—
2.4
—
—
5.2
—
—
6.2
—
Unit
Comment
μA
ADLSMP = 0
ADCO = 1
μA
MHz
tADACK =
1/fADACK
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
29
Electrical Characteristics
Table 14. 16-bit ADC Characteristics full operating range(VREFH = VDDAD > 1.8, VREFL = VSSAD, FADCK < 8MHz)
Characteristic
Total
Unadjusted
Error
Differential
Non-Linearity
Integral
Non-Linearity
Zero-Scale
Error
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
TUE
—
—
±16
±20
+48/-40
+56/-28
LSB3
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.5
±1.75
±3.0
±3.5
32x
Hardware
Averaging
(AVGE = %1
AVGS = %11)
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.7
±0.8
±1.5
±1.5
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.5
±0.5
±1.0
±1.0
16-bit differential mode
16-bit single-ended mode
T
—
—
±2.5
±2.5
+5/-3
+5/-3
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±1
±1
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.5
±0.5
±0.75
±0.75
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
±6.0
±10.0
±16.0
±20.0
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.0
±1.0
±2.5
±2.5
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.5
±0.5
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.3
±0.3
±0.5
±0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
±4.0
±4.0
+32/-24
+24/-16
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±2.5
±2.0
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
DNL
INL
EZS
LSB2
LSB2
LSB2
VADIN = VSSAD
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
30
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 14. 16-bit ADC Characteristics full operating range(VREFH = VDDAD > 1.8, VREFL = VSSAD, FADCK < 8MHz)
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
EFS
—
—
+10/0
+14/0
+42/-2
+46/-2
LSB2
VADIN = VDDAD
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.0
±1.0
±3.5
±3.5
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.4
±0.4
±1.5
±1.5
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
Quantization
Error
16 bit modes
D
—
-1 to 0
—
—
—
±0.5
Effective
Number of Bits
16 bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
C
12.8
12.7
12.6
12.5
11.9
14.2
13.8
13.6
13.3
12.5
—
—
—
—
—
16 bit single-ended mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
D
—
—
—
—
—
13.2
12.8
12.6
12.3
11.5
—
—
—
—
—
Characteristic
Full-Scale
Error
EQ
<13 bit modes
ENOB
Signal to Noise
plus Distortion
See ENOB
Total Harmonic
Distortion
16-bit differential mode
Avg = 32
C
16-bit single-ended mode
Avg = 32
D
16-bit differential mode
Avg = 32
C
16-bit single-ended mode
Avg = 32
D
Input Leakage
Error
all modes
D
EIL
Temp Sensor
Slope
-40°C– 25°C
C
m
Temp Sensor
Voltage
25°C
Spurious Free
Dynamic
Range
SINAD
Bits
SINAD = 6.02 ⋅ ENOB + 1.76
—
-91.5
-74.3
—
-85.5
—
75.0
92.2
—
—
86.2
—
SFDR
VTEMP25
IIn * RAS
—
1.646
—
—
1.769
—
—
701.2
—
Fin =
Fsample/100
dB
THD
25°C– 125°C
C
LSB2
dB
Fin =
Fsample/100
dB
Fin =
Fsample/100
mV
IIn = leakage
current
(refer to DC
characteristics)
mV/°C
mV
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
31
Electrical Characteristics
1
All accuracy numbers assume the ADC is calibrated with VREFH = VDDAD
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
3
1 LSB = (VREFH – VREFL)/2N
2
Table 15. 16-bit ADC Characteristics(VREFH = VDDAD > 2.7V, VREFL = VSSAD, FADCK < 4MHz, ADHSC=1)
Characteristic
Total
Unadjusted
Error
Differential
Non-Linearity
Integral
Non-Linearity
Zero-Scale
Error
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
TUE
—
—
±16
±20
+24/-24
+32/-20
LSB3
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.5
±1.75
±2.0
±2.5
32x
Hardware
Averaging
(AVGE = %1
AVGS = %11)
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.7
±0.8
±1.0
±1.25
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.5
±0.5
±1.0
±1.0
16-bit differential mode
16-bit single-ended mode
T
—
—
±2.5
±2.5
±3
±3
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±1
±1
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.5
±0.5
±0.75
±0.75
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
±6.0
±10.0
±12.0
±16.0
13-bit differential mode
12-bit single-ended mode
T
—
—
±1.0
±1.0
±2.0
±2.0
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.5
±0.5
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.3
±0.3
±0.5
±0.5
16-bit differential mode
16-bit single-ended mode
T
—
—
±4.0
±4.0
+16/0
+16/-8
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±2.0
±2.0
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
DNL
INL
EZS
LSB2
LSB2
LSB2
VADIN = VSSAD
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
32
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 15. 16-bit ADC Characteristics(VREFH = VDDAD > 2.7V, VREFL = VSSAD, FADCK < 4MHz, ADHSC=1)
Conditions1
C
Symb
Min
Typ2
Max
Unit
Comment
16-bit differential mode
16-bit single-ended mode
T
EFS
—
—
+8/0
+12/0
+24/0
+24/0
LSB2
VADIN = VDDAD
13-bit differential mode
12-bit single-ended mode
T
—
—
±0.7
±0.7
±2.0
±2.5
11-bit differential mode
10-bit single-ended mode
T
—
—
±0.4
±0.4
±1.0
±1.0
9-bit differential mode
8-bit single-ended mode
T
—
—
±0.2
±0.2
±0.5
±0.5
16 bit modes
D
—
-1 to 0
—
—
—
±0.5
14.3
13.8
13.4
13.1
12.4
14.5
14.0
13.7
13.4
12.6
—
—
—
—
—
TBD
TBD
TBD
TBD
TBD
13.5
13.0
12.7
12.4
11.6
—
—
—
—
—
Characteristic
Full-Scale
Error
Quantization
Error
Effective
Number of Bits
EQ
<13 bit modes
16 bit differential mode
Avg = 32
Avg = 16
Avg = 8
Avg = 4
Avg = 1
C
ENOB
16 bit single-ended mode
Avg = 32
Avg = 16
Avg = 8
Avg = 4
Avg = 1
Signal to Noise
plus Distortion
See ENOB
Total Harmonic
Distortion
16-bit differential mode
Avg = 32
C
16-bit single-ended mode
Avg = 32
D
16-bit differential mode
Avg = 32
C
16-bit single-ended mode
Avg = 32
D
Input Leakage
Error
all modes
D
EIL
Temp Sensor
Slope
–40°C–25°C
D
m
Temp Sensor
Voltage
25°C
Spurious Free
Dynamic
Range
SINAD
D
Bits
SINAD = 6.02 ⋅ ENOB + 1.76
THD
—
-95.8
-90.4
—
—
—
91.0
96.5
—
—
—
—
SFDR
25°C–125°C
VTEMP25
LSB2
IIn * RAS
—
1.646
—
—
1.769
—
—
701.2
—
Fin =
Fsample/100
dB
dB
Fin =
Fsample/100
dB
Fin =
Fsample/100
mV
IIn = leakage
current
(refer to DC
characteristics)
mV/°C
mV
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
33
Electrical Characteristics
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=2.0MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
3
1 LSB = (VREFH–VREFL)/2N
2
2.9
External Oscillator (XOSC) Characteristics
Reference Figure 11 and Figure 12 for crystal or resonator circuits. XOSC1 operates only in low power
low range mode. XOSC2 operates in all the power and range modes.
Table 16. XOSC Specifications (Temperature Range = –40 to 85 °C Ambient)
Num
C
Characteristic
1
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
C
High range (RANGE = 1), high gain (HGO = 1)
High range (RANGE = 1), low power (HGO = 0)
2
D
Symbol
Min
Typ1
Max
Unit
flo
fhi
fhi
32
1
1
—
—
—
38.4
16
8
kHz
MHz
MHz
Load capacitors
Low range (RANGE=0), low power (HGO = 0)
Other oscillator settings
See Note2
See Note3
C1,C2
Feedback resistor
3
4
D
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range (RANGE = 1, HGO = X)
Series resistor —
Low range, low power (RANGE = 0, HGO = 0)2
Low range, high gain (RANGE = 0, HGO = 1)
High range, low power (RANGE = 1, HGO = 0)
D
High range, high gain (RANGE = 1, HGO = 1)
RF
RS
≥ 8 MHz
4 MHz
1 MHz
—
—
—
—
10
1
—
—
—
—
—
—
—
0
100
—
—
—
—
—
—
0
0
0
0
10
20
—
—
—
—
600
400
5
15
—
—
—
—
ms
0.03125
0
—
—
50.33
50.33
MHz
MHz
MΩ
kΩ
Crystal start-up time 4
5
6
T
D
Low range, low power
Low range, high power
High range, low power
High range, high power
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
FEE mode
FBE or FBELP mode
t
CSTL
t
CSTH
fextal
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO = 0.
3
See crystal or resonator manufacturer’s recommendation.
4 Proper PC board layout procedures must be followed to achieve specifications.
1
2
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
34
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
XOSC
EXTAL
XTAL
RF
RS
Crystal or Resonator
C1
C2
Figure 11. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
XOSC
EXTAL
XTAL
Crystal or Resonator
Figure 12. Typical Crystal or Resonator Circuit: Low Range/Low Gain
2.10
Internal Clock Source (ICS) Characteristics
Table 17. ICS Frequency Specifications (Temperature Range = –40 to 85 °C Ambient)
Symbol
Min
Typical1
Max
Unit
Average internal reference frequency — factory trimmed
at VDD = 3.6 V and temperature = 25 °C
fint_ft
—
32.768
—
kHz
P
Internal reference frequency — user trimmed
fint_ut
31.25
—
39.06
kHz
T
Internal reference start-up time
tIRST
—
60
100
μs
16
—
20
32
—
40
Num
C
1
P
2
3
Characteristic
P
4
5
Low range (DRS = 00)
DCO output frequency range
C
— trimmed2
P
High range (DRS = 10)
48
—
60
P
Low range (DRS = 00)
—
19.92
—
—
39.85
—
—
59.77
—
P
P
DCO output frequency2
Reference = 32768 Hz
and DMX32 = 1
Mid range (DRS = 01)
Mid range (DRS = 01)
fdco_u
fdco_DMX32
High range (DRS = 10)
MHz
MHz
6
C
Resolution of trimmed DCO output frequency at fixed voltage
and temperature (using FTRIM)
Δfdco_res_t
—
±0.1
±0.2
%fdco
7
C
Resolution of trimmed DCO output frequency at fixed voltage
and temperature (not using FTRIM)
Δfdco_res_t
—
±0.2
±0.4
%fdco
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
35
Electrical Characteristics
Table 17. ICS Frequency Specifications (Temperature Range = –40 to 85 °C Ambient) (continued)
Symbol
Min
Typical1
Max
Unit
Total deviation of trimmed DCO output frequency over voltage
and temperature
Δfdco_t
—
0.5
–1.0
±2
%fdco
Total deviation of trimmed DCO output frequency over fixed
voltage and temperature range of 0 °C to 70 °C
Δfdco_t
—
±0.5
±1
%fdco
tAcquire
—
—
1
ms
CJitter
—
0.02
0.2
%fdco
Num
C
Characteristic
8
C
9
C
10
C FLL acquisition time 3
11
C
Long term jitter of DCO output clock (averaged over 2 ms
interval)4
Data in Typical column was characterized at 3.0 V, 25 °C or is typical recommended value.
The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device.
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Bus.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
1
2
60
Freq (Mhz)
50
40
HR
30
MR
LR
20
10
0
-40
-30
-20
-10
0
10
25
35
45
55
65
75
85
95
Temp (C)
Figure 13. Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 3.0 V)
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
36
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
60
HR
Freq (Mhz)
50
MR
40
LR
30
20
10
0
2.00 V
2.25 V
2.50 V
2.75 V
3.00 V
3.25 V
3.50 V
3.75 V
4.00 V
Vdd (V)
Figure 14. Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 25 °C)
o
2.11
LCD Specifications
Table 18. LCD Electricals, 3 V Glass
N
C
1
D
2
D
LCD charge pump capacitance
3
D
LCD bypass capacitance
4
D
LCD glass capacitance
5
Characteristic
LCD frame frequency
VIREG
7
D
VIREG trim resolution
8
D
VIREG ripple
9
D
VIREG current adder
10
D
Min
Typical
Max
Unit
fFrame
28
30
58
Hz
CLCD
100
100
nF
CBYLCD
100
100
nF
pF
Cglass
HRefSel = 0
D
6
Symbol
HRefSel = 1
VIREG
ΔRTRIM
HRefSel = 0
VLCD buffered adder
RVEN = 1
8000
1.00
1.15
1.49
1.67
1.851
V
%
VIREG
1.5
0.1
—
HRefSel = 1
3
2000
.89
0.15
V
IVIREG
—
12
μA
IBuff
—
1
μA
1
VIREG Max can not exceed VDD – 0.15 V
2000 pF Load LCD, frame frequency = 32 Hz
3 VSUPPLY = 10, BYPASS = 0
2
2.12
AC Characteristics
This section describes AC timing characteristics for each peripheral system.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
37
Electrical Characteristics
2.12.1
Control Timing
Table 19. Control Timing
Num
C
1
D
2
D
Symbol
Min
Typical1
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
DC
—
25.165
MHz
Internal low-power oscillator period
tLPO
700
1300
μs
textrst
100
—
ns
Parameter
2
3
D
External reset pulse width
(tcyc = 1/fSelf_reset)
4
D
Reset low drive
trstdrv
66 × tcyc
—
ns
5
D
Active background debug mode latch setup time
tMSSU
500
—
ns
6
D
Active background debug mode latch hold time
tMSH
100
—
ns
7
D
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 × tcyc
—
—
ns
8
D
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 × tcyc
—
—
ns
D
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0), low drive
Slew rate control enabled (PTxSE = 1), low drive
Slew rate control disabled (PTxSE = 0), low drive
Slew rate control enabled (PTxSE = 1), low drive
tRise, tFall
—
—
11
35
40
75
IRQ pulse width
KBIPx pulse width
9
ns
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may
not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 105 °C.
1
2
textrst
RESET PIN
Figure 15. Reset Timing
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
38
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 16. IRQ/KBIPx Timing
2.12.2
Timer (TPM/FTM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that
can be used as the optional external source to the timer counter. These synchronizers operate from the
current bus rate clock.
Table 20. TPM Input Timing
No.
C
Function
Symbol
Min
Max
Unit
1
D
External clock frequency
fTCLK
0
fBus/4
Hz
2
D
External clock period
tTCLK
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTCLK
tclkh
TCLK
tclkl
Figure 17. Timer External Clock
tICPW
TPMCHn
TPMCHn
tICPW
Figure 18. Timer Input Capture Pulse
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
39
Electrical Characteristics
2.13
VREF Characteristics
Table 21. VREF Electrical Specifications
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
1
—
Supply voltage
VDDAD
1.80
—
3.60
V
2
—
Operating temperature range
Top
–40
—
105
°C
3
D
Load capability
Iload
—
—
10
mA
4
C
P
Voltage reference output
untrimmed
factory trimmed
VREFO
1.070
1.13
—
1.150
1.202
1.17
V
V
5
D
20
—
100
μV/mA
Load regulation
mode = 10, Iload = 1 mA
Line regulation (power supply
rejection)
6
T
7
T
Bandgap only (mode = 00)
IBG
—
72
—
μA
8
C
Low power mode (mode = 01)
ILP
—
90
125
μA
9
T
Tight regulation mode (mode =10)
ITR
—
0.27
—
mA
2.14
DC
AC
±0.1 from room temp voltage
–60
mV
dB
SPI Characteristics
Table 22 and Figure 19 through Figure 22 describe the timing requirements for the SPI system.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
40
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
Table 22. SPI Electrical Characteristic1,2
Num3
C
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
Characteristic4
Symbol
Min
Max
Unit
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
Master
Slave
tSPSCK
2
4
2048
—
tcyc
Master
Slave
tLead
1/2
—
—
—
tSPSCK
tcyc
Master
Slave
tLag
1/2
—
—
—
tSPSCK
tcyc
tWSPSCK
tcyc – 30
1024 tcyc
—
ns
Master
Slave
tSI
15
15
—
—
ns
Master
Slave
tHI
0
25
—
—
ns
ta
—
1
tcyc
tdis
—
1
tcyc
Master
Slave
tv
—
—
25
25
ns
Master
Slave
tHO
0
0
—
—
ns
Input
Output
tRI
tRO
—
—
tcyc – 25
—25
ns
Input
Output
tFI
tFO
—
—
tcyc – 25
—25
ns
Operating frequency
SPSCK period
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Master
Slave
Data setup time (inputs)
Data hold time (inputs)
9
D
10
D
11
D
12
D
13
D
Slave access time5
Slave MISO disable
time6
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time
Fall time
1
The performance of SPI2 depends on the configuration of power supply of the LCD pins. When the LCD pins
are configured with full complementary drive enabled (FCDEN = 1, VSUPPLY = 11 and RVEN = 0), and VLL3
is driven with external VDD, the SPI2 can operate at the max performance as the above table. When the internal
LCD charge pump is used to power the LCD pins, the SPI2 is configured with open-drain outputs. Its
performance depends on the value of the external pullup resistor implemented, and the max operating
frequency must be limited to 1 MHz.
2 SPI3 has open-drain outputs and its performance depends on the value of the external pullup resistor
implemented.
3
Refer to Figure 19 through Figure 22.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
41
Electrical Characteristics
4
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
5
Time to data active from high-impedance state.
6
Hold time to high-impedance state.
SS1
(OUTPUT)
2
2
SCK
(CPOL = 0)
(OUTPUT)
3
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
11
MOSI
(OUTPUT)
LSB IN
11
MSB OUT2
12
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
2
2
SCK
(CPOL = 0)
(OUTPUT)
3
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN(2)
11
MOSI
(OUTPUT)
BIT 6 . . . 1
LSB IN
12
MSB OUT(2)
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 20. SPI Master Timing (CPHA = 1)
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
42
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
2
SCK
(CPOL = 1)
(INPUT)
5
4
8
MISO
(OUTPUT)
12
11
BIT 6 . . . 1
MSB OUT
SLAVE
SLAVE LSB OUT
SEE
NOTE
7
6
MOSI
(INPUT)
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 21. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
2
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
(INPUT)
5
4
11
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
SLAVE
12
MSB OUT
6
BIT 6 . . . 1
9
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined but normally LSB of character just received
Figure 22. SPI Slave Timing (CPHA = 1)
2.15
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash
memory.
Program and erase operations do not require any special power sources other than the normal VDD supply.
For more detailed information about program/erase operations, see the Memory section of the
MCF51EM256 Series ColdFire Microcontroller Reference Manual.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
43
Electrical Characteristics
Table 23. Flash Characteristics
N
C
1
D
2
Characteristic
Symbol
Min
Supply voltage for program/erase
–40 °C to 85 °C
Vprog/erase
D
Supply voltage for read operation
3
D
Internal FCLK frequency1
4
D
Internal FCLK period (1/fFCLK)
Max
Unit
1.8
3.6
V
VRead
1.8
3.6
V
fFCLK
150
200
kHz
tFcyc
5
6.67
μs
tprog
9
tFcyc
Longword program time (burst mode)2
tBurst
4
tFcyc
P
Page erase time2
tPage
4000
tFcyc
P
2
tMass
20,000
tFcyc
5
P
Longword program time (random location)
6
P
7
8
2
Typical
Mass erase time
current3
9
Longword program
10
Page erase current3
11
C
Program/erase endurance4
TL to TH = –40 °C to 85 °C
T = 25 °C
12
C
Data retention5
RIDDBP
—
9.7
—
mA
RIDDPE
—
7.6
—
mA
10,000
—
—
100,000
—
—
cycles
15
100
—
years
tD_ret
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3
The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with
VDD = 3.0 V, bus frequency = 4.0 MHz.
4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer
to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
2
2.16
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the
MCU resides. Board design and layout, circuit topology choices, location and characteristics of external
components as well as MCU software operation all play a significant role in EMC performance. The
system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263,
AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
2.16.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell
method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed
with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test
software. The radiated emissions from the microcontroller are measured in a TEM cell in two package
orientations (North and East). For more detailed information concerning the evaluation results, conditions
and setup, please refer to the EMC Evaluation Report for this device.
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
44
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanical Outline Drawings
3
Mechanical Outline Drawings
3.1
80-pin LQFP Package
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
45
Mechanical Outline Drawings
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
46
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanical Outline Drawings
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
47
Mechanical Outline Drawings
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
48
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanical Outline Drawings
3.2
100-pin LQFP Package
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
49
Mechanical Outline Drawings
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
50
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
Mechanical Outline Drawings
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
51
Mechanical Outline Drawings
MCF51EM256 Series ColdFire Microcontroller Data Sheet, Rev.2
52
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
4
Revision History
Table 24. Revision History
Revision
Date
Description
1
10/15/2009
Initial public release.
2
4/29/2010
Updated teh descriptions of SPI in the Table 2.
Changed the FSPIx to SPI16 to keep the term in accordance.
Updated Figure 4 to Figure 8.
Updated WIDD, S2IDD, S3IDD in the Table 11.
Updated the ADC characteristics in the Table 13 to Table 15.
Updated description of XOSC in the Section 2.9, “External Oscillator (XOSC)
Characteristics.”
Updated tCSTL in the Table 16.
Updated the the classification of IBG and ITR to T and added Voltage reference output
(factory trimmed) in the Table 21.
Update SPI data in the Table 22.
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Preliminary—Subject to Change Without Notice
MCF51EM256
Rev.2
4/2010