IRF IRS2609DSPBF Half-bridge driver Datasheet

IRS2609DSPbF
June 1, 2011
IRS2609DSPbF
HALF-BRIDGE DRIVER
Features
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•
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•
•
•
•
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•
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Floating channel designed for bootstrap operation
Fully operational to +600 V
Tolerant to negative transient voltage – dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V, 5 V and 15 V input logic compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
High side output in phase with IN input
Internal 530 ns dead-time
Lower di/dt gate driver for better noise immunity
Shut down input turns off both channels
Integrated bootstrap diode
RoHS compliant
Packages
8-Lead SOIC
Product Summary
VOFFSET
IO+/VOUT
ton/off (typ.)
Dead Time
600 V max.
120 mA / 250 mA
10 V – 20 V
750 ns & 200 ns
530 ns
Description
Applications:
The IRS2609D is a high voltage, high speed power
MOSFET and IGBT drivers with dependent high and low
side referenced output channels. Proprietary HVIC and latch
immune CMOS technologies enable ruggedized monolithic
construction. The logic input is compatible with Standard
CMOS or LSTTL output, down to 3.3 V logic. The output
drivers feature a high pulse current buffer stage designed
for minimum driver cross-conduction. The floating channel
can be used to drive an N-channel power MOSFET or IGBT
in the high side configuration which operates up to 600 V.
*Air Conditioner
*Micro/Mini Inverter Drives
*General Purpose Inverters
*Motor Control
Typical Connection
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IRS2609DSPbF
†
Qualification Information
Industrial††
Comments: This IC has passed JEDEC’s
Industrial qualification. IR’s Consumer
qualification level is granted by extension of the
higher Industrial level.
Qualification Level
Moisture Sensitivity Level
Human Body Model
ESD
Machine Model
IC Latch-Up Test
RoHS Compliant
MSL2, 260°C
(per IPC/JEDEC J-STD-020)
Class 2
(per JEDEC standard JESD22-A114)
Class B
(per EIA/JEDEC standard EIA/JESD22-A115)
Class I, Level A
(per JESD78)
Yes
† Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
†† Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information.
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IRS2609DSPbF
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol
VB
Definition
High side floating absolute voltage
Min.
Max.
-0.3
620
Units
VS
High side floating supply offset voltage
VB - 20
VB + 0.3
VHO
High side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low side and logic fixed supply voltage
-0.3
20
VLO
VIN
Low side output voltage
-0.3
COM -0.3
VCC + 0.3
VCC + 0.3
Logic input voltage (IN & SD)
V
COM
Logic ground
VCC - 20
VCC + 0.3
dVS/dt
Allowable offset supply voltage transient
—
50
V/ns
Package power dissipation @ TA ≤ +25 °C
—
0.625
W
Thermal resistance, junction to ambient
—
200
°C/W
PD
RthJA
TJ
Junction temperature
—
150
TS
Storage temperature
-50
150
TL
Lead temperature (soldering, 10 seconds)
—
300
°C
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The VS and COM offset rating
are tested with all supplies biased at 15 V differential.
Symbol
Definition
Min.
Max.
VS +10
COM- 8(Note 1)
VS +20
600
-50 (Note2)
600
VS
VB
VB
High side floating supply absolute voltage
VS
Static High side floating supply offset voltage
VSt
VHO
Transient High side floating supply offset voltage
High side floating output voltage
VCC
Low side and logic fixed supply voltage
10
20
VLO
Low side output voltage
0
VCC
VIN
Logic input voltage (IN & SD)
Units
V
VSS
VCC
TA
Ambient temperature
-40
125
°C
Note 1: Logic operational for VS of -8 V to +600 V. Logic state held for VS of -8 V to – VBS.
Note 2: Operational for transient negative VS of COM - 50 V with a 50 ns pulse width. Guaranteed by design. Refer
to the Application Information section of this datasheet for more details.
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IRS2609DSPbF
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, COM = VCC, CL = 1000 pF, TA = 25 °C, DT = VSS unless otherwise specified.
Symbol
Definition
Min Typ Max Units Test Conditions
ton
Turn-on propagation delay
—
750
1100
toff
Turn-off propagation delay
—
250
400
tsd
Shut-down propagation delay
—
250
400
MT
Delay matching, HS & LS turn-on/off
—
—
60
tr
Turn-on rise time
—
150
220
t
Turn-off fall time
f
DT
MT
MDT
Deadtime: LO turn-off to HO turn-on(DTLO-HO)
HO turn-off to LO turn-on (DTHO-LO)
Delay matching time (t ON , t OFF)
Deadtime matching = DTLO-HO - DTHO-LO
&
VS = 0 V or 600 V
VS = 0 V or 600 V
ns
VS = 0 V
—
50
80
VS = 0 V
350
530
800
—
—
—
—
60
60
VIN = 0 V & 5 V
Without external
deadtime
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15 V, VCC = COM, DT = VCC and TA = 25 °C unless otherwise specified. The VIL, VIH and IIN
parameters are referenced to VCC/COM and are applicable to the respective input leads: IN and SD. The VO, IO and
Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO.
Symbol
Definition
Min Typ Max Units Test Conditions
VIH
logic “1” input voltage for HO & logic “0” for LO
2.2
VIL
logic “0” input voltage for HO & logic “1” for LO
—
—
0.8
VOH
High level output voltage, VBIAS - VO
—
0.8
1.4
VOL
Low level output voltage, VO
—
0.3
0.6
ILK
Offset supply leakage current
—
—
50
VB = VS = 600 V
IQBS
Quiescent VBS supply current
—
45
70
VIN = 0 V or 4 V
IQCC
Quiescent VCC supply current
IIN+
IIN-
Logic “1” input bias current
Logic “0” input bias current
SD input positive going threshold
SD input negative going threshold
VCC and VBS supply undervoltage positive going
Threshold
VCC and VBS supply undervoltage negative going
Threshold
ISD, TH+
ISD, THVCCUV+
VBSUV+
VCCUVVBSUVVCCUVH
VBSUVH
Hysteresis
—
—
1000 2000 3000
—
—
—
—
5
—
15
10
20
2
30
20
8.0
8.9
9.8
7.4
8.2
9.0
—
0.7
—
IO+
Output high short circuit pulsed current
120
200
—
IO-
Output low short circuit pulsed current
250
350
—
—
200
—
V
IO = 20 mA
µA
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Bootstrap resistance
VIN = 0 V or 4 V
VIN = 4 V
VIN = 0 V
V
mA
Rbs
IO = 20 mA
VO = 0 V,
PW ≤ 10 us
VO = 15 V,
PW ≤ 10 us
Ohm
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IRS2609DSPbF
Functional Block Diagrams
Lead Definitions
Symbol
IN
SD
Description
VB
Logic input for high and low side gate driver outputs (HO and LO), in phase
Logic input for shutdown
High side floating supply
HO
VS
High side gate drive output
High side floating supply return
VCC
Low side and logic fixed supply
LO
COM
Low side gate drive output
Low side return
Lead Assignments
IRS2609DS
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IRS2609DSPbF
Application Information and Additional Details
Informations regarding the following topics are included as subsections within this section of the datasheet.
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IGBT/MOSFET Gate Drive
Switching and Timing Relationships
Deadtime
Matched Propagation Delays
Shut down Input
Input Logic Compatibility
Undervoltage Lockout Protection
Shoot-Through Protection
Integrated Bootstrap Functionality
Negative VS Transient SOA
PCB Layout Tips
Integrated Bootstrap FET limitation
Additional Documentation
IGBT/MOSFET Gate Drive
The IRS2609D HVICs are designed to drive MOSFET or IGBT power devices. Figures 1 and 2 illustrate several parameters
associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power switch, is
defined as IO. The voltage that drives the gate of the external power switch is defined as VHO for the high-side power switch and VLO
for the low-side power switch; this parameter is sometimes generically called VOUT and in this case does not differentiate between the
high-side or low-side output voltage.
VB
(or VCC)
VB
(or VCC)
IO+
HO
(or LO)
+
HO
(or LO)
IO-
VHO (or VLO)
VS
(or COM)
-
Figure 1: HVIC sourcing current
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VS
(or COM)
Figure 2: HVIC sinking current
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IRS2609DSPbF
Switching and Timing Relationships
The relationships between the input and output signals of the IRS2609D are illustrated below in Figures 3, 4. From these figures, we
can see the definitions of several timing parameters (i.e. tON, tOFF, tR, and tF) associated with this device.
Figure 3: Switching time waveforms
Figure 4: Input/output timing diagram
Deadtime
This family of HVICs features integrated deadtime protection circuitry. The deadtime for these ICs is fixed; other ICs within IR’s HVIC
portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum
deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being turned
off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserter whenever the
external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver. Figure 5 illustrates the
deadtime period and the relationship between the output gate signals.
The deadtime circuitry of the IRS2609D is matched with respect to the high- and low-side outputs. Figure 6 defines the two deadtime
parameters (i.e., DTLO-HO and DTHO-LO); the deadtime matching parameter (MDT) associated with the IRS2609D specifies the
maximum difference between DTLO-HO and DTHO-LO.
Matched Propagation Delays
The IRS2609D family of HVICs is designed with propagation delay matching circuitry. With this feature, the IC’s response at the
output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-side channels and the
high-side channels; the maximum difference is specified by the delay matching parameter (MT). The propagation turn-on delay (tON)
of the IRS2609D is matched to the propagation turn-on delay (tOFF).
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IRS2609DSPbF
Shut down Input
The IRS2609D family of HVICs is equipped with a shut down (/SD) input pin that is used to shutdown or enable the HVIC. When the
/SD pin is in the high state the HVIC is able to operate normally. When the /SD pin is in low state the HVIC is tristated.
50%
50%
IN
90%
HO
LO
DTLO-HO
10%
90%
DTHO-LO
10%
MDT = DTLO-HO
Figure 5: Shut down
- DTHO-LO
Figure 6: Dead time Definition
Figure 7: Delay Matching waveform Definition
Input Logic Compatibility
The inputs of this IC are compatible with standard CMOS and TTL outputs. The IRS2609D has been designed to be compatible with
3.3 V and 5 V logic-level signals. The IRS2609D features an integrated 5.2 V Zener clamp on the /SD. Figure 8 illustrates an input
signal to the IRS2609D, its input threshold values, and the logic state of the IC as a result of the input signal.
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IRS2609DSPbF
Input Signal
(IRS23364D)
V IH
Input Logic
Level
VIL
High
Low
Low
Figure 8: HIN & LIN input thresholds
Undervoltage Lockout Protection
This family of ICs provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and the VBS
(high-side circuitry) power supply. Figure 9 is used to illustrate this concept; VCC (or VBS) is plotted over time and as the waveform
crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC will not turn-on. Additionally, if the VCC voltage
decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will recognize a fault condition and
shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform the controller of the
fault condition.
Upon power-up, should the VBS voltage fail to reach the VBSUV threshold, the IC will not turn-on. Additionally, if the VBS voltage
decreases below the VBSUV threshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and
shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to fully
enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low voltage, resulting
in the power switch conducting current while the channel impedance is high; this could result in very high conduction losses within the
power device and could lead to power device failure.
Figure 9: UVLO protection
Shoot-Through Protection
The IRS2609D high-voltage ICs is equipped with shoot-through protection circuitry (also known as cross-conduction prevention
circuitry).
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IRS2609DSPbF
Integrated Bootstrap Functionality
The IRS2609D embeds an integrated bootstrap FET that allows an alternative drive of the bootstrap supply for a wide range of
applications. A bootstrap FET is connected between the floating supply VB and VCC (see Fig. 10).
Vcc
BootFet
Vb
Figure 10: Semplified BootFET connection
The integrated bootstrap feature can be used either in parallel with the external bootstrap network (diode and resistor) or as
a replacement of it. The use of the integrated bootstrap as a replacement of the external bootstrap network may have some
limitations at very high PWM duty cycle, corresponding to very short LIN pulses, due to the bootstrap FET equivalent
resistance RBS.
The summary for the bootstrap state follows:
•
Bootstrap turns-off (immediately) or stays off when at least one of the following conditions are met:
1- /SD is low
2- /SD is high, IN is low and VB is high (> 1.1*VCC)
3- /SD is high, IN is high (DT period excluded)
4- /SD is high, IN is high and VB is high (> 1.1*VCC) (during DT period)
•
Bootstrap turns-on when:
1- /SD in high, IN is low and VB is low (< 1.1(VCC))
2- /SD in high, IN is high and VB is low (< 1.1(VCC)) (during the DT period). Please refer to the BootFET timing
diagram for more details.
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IRS2609DSPbF
IN
DT
HO
DT
LO
/SD
BootStrap
Fet
VB
1.1*Vcc
+
Figure 11: BootFET timing diagram
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IRS2609DSPbF
Negative VS Transient SOA
A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the power
switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in Figure 12; here we
define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figures 13 and 14) switches off, while the U phase current is flowing to an inductive load,
a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch of the same inverter
leg. At the same instance, the voltage node VS1, swings from the positive DC bus voltage to the negative DC bus voltage.
Figure 12: Three phase inverter
DC+ BUS
Q1
ON
IU
VS1
Q2
OFF
D2
DC- BUS
Figure 13: Q1 conducting
Figure 14: D2 conducting
Also when the V phase current flows from the inductive load back to the inverter (see Figures 15 and 16), and Q4 IGBT switches on,
the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2, swings from the positive DC bus voltage
to the negative DC bus voltage.
Figure 15: D3 conducting
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Figure 16: Q4 conducting
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IRS2609DSPbF
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather it swings below the
level of the negative DC bus. This undershoot voltage is called “negative VS transient”.
The circuit shown in Figure 17 depicts one leg of the three phase inverter; Figures 18 and 19 show a simplified illustration of the
commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the PCB tracks
are lumped together in LC and LE for each IGBT. When the high-side switch is on, VS1 is below the DC+ voltage by the voltage drops
associated with the power switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current
momentarily flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in these
figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load and a negative voltage
between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential than the VS pin).
Figure 17: Parasitic Elements
Figure 18: VS positive
Figure 19: VS negative
In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative VS transient voltage can
exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications. An
indication of the IRS2609D’s robustness can be seen in Figure 20, where there is represented the IRS2609D Safe Operating Area at
VBS=15V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey area (outside SOA) may lead to IC
permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs transients
fall inside SOA.
At VBS=15V in case of -VS transients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design the
high-side outputs in the off state for 4.5 µs.
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IRS2609DSPbF
Figure 20: Negative VS transient SOA for IRS2608D @ VBS=15V
Even though the IRS2609D has been shown able to handle these large negative VS transient conditions, it is highly recommended
that the circuit designer always limit the negative VS transients as much as possible by careful PCB layout and component use.
PCB Layout Tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating voltage
pins (VB and VS) near the respective high voltage portions of the device. Please see the Case Outline information in this datasheet
for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage floating
side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 21). In order to
reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as
possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic capacitance. The
parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus increasing the possibility
of a self turn-on effect.
Figure 21: Antenna Loops
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IRS2609DSPbF
Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A ceramic 1 µF ceramic
capacitor is suitable for most applications. This component should be placed as close as possible to the pins in order to reduce
parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch node;
it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended to 1) minimize
the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail stray inductance.
However, where negative VS spikes remain excessive, further steps may be taken to reduce the spike. This includes placing a
resistor (5 Ω or less) between the VS pin and the switch node (see Figure 22), and in some cases using a clamping diode between
COM and VS (see Figure 23). See DT04-4 at www.irf.com for more detailed information.
Figure 22: VS resistor
Figure 23: VS clamping diode
Integrated Bootstrap FET limitation
The integrated Bootstrap FET functionality has an operational limitation under the following bias conditions applied to the HVIC:
•
•
VCC pin voltage = 0V
AND
VS or VB pin voltage > 0
In the absence of a VCC bias, the integrated bootstrap FET voltage blocking capability is compromised and a current conduction
path is created between VCC & VB pins, as illustrated in Fig.24 below, resulting in power loss and possible damage to the HVIC.
Figure 24: Current conduction path between VCC and VB pin
Relevant Application Situations:
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IRS2609DSPbF
The above mentioned bias condition may be encountered under the following situations:
•
In a motor control application, a permanent magnet motor naturally rotating while VCC power is OFF. In this
condition, Back EMF is generated at a motor terminal which causes high voltage bias on VS nodes resulting
unwanted current flow to VCC.
•
Potential situations in other applications where VS/VB node voltage potential increases before the VCC voltage is
available (for example due to sequencing delays in SMPS supplying VCC bias)
Application Workaround:
Insertion of a standard p-n junction diode between VCC pin of IC and positive terminal of VCC capacitors (as illustrated in Fig.25)
prevents current conduction “out-of” VCC pin of gate driver IC. It is important not to connect the VCC capacitor directly to pin of
IC. Diode selection is based on 25V rating or above & current capability aligned to ICC consumption of IC - 100mA should cover
most application situations. As an example, Part number # LL4154 from Diodes Inc (25V/150mA standard diode) can be used.
VCC
VCC
Capacitor
VB
VSS
(or COM)
Figure 25: Diode insertion between VCC pin and VCC capacitor
Note that the forward voltage drop on the diode (VF) must be taken into account when biasing the VCC pin of the IC to meet
UVLO requirements. VCC pin Bias = VCC Supply Voltage – VF of Diode.
Additional Documentation
Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and the
document number to quickly locate them. Below is a short list of some of these documents.
DT97-3: Managing Transients in Control IC Driven Power Stages
AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
DT04-4: Using Monolithic High Voltage Gate Drivers
AN-978: HV Floating MOS-Gate Driver ICs
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IRS2609DSPbF
Parameters trend in temperature
1500
Turn-Off Propagation Delay (ns)
Turn-On Propagation Delay (ns)
Figures 26-49 provide information on the experimental performance of the IRS2609D(S) HVIC. The line plotted in each
figure is generated from actual lab data. A large number of individual samples from multiple wafer lots were tested at three
temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The line labeled Exp. consist
of three data points (one data point at each of the tested temperatures) that have been connected together to illustrate the
understood trend. The individual data points on the curve were determined by calculating the averaged experimental value
of the parameter (for a given temperature).
1200
900
Exp.
600
300
0
-50
-25
0
25
50
75
100
500
400
300
Exp.
200
100
0
125
-50
-25
0
Temperature (oC)
Fig. 26. Turn-on Propagation Delay vs.
Temperature
50
75
100
125
Fig. 27. Turn-off Propagation Delay vs.
Temperature
250
Turn-Off fall Time (ns)
Turn-On Rise Time (ns)
25
Temperature (oC)
200
150
100
125
100
75
50
Exp.
Exp.
50
`
25
0
0
-50
-25
0
25
50
75
100
o
Temperature ( C)
Fig. 28. Turn-on Rise Time vs. Temperature
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125
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Fig. 29. Turn-off Rise Time vs. Temperature
17
4
4
3
3
VBSUV hysteresis (V)
VCCUV hysteresis (V)
IRS2609DSPbF
2
1
Exp.
2
1
Exp.
0
0
-50
-25
0
25
50
75
100
-50
125
-25
0
25
Fig. 30. VCC Supply UV Hysteresis vs.
Temperature
75
100
125
Fig. 31. VBS Supply UV Hysteresis vs.
Temperature
100
VBS Quiescent Current (µA)
10
VCC Quiescent Current (mA)
50
Temperature (oC)
Temperature (oC)
8
6
4
2
Exp.
0
-50
-25
0
25
50
75
100
80
60
Exp.
40
20
`
0
-50
125
-25
0
25
50
75
100
125
o
Temperature ( C)
Temperature (oC)
Fig. 33. VBS Quiescent Supply Current vs.
Temperature
Fig. 32. VCC Quiescent Supply Current vs.
Temperature
12
12
VCCUV- Threshold (V)
VCCUV+ Threshold (V)
Exp.
9
6
3
0
9
Exp.
6
3
0
-50
-25
0
25
50
75
100
o
Temperature ( C)
Fig. 35. VCCUV+ Threshold vs. Temperature
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125
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Fig. 36. VCCUV- Threshold vs. Temperature
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IRS2609DSPbF
12
12
9
VBSUV- Threshold (V)
VBSUV+ Threshold (V)
Exp.
9
6
3
Exp.
6
3
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (oC)
75
100
125
Temperature ( C)
Fig. 38. VBSUV- Threshold vs. Temperature
400
300
200
EXP.
100
0
-50
-25
0
25
50
75
100
125
High Level Output Voltage (mV)
400
Low Level Output Voltage (mV)
50
o
Fig. 37. VBSUV+ Threshold vs. Temperature
300
200
Exp.
100
0
-50
-25
0
o
25
50
75
100
125
o
Temperature ( C)
Temperature ( C)
Fig. 39. High Level Output Voltage vs.
Temperature
Fig. 38. Low Level Output Voltage vs. Temperature
500
8
400
6
IN VTH+ (V)
Bootstrap Resistance (Ω)
25
300
200
4
Exp.
Exp.
2
100
0
0
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 40. Bootstrap Resistance vs. Temperature
www.irf.com
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 41. IN VTH+ vs. Temperature
19
8
8
6
6
HIN VTH+ (V)
IN VTH- (V)
IRS2609DSPbF
4
2
4
Exp.
2
Exp.
0
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
o
100
125
Temperature ( C)
Fig. 42. LIN VTH- vs. Temperature
Fig. 43. HIN VTH+ vs. Temperature
8
50
6
40
Tbson_VccTYP(ns)
HIN VTH- (V)
75
o
Temperature ( C)
4
2
Exp.
0
30
20
Exp.
10
0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
Temperature (oC)
75
100
125
Temperature ( C)
Fig. 45. Tbson_VCCTYP vs. Temperature
1000
400
800
Deadtime (ns)
500
Exp.
300
50
o
Fig. 44. HIN VTH- vs. Temperature
Shut-down propagation delay (ns)
50
200
100
0
Exp.
600
400
200
0
-50
-25
0
25
50
75
100
Temperature (oC)
Fig. 46. Shut-down Propagation Delay vs.
Temperature
www.irf.com
125
-50
-25
0
25
50
75
100
125
o
Temperature ( C)
Fig. 47. Deadtime vs. Temperature
20
IRS2609DSPbF
30
50
25
40
20
20
MDT (ns)
MT (ns)
30
Exp.
10
15
Exp.
10
5
0
0
-50
-25
0
25
50
75
100
o
Temperature ( C)
Fig. 48. Delay Matching vs. Temperature
www.irf.com
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Fig. 49. Deadtime Matching vs. Temperature
21
IRS2609DSPbF
Case Outlines
www.irf.com
22
IRS2609DSPbF
Tape and Reel Details: 8L-SOIC
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
7.90
8.10
B
3.90
4.10
C
11.70
12.30
D
5.45
5.55
E
6.30
6.50
F
5.10
5.30
G
1.50
n/a
H
1.50
1.60
8SOICN
Imperial
Min
Max
0.311
0.318
0.153
0.161
0.46
0.484
0.214
0.218
0.248
0.255
0.200
0.208
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
18.40
G
14.50
17.10
H
12.40
14.40
www.irf.com
Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
0.724
0.570
0.673
0.488
0.566
23
IRS2609DSPbF
ORDER INFORMATION
8-Lead SOIC IRS2609DSPbF
8-Lead SOIC Tape & Reel IRS2609DSTRPbF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other
rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or
patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This document
supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
www.irf.com
24
IRS2609DSPbF
Revision History
Revision Date
1.5
03-17-08
1.6
03-17-08
1.6a
03-21-08
1.7
04-18-08
May 8, 08
06-18-08
08-18-2009
www.irf.com
Comments/Changed items
Added application note to include negative Vs curve
Added Qualification Information on Page 2, Disclaimer information on Page
25, and updated information on Pages 21-23
Removed revision letter from JEDEC standards under Qualification
Information table.
Added “RoHS compliant” statement to front page, Changed latch up level to
A, added MT parameter.
Changed file name from using revision to using date, Page1: corrected IGBT,
Page5: corrected p/n on lead assignment diagram to IRS2609DS
Corrected internal dead time on front page to 530ns instead of 540ns.
Removed reference to trapezoidal modulation in Integrated Bootstrap
Functionality section
25
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