Freescale MC68HC705E6FB Hcmos microcontroller unit Datasheet

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MC68HC05E6/D
MC68HC05E6
MC68HC705E6
Rev. 1.0
HCMOS Microcontroller Unit
TECHNICAL DATA
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List of Sections
List of Sections
List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Modes of Operation and Pin Descriptions . . . . . . . . . . 13
Memory and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Core Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Programmable Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
A-to-D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 105
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Literature Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
© Motorola, Inc., 1999
MC68HC05E6 — Rev. 1.0
List of Sections
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List of Sections
MC68HC05E6 — Rev. 1.0
List of Sections
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Table of Contents
Table of Contents
General Description
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Modes of Operation
and Pin
Descriptions
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Memory and
Registers
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ROM (MC68HC05E6 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EPROM (MC68HC705E6 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Input/Output Ports
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
MC68HC05E6 — Rev. 1.0
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Table of Contents
Core Timer
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Real time interrupts (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Computer operating properly (COP) watchdog timer . . . . . . . . . . . . .47
Core timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Core timer during WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Core timer during STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Programmable
Timer
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Keyboard/timer register (KEY/TIM) . . . . . . . . . . . . . . . . . . . . . . . . . .52
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Timer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Timer during WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Timer during STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Timer state diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
A-to-D Converter
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
A/D converter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
A/D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
A/D converter during WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
A/D converter during STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . .71
A/D analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Resets and
Interrupts
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Nonmaskable software interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . .78
Maskable hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Hardware controlled interrupt sequence . . . . . . . . . . . . . . . . . . . . . . .83
MC68HC05E6 — Rev. 1.0
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Table of Contents
Central
Processing Unit
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
86
86
89
90
90
93
98
Electrical
Specifications
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal characteristics and power considerations . . . . . . . . . . . . .
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A/D converter electrical characteristics . . . . . . . . . . . . . . . . . . . . .
Mechanical Data
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Ordering
Information
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verification media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
121
121
123
123
Literature Updates
Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Motorola SPS World Marketing World Wide Web Server . . . . . . . .
Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . . . . . .
137
138
138
138
138
105
105
106
107
108
111
114
MC68HC05E6 — Rev. 1.0
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Table of Contents
MC68HC05E6 — Rev. 1.0
Table of Contents
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General Description
General Description
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Introduction
The MC68HC05E6 is a member of the M68HC05 family of HCMOS
microcomputers. Features of the MC68HC05E6 include 6K bytes of user
ROM, 160 bytes of EEPROM, a keyboard interface, an A/D converter and
a 16-bit timer. The device is further enhanced by a core timer which
enables real time interrupts at, for example, 8ms intervals and a
watchdog facility which guards against CPU ‘runaway’. The on-board
EEPROM facilitates storage of alterable, non-volatile, user specified
data, such as personalisation data or control parameters. The features
highlighted make the part ideally suited to various control applications,
while the low voltage design and low cost option ensure that it can also
be used in telecommunications applications such as telephone handsets.
For maximum I/O capability, the 44-pin version of the MC68HC05E6 is
recommended, however for cost-sensitive applications a 28-pin version
is also available.
NOTE:
The entire data sheet applies to the 44-pin version of the device,
however some of the features are not available to the user when the part
is bonded in the 28-pin package (see Figure 1).
The MC68HC705E6 is an EPROM version of the MC68HC05E6, with
the user ROM replaced by a similar amount of EPROM. All references
to the MC68HC05E6 apply equally to the MC68HC705E6, unless
otherwise noted.
MC68HC05E6 — Rev. 1.0
1-gen
General Description
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General Description
References specific to the MC68HC705E6 are italicised in the text.
NOTE:
Information given for the MC68HC705E6 cannot be guaranteed. All
values are design targets only and may change before the device is
qualified.
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Features
•
Fully static design featuring the industry-standard M68HC05 core
•
On-chip oscillator with crystal or ceramic resonator clock options
•
6000 bytes of user ROM plus 16 bytes of user vectors
(MC68HC05E6); 6144 bytes of user EPROM plus 16 bytes of user
vectors (MC68HC705E6)
•
240 bytes of bootloader ROM (MC68HC705E6)
•
160 bytes of EEPROM
•
128 bytes of RAM
•
Single supply voltage (no external voltage required for EEPROM
programming)
•
4-channel, 8-bit A/D converter
•
16-bit programmable timer with input capture and output compare
•
15-stage multipurpose core timer with overflow, watchdog and
real-time interrupt
•
32 programmable bidirectional I/O lines and four input-only lines
including eight fixed wire pull-ups (port A), eight fixed wire
pull-downs (port B) and 16 software selectable pull-ups (ports C
and D)
•
Keyboard interrupt facility available on all pins of port C
•
Low voltage indicator (LVI)
•
Power saving STOP and WAIT modes
•
Available in 44-pin QFP and 28-pin SOIC packages; four of the
ports are not fully bonded out in the 28-pin package (see Figure 1)
MC68HC05E6 — Rev. 1.0
2-gen
General Description
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General Description
Mask options
Mask options
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There are two mask options on the MC68HC05E6 which are
programmed during manufacture and therefore must be specified on the
order form; COP watchdog timer enable/disable and STOP instruction
enable/disable.
LVI/options
register (LVI/OPT)
In addition, the IRQ pin can be configured to be either edge or
edge-and-level sensitive. This is done using the IRQ bit in the
LVI/options register at $0F.
There are two options on the MC68HC705E6 which are programmed
using configuration bits in the LVI/options register; COP watchdog timer
enable/disable and edge or edge-and-level sensitive IRQ triggering. The
STOP instruction is permanently enabled on the MC68HC705E6.
Address
LVI/options (LVIOPT)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
$000F LVIINT LVIVAL LVIRST LVIENA
bit 1
bit 0
State
on reset
COP
IRQ
0u00 0u00
COP — Computer operating properly watchdog enable/disable
1 = COP watchdog disabled.
0 = COP watchdog enabled.
Reset clears this bit, thus the COP watchdog is enabled automatically
after reset. Because of the ‘write-once’ nature of the COP bit, it is
recommended that it be written to immediately after reset to lock the
desired state.
IRQ — Interrupt triggering sensitivity
1 = IRQ is negative edge-and-level sensitive
0 = IRQ is negative edge sensitive only
Reset clears the IRQ bit.
NOTE:
The bits in the LVIOPT register which are shaded are not relevant to this
section of the data sheet. These bits are described in Resets and
Interrupts.
MC68HC05E6 — Rev. 1.0
3-gen
General Description
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General Description
6000 bytes user ROM/ 6144 bytes user EPROM
(plus 16 bytes for vectors)
(plus 16 bytes for vectors)
8-bit
analog-to-digital
converter
AD3
AD2
AD1
AD0
Port G
224 bytes
bootloader ROM
PG3
PG2
PG1
PG0
Not available
28-pin package
in
Not available
28-pin package
in
Not
in
VREFH
Port A
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Port B
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Port C
160 bytes EEPROM
PC7
28-pin package
PC6
PC5
PC4
PC3
PC2
PC1/TCMP
PC0/TCAP
OSC1
OSC2
Oscillator
Core
timer
M68HC05
CPU
RESET
IRQ/VPP
LVI
16-bit timer
TCMP
TCAP
Keyboard interrupt
COP
available
Port D
VDD
VSS
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
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128 bytes RAM
Not available in 28-pin package
Figure 1 MC68HC05E6 and MC68HC705E6 block diagram
MC68HC05E6 — Rev. 1.0
4-gen
General Description
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Modes of Operation and Pin Descriptions
Modes of Operation and Pin Descriptions
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Contents
Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Modes of operation
The MC68HC05E6 operates in single chip mode only. The
MC68HC705E6 has two modes of operation; single chip and EPROM
bootloader mode. Table 1 shows the conditions required to enter the
EPROM modes of operation on the rising edge of RESET.
Table 1 MC68HC705E6 operating mode entry conditions
RESET
IRQ/VPP
VSS to
VDD
2VDD
Single chip mode
PC4
PC3
PC2
Mode
x
x
x
Single chip
1
1
1
0
1
1
1
Verify only
0
EPROM bootloader Program 1 byte
1
Program 4 bytes
x = don’t care
This is the normal operating mode of the MC68HC05E6. In this mode the
device functions as a self-contained microcomputer (MCU) with all
on-board peripherals, including the 8-bit I/O ports (A, B, C and D) and
the 4-bit input-only port (G), available to the user. All address and data
activity occurs within the MCU.
Single chip mode is entered on the rising edge of RESET if the voltage
level on the IRQ pin is within the normal operating range.
MC68HC05E6 — Rev. 1.0
1-pin
Modes of Operation and Pin Descriptions
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Modes of Operation and Pin Descriptions
NOTE:
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EPROM
bootloader mode
for the
MC68HC705E6
For the MC68HC705E6, all vectors are fetched from EPROM in single
chip mode; therefore, the EPROM must be programmed (via the
bootloader mode) before the device is powered up in single chip mode.
This mode is used for programming the on-board EPROM. The pin
assignments are identical to those of single chip mode (see Figure 3).
Because the addresses in the MC68HC705E6 and the external EPROM
containing the user code are incremented independently, it is essential
that the data layout in the 27256 EPROM conforms exactly to the
MC68HC705E6 memory map.
MC68HC05E6 — Rev. 1.0
2-pin
Modes of Operation and Pin Descriptions
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Modes of Operation and Pin Descriptions
Modes of operation
The bootloader uses two external latches to address the memory device
containing the code to be copied. Figure 2 shows a suggested EPROM
programming circuit.
9
8
7
6
5
4
3
2
33 kΩ
VDD
IRQ/VPP
4MHz
OSC1
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OSC2
10 MΩ
22 pF
22 pF
PB3
100 kΩ
S4
RESET
100 nF
9
8
7
6
5
4
3
2
MC68HC705E6
VDD
VDD
PC1
470 Ω
OE
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CLK
OE
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
PB2
S1
PC4
S2
PC3
S3
PC2
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
VDD
VSS
GREEN
VDD
1
12
13
14
15
16
17
18
19
1
27
26
2
23
21
24
25
A14 VPP
A13
A12
A11
A10
A9
A8
1
12
13
14
15
16
17
18
19
3
4
5
6
7
8
9
10
20
22
RED
PC0
470 Ω
11
CLK
19
18
17
16
15
13
12
11
A7
A6
A5
A4
A3
A2
A1
A0
27256
1N4148
11
HC573
PB4
HC573
10 Ω
VPP
CE
OE
D7
D6
D5
D4
D3
D2
D1
D0
VDD
Figure 2 EPROM programming circuit
NOTE:
This mode must not be used in the user’s application.
MC68HC05E6 — Rev. 1.0
3-pin
Modes of Operation and Pin Descriptions
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Modes of Operation and Pin Descriptions
Bootloader
functions
The bootloader code deals with the copying of user code from an
external EPROM into the on-chip EPROM. The bootloader function can
only be used with an external EPROM. The bootloader performs a
programming pass followed by a verify pass.
Freescale Semiconductor, Inc...
Two pins, PC0 and PC1, are used to drive the PROG and VERF LED
outputs. While the EPROM is being programmed, the PROG LED lights
up; when programming is complete, the internal EPROM contents are
compared to that of the external EPROM and, if they match exactly, the
VERF LED lights up.
The EPROM must be in the erased state before performing a program
cycle. The erased state of the EPROM is $00.
EPROM
programming
instructions
The following procedure should be carried out when programming the
EPROM. In order to prevent damage to the device, VDD should always be
applied to the part before VPP when applying power. Similarly, VPP should
be removed from the part before VDD when switching the power off.
1. Turn off power to the circuit.
2. Install the MCU and the EPROM.
3. Select the bootloader function:
Program 1 byte: Open S1 and S2 and close S3.
Program 4 bytes: Open S1, S2 and S3.
Verify only: Open S1 and S3 and close S2.
4. Close switch S4 to hold the MCU in reset.
5. Apply VDD to the circuit.
6. Apply the EPROM programming voltage (VPP) to the circuit.
7. Open switch S4 to take the MCU out of reset.
During programming the PROG LED turns on and is switched off
when the verification routine begins. If verification is successful,
the VERF LED turns on. If the bootloader finds an error during
verification, it puts the error address on the external address bus
and stops running.
8. Close switch S4 to hold the MCU in reset.
9. Remove the VPP voltage.
10. Remove the VDD voltage.
NOTE:
EPROM programming must be carried out at room temperature.
MC68HC05E6 — Rev. 1.0
4-pin
Modes of Operation and Pin Descriptions
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Modes of Operation and Pin Descriptions
Pin descriptions
Freescale Semiconductor, Inc...
Pin descriptions
IRQ/VPP
1
28
VSS
RESET
2
27
VDD
OSC1
3
26
PA0
OSC2
4
25
PA1
LVI
5
24
PA2
PG0/AD0
6
23
PA3
VREFH
7
22
PA4
PB4
8
21
PA5
PB3
9
20
PA6
PB2
10
19
PA7
PB1
11
18
PC0/TCAP
PB0
12
17
PC1/TCMP
PC5
13
16
PC2
PC4
14
15
PC3
44
43
42
41
40
39
38
37
36
35
34
LVI
PB7
OSC2
OSC1
RESET
IRQ/VPP
VSS
VDD
PA0
PD0
PA1
Figure 3 28-pin SOIC pinout
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
PA2
PD1
PA3
PD2
PA4
PD3
PA5
PD4
PA6
PD5
PA7
PB0
PC7
PC6
PC5
PC4
PC3
PD7
PC2
PC1/TCMP
PD6
PC0/TCAP
12
13
14
15
16
17
18
19
20
21
22
PB6
PG0/AD0
PG1/AD1
PG2/AD2
PG3/AD3
VREFH
PB5
PB4
PB3
PB2
PB1
Figure 4 44-pin QFP pinout
MC68HC05E6 — Rev. 1.0
5-pin
Modes of Operation and Pin Descriptions
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Modes of Operation and Pin Descriptions
Freescale Semiconductor, Inc...
VDD and VSS
Power is supplied to the microcontroller using these two pins. VDD is the
positive supply and VSS is ground.
It is in the nature of CMOS designs that very fast signal transitions occur
on the MCU pins. These short rise and fall times place very high
short-duration current demands on the power supply. To prevent noise
problems, special care must be taken to provide good power supply
bypassing at the MCU. Bypass capacitors should have good high
frequency characteristics and be as close to the MCU as possible.
Bypassing requirements vary, depending on how heavily the MCU pins
are loaded.
IRQ/VPP
This is an input-only pin for external interrupt sources. Interrupt triggering
can be selected to be negative edge sensitive or negative edge-and-level
sensitive by correctly configuring the IRQ bit in the LVIOPT register (see
Mask options). The IRQ pin contains an internal Schmitt trigger as part of
its input to improve noise immunity. For the MC68HC705E6, this pin also
serves as the input pin for the EPROM programming voltage (VPP).
OSC1, OSC2
These pins provide control input for an on-chip oscillator circuit. A
crystal, ceramic resonator or external clock signal connected to these
pins supplies the oscillator clock. The oscillator frequency (fOSC) is
divided by two to give the internal bus frequency (fOP).
Crystal
The circuit shown in Figure 5(a) is recommended when using either a
crystal or a ceramic resonator. Figure 5(e) provides the recommended
capacitance and feedback resistance values. The internal oscillator is
designed to interface with an AT-cut parallel-resonant quartz crystal
resonator in the frequency range specified for fOSC (see Table 23). Use
of an external CMOS oscillator is recommended when crystals outside
the specified ranges are to be used. The crystal and associated
components should be mounted as close as possible to the input pins to
minimise output distortion and start-up stabilization time. The
manufacturer of the particular crystal being considered should be
consulted for specific information.
MC68HC05E6 — Rev. 1.0
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Modes of Operation and Pin Descriptions
Pin descriptions
Ceramic
resonator
A ceramic resonator may be used instead of a crystal in cost sensitive
applications. The circuit shown in Figure 5(a) is recommended when
using either a crystal or a ceramic resonator. Figure 5(e) lists the
recommended capacitance and feedback resistance values. The
manufacturer of the particular ceramic resonator being considered
should be consulted for specific information.
External clock
An external clock should be applied to the OSC1 input, with the OSC2
pin left unconnected, as shown in Figure 5(c). The tOCOV specification
(see Table 23) does not apply when using an external clock input. The
equivalent specification of the external clock source should be used in
lieu of tOCOV.
LVI
This active low input pin is used to indicate a drop in supply voltage
below a useful operating level. Driving this pin low initiates either a
pre-defined software routine or a hardware interrupt (see Low voltage
indicator interrupt). The LVI pin contains an internal Schmitt trigger to
improve noise immunity.
RESET
This active low input-only pin is used to reset the MCU. Applying a logic
zero to this pin forces the device to a known start-up state. The RESET
pin has an internal Schmitt trigger to improve noise immunity.
PA0ÐPA7
These eight I/O lines comprise port A. The state of any pin is software
programmable, and all the pins are configured as inputs with fixed
pull-up resistors during power-on or reset.
PB0ÐPB7
These eight pins comprise port B. The state of any pin is software
programmable, and all the pins are configured as inputs with fixed
pull-down resistors during power-on or reset.
NOTE:
PB5–PB7 are not bonded out in the 28-pin package.
MC68HC05E6 — Rev. 1.0
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Modes of Operation and Pin Descriptions
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Modes of Operation and Pin Descriptions
MCU
OSC1
L
OSC2
C1
RS
OSC1
OSC2
RP
Freescale Semiconductor, Inc...
C0
COSC1
COSC2
(b) Crystal equivalent circuit
(a) Crystal/ceramic resonator
oscillator connections
MCU
OSC1
OSC2
External
clock
NC
(c) External clock source connections
RS(max)
C0
C1
COSC1
COSC2
RP
Q
Crystal
2MHz
4MHz
400
75
5
7
8
12
15 – 40 15 – 30
15 – 30 15 – 25
10
10
30 000 40 000
Unit
Ω
pF
ƒF
pF
pF
MΩ
—
Ceramic resonator
2 – 4MHz
Unit
RS(typ)
10
Ω
C0
40
pF
C1
4.3
pF
COSC1
30
pF
COSC2
30
pF
RP
1 – 10
MΩ
Q
1250
—
(e) Crystal and ceramic resonator parameters
Figure 5 Oscillator connections
MC68HC05E6 — Rev. 1.0
8-pin
Modes of Operation and Pin Descriptions
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Modes of Operation and Pin Descriptions
Pin descriptions
Freescale Semiconductor, Inc...
PC0ÐPC7
These eight port pins comprise port C. The state of any pin is software
programmable, and all the pins can be configured as inputs with pull-up
resistors or open-drain outputs using the data direction register and
configuration register. During power-on or reset, all port C registers are
cleared, thereby returning the port pins to normal inputs with pull-up
resistors. In addition to their normal I/O functions, PC0 is shared with the
input capture function (TCAP) of the programmable timer and PC1 with
the output compare function (TCMP); see Port C. PC0–PC7 are used to
provide a keyboard interrupt facility when configured as inputs and not
used for timer functions. They contain an internal Schmitt trigger as part
of their input to improve noise immunity.
NOTE:
PD0ÐPD7
These eight port pins comprise port D. The state of any pin is software
programmable, and all the pins can be configured as inputs with pull-up
resistors or open-drain outputs using the configuration register. During
power-on or reset, all port D registers are cleared, thereby returning the
port pins to normal inputs with pull-up resistors.
NOTE:
PG0ÐPG3
PD0–PD7 are not bonded out in the 28-pin package.
These four input-only port pins comprise port G. In addition to their
normal input functions, the pins are shared with the A/D converter
subsystem where they are used as the digital input pins AD0–AD3 (see
A-to-D Converter).
NOTE:
VREFH
PC6 and PC7 are not available in the 28-pin package.
PG1–PG3 are not bonded out in the 28-pin package; the A/D converter
has only one input channel.
This pin provides the high voltage reference for the A/D converter. The
low voltage reference (VREFL) is tied to VSS internally.
MC68HC05E6 — Rev. 1.0
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Modes of Operation and Pin Descriptions
Low power modes
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STOP
The STOP instruction places the MCU in its lowest power consumption
mode. In STOP mode, the internal oscillator is turned off, halting all
internal processing including timer (and COP watchdog timer) operation.
The I-bit in the CCR is cleared to enable external interrupts. All other
registers, the remaining bits in the CTCSR, and memory contents
remain unaltered. All input/output lines remain unchanged. The
processor can be brought out of STOP mode only by an external
interrupt, a keyboard interrupt (if enabled), an LVI interrupt (if enabled),
or a reset (see Figure 6). On the MC68HC05E6, the STOP instruction
can be disabled using a mask option, in which case it is executed as a
no operation (NOP).
NOTE:
WAIT
When exiting STOP mode there is a 4064 cycle delay before normal
operation resumes.
The WAIT instruction places the MCU in a low power consumption
mode, but WAIT mode consumes more power than STOP mode. All
CPU action is suspended, but the core timer, the 16-bit timer and the A/D
converter remain active. An external, keyboard or LVI interrupt or an
interrupt from the core timer or 16-bit timer, if enabled, will cause the
MCU to exit WAIT mode.
During WAIT mode, the I-bit in the CCR is cleared to enable interrupts.
All other registers, memory and input/output lines remain in their
previous state. The core timer interrupts may be enabled to allow a
periodic exit from WAIT mode. See Figure 6.
MC68HC05E6 — Rev. 1.0
10-pin
Modes of Operation and Pin Descriptions
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Modes of Operation and Pin Descriptions
Low power modes
STOP
WAIT
Stop oscillator
and all clocks;
clear I-mask
Oscillator active;
stop processing;
clear I-mask
Reset
?
Reset
?
No
No
Yes
No
Yes
Any
external, keyboard
LVI, core or 16-bit timer
interrupt
?
Any
external,
keyboard or LVI interrupt
?
Yes
No
Yes
Turn on oscillator;
wait tPORL for
stabilization
Restart
processor
clocks
Fetch
interrupt or reset
vector
Fetch
interrupt or reset
vector
Figure 6 STOP and WAIT flowcharts
MC68HC05E6 — Rev. 1.0
11-pin
Modes of Operation and Pin Descriptions
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Modes of Operation and Pin Descriptions
MC68HC05E6 — Rev. 1.0
12-pin
Modes of Operation and Pin Descriptions
For More Information On This Product,
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Memory and Registers
Memory and Registers
Freescale Semiconductor, Inc...
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bootloader ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ROM (MC68HC05E6 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EPROM (MC68HC705E6 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Introduction
The MC68HC05E6 has an 8K byte memory map consisting of registers
(for I/O, control and status), user RAM, user ROM or EPROM, EEPROM
and reset and interrupt vectors as shown in Figure 7. In addition to the
above, the MC68HC705E6 also has an area of bootloader ROM.
Registers
All the I/O, control and status registers of the MC68HC(7)05E6 are
contained within the first 32-byte block of the memory map, as detailed
in Table 3.
MC68HC05E6 — Rev. 1.0
1-mem
Memory and Registers
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Memory and Registers
RAM
The user RAM consists of 128 bytes of memory, from $0080 to $00FF.
This is shared with a 64-byte stack area. The stack begins at $00FF and
may extend down to $00C0.
Freescale Semiconductor, Inc...
NOTE:
Using the stack area for data storage or temporary work locations
requires care to prevent the data being overwritten due to stacking from
an interrupt or subroutine call.
Bootloader ROM
The MC68HC705E6 has 224 bytes of bootloader ROM which ranges
from $1F00 to $1FDF. This program contains code to program the
EPROM by copying from a 27256 EPROM master device.
NOTE:
The bootloader ROM is not accessible if the ELATCH bit in the EPROM
programming register ($1D) is set.
ROM (MC68HC05E6 only)
The MC68HC05E6 has 6000 bytes of ROM located from $0800 to
$1F6F plus 16 bytes of user vectors from $1FF0 to $1FFF.
EPROM (MC68HC705E6 only)
The MC68HC705E6 has 6144 bytes of EPROM located from $0700 to
$1EFF, plus 16 bytes of user vectors from $1FF0 to $1FFF. Four bytes
of EPROM can be programmed simultaneously by correctly
manipulating the bits in the EPROM programming register.
MC68HC05E6 — Rev. 1.0
2-mem
Memory and Registers
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Memory and Registers
EPROM (MC68HC705E6 only)
EPROM
programming
register (PROG)
Address bit 7
Freescale Semiconductor, Inc...
EPROM programming (PROG) $001D
0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
0
0
0
0
ELATCH
0
bit 0
State
on reset
EPGM 0000 0000
ELATCH — EPROM latch control
1 = EPROM address and data buses configured for programming.
0 = EPROM address and data buses configured for normal reads.
Causes address and data buses to be latched when a write to EPROM
is carried out. EPROM cannot be read if ELATCH = 1. This bit should not
be set when no programming voltage is applied to the VPP pin.
EPGM — EPROM program control
1 = Programming power connected to the EPROM array.
0 = Programming power disconnected from the EPROM array.
NOTE:
EPROM
programming
procedure
ELATCH and EPGM cannot be set on the same write operation. EPGM
can only be set if ELATCH is set. EPGM is automatically cleared when
ELATCH is cleared.
The following steps should be taken to program a byte of EPROM:
1. Apply the programming voltage VPP to the IRQ/VPP pin.
2. Set the ELATCH bit.
3. Write to the EPROM address.
4. Set the EPGM bit for a time tEPGM to apply the programming
voltage.
5. Clear the ELATCH bit.
If the address bytes A15–A2 do not change, i.e. all bytes are located
within the same 4 byte address block, then multibyte programming is
permitted. The multibyte programming facility allows 4 bytes of data to
be written to the desired addresses after the ELATCH bit has been set
(see Table 1 for multibyte programming entry conditions).
NOTE:
The erased state of the EPROM is $00.
MC68HC05E6 — Rev. 1.0
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Memory and Registers
EEPROM
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The 160 byte block of EEPROM is located at address $0100 to $019F.
The EEPROM can be programmed on a single-byte basis by
manipulating the EEPROM programming register at $001C. The voltage
necessary for programming and erasing the internal EEPROM is
generated by an on-chip charge pump. No external programming
voltage is necessary.
NOTE:
The erased state of an EEPROM cell is ‘1’. This means that a write
forces zeroes to the bits specified, whilst bits defined as ones are
unchanged by the write operation.
EEPROM
programming
register (EPROG)
Address bit 7
EEPROM programming
$001C
(EPROG)
0
bit 2
bit 1
bit 0
State
on reset
bit 6
bit 5
bit 4
bit 3
CPEN
0
ER1
ER0 EELATCH EERC EEPGM 0000 0000
CPEN — Charge pump enable
1 = The charge pump, which produces the internal programming
voltage for the EEPROM, is enabled; the programming voltage
is available as soon as the EEPGM bit is set. The EELATCH
bit should also be set in order that programming can take
place.
0 = The charge pump is disabled.
This bit should always be cleared when the charge pump is not in use.
ER1–ER0 — Erase select bits
ER1 and ER0 form a 2-bit field which is used to select one of three
erase modes: byte, block or bulk. Table 2 shows the modes selected
for each bit configuration.
In byte erase mode, only the selected byte is erased. In block erase
mode, a 32-byte block of EEPROM is erased (the EEPROM memory
MC68HC05E6 — Rev. 1.0
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Memory and Registers
EEPROM
Table 2 Erase mode select
ER1
0
0
1
1
ER0
0
1
0
1
Mode
No erase
Byte erase
Block erase
Bulk erase
Freescale Semiconductor, Inc...
space is arranged into five 32-byte blocks: $0100–$011F,
$0120–$013F, $0140–$015F, $0160–$017F and $0180–$019F).
Performing a bulk erase to any EEPROM address will erase the entire
160 byte EEPROM array.
EELATCH — EEPROM latch control
1 = EEPROM address and data buses are configured for
programming; reads from the array are inhibited while this bit
is set.
0 = EEPROM address and data buses are configured for normal
reads.
EERC — EEPROM RC oscillator control
1 = The EEPROM section uses the internal RC oscillator instead of
the CPU clock; a time delay of tRCON should be allowed for the
RC oscillator to stabilize (see Table 23).
0 = The EEPROM section uses the CPU clock.
NOTE:
The EERC bit should always be set if the bus frequency falls below 1.0
MHz.
EEPGM — EEPROM programming power enable/disable
1 = Voltage from the charge pump is supplied to the EEPROM
array in order that programming or erasing may take place.
0 = Voltage from the charge pump is removed from the EEPROM
array.
EEPROM
programming and
erasing
procedures
To program a byte of EEPROM, set EELATCH = CPEN = 1, set ER1 =
ER0 = 0, write data to the desired address and then set EEPGM for a
time tEPGM.
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Memory and Registers
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There are three possibilities for erasing data from the EEPROM array,
depending on the amount of data to be affected.
•
To erase a byte of EEPROM, set EELATCH = CPEN = 1, set ER1
= 0 and ER0 = 1, write data to the desired address and then set
EEPGM for a time tEBYT (see Table 23).
•
To erase a block of EEPROM, set EELATCH = CPEN = 1, set ER1
= 1 and ER0 = 0, write data to any address in the block and then
set EEPGM for a time tEBLOCK (see Table 23).
•
To bulk erase the EEPROM, set EELATCH = CPEN = 1, set ER1
= ER0 = 1, write data to any address in the array and then set
EEPGM for a time tEBULK (see Table 23).
To terminate the programming or erase sequence, clear EEPGM, wait
for a time tFPV to allow the programming voltage to fall, and then clear
EELATCH and CPEN to release the buses (see Table 23). Following
each erase or programming sequence, clear all programming control
bits.
Example program
The following program is an example of the EEPROM programming
sequence using the timer to implement the required delay and assuming
a 1 MHz bus frequency.
TCSR
REGISTER
TCNT
TOF
PROG
CPEN
ER1
ER0
EELATCH
EERC
EEPGM
EESTART
SUMPIN
ORG
START
EQU
$0008
TIMER CONTROL AND STATUS
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
$0009
7
$001C
6
4
3
2
1
0
$0100
$FF
TIMER COUNTER REGISTER
TOF BIT OF TCSR
EEPROM PROGRAM REGISTER
CHARGE PUMP ENABLE BIT
ERASE SELECT BIT 1
ERASE SELECT BIT 0
LATCH BIT
RC/OSC SELECTOR BIT
EEPROM PROGRAM BIT
STARTING ADDRESS OF EEPROM
DUMMY DATA
EQU
BSET
BSR
BSET
BSET
$1000
*
EERC, PROG
DELAY
CPEN, PROG
EELATCH, PROG
SELECT RC OSCILLATOR
RC OSCILLATOR STABILIZATION
TURN ON CHARGE PUMP
ENABLE LATCH BIT
MC68HC05E6 — Rev. 1.0
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EEPROM
Freescale Semiconductor, Inc...
OK
BCLR
BCLR
ER1, PROG
ER0, PROG
SELECT PROGRAM (NOT ERASE)
SELECT PROGRAM (NOT ERASE)
LDA
STA
BSET
JSR
BCLR
#SUMPIN
EESTART
EEPGM, PROG
DELAY
EEPGM, PROG
GET DATA
JSR
BCLR
BCLR
CMP
BNE
CLC
DELAY
EELATCH, PROG
CPEN, PROG
EESTART
OUT1
WAIT FOR PROG VOLTAGE TO FALL
CLEAR LATCH
DISABLE CHARGE PUMP
VERIFY
OUT
RTS
OUT1
SEC
RTS
ENABLE PROGRAMMING POWER
WAIT FOR PROGRAMMING TIME
CLEAR EEPGM
CLEAR CARRY BIT IF NO ERROR
FLAG AN ERROR
*THIS ROUTINE GIVES A 15MS (+/-1MS) DELAY AT 1 MHZ BUS. THE SAME
*DELAY ROUTINE IS USED IN THIS EXAMPLE FOR SIMPLICITY, USING THE
*LONGEST DELAY TIME. USERS WILL WANT TO WRITE SHORTER DELAY
*ROUTINES FOR APPLICATIONS IN WHICH SPEED IS IMPORTANT.
DELAY
TIMLP
EQU
LDX
BSET
BRCLR
DECX
BNE
RTS
*
#15
3, TCSR
TOF, TCSR, *
COUNT OF 15
CLEAR TOF
WAIT FOR TOF FLAG
TIMLP
COUNT DOWN TO 0
MC68HC05E6 — Rev. 1.0
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Memory and Registers
MC68HC05E6
Registers
$0000
I/O
(32 bytes)
$0020
Reserved
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$0080
$00C0
$00FF
$0100
RAM
(128 bytes)
Stack
EEPROM
(160 bytes)
$01A0
Reserved
MC68HC705E6
$0800
$0700
User ROM
(6000 bytes)
User EPROM
(6144 bytes)
$1F70
$1F00
Reserved
Bootloader
ROM
(240 bytes)
$1FF0
Port A data (PORTA)
$00
Port B data (PORTB)
Port C data (PORTC)
$01
Port D data (PORTD)
$03
Port A data direction (DDRA)
$04
Port B data direction (DDRB)
Port C data direction (DDRC)
$05
Port D data direction (DDRD)
$07
Core timer control & status (CTCSR)
$08
Core timer counter (CTCR)
$09
Port C select/interrupt (SEL)
$0A
Port D configuration (CONFD)
$0B
Port G data (PORTG)
$0C
Reserved
Port C configuration (CONFC)
$0D
LVI/options (LVIOPT)
$0F
$1FFF
User vectors
(16 bytes)
$06
$0E
A/D data (ADDAT)
$10
A/D status/control (ADSTAT)
$11
Timer control (TCR)
$12
Timer status (TSR)
$13
Input capture high (ICH)
$14
Input capture low (ICL)
$15
Output compare high (OCH)
$16
Output compare low (OCL)
$17
Timer counter high (TCH)
$18
Timer counter low (TCL)
$19
Alternate counter high (TCH)
$1A
Alternate counter low (TCL)
$1B
EEPROM programming(EPROG)
$1C
EPROM programming(PROG)
$1D
$1E
Reserved
$1FEF
User vectors
(16 bytes)
$02
$1F
COPCLR
$1FF0
Reserved
$1FF1
Keyboard wake-up
$1FF2–$1FF3
16-bit timer
$1FF4–$1FF5
LVI
$1FF6–$1FF7
Core timer
$1FF8–$1FF9
IRQ
$1FFA–$1FFB
SWI
$1FFC–$1FFD
RESET
$1FFE–$1FFF
Figure 7 Memory map of the MC68HC05E6 and MC68HC705E6
MC68HC05E6 — Rev. 1.0
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EEPROM
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Table 3 Register outline
Address
Port A data (PORTA)
$0000
Undefined
Port B data (PORTB)
$0001
Undefined
Port C data (PORTC)
$0002
Undefined
Port D data (PORTD)
$0003
Undefined
Port A data direction (DDRA)
$0004
0000 0000
Port B data direction (DDRB)
$0005
0000 0000
Port C data direction (DDRC)
$0006
0000 0000
Port D data direction (DDRD)
$0007
0000 0000
Core timer control/status (CTCSR) $0008
Core timer counter (CTCR)
$0009
bit 7
CTOF
bit 6
RTIF
bit 5
bit 4
CTOFE RTIE
bit 3
RTOF
bit 2
RRTIF
bit 1
RT1
bit 0
State on
Reset
Register name
RT0
0000 0011
0000 0000
KSF
KIE
SEL1
KIRST
SEL0
000u uu00
Keyboard/timer (KEY/TIM)
$000A
Port D configuration (CONFD)
$000B
0000 0000
Port G data (PORTG)
$000C
Undefined
Reserved
$000D
Port C configuration (CONFC)
$000E
LVI/options (LVIOPT)
$000F
A/D data (ADDATA)
$0010
A/D status/control (ADSTAT)
$0011
0000 0000
LVIINT LVIVAL LVIRST
COP(1)
LVIE
IRQ
0u00 uu00
Undefined
COCO ADRC ADON
0
0
CH2
CH1
CH0
0u00 0uuu
Timer control (TCR)
$0012
ICIE
OCIE
TOIE
0
0
0
IEDG
OLV
0000 00u0
Timer status (TSR)
$0013
ICF
OCF
TOF
0
0
0
0
0
0000 0000
Input capture high (ICH)
$0014
(bit 15)
(bit 8)
Undefined
Input capture low (ICL)
$0015
Output compare high (OCH)
$0016
Output compare low (OCL)
$0017
Timer counter high (TCH)
$0018
Timer counter low (TCL)
$0019
Alternate counter high (ACH)
$001A
Alternate counter low (ACL)
$001B
EEPROM programming (EPROG) $001C
EPROM programming
(PROG)(1)
Reserved
COPCLR
$001D
Undefined
(bit 15)
(bit 8)
Undefined
Undefined
(bit 15)
(bit 8) 1111 1111
1111 1100
(bit 15)
(bit 8) 1111 1111
1111 1100
0
CPEN
0
ER1
0
0
0
0
ER0 EELATCH EERC EEPGM 0000 0000
0
ELATCH
0
EPGM 0000 0000
$001E
$001F
$1FF0
1. MC68HC705E6 only
CCLR 0000 0000
u = undefined
MC68HC05E6 — Rev. 1.0
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Memory and Registers
MC68HC05E6 — Rev. 1.0
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Input/Output Ports
Input/Output Ports
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Introduction
In single chip mode, the MC68HC05E6 has a total of 32 I/O lines,
arranged as three 8-bit I/O ports (A, B and D), one 8-bit I/O port (C)
which shares two pins with the timer subsystem, and one 4-bit input-only
port (G) which is shared with the A/D converter. Each I/O line is
individually programmable as either input or output, under the software
control of the data direction registers. All of the port C pins can be
configured to respond to keyboard interrupts.
To avoid glitches on the output pins, data should be written to the I/O port
data register before writing ones to the corresponding data direction
register bits to set the pins to output mode.
MC68HC05E6 — Rev. 1.0
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Input/output programming
The bidirectional port lines may be programmed as inputs or outputs
under software control. The direction of each pin is determined by the
state of the corresponding bit in the port data direction register (DDR).
Each I/O port has an associated DDR. Any I/O port pin is configured as
an output if its corresponding DDR bit is set. A pin is configured as an
input if its corresponding DDR bit is cleared.
M68HC05 internal connections
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At power-on or reset, all DDRs are cleared, thus configuring all port pins
as inputs. The data direction registers can be written to or read by the
MCU. During the programmed output state, a read of the data register
actually reads the value of the output data buffer and not the I/O pin. The
operation of the standard port hardware is shown schematically in
Figure 8.
Data direction
register bit
DDRn
Latched data
register bit
DATA
Output
buffer
O/P
data
buffer
Input
buffer
I/O
pin
DDRn
DATA
I/O Pin

Output 
1
0
0
1
1
1


0
0
tristate
0
1
tristate
Input
Figure 8 Standard I/O port structure
This is further summarized in Table 4, which shows the effect of reading
from, or writing to an I/O pin in various circumstances. Note that the
read/write signal shown is internal and not available to the user.
Table 4 I/O pin states
R/W
0
0
1
1
DDRn
0
1
0
1
Action of MCU write to/read of data bit
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch, and output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in output mode. The output data latch is read.
MC68HC05E6 — Rev. 1.0
2-ports
Input/Output Ports
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Input/Output Ports
Port A
Port A
This 8-bit port comprises a data register and a data direction register.
When the pins of port A are configured as inputs they have fixed pull-up
resistors connected to them.
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The pull-ups and pull-downs associated with ports A, B and C are MOS
transistors which vary with the supply voltage and the loading on the
pins.
Reset does not affect the state of the data register, but clears the data
direction register, thereby returning all port pins to input mode with
pull-up resistors. Writing a ‘1’ to any DDR bit sets the corresponding port
pin to output mode.
Port B
This 8-bit port comprises a data register and a data direction register.
When the pins of port B are configured as inputs they have fixed
pull-down resistors connected to them.
Reset does not affect the state of the data register, but clears the data
direction register, thereby returning all port pins to input mode with
pull-down resistors. Writing a ‘1’ to any DDR bit sets the corresponding
port pin to output mode.
NOTE:
PB5–PB7 are not available in the 28-pin package.
Port C
This 8-bit bidirectional port shares two of its pins with the timer
subsystem and comprises a data register (PORTC), a data direction
register (DDRC) and a configuration register (CONFC). The behaviour
of the port C I/O pins is determined by the configuration of the DDRC and
the CONFC registers as shown in Table 5. During power-on or reset, all
MC68HC05E6 — Rev. 1.0
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port C registers are cleared, thereby returning the port pins to normal
inputs with pull-up resistors.
Table 5 Port C I/O pin configurations
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DDRC CONFC
Function
0
0
Input with pull-up
0
1
Input without pull-up
1
0
Push-pull output
1
1
Open-drain output
NOTE:
Due to an internal clamp diode, the pins cannot be pulled higher than
VDD, even when configured as open-drain outputs, that is, maximum
ratings for input voltage still apply to open drain outputs.
When configured as input pins, port C bits 0–7 provide a wired-OR
keyboard interrupt facility and will generate an interrupt, provided the
keyboard interrupt enable bit (KIE) in the keyboard/timer register
(KEY/TIM) is set. When configured as inputs with keyboard interrupt
capability, the pins can also have pull-ups connected to them by
correctly configuring the DDRC and CONFC bits as outlined in Table 5.
The structure of the port C pins is shown diagrammatically in Figure 9.
Once a high to low transition is sensed on any of the port C lines
(PC0–PC7) configured as inputs and not being used by the timer, a
keyboard interrupt will be generated and the keyboard status flag will be
set, provided the interrupt mask bit of the condition code register is
cleared and KIE is set. The interrupt service routine is specified by the
contents of the memory locations $1FF2 and $1FF3. The interrupt is
cleared by writing a ‘1’ to the KIRST bit in the KEY/TIM register. The
keyboard interrupt is negative edge-and-level sensitive and will force the
processor out of STOP or WAIT mode.
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Port C
KIE bit
Internal
interrupt
Edge
detect
PC0–PC7
VDD
Bit x
CONFC
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DDRn
PCx
Input
buffer
DBx
Output
data buffer
Latched
register
Output
buffer
Figure 9 Port C keyboard interrupt function
NOTE:
PC6 and PC7 are not available in the 28-pin package.
Keyboard/timer
register (KEY/TIM)
Address bit 7
Keyboard/timer (KEY/TIM)
$000A
KSF
bit 6
bit 5
KIE
KIRST
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
SEL1 SEL0 0000 0000
KSF — Keyboard status flag
1 = This read-only flag is set when there is a high to low transition
on any of the port C pins configured as inputs.
0 = No high to low transition has been detected on any of the port
C pins configured as inputs.
Writing a ‘1’ to KIRST will clear the interrupt status flag.
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KIE — Keyboard interrupt enable
1 = A keyboard interrupt will be generated if KSF is set and the I-bit
in the CCR is clear.
0 = No keyboard interrupt will be generated, regardless of the state
of the KSF flag and the I-bit.
KIRST — Keyboard interrupt reset
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This bit should be set at the end of the interrupt service routine in
order to clear the status flag (KSF). KIRST always reads zero.
Clearing this bit has no effect.
SEL1 — Timer select bit 1
In addition to its normal I/O function, PC1 is shared with the output
compare function (TCMP) of the programmable timer. The SEL1 bit
switches the pin between the two functions.
1 = Port C bit 1 is configured as the TCMP pin of the programmable
timer.
0 = Port C bit 1 is configured as a standard I/O pin.
Clearing CONFC bit 1 makes TCMP a push-pull output, while setting
this bit creates an open-drain output.
SEL0 — Timer select bit 0
In addition to its normal I/O function, PC0 is shared with the input
capture function (TCAP) of the programmable timer. The SEL0 bit
switches the pin between the two functions.
1 = Port C bit 0 is configured as the TCAP pin of the programmable
timer.
0 = Port C bit 0 is configured as a standard I/O pin.
An internal pull-up resistor can be connected to the pin by clearing bit
0 of the CONFC register; alternatively it can be disconnected by
setting this bit.
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Port D
Port D
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Port D is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. Port D comprises a data register (PORTD), a
data direction register (DDRD) and a configuration register (CONFD).
The behaviour of the port D I/O pins is determined by the configuration
of the DDRD and the CONFD registers as shown in Table 6. During
power-on or reset, all port D registers are cleared, thereby returning the
port pins to normal inputs with pull-up resistors.
Table 6 Port D I/O pin configurations
DDRD CONFD
Function
0
0
Input with pull-up
0
1
Input without pull-up
1
0
Push-pull output
1
1
Open-drain output
NOTE:
PD0–PD7 are not available in the 28-pin package.
NOTE:
Due to an internal clamp diode, the pins cannot be pulled higher than
VDD, even when configured as open-drain outputs, that is, maximum
ratings for input voltage still apply to open drain outputs.
Port G
Port G is a 4-bit input-only port which shares all of its pins with the A/D
converter. When the A/D converter is enabled, PG0–PG3 read the four
analog inputs. Port G can be read at any time, however reading the port
during an A/D conversion sequence may inject noise on the analog
inputs, resulting in reduced accuracy of the conversion. Because port G
is an input-only port, there is no data direction register associated with it.
NOTE:
PG1–PG3 are not available in the 28-pin package, therefore the A/D
converter has only one input channel.
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The A/D converter is enabled by setting the ADON bit in the A/D
status/control (ADSTAT) register.
Address bit 7
A/D status/control (ADSTAT)
bit 6
bit 5
$0011 COCO ADRC ADON
State
on reset
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
CH2
CH1
CH0 0u00 0uuu
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ADON — A/D converter enable/disable
1 = A/D converter is enabled.
0 = A/D converter is disabled.
The shaded bits in the ADSTAT register are described fully in A/D
status/control register (ADSTAT).
NOTE:
Performing a digital read of port G with levels other than VDD or VSS on
the pins will result in greater power dissipation during the read cycles.
Port registers
The following sections explain in detail the individual bits in the data and
control registers associated with the ports.
Port data registers
(PORTA, PORTB,
PORTC and PORTD)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port A data (PORTA)
$0000
Undefined
Port B data (PORTB)
$0001
Undefined
Port C data (PORTC)
$0002
Undefined
Port D data (PORTD)
$0003
Undefined
For all port registers, each bit can be configured as input or output via
the corresponding data direction bit in the port data direction register
(DDRx).
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Port registers
Port G data
register (PORTG)
Address bit 7
Port G data (PORTG)
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$000C
State
on reset
Undefined
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Port G is a 4-bit input-only port and therefore has no data direction
register associated with it.
Data direction
registers (DDRA,
DDRB, DDRC and
DDRD)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port A data direction (DDRA)
$0004
0000 0000
Port B data direction (DDRB)
$0005
0000 0000
Port C data direction (DDRC)
$0006
0000 0000
Port D data direction (DDRD)
$0007
0000 0000
Writing a ‘1’ to any bit configures the corresponding port pin as an output;
conversely, writing any bit to ‘0’ configures the corresponding port pin as
an input.
Reset clears these registers, thus configuring all pins as inputs.
Port configuration
registers (CONFC
and CONFD)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port C configuration (CONFC)
$000E
0000 0000
Port D configuration (CONFD)
$000B
0000 0000
The port configuration registers (CONFC and CONFD) are used in
conjunction with the data direction registers of ports C and D to correctly
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configure the input/output pin. The effect of setting or clearing bits in
these registers is shown in Table 5.
Table 7 Port C and port D I/O pin configurations
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DDRx
0
0
1
1
CONFx
0
1
0
1
Function
Input with pull-up
Input without pull-up
Push-pull output
Open-drain output
Reset clears both of these registers.
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Core Timer
Core Timer
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Real time interrupts (RTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Computer operating properly (COP) watchdog timer . . . . . . . . . . . . . 47
Core timer registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Core timer during WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Core timer during STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Introduction
The MC68HC05E6 has a 15-stage ripple counter called the core timer
(CTIMER). Features of this timer are: timer overflow, power-on reset
(POR), real time interrupt (RTI) with four selectable interrupt rates, and
a computer operating properly (COP) watchdog timer.
As shown in Figure 10, the timer is driven by the internal bus clock
divided by four with a fixed prescaler. This signal drives an 8-bit ripple
counter. The value of this 8-bit ripple counter can be read by the CPU at
any time, by accessing the CTIMER counter register (CTCR) at address
$09. A timer overflow function is implemented on the last stage of this
counter, giving a possible interrupt at the rate of fOP/1024. (The POR
signal (tPORL) is also derived from this register, at fOP/4064.) The
counter register circuit is followed by four more stages, with the resulting
clock (fOP/16384) driving the real time interrupt circuit. The RTI circuit
consists of three divider stages with a 1-of-4 selector. The output of the
RTI circuit is further divided by eight to drive the COP watchdog timer
circuit. The RTI rate selector bits, and the RTI and CTIMER overflow
enable bits and flags, are located in the CTIMER control and status
register (CTCSR) at location $08.
MC68HC05E6 — Rev. 1.0
1-ctimer
Core Timer
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Core Timer
Internal bus
8
Internal processor clock
fOP
$09 CTCR
(Core timer counter)
fOP / 22
8
(÷4)
fOP / 210
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7-bit counter
Overflow
detect
circuit
fOP / 217
fOP / 214
COP
clear
RTI select circuit
$08 CTCSR
(Core timer control & status)
8
CTOF RTIF CTOFE RTIE RCTOF RRTIF RT1
RT0
COP watchdog
timer
(÷8)
Interrupt circuit
To interrupt logic
To
reset
logic
Figure 10 Core timer block diagram
CTOF (core timer overflow flag) is a read-only status bit which is set
when the 8-bit ripple counter rolls over from $FF to $00. A CPU interrupt
request will be generated if CTOFE is set. Clearing CTOF is done by
writing a ‘1’ to the RCTOF bit (bit 3) in the CTCSR. Reset clears CTOF.
When CTOFE (core timer overflow enable) is set, a CPU interrupt
request is generated when the CTOF bit is set. Reset clears CTOFE.
The core timer counter register (CTCR) is a read-only register that
contains the current value of the 8-bit ripple counter at the beginning of
the timer chain. This counter is clocked at fOP/4 and can be used for
various functions including a software input capture. Extended time
MC68HC05E6 — Rev. 1.0
2-ctimer
Core Timer
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Real time interrupts (RTI)
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periods can be attained using the CTIMER overflow function to
increment a temporary RAM storage location thereby simulating a 16-bit
(or more) counter.
The power-on cycle clears the entire counter chain and begins clocking
the counter. After tPORL cycles, the power-on reset circuit is released,
which again clears the counter chain and allows the device to come out
of reset. At this point, if RESET is not asserted, the timer will start
counting up from zero and normal device operation will begin. When
RESET is asserted at any time during operation (other than POR), the
counter chain will be cleared.
Real time interrupts (RTI)
The real time interrupt circuit consists of a three stage divider and a
1-of-4 selector. The clock frequency that drives the RTI circuit is fOP/214
(or fOP/16384), with three additional divider stages. Register details are
given in Core timer registers.
Computer operating properly (COP) watchdog timer
The COP watchdog timer function is implemented by taking the output
of the RTI circuit and further dividing it by eight, as shown in Figure 10.
Note that the minimum COP timeout period is seven times the RTI
period. This is because the COP will be cleared asynchronously with
respect to the value in the core timer counter register/RTI divider, hence
the actual COP timeout period will vary between 7x and 8x the RTI
period.
The COP function is a mask option, enabled or disabled during device
manufacture. On the MC68HC705E6, the COP function is controlled
using the COP bit in the LVI/options register (see Mask options).
MC68HC05E6 — Rev. 1.0
3-ctimer
Core Timer
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Core Timer
COP clear register
(COPCLR)
If the COP circuit times out, an internal reset is generated and the normal
reset vector is fetched. COP timeout is prevented by writing a ‘0’ to bit 0
(CCLR) of the COPCLR register (address $1FF0). When the COP is
cleared, only the final divide-by-eight stage is cleared (see Figure 10).
Address bit 7
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COPCLR
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
$1FF0
bit 0
State
on reset
CCLR 0000 0000
Core timer registers
Core timer control
and status register
(CTCSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Core timer control/status (CTCSR) $0008 CTOF RTIF CTOFE RTIE RCTOF RRTIF RT1
bit 0
State
on reset
RT0 uu00 0011
CTOF — Core timer overflow
1 = This read-only flag is set whenever a core timer overflow
occurs.
0 = No core timer overflow has occurred.
This bit is set when the core timer counter register rolls over from $FF
to $00; an interrupt request will be generated if CTOFE is set. When
set, the bit may be cleared by writing a ‘1’ to the RCTOF bit.
RTIF — Real time interrupt flag
1 = This read-only flag is set when the pre-selected RTI period has
elapsed. The RTI period is selected using the RT0 and RT1
bits as shown in Table 8.
0 = The pre-selected RTI period has not elapsed.
This bit is set when the output of the chosen stage becomes active;
an interrupt request will be generated if RTIE is set. When set, the bit
may be cleared by writing a ‘1’ to the RRTIF bit.
MC68HC05E6 — Rev. 1.0
4-ctimer
Core Timer
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Core Timer
Core timer registers
CTOFE — Core timer overflow interrupt enable
1 = A core timer overflow interrupt will be generated if CTOF is set
and the I-bit in the CCR is clear.
0 = No core timer overflow interrupt will be generated regardless of
the state of the CTOF flag and the I-bit.
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RTIE — Real time interrupt enable
1 = A real time interrupt will be generated if RTIF is set and the I-bit
in the CCR is clear.
0 = No real time interrupt will be generated regardless of the state
of the RTIF flag and the I-bit.
RCTOF — Reset core timer overflow flag
This bit always reads as zero. Writing a ‘1’ to the RCTOF bit clears the
timer overflow flag. Writing a ‘0’ to it has no effect.
RRTIF — Reset real time interrupt flag
This bit always reads as zero. Writing a ‘1’ to the RRTIF bit clears the
real time interrupt flag. Writing a ‘0’ to it has no effect.
RT1, T0 — Real time interrupt rate select
These two bits select one of four taps from the real time interrupt
circuitry. Reset sets both RT0 and RT1 to one, selecting the lowest
periodic rate and therefore the maximum time in which to alter them if
necessary. The COP reset times are also determined by these two
bits. Care should be taken when altering RT0 and RT1 if a timeout is
imminent, or if the timeout period is uncertain. If the selected tap is
modified during a cycle in which the counter is switching, an RTIF
could be missed or an additional one could be generated. To avoid
problems, the COP should be cleared before changing the RTI taps.
See Table 8 for some example RTI periods.
MC68HC05E6 — Rev. 1.0
5-ctimer
Core Timer
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Core Timer
Table 8 Example RTI periods
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Bus frequency
fOP = 500 kHz
RT1
RT0
Division
ratio
RTI
period
0
0
1
1
0
1
0
1
214
215
216
217
32.8ms
65.5ms
131.1ms
262.1ms
Bus frequency
fOP = 1 MHz
Minimum
COP
period
229.38ms
458.75ms
917.5ms
1.835s
RTI
period
16.4ms
32.8ms
65.5ms
131.1ms
Bus frequency
fOP = 2 MHz
Minimum
COP
period
114.69ms
229.38ms
458.75ms
917.50ms
RTI
period
8.2ms
16.4ms
32.8ms
65.5ms
Minimum
COP
period
57.34ms
114.69ms
229.38ms
458.75ms
Core timer counter
register (CTCR)
Address bit 7
Core timer counter (CTCR)
bit 6
bit 5
bit 4
bit 3
$0009
bit 2
bit 1
bit 0
State
on reset
0000 0000
The core timer counter register is a read-only register, which contains
the current value of the 8-bit ripple counter at the beginning of the timer
chain. Reset clears this register.
Core timer during WAIT
The CPU clock halts during the WAIT mode, but the core timer remains
active. If the CTIMER interrupts are enabled, then a CTIMER interrupt
will cause the processor to exit the WAIT mode.
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited
by an external interrupt or an external reset, the internal oscillator will
restart, followed by an internal processor stabilization delay (tPORL). The
timer is then cleared and operation resumes.
MC68HC05E6 — Rev. 1.0
6-ctimer
Core Timer
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Programmable Timer
Programmable Timer
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Keyboard/timer register (KEY/TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Timer functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Timer during WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Timer during STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Timer state diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Introduction
The programmable timer on the MC68HC05E6 consists of a 16-bit
read-only free-running counter, with a fixed divide-by-four prescaler,
plus the input capture/output compare circuitry. Selected input edges
cause the current counter value to be latched into a 16-bit input capture
register so that software can later read this value to determine when the
edge occurred. When the free running counter value matches the value
in the output compare registers, the programmed pin action takes place.
Refer to Figure 11 for a block diagram of the timer. The input capture and
output compare functions can only be enabled by setting bit 0 and bit 1
of the keyboard/timer register.
MC68HC05E6 — Rev. 1.0
1-ptimer
Programmable Timer
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Programmable Timer
Keyboard/timer register (KEY/TIM)
Address bit 7
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Keyboard/timer (KEY/TIM)
$000A
KSF
bit 6
bit 5
KIE
KIRST
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
SEL1 SEL0 0000 0000
SEL1 — Timer select bit 1
1 = Port C bit 1 is configured as the TCMP pin of the programmable
timer.
0 = Port C bit 1 is configured as a standard I/O pin.
SEL0 — Timer select bit 0
1 = Port C bit 0 is configured as the TCAP pin of the programmable
timer.
0 = Port C bit 0 is configured as a standard I/O pin.
The timer has a 16-bit architecture, hence each specific functional
segment is represented by two 8-bit registers. These registers contain
the high and low byte of that functional segment. Accessing the low byte
of a specific timer function allows full control of that function; however,
an access of the high byte inhibits that specific timer function until the low
byte is also accessed.
NOTE:
The I-bit in the CCR should be set while manipulating both the high and
low byte register of a specific timer function to ensure that an interrupt
does not occur.
Counter
The key element in the programmable timer is a 16-bit, free-running
counter, or counter register, preceded by a prescaler that divides the
internal processor clock by four. The prescaler gives the timer a
resolution of 2µs if the internal bus clock is 2MHz. The counter is
incremented during the low portion of the internal bus clock. Software
can read the counter at any time without affecting its value.
MC68HC05E6 — Rev. 1.0
2-ptimer
Programmable Timer
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Programmable Timer
Counter
Internal bus
8
Internal
processor
clock
High
byte
Low
byte
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Output
compare
register
$16
8-bit
buffer
High
byte
fOP
(÷4)
$17
Low byte
16-bit
free-running
counter
$18
Alternate
counter
register
$1A
Output
compare
circuit
High
byte
Low
byte
$14
Input
capture
register
$19
$15
$1B
Overflow
detect
circuit
Edge
detect
circuit
Output level
register
CLK
ICF
OCF
TOF
D C Q
$13 TSR
(Timer status register)
ICIE
OCIE TOIE
0
0
0
IEDG
OLV
RESET
$12 TCR
(Timer control register)
TCMP
(Output level)
Interrupt circuit
TCAP
(Input edge)
Figure 11 16-bit programmable timer block diagram
MC68HC05E6 — Rev. 1.0
3-ptimer
Programmable Timer
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Programmable Timer
Counter high
register, Counter
low register,
Alternate counter
high register,
Alternate counter
low register
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Address bit 7
Timer counter high (TCH)
$0018 (bit 15)
Timer counter low (TCL)
$0019
Alternate counter high (ACH)
$001A (bit 15)
Alternate counter low (ACL)
$001B
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
(bit 8) 1111 1111
1111 1100
(bit 8) 1111 1111
1111 1100
The double-byte, free-running counter can be read from either of two
locations, the counter register at $18 – $19 or the alternate counter
register at $1A – $1B. A read from only the less significant byte (LSB) of
the free-running counter, $19 or $1B, receives the count value at the
time of the read. If a read of the free-running counter or alternate counter
register first addresses the more significant byte (MSB), $18 or $1A, the
LSB is transferred to a buffer. This buffer value remains fixed after the
first MSB read, even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or alternate counter
register LSB and thus completes a read sequence of the total counter
value. In reading either the free-running counter or alternate counter
register, if the MSB is read, the LSB must also be read to complete the
sequence. If the timer overflow flag (TOF) is set when the counter
register LSB is read, then a read of the TSR will clear the flag.
The alternate counter register differs from the counter register only in
that a read of the LSB does not clear TOF. Therefore, to avoid the
possibility of missing timer overflow interrupts due to clearing of TOF, the
alternate counter register should be used where this is a critical issue.
The free-running counter is set to $FFFC during reset and is always a
read-only register. During a power-on reset, the counter is also preset to
$FFFC and begins running after the oscillator start-up delay. Because
the free-running counter is 16 bits preceded by a fixed divide-by-four
prescaler, the value in the free-running counter repeats every 262144
MC68HC05E6 — Rev. 1.0
4-ptimer
Programmable Timer
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Programmable Timer
Timer functions
internal bus clock cycles. TOF is set when the counter overflows (from
$FFFF to $0000); this will cause an interrupt if TOIE is set.
Bits 8 – 15 — MSB of counter/alternate counter register
A read of only the more significant byte (MSB) transfers the LSB to a
buffer, which remains fixed after the first MSB read, until the LSB is also
read.
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Bits 0 – 7 — LSB of counter/alternate counter register
A read of only the less significant byte (LSB) receives the count value at
the time of reading.
Timer functions
The 16-bit programmable timer is monitored and controlled by a group
of ten registers, full details of which are contained in the following
paragraphs. An explanation of the timer functions is also given.
Timer control
register Ð TCR
The timer control register at location $12 is used to enable the input
capture (ICIE), output compare (OCIE), and timer overflow (TOIE)
interrupt enable functions as well as selecting input edge sensitivity
(IEDG) and output level polarity (OLV).
Address bit 7
Timer control (TCR)
$0012
ICIE
State
on reset
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OCIE
TOIE
0
0
0
IEDG
OLV 0000 00u0
ICIE — Input capture interrupt enable
1 = Input capture interrupt enabled.
0 = Input capture interrupt disabled.
OCIE — Output compare interrupt enable
1 = Output compare interrupt enabled.
0 = Output compare interrupt disabled.
MC68HC05E6 — Rev. 1.0
5-ptimer
Programmable Timer
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Programmable Timer
TOIE — Timer overflow interrupt enable
1 = Timer overflow interrupt enabled.
0 = Timer overflow interrupt disabled.
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IEDG — Input edge
1 = TCAP is positive-going edge sensitive.
0 = TCAP is negative-going edge sensitive.
When IEDG is set, a positive-going edge on the TCAP pin will trigger
a transfer of the free-running counter value to the input capture
register. When clear, a negative-going edge triggers the transfer.
OLV — Output level
1 = A high output level will appear on the TCMP pin.
0 = A low output level will appear on the TCMP pin.
When OLV is set, a high output level will be clocked into the output
level register by the next successful output compare, and will appear
on the TCMP pin. When clear, it will be a low level that will appear on
the TCMP pin.
Timer status
register Ð TSR
The timer status register at location ($13) contains the status bits for the
input capture, output compare and timer overflow interrupt conditions.
Accessing the timer status register satisfies the first condition required
to clear the status bits. The remaining step is to access the register
corresponding to the status bit.
Address bit 7
Timer status (TSR)
$0013
ICF
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
OCF
TOF
0
0
0
0
0
uuu0 0000
ICF — Input capture flag
1 = A valid input capture has occurred.
0 = No input capture has occurred.
This bit is set when the selected polarity of edge is detected by the
input capture edge detector; an input capture interrupt will be
generated if ICIE is set. ICF is cleared by reading the TSR and then
the input capture low register at $15.
MC68HC05E6 — Rev. 1.0
6-ptimer
Programmable Timer
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Programmable Timer
Timer functions
OCF — Output compare flag
1 = A valid output compare has occurred.
0 = No output compare has occurred.
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This bit is set when the output compare register contents match those
of the free-running counter; an output compare interrupt will be
generated if OCIE is set. OCF is cleared by reading the TSR and then
the output compare low register at $17.
TOF — Timer overflow flag
1 = Timer overflow has occurred.
0 = No timer overflow has occurred.
This bit is set when the free-running counter overflows from $FFFF to
$0000; a timer overflow interrupt will occur if TOIE is set. TOF is
cleared by reading the TSR and the counter low register at $19.
When using the timer overflow function and reading the free-running
counter at random times to measure an elapsed time, a problem may
occur whereby the timer overflow flag is unintentionally cleared if:
1. the timer status register is read or written when TOF is set and
2. the LSB of the free-running counter is read, but not for the purpose
of servicing the flag.
Reading the alternate counter register instead of the counter register
will avoid this potential problem.
Input capture
function
‘Input capture’ is a technique whereby an external signal (connected to
the TCAP pin) is used to trigger a read of the free-running counter. In this
way it is possible to relate the timing of an external signal to the internal
counter value, and hence to elapsed time.
MC68HC05E6 — Rev. 1.0
7-ptimer
Programmable Timer
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Programmable Timer
Input capture high
register, Input
capture low
register
Address bit 7
Input capture high (ICH)
$0014 (bit 15)
Input capture low (ICL)
$0015
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
(bit 8) Undefined
Undefined
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The two 8-bit registers that make up the 16-bit input capture register are
read-only, and are used to latch the value of the free-running counter after
the input capture edge detector senses a valid transition. The level
transition that triggers the counter transfer is defined by the input edge bit
(IEDG). The most significant 8 bits are stored in the input capture high
register at $14, the least significant in the input capture low register at $15.
The result obtained from an input capture will be one greater than the
value of the free-running counter on the rising edge of the internal bus
clock preceding the external transition. This delay is required for internal
synchronisation. Resolution is one count of the free-running counter,
which is four internal bus clock cycles. The free-running counter
contents are transferred to the input capture register on each valid signal
transition whether the input capture flag (ICF) is set or clear. The input
capture register always contains the free-running counter value that
corresponds to the most recent input capture. After a read of the input
capture register MSB ($14), the counter transfer is inhibited until the LSB
($15) is also read. This characteristic causes the time used in the input
capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the input capture register
LSB ($15) does not inhibit the free-running counter transfer since the two
actions occur on opposite edges of the internal bus clock.
The contents of the input capture register are undefined following reset.
Output compare
function
‘Output compare’ is a technique that may be used, for example, to
generate an output waveform, or to signal when a specific time period
has elapsed, by presetting the output compare register to the
appropriate value.
MC68HC05E6 — Rev. 1.0
8-ptimer
Programmable Timer
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Programmable Timer
Timer functions
Output compare
high register,
Output compare
low register
Address
bit 7
Output compare high (OCH)
$0016 (bit 15)
Output compare low (OCL)
$0017
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
(bit 8) Undefined
Undefined
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The 16-bit output compare register is made up of two 8-bit registers at
locations $16 (MSB) and $17 (LSB). The contents of the output compare
register are continually compared with the contents of the free-running
counter and, if a match is found, the output compare flag (OCF) in the
timer status register is set and the output level (OLV) bit clocked to the
output level register. The output compare register values and the output
level bit should be changed after each successful comparison to
establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable
bit (OCIE) is set. (The free-running counter is updated every four internal
bus clock cycles.)
After a processor write cycle to the output compare register containing
the MSB ($16), the output compare function is inhibited until the LSB
($17) is also written. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB will not inhibit the
compare function. The processor can write to either byte of the output
compare register without affecting the other byte. The output level (OLV)
bit is clocked to the output level register whether the output compare flag
(OCF) is set or clear. The minimum time required to update the output
compare register is a function of the program rather than the internal
hardware. Because the output compare flag and the output compare
register are not defined at power on, and are not affected by reset, care
must be taken when initialising output compare functions with software.
The following procedure is recommended:
1. write to output compare high to inhibit further compares,
2. read the timer status register to clear OCF (if set,
3. write to output compare low to enable the output compare
function.
MC68HC05E6 — Rev. 1.0
9-ptimer
Programmable Timer
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Programmable Timer
All bits of the output compare register are readable and writable and are
not altered by the timer hardware or reset. If the compare function is not
needed, the two bytes of the output compare register can be used as
storage locations.
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Timer during WAIT mode
In WAIT mode all CPU action is suspended, but the programmable timer
continues counting. An interrupt from an input capture, an output
compare or a timer overflow, if enabled, will cause the processor to exit
WAIT mode.
Timer during STOP mode
In the STOP mode all MCU clocks are stopped, hence the timer stops
counting. If STOP is exited by an interrupt, the counter retains the last
count value. If the device is reset, then the counter is forced to $FFFC.
During STOP, if at least one valid input capture edge occurs at the TCAP
pin, the input capture detect circuit is armed. This does not set any timer
flags nor wake up the MCU. When the MCU does wake up, however,
there is an active input capture flag and data from the first valid edge that
occurred during the STOP period. If the device is reset to exit STOP
mode, then no input capture flag or data remains, even if a valid input
capture edge occurred.
Timer state diagrams
The relationships between the internal clock signals, the counter
contents and the status of the flag bits are shown in the following
diagrams. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
MC68HC05E6 — Rev. 1.0
10-ptimer
Programmable Timer
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Programmable Timer
Timer state diagrams
Internal
processor clock
Internal
reset
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

Internal 
timer clocks


16-bit
counter
T00
T01
T10
T11
$FFFC
$FFFD
$FFFE
$FFFF
External reset
or end of POR
The counter and timer control registers are the only ones affected by power-on
or external reset.
Figure 12 Timer state timing diagram for reset
MC68HC05E6 — Rev. 1.0
11-ptimer
Programmable Timer
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Programmable Timer
Internal
processor clock


Internal
timer clocks 


T10
T11
$F123
$F124
$F125
$F126
}
}
}
Input
edge
T01
}
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16-bit
counter
T00
Internal
capture latch
Input capture
register
$????
$F124
Input capture
flag
If the input edge occurs in the shaded area from one timer state T10 to the next
timer state T10, then the input capture flag will be set during the next T11 state.
Figure 13 Timer state timing diagram for input capture
MC68HC05E6 — Rev. 1.0
12-ptimer
Programmable Timer
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Programmable Timer
Timer state diagrams
Internal
processor clock
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

Internal 
timer clocks


16-bit
counter
T00
T01
T10
T11
$F456
$F457
$F458
$F459
(Note 1)
Output compare
register
Compare register
latch
Output compare
flag and TCMP
CPU writes $F457
$F457
(Note 1)
(Note 2)
(1) The CPU write to the compare registers may take place at any time, but a compare
only occurs at timer state T01. Thus a four cycle difference may exist between the write
to the compare register and the actual compare.
(2) The output compare flag is set at the timer state T11 that follows the comparison
match ($F457 in this example).
Figure 14 Timer state timing diagram for output compare
MC68HC05E6 — Rev. 1.0
13-ptimer
Programmable Timer
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Programmable Timer
Internal
processor clock
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

Internal 
timer clocks


16-bit
counter
T00
T01
T10
T11
$FFFF
$0000
$0001
$0002
Timer overflow
flag
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF
to $0000). It is cleared by a read of the timer status register during the internal
processor clock high time, followed by a read of the counter low register.
Figure 15 Timer state timing diagram for timer overflow
MC68HC05E6 — Rev. 1.0
14-ptimer
Programmable Timer
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A-to-D Converter
A-to-D Converter
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
A/D converter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
A/D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
A/D converter during WAIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
A/D converter during STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A/D analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Introduction
The analog to digital converter system consists of a four-channel,
multiplexed input and a successive approximation A/D converter. The
four A/D input channels are connected to pins PG0–PG3 and the
particular input to be selected is determined by the setting/clearing of the
CHx bits in the A/D status/control register at $11 (ADSTAT). A further
four channels are available internally for test purposes. In addition to the
ADSTAT register there is one 8-bit result data register at address $10
(ADDATA).
NOTE:
PG1–PG3 are not available in the 28-pin package; in this package the
A/D converter has only one external input line.
The A/D converter is ratiometric and a dedicated pin, VREFH, is used to
supply the upper reference voltage level of each analog input. The lower
voltage reference point, VREFL, is internally connected to the VSS pin.
An input voltage equal to or greater than VRH converts to $FF (full scale)
with no overflow indication. For ratiometric conversions, the source of
each analog input should use VREFH as the supply voltage and be
referenced to VREFL.
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A-to-D Converter
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The A/D converter can operate from either the bus clock or an internal
RC type oscillator. The internal RC type oscillator is activated by the
ADRC bit in the A/D status/control register (ADSTAT) and can be used
to give a sufficiently high clock rate to the A/D converter when the bus
speed is too low to provide accurate results (see A/D status/control
register (ADSTAT)). When the A/D converter is not being used it can be
disconnected using the ADON bit in the ADSTAT register, in order to
save power (see A/D status/control register (ADSTAT)).
A/D converter operation
The A/D converter consists of an analog multiplexer, an 8-bit
digital-to-analog capacitor array, a comparator and a successive
approximation register (SAR). See A/D converter block diagram.
There are four A/D input options that can be selected by the multiplexer:
AD0/PG0, AD1/PG1, AD2/PG2 or AD3/PG3. Selection is made via the
CHx bits in the ADSTAT register (see A/D status/control register
(ADSTAT)). These bits can also be used to select one of the internal test
channels.
The A/D reference input (AD0–AD3) is applied to a precision internal
digital-to-analog converter. Control logic drives this D/A converter and
the analog output is successively compared with the analog input
sampled at the beginning of the conversion. The conversion is
monotonic with no missing codes.
The result of each successive comparison is stored in the SAR and,
when the conversion is complete, the contents of the SAR are
transferred to the read-only result data register ($10), and the
conversion complete flag, COCO, is set in the A/D status/control register
($11).
NOTE:
Any write to the A/D status/control register will abort the current
conversion, reset the conversion complete flag and start a new
conversion on the selected channel.
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A/D converter operation
AD3
VRH
VRL
8-bit capacitive DAC
with sample and hold
AD1
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AD0
VRH
Analog MUX
(Channel assignment)
AD2
Successive approximation
register and control
Result
A/D status/control register (ADSTAT) $11
CH0
CH1
CH2
0
0
ADON ADRC COCO
(VRH +VRL)/2
VRL
A/D result register (ADDATA) $10
Figure 16 A/D converter block diagram
At power-on or external reset, both the ADRC and ADON bits are
cleared, thus the A/D is disabled.
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A-to-D Converter
A/D registers
A/D status/control
register (ADSTAT)
Address bit 7
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A/D status/control (ADSTAT)
bit 6
bit 5
$0011 COCO ADRC ADON
State
on reset
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
CH2
CH1
CH0 0u00 0uuu
COCO — Conversion complete flag
Each channel of conversion takes 32 clock cycles at fOP, where fOP is
equal to or greater than 1MHz.
1 = COCO flag is set each time a conversion is complete, allowing
the new result to be read from the A/D result data register
($10). The converter then starts a new conversion.
0 = COCO is cleared by reading the result data register or writing
to the status/control register.
Reset clears the COCO flag.
ADRC — A/D RC oscillator control
If the MCU bus frequency is less than 1MHz, an internal RC oscillator
must be used for the A/D conversion clock. This selection is made by
setting the ADRC bit in ADSTAT. The ADRC bit allows the user to
control the A/D RC oscillator.
1 = The A/D RC oscillator is turned on and, if ADON is set, the A/D
runs from the RC oscillator clock (see Table 9).
0 = The A/D RC oscillator is turned off and, if ADON is set, the A/D
runs from the CPU clock.
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A/D registers
When the A/D RC oscillator is turned on, it takes a time tADRC to
stabilize (see Table 23). During this time A/D conversion results may
be inaccurate.
Table 9 A/D clock selection
ADRC ADON
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0
0
1
1
0
1
0
1
RC
oscillator
OFF
OFF
ON
ON
A/D
converter
OFF
ON
OFF
ON
Comments
A/D switched off.
A/D using CPU clock.
Allows the RC oscillator to stabilize.
A/D using RC oscillator clock.
When the internal RC oscillator is being used as the conversion clock,
the following limitations apply.
1. Due to the frequency tolerance of the RC oscillator and its
asynchronism with regard to the MCU bus clock, the conversion
complete flag (COCO) must be used to determine when a
conversion sequence has been completed.
2. The conversion process runs at the nominal 1.5MHz rate but the
conversion results must be transferred to the MCU result registers
synchronously with the MCU bus clock in order that conversion
time is limited to a maximum of one channel per bus clock cycle.
3. If the system clock is running faster than the RC oscillator, the RC
oscillator should be switched off and the system clock used as the
conversion clock.
ADON — A/D converter on
The ADON bit allows the user to enable/disable the A/D converter.
1 = A/D converter is switched on.
0 = A/D converter is switched off.
When the A/D converter is switched on, it takes a time tADON for the
current sources to stabilize (see Table 23). During this time A/D
conversion results may be inaccurate.
Power-on or external reset will clear the ADON bit, thus disabling the
A/D converter.
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CH2–CH0 — A/D channel selection
The CH2–CH0 bits allow the user to determine which channel of the
A/D converter multiplexer is selected (see Table 10).
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Table 10 A/D channel assignment
CH2
0
0
0
0
1
1
1
1
CH1
0
0
1
1
0
0
1
1
CH0
0
1
0
1
0
1
0
1
Channel
0
1
2
3
4
5
6
7
Signal
AD0/PG0
AD1/PG1
AD2/PG2
AD3/PG3
VRH
(VRH+VRL)/2
VRL
Factory test
A/D result data
register (ADDATA)
Address bit 7
A/D data (ADDATA)
bit 6
bit 5
bit 4
bit 3
bit 2
$0010
bit 1
bit 0
State
on reset
Undefined
ADDATA is a read-only register which is used to store the result of an
A/D conversion. The result is loaded into the register from the SAR and
the conversion complete flag (COCO) in the ADSTAT register is set.
NOTE:
Performing a digital read of port G with levels other than VDD or VSS on
the pins will result in greater power dissipation during the read cycles.
A/D converter during WAIT mode
The A/D converter continues to operate normally during WAIT mode. To
decrease power consumption during WAIT, it is recommended that both
the ADON and ADRC bits in the ADSTAT register are cleared, if the A/D
converter is not being used. If the A/D converter is being used and the
system clock frequency is above 1MHz, the ADRC bit should be cleared
to disable the internal RC oscillator.
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A/D converter during STOP mode
A/D converter during STOP mode
In STOP mode the comparator and charge pump are turned off and the
A/D converter ceases to operate. Any pending conversion is aborted.
A/D analog input
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The external analog voltage value to be processed by the A/D converter
is sampled on an internal capacitor through a resistive path, provided by
input-selection switches and a sampling aperture time switch, as shown
in Figure 17. Sampling time is limited to 12 bus clock cycles. After
sampling, the analog value is stored on the capacitor and held until the
end of conversion. During this hold time, the analog input is
disconnected from the internal A/D system and the external voltage
source sees a high impedance input.
The equivalent analog input during sampling is an RC low-pass filter with
a minimum resistance of 50 kΩ and a capacitance of at least 10pF. (It
should be noted that these are typical values measured at room
temperature).
Input protection device
Analog
input
pin
(AD0–AD3)
< 2pF
≥ 50kΩ
+ ~20V
– ~0.7V
400 nA
junction
leakage
≥ 10pF
DAC
capacitance
VREFL
The analog switch is closed during the 12 cycle sample time only.
Figure 17 Electrical model of an A/D input pin
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A-to-D Converter
MC68HC05E6 — Rev. 1.0
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Resets and Interrupts
Resets and Interrupts
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Contents
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Nonmaskable software interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . 78
Maskable hardware interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Hardware controlled interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . 83
Resets
The MC68HC05E6 can be reset in four ways: by the initial power-on
reset function, by an active low input to the RESET pin, by a COP
watchdog reset (if the watchdog timer is enabled) and by an opcode
fetch from an illegal address. Any of these resets will cause the program
to go to its starting address, specified by the contents of memory
locations $1FFE and $1FFF, and cause the interrupt mask of the
condition code register to be set.
Power-on reset
A power-on reset occurs when a positive transition is detected on VDD.
The power-on reset function is strictly for power turn-on conditions and
should not be used to detect drops in the power supply voltage. The
power-on circuitry provides a stabilization delay (tPORL) from when the
oscillator becomes active. If the external RESET pin is low at the end of
this delay then the processor remains in the reset state until RESET
goes high. The user must ensure that the voltage on VDD has risen to a
point where the MCU can operate properly by the time tPORL has elapsed.
If there is doubt, the external RESET pin should remain low until the
voltage on VDD has reached the specified minimum operating voltage.
This may be accomplished by connecting an external RC circuit to the
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tVDDR
VDD
VDD threshold (1-2V typical)
tOXOV
OSC1
tPORL
tCYC
Internal
processor clock
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RESET
tRL (or tDOGL )
(Internal power-on reset)
Internal
address bus
1FFE 1FFE 1FFE 1FFE 1FFF
New
PC
1FFE 1FFE 1FFE 1FFE
Reset sequence
Internal
data bus
New
PCH
(External hardware reset)
1FFF
New
PC
New
PCL
Op
code
Reset sequence
New
PCL
Op
code
Program
execution
begins
New
PCH
Program
execution
begins
Figure 18 Reset timing diagram
RESET pin to generate a power-on reset (POR). In this case, the time
constant must be great enough (at least 100ms) to allow the oscillator
circuit to stabilize.
RESET pin
When the oscillator is running in a stable state, the MCU is reset when a
logic zero is applied to the RESET input for a minimum period of 1.5
machine cycles (tCYC). This pin contains an internal Schmitt trigger as
part of its input to improve noise immunity. When the RESET pin goes
high, the MCU will resume operation on the following cycle.
Computer
operating properly
(COP) reset
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence.
NOTE:
COP timeout is prevented by periodically writing a ‘0’ to bit 0 of address
$1FF0.
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Interrupts
If the COP watchdog timer is allowed to timeout, an internal reset is
generated to reset the MCU. Because the internal reset signal is used,
the MCU comes out of a COP reset in the same operating mode it was
in when the COP timeout was generated.
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The COP reset function is enabled or disabled by a mask option on the
MC68HC05E6 or by the COP bit in the LVIOPT register on the
MC68HC705E6 (see Mask options).
Illegal address
reset
NOTE:
When an opcode fetch occurs from an address which is not part of the
RAM ($0080–$00FF), ROM/EPROM ($0800–$1FFF)/($0700–$1FFF)
or EEPROM ($0100–$019F), the device is automatically reset.
No RTS or RTI instruction should be placed at the end of a memory
block, i.e. at address $017F, since this would result in an illegal address
reset.
Interrupts
The MCU can be interrupted by six different sources (five maskable
hardware interrupts and one nonmaskable software interrupt):
•
External signal on the IRQ pin
•
Core timer interrupt
•
Low voltage indication interrupt (LVI)
•
16-bit programmable timer interrupt
•
Keyboard interrupt
•
Software interrupt instruction (SWI)
Interrupts cause the processor to save the register contents on the stack
and to set the interrupt mask (I-bit) to prevent additional interrupts. The
RTI instruction (ReTurn from Interrupt) causes the register contents to
be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the interrupt mask bit (I-bit) will be cleared
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providing the corresponding enable bit stored on the stack is zero, i.e.
the interrupt is disabled.
Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is complete. The current instruction is the one already fetched
and being operated on. When the current instruction is complete, the
processor checks all pending hardware interrupts. If interrupts are not
masked (CCR I-bit clear) and the corresponding interrupt enable bit is
set, the processor proceeds with interrupt processing; otherwise, the
next instruction is fetched and executed.
NOTE:
Interrupt priorities
Power-on or external reset clear all interrupt enable bits thus preventing
interrupts during the reset sequence.
Each potential interrupt source is assigned a priority which means that if
more than one interrupt is pending at the same time, the processor will
service the one with the highest priority first. For example, if both an
external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
Table 11 shows the relative priorities of all the possible interrupt
sources. Figure 19 shows the interrupt processing flow.
Table 11 Interrupt priorities
Source
Register
Flags
Reset
—
—
Software interrupt (SWI)
—
—
External interrupt (IRQ)
—
—
Core timer
CTCSR
CTOF, RTIF
Low voltage interrupt
LVIOPT
LVIINT
16-bit timer
TSR
ICF, OCF, TOF
Keyboard interrupt
KEY/TIM
KSF
MC68HC05E6 — Rev. 1.0
Vector address
$1FFE, $1FFF
$1FFC, $1FFD
$1FFA, $1FFB
$1FF8, $1FF9
$1FF6–$1FF7
$1FF4, $1FF5
$1FF2, $1FF3
Priority
highest
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Resets and Interrupts
Interrupts
Reset
Yes
Is I-bit set?
No
Yes
IRQ?
Clear IRQ request
latch
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No
Core timer?
Yes
Stack
PC, X, A, CC
Yes
Set I-bit
No
LVI?
No
Load PC from:
SWI:
$1FFC-$1FFD
IRQ:
$1FFA-$1FFB
Core timer: $1FF8-$1FF9
LVI:
$1FF6-$1FF7
Timer:
$1FF4-$1FF5
Keyboard: $1FF2-$1FF3
Yes
16-bit timer?
No
Yes
Keyboard?
No
Fetch next
instruction
SWINo
instruction?
Yes
No
RTI
instruction?
Yes
Restore registers from
stack:
CC, A, X, PC
No
Execute instruction
Figure 19 Interrupt flow chart
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Nonmaskable software interrupt (SWI)
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The software interrupt (SWI) is an executable instruction and a
nonmaskable interrupt: it is executed regardless of the state of the I-bit
in the CCR. If the I-bit is zero (interrupts enabled), SWI is executed after
interrupts that were pending when the SWI was fetched, but before
interrupts generated after the SWI was fetched. The SWI interrupt
service routine address is specified by the contents of memory locations
$1FFC and $1FFD.
Maskable hardware interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts
(internal and external) are masked. Clearing the I-bit allows interrupt
processing to occur.
NOTE:
The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I-bit is cleared.
External interrupt
(IRQ)
This external interrupt source will vector to the start address contained
in memory locations $1FFA and $1FFB. IRQ can be selected to be either
edge sensitive or edge-and-level sensitive (see Mask options) by the
IRQ bit in the LVIOPT register.
Core timer
interrupts
There are two core timer interrupt flags that cause an interrupt whenever
an interrupt is enabled and its flag becomes set (RTIF and CTOF). The
interrupt flags and enable bits are located in the core timer control and
status register (CTCSR). These interrupts vector to the same interrupt
service routine, whose start address is contained in memory locations
$1FF8 and $1FF9. Full details of the core timer can be found in Core
Timer.
To make use of the real time interrupt, the RTIE bit must first be set. The
RTIF bit will then be set after the specified number of counts.
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Resets and Interrupts
Maskable hardware interrupts
To make use of the core timer overflow interrupt, the CTOFE bit must
first be set. The CTOF bit will then be set when the core timer counter
register overflows from $FF to $00.
Low voltage
indicator interrupt
The low voltage indicator on the MC68HC05E6 can be configured to
respond to a drop in supply voltage in two different ways: it can be
serviced by the user software or it can be set up to automatically
generate a system interrupt.
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In both cases, the power supply could be connected to a low voltage
detection circuit which is in turn connected to the LVI pin of the device.
This allows the voltage from the power supply to be monitored and, if the
voltage being supplied to the device falls below a useful operating
voltage, the LVI pin will be driven low and the LVIVAL bit in the
LVI/options register (LVIOPT) will be cleared.
It is at this point that the user can decide which way the system should
respond. The first method is one in which the user program continually
checks the LVIVAL bit for a ‘0’, at which point it enters a particular routine
whereby all useful information is saved and the device enters a
predefined operating state, e.g. WAIT or STOP mode.
The second method is one whereby a ‘0’ in the LVIVAL bit of LVIOPT
automatically generates a system interrupt, provided LVIE is set. The
occurrence of a valid LVI interrupt can be detected by reading the
LVIINT bit of the LVI/options register. The LVI interrupt has a dedicated
vector at $1FF6–$1FF7.
NOTE:
The interrupt service routine must reset the interrupt by writing a ‘1’ to
the LVIRST bit in LVIOPT.
The main feature of these methods of LVI handling is that the user can
shut down the micro and the application in an orderly manner before the
voltage drops below a useful operating voltage.
If the CPU performs a power-on reset due to a supply voltage below the
power-on trip level, no interrupt will be performed and the CPU start-up
will be delayed until LVI becomes high (see Figure 20).
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VDD
Internal POR
LVI input
CPU reset sequence
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Figure 20 LVI power-on sequence
Alternatively, during power-down, when the power to VDD has fallen below
a useful operating level, the LVI interrupt will not be generated until the LVI
input pin has been driven low (see Figure 21).
VDD
LVI input
LVI interrupt routine (if enabled)
Interrupt handling and shutdown sequence
Figure 21 LVI power-down sequence
Having dropped to a level which drives the LVI pin low, while staying
above the data retention level, the power supply then rises again to the
normal operating range along with a low to high transition of LVI, an
interrupt will be generated to wake-up the CPU. The system clock is
restarted if it was halted using the STOP instruction (see Figure 22).
NOTE:
All interrupts which should not wake-up the CPU should be disabled
prior to entering the low power mode.
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Resets and Interrupts
Maskable hardware interrupts
VDD
LVI input
LVI interrupt routine
Start-up sequence
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Figure 22 LVI recovery sequence
NOTE:
The LVI pin can be used as an additional one bit input by testing the
LVIVAL bit in the LVIOPT register. It can also be used as a falling and
rising edge sensitive interrupt input. The only restrictions which apply are
that the pin must be held high during power-on.
LVI/options
register
Address bit 7
LVI/options (LVIOPT)
bit 6
bit 5
bit 4
bit 3
bit 2
$000F LVIINT LVIVAL LVIRST LVIE
State
on reset
bit 1
bit 0
COP
IRQ 0u00 0u00
LVIINT — LVI interrupt flag
1 = A valid LVI interrupt has been generated.
0 = No valid LVI interrupt has been generated.
This flag bit is cleared by writing a ‘1’ to the LVIRST bit and by reset.
LVIVAL — LVI pin level
This bit reflects the level on the LVI input pin and is used by the user
to check the voltage being supplied to VDD.
1 = The LVI pin is high; power supply is above a useful operating
level, as determined by voltage detector circuit external to
device.
0 = The LVI pin is low; power supply has fallen below a useful
operating level, as determined by voltage detector circuit
external to device.
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LVIRST — LVI interrupt reset
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This bit is write-only; any read will always return zero. Writing a ‘1’ to
this bit resets the LVI interrupt routine.
LVIE — LVI interrupt enable
1 = LVI interrupts enabled; an interrupt will be generated on each
high to low transition and each low to high transition of the LVI
pin (but not the first low to high transition during, or after a
power-on reset).
0 = LVI interrupts disabled; a high to low transition on the LVI pin
will be handled by the user software.
NOTE:
16-bit timer
interrupts
The bits which are shown shaded in the LVI/options register are
described in Mask options.
There are three different timer interrupt flags (ICF, OCF and TOF) that
will cause a timer interrupt whenever they are set and enabled. These
three interrupt flags are found in the three most significant bits of the
timer status register (TSR) at location $13. ICF, OCF and TOF will vector
to the service routine defined by $1FF4 - $1FF5 as shown in Table 11.
There are three corresponding enable bits (ICIE, OCIE and TOIE) which
are located in the timer control register (TCR) at address $12. Full details
of the programmable timer can be found in Programmable Timer.
Keyboard interrupt
When configured as input pins, port C bits 0–7 provide a wired-OR
keyboard interrupt facility and will generate an interrupt provided the
keyboard interrupt enable bit (KIE) in the keyboard/timer register
(KEY/TIM) is set.When configured as inputs with keyboard interrupt
capability, the pins can also have pull-ups connected to them by
correctly configuring the DDRC and CONFC bits as outlined in Table 5.
The interrupt vector for this interrupt is located at $1FF2, $1FF3. Further
information on the keyboard interrupt facility can be found in Port C.
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Resets and Interrupts
Hardware controlled interrupt sequence
Hardware controlled interrupt sequence
The following three functions, reset, STOP and WAIT, are not in the
strictest sense interrupts. However, they are acted upon in a similar
manner. Flowcharts for STOP and WAIT are shown in STOP and WAIT
flowcharts.
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RESET: A reset condition causes the program to vector to its starting
address, which is contained in memory locations $1FFE (MSB)
and $1FFF (LSB). The I-bit in the condition code register is
also set, to disable interrupts.
STOP:
The STOP instruction places the MCU in its lowest power
consumption mode. In STOP mode, the internal oscillator is
turned off, halting all internal processing including timer (and
COP watchdog timer) operation.
WAIT:
The WAIT instruction places the MCU in a low power
consumption mode, but WAIT mode consumes more power
than STOP mode. All CPU action is suspended, but the core
timer, the 16-bit timer and the A/D converter remain active. An
external, keyboard or LVI interrupt or an interrupt from the core
timer or 16-bit timer, if enabled, will cause the MCU to exit
WAIT mode.
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Resets and Interrupts
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Central Processing Unit
Central Processing Unit
Contents
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Arithmetic/Logic Unit (ALU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Instruction Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
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Introduction
This chapter describes the CPU registers and the HC05 instruction set.
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CPU Registers
Figure 23 shows the five CPU registers. CPU registers are not part of the
memory map.
7
0
A
ACCUMULATOR (A)
7
0
X
15
0
6
0
0
0
0
15
0
0
10
0
1
8
7
INDEX REGISTER (X)
5
0
1
SP
STACK POINTER (SP)
0
PCH
PCL
7
1
1
5
4
1
H
PROGRAM COUNTER (PC)
0
I
N
Z
C
CONDITION CODE REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 23 Programming Model
Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and results of arithmetic and
non-arithmetic operations.
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CPU Registers
BIT 7
BIT 6
BIT 5
BIT 4
RESET:
BIT 3
BIT 2
BIT 1
BIT 0
Unaffected by reset
Figure 24 Accumulator
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Index Register
In the indexed addressing modes, the CPU uses the byte in the index
register to determine the conditional address of the operand.
BIT 7
BIT 6
BIT 5
BIT 4
RESET:
BIT 3
BIT 2
BIT 1
BIT 0
Unaffected by reset
Figure 25 Index Register
The 8-bit index register can also serve as a temporary data storage
location.
Stack Pointer
RESET:
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset or after the reset stack pointer
(RSP) instruction, the stack pointer is preset to $00FF. The address in
the stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
BIT 15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
5
4
3
2
1
BIT 0
1
1
1
1
1
1
Figure 26 Stack Pointer
The ten most significant bits of the stack pointer are permanently fixed
at 000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine uses two stack locations.
An interrupt uses five locations.
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Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched. The two most significant bits
of the program counter are ignored internally.
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Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
RESET:
BIT 15
14
–
–
–
–
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
Loaded with vector from $3FFE AND $3FFF
Figure 27 Program Counter
Condition Code
Register
RESET:
The condition code register is an 8-bit register whose three most
significant bits are permanently fixed at 111. The condition code register
contains the interrupt mask and four flags that indicate the results of the
instruction just executed. The following paragraphs describe the
functions of the condition code register.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
1
1
1
H
I
N
C
Z
1
1
1
U
1
U
U
U
Figure 28 Condition Code Register
Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3 and
4 of the accumulator during an ADD or ADC operation. The half-carry
flag is required for binary-coded decimal (BCD) arithmetic operations.
Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic zero, the CPU saves the CPU
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Arithmetic/Logic Unit (ALU)
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask is
set, the interrupt request is latched. Normally, the CPU processes the
latched interrupt as soon as the interrupt mask is cleared again.
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A return from interrupt (RTI) instruction pulls the CPU registers from the
stack, restoring the interrupt mask to its cleared state. After any reset,
the interrupt mask is set and can be cleared only by a software
instruction.
Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result.
Zero Flag
The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00.
Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logical operations defined by the
instruction set.
The binary arithmetic circuits decode instructions and set up the ALU for
the selected operation. Most binary arithmetic is based on the addition
algorithm, carrying out subtraction as negative addition. Multiplication is
not performed as a discrete operation but as a chain of addition and shift
operations within the ALU. The multiply instruction (MUL) requires 11
internal clock cycles to complete this chain of operations.
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Instruction Set Overview
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The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
Inherent
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
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Central Processing Unit
Addressing Modes
Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
Indexed, 8-Bit
Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
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k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
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Indexed,16-Bit
Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
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Instruction Types
Instruction Types
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The MCU instructions fall into the following five categories:
Register/Memory
Instructions
•
Register/Memory Instructions
•
Read-Modify-Write Instructions
•
Jump/Branch Instructions
•
Bit Manipulation Instructions
•
Control Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 12 Register/Memory Instructions
Instruction
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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Read-Modify-Writ
e Instructions
NOTE:
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
Do not use read-modify-write operations on write-only registers.
Table 13 Read-Modify-Write Instructions
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Instruction
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence because it does not write a replacement value.
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Instruction Types
Jump/Branch
Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
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The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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Table 14 Jump and Branch Instructions
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Instruction
Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
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Instruction Types
Bit Manipulation
Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 15 Bit Manipulation Instructions
Instruction
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Bit Clear
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
Bit Set
Control
Instructions
Mnemonic
BSET
These instructions act on CPU registers and control CPU operation
during program execution.
Table 16 Control Instructions
Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
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Instruction Set Summary
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕◊ — ↕◊ ↕◊ ↕◊
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
↕◊ — ↕◊ ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
— — ↕◊ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
— — ↕◊ ↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
A ← (A) ∧ (M)
Logical AND
Arithmetic Shift Left (Same as LSL)
C
0
b7
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right
BCC rel
Branch if Carry Bit Clear
↕
b0
C
b7
— — ↕◊ ↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
REL
ff
5
3
3
6
5
5
3
3
6
5
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
Mn ← 0
— — — — —
ff
Cycles
Description
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Effect on
CCR
Address
Mode
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Source
Form
Operand
Table 17 Instruction Set Summary
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
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Instruction Set Summary
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H I N Z C
Operand
Cycles
Operation
Opcode
Source
Form
Address
Mode
Table 17 Instruction Set Summary (Continued)
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
Description
Effect on
CCR
BHS rel
Branch if Higher or Same
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
(A) ∧ (M)
— — ↕◊ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
REL
23
rr
3
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
— — — — —
REL
2C
rr
3
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕◊
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ◊↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
C←0
— — — — 0
INH
98
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
REL
2
MC68HC05E6 — Rev. 1.0
15-cpu
Central Processing Unit
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CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
I←0
Clear Interrupt Mask
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Unconditional Jump
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
Increment Byte
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
MC68HC05E6 — Rev. 1.0
H I N Z C
— 0 — — —
INH
9A
— — 0 1 —
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
— — ↕◊ ◊↕ ◊↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
— — ↕◊ ↕◊ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
— — ↕◊ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
— — ↕◊ ↕◊ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
— — ↕◊ ↕
— — ↕◊ ↕◊
— — — — —
Cycles
Description
Opcode
CLI
Operation
Effect on
CCR
Address
Mode
Source
Form
Operand
Table 17 Instruction Set Summary (Continued)
2
dd
ff
dd
ff
dd
ff
dd
ff
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
16-cpu
Central Processing Unit
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Central Processing Unit
Instruction Set Summary
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
A ← (M)
Load Accumulator with Memory Byte
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
C
0
b7
Logical Shift Right
MUL
Unsigned Multiply
— — ↕◊ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
— — ↕◊ ↕◊ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
— — ↕◊ ↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
C
b7
0 — — — 0
INH
42
— — ↕◊ ↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
NOP
No Operation
— — — — —
INH
9D
— — ↕◊ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA ii
2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff
4
FA
3
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
— — ↕◊ ↕
DIR
INH
INH
IX1
IX
39
49
59
69
79
Rotate Byte Left through Carry Bit
C
b7
— — 0 ↕
↕
b0
X : A ← (X) × (A)
Negate Byte (Two’s Complement)
↕
b0
↕
↕
ff
ff
Cycles
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
b0
0
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
— — — — —
DIR
EXT
IX2
IX1
IX
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Description
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Effect on
CCR
Address
Mode
Source
Form
Operand
Table 17 Instruction Set Summary (Continued)
5
3
3
6
5
5
3
3
6
5
11
dd
ff
5
3
3
6
5
2
dd
ff
5
3
3
6
5
MC68HC05E6 — Rev. 1.0
17-cpu
Central Processing Unit
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Central Processing Unit
Opcode
Operand
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕◊ ↕
↕
INH
80
9
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
81
6
— — ◊↕ ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Freescale Semiconductor, Inc...
Source
Form
Operation
Effect on
CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
RTS
C
b7
— — ↕◊ ↕
↕
b0
↕
↕
ff
Cycles
Address
Mode
Table 17 Instruction Set Summary (Continued)
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ↕◊ ↕ —
DIR
EXT
IX2
IX1
IX
B7 dd 4
C7 hh ll 5
D7 ee ff 6
E7 ff
5
F7
4
— 0 — — —
INH
8E
— — ↕◊ ↕ —
DIR
EXT
IX2
IX1
IX
BF dd 4
CF hh ll 5
DF ee ff 6
EF ff
5
FF
4
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
10
INH
97
2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Store Index Register In Memory
Subtract Memory Byte from Accumulator
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
A ← (A) – (M) – (C)
M ← (A)
M ← (X)
A ← (A) – (M)
X ← (A)
MC68HC05E6 — Rev. 1.0
↕
— — — — —
2
18-cpu
Central Processing Unit
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Freescale Semiconductor, Inc.
Central Processing Unit
Instruction Set Summary
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
— — — — —
INH
9F
2
0
— — —
◊
INH
8F
2
Effect on
CCR
H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
WAIT
Stop CPU Clock and Enable Interrupts
A Accumulatoropr
C Carry/borrow flagPC
CCRCondition code registerPCH
ddDirect address of operandPCL
dd rrDirect address of operand and relative offset of branch instructionREL
DIRDirect addressing moderel
ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingrr
EXTExtended addressing modeSP
ff Offset byte in indexed, 8-bit offset addressingX
H Half-carry flagZ
hh llHigh and low bytes of operand address in extended addressing#
I Interrupt mask∧
ii Immediate operand byte∨
IMMImmediate addressing mode⊕
INHInherent addressing mode( )
IXIndexed, no offset addressing mode–( )
IX1Indexed, 8-bit offset addressing mode←
IX2Indexed, 16-bit offset addressing mode?
MMemory location:
N Negative flag↕
n Any bit—
(M) – $00
A ← (X)
— — ↕
—
↕ —
ff
Cycles
Description
Operand
Operation
Opcode
Freescale Semiconductor, Inc...
Source
Form
Address
Mode
Table 17 Instruction Set Summary (Continued)
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
MC68HC05E6 — Rev. 1.0
19-cpu
Central Processing Unit
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Central Processing Unit
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F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
DIR
2
REL
Branch
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
INH = InherentREL = Relative
IMM = ImmediateIX = Indexed, No Offset
DIR = DirectIX1 = Indexed, 8-Bit Offset
EXT = ExtendedIX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
A
IMM
MSB
0
LSB
0
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
D
IX2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
C
EXT
Register/Memory
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
9
2
STOP
INH
2
2
TXA
WAIT
INH 1
INH
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
5
5
3
5
3
3
6
5
BRSET0
BRA
BSET0
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BRN
BCLR0
1
3
DIR 2
DIR 2
REL
5
11
5
3
MUL
BSET1
BHI
BRSET1
REL
3
1
DIR 2
INH
DIR 2
5
5
3
5
3
3
6
5
BRCLR1
BLS
BCLR1
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BCC
BSET2
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BNE
BSET3
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BEQ
BCLR3
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BHCC
BSET4
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BHCS
BCLR4
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BPL
BSET5
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BMI
BCLR5
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BMC
BSET6
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BMS
BCLR6
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BIL
BSET7
3
1
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR7
BIH
BCLR7
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
0
DIR
Bit Manipulation
Table 18 Opcode Map
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
Central Processing Unit
20-cpu
Freescale Semiconductor, Inc.
Electrical Specifications
Electrical Specifications
Freescale Semiconductor, Inc...
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Thermal characteristics and power considerations . . . . . . . . . . . . . . 107
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
A/D converter electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 114
Introduction
This section contains the electrical specifications and associated timing
information for the MC68HC05E6 and target data for the
MC68HC705E6.
NOTE:
Information given cannot be guaranteed. All values are design targets
only and may change before the MC68HC705E6 is qualified.
MC68HC05E6 — Rev. 1.0
1-elec
Electrical Specifications
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Electrical SpeciÞcations
Maximum ratings
Table 19 Maximum ratings
Freescale Semiconductor, Inc...
Rating
Symbol
Value
Unit
Supply voltage(1)
VDD
– 0.3 to +7.0
V
Input voltage:
VIN
VSS – 0.3 to
VDD + 0.3
V
Input voltage:
Bootloader mode (VPP – MC68HC705E6)
VIN
VSS – 0.3 to
2VDD + 0.3
V
TL to TH
0 to 70
–40 to +85
–40 to +105
–40 to +125
°C
TL to TH
0 to 70
–40 to +85
–40 to +105
–40 to +125
°C
TSTG
– 65 to +150
°C
ID
25
mA
Operating temperature range (VDD = 5V±10%)
MC68HC05E6 / MC68HC705E6
MC68HC05EC / MC68HC705E6C
MC68HC05EV / MC68HC705E6V
MC68HC05EM / MC68HC705E6M
Operating temperature range (VDD = 3.3V±10%)
MC68HC05E6 / MC68HC705E6
MC68HC05EC / MC68HC705E6C
MC68HC05EV / MC68HC705E6V
MC68HC05EM / MC68HC705E6M
Storage temperature range
Current drain per pin (excluding VDD and VSS)(2)
TA
TA
1. All voltages are with respect to VSS.
2. Maximum current drain per pin is for one pin at a time, limited by an external resistor.
NOTE:
This device contains circuitry designed to protect against damage due to
high electrostatic voltages or electric fields. However, it is recommended
that normal precautions be taken to avoid the application of any voltages
higher than those given in the maximum ratings table to this high
impedance circuit. For maximum reliability all unused inputs should be
tied to either VSS or VDD.
MC68HC05E6 — Rev. 1.0
2-elec
Electrical Specifications
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Electrical Specifications
Thermal characteristics and power considerations
Thermal characteristics and power considerations
Table 20 Package thermal characteristics
Characteristics
Thermal resistance
– Plastic 44 pin QFP package
– Plastic 28 pin SOIC package
Symbol
Value
Unit
θJA
θJA
60
60
°C/W
°C/W
Freescale Semiconductor, Inc...
The average chip junction temperature, TJ, in degrees Celcius can be
obtained from the following equation:
T J = T A + ( P D • θ JA )
[1]
where:
TA = Ambient temperature (°C)
θJA = Package thermal resistance, junction-to-ambient (°C/W)
PD = PINT + PI/O (W)
PINT = Internal chip power = IDD • VDD (W)
PI/O = Power dissipation on input and output pins (user determined)
An approximate relationship between PD and TJ (if PI/O is neglected) is:
K
P D = --------------------T J + 273
[2]
Solving equations [1] and [2] for K gives:
K = P D • ( T A + 273 ) + θ JA • P D2
[3]
where K is a constant for a particular part. K can be determined by
measuring PD (at equilibrium) for a known TA. Using this value of K, the
values of PD and TJ can be obtained for any value of TA by solving the
above equations. The package thermal characteristics are shown in
Table 20.
VDD = 4.5 V
R2
Pins
PA0–7, PB0–7, PC0–7, PD0–7, PG0–3
R1
R2
C
3.26kΩ
2.38kΩ
50pF
Test
point
C
R1
Figure 29 Equivalent test load
MC68HC05E6 — Rev. 1.0
3-elec
Electrical Specifications
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Electrical SpeciÞcations
DC electrical characteristics
Table 21 DC electrical characteristics for 5V operation
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage(3) (ILOAD = – 10 µA)
PA0–7, PB0–7, PC0–7, PD0–7
VOH
VDD – 0.1
—
—
V
Output low voltage(3) (ILOAD = +10 µA)
PA0–7, PB0–7, PC0–7, PD0–7
VOL
—
—
0.1
V
Output high voltage (ILOAD = – 0.8 mA)
PA0–7, PB0–7, PC0–7, PD0–7
VOH
VDD – 0.8
VDD – 0.4
—
V
Output low voltage (ILOAD = +1.6 mA)
PA0–7, PB0–7, PC0–7, PD0–7
VOL
—
0.1
0.4
V
Input high voltage
PA0–7, PB0–5, PC0–7, PD0–7,
PG0–3, OSC1, IRQ, RESET, LVI
VIH
0.7VDD
—
VDD
V
Input low voltage
PA0–7, PB0–5, PC0–7, PD0–7,
PG0–3, OSC1, IRQ, RESET, LVI
VIL
VSS
—
0.2VDD
V
Pull-up source current (VIN = 0.2 VDD)
PA0–7, PC0–7, PD0–7 (if enabled),
IPU
30
75
180
µA
Pull-down sink current (VIN = 0.7 VDD)
PB0–7
IPD
30
50
180
µA
—
—
3.5
1.0
6
2
mA
mA
—
—
—
1.0
1.0
1.0
8
20
45
µA
µA
µA
IOZ
—
0.2
1.0
µA
COUT
—
—
12
pF
VPP
IPP
16
—
4
16.5
—
—
17
20
10
V
mA
ms
Supply current(4)
RUN
WAIT
STOP (oscillators off)
–40 to +85°C
–40 to +105°C
–40 to +125°C
IDD
I/O ports high-Z leakage current
PC0–7, PD0–7, IRQ, RESET, LVI
Capacitance(3)
Ports (as input or output)
MC68HC705E6 EPROM
Programming voltage
Programming current
Programming time
tPROG
MC68HC05E6 — Rev. 1.0
4-elec
Electrical Specifications
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Electrical Specifications
DC electrical characteristics
1. All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see VDD and VSS).
2. Typical values are at mid point of voltage range and at 25°C only.
3. Characteristic guaranteed by design, but not tested.
Freescale Semiconductor, Inc...
4. RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2 MHz); all inputs 0.2V from rail; no
DC loads; maximum load on outputs 50pF (except OSC2 load 20pF).
WAIT IDD: only the timer system active; current varies linearly with the OSC2 capacitance.
WAIT and STOP IDD: all ports configured as inputs; VIL = 0.2V and VIH = VDD – 0.2V.
STOP IDD: measured with OSC1 = VDD.
MC68HC05E6 — Rev. 1.0
5-elec
Electrical Specifications
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Electrical SpeciÞcations
Table 22 DC electrical characteristics for 3.3V operation
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Output high voltage(3) (ILOAD = – 10 µA)
PA0–7, PB0–7, PC0–7, PD0–7
VOH
VDD – 0.1
—
—
V
Output low voltage(3) (ILOAD = +10 µA)
PA0–7, PB0–7, PC0–7, PD0–7
VOL
—
—
0.1
V
Output high voltage (ILOAD = – 0.4 mA)
PA0–7, PB0–7, PC0–7, PD0–7
VOH
VDD – 0.8
—
—
V
Output low voltage (ILOAD = +0.8 mA)
PA0–7, PB0–7, PC0–7, PD0–7
VOL
—
–
0.4
V
Input high voltage
PA0–7, PB0–5, PC0–7, PD0–7,
PG0–3, OSC1, IRQ, RESET, LVI
VIH
0.7VDD
—
VDD
V
Input low voltage
PA0–7, PB0–5, PC0–7, PD0–7,
PG0–3, OSC1, IRQ, RESET, LVI
VIL
VSS
—
0.2VDD
V
Pull-up source current (VIN = 0.2 VDD)
PA0–7, PC0–7, PD0–7 (if enabled),
IPU
5
30
70
µA
Pull-down sink current (VIN = 0.7 VDD)
PB0–7
IPD
5
15
70
µA
—
—
1.5
1.0
2.5
1.8
mA
mA
—
—
—
1.0
1.0
1.0
6.0
15
25
µA
µA
µA
IOZ
—
0.2
1.0
µA
COUT
—
—
12
pF
Supply current(4)
RUN (at 2.1 MHz bus frequency)
WAIT (at 2.1 MHz bus frequency)
STOP (oscillators off)
–40 to +85°C
–40 to +105°C
–40 to +125°C
I/O ports high-Z leakage current
PC0–7, PD0–7, IRQ, RESET, LVI
Capacitance(3)
Ports (as input or output)
IDD
1. All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs (see VDD and VSS).
2. Typical values are at mid point of voltage range and at 25°C only.
3. Characteristic guaranteed by design, but not tested.
4. RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.1 MHz); all inputs 0.2V from rail; no
DC loads; maximum load on outputs 50pF (except OSC2 load 20pF).
WAIT IDD: only the timer system active; current varies linearly with the OSC2 capacitance.
WAIT and STOP IDD: all ports configured as inputs; VIL = 0.2V and VIH = VDD – 0.2V.
STOP IDD: measured with OSC1 = VDD.
MC68HC05E6 — Rev. 1.0
6-elec
Electrical Specifications
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Electrical Specifications
AC electrical characteristics
AC electrical characteristics
Table 23 AC electrical characteristics for 5V operation
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal
External clock
fOSC
fOSC
—
dc
4.2
4.2
MHz
MHz
Internal operating frequency
Crystal (fOSC /2)
External clock (fOSC /2)
fOP
fOP
—
dc
2.1
2.1
MHz
MHz
Processor cycle time
tCYC
480
—
ns
Ceramic resonator start-up time
tOCOV
—
10
ms
Ceramic resonator STOP recovery start-up time
tICCH
—
10
ms
OSC1 pulse width
tOH, tOL
90
—
ns
RESET pulse width
tRL
1.5
—
tCYC
EEPROM byte erase time
tEBYT
—
10
ms
EEPROM block erase time
tEBLOCK
—
100
ms
EEPROM bulk erase time
tEBULK
—
200
ms
EEPROM byte program time
tEEPGM
—
10
ms
tFPV
—
10
µs
RC oscillator stabilization (EEPROM, A/D)(1)
tADRC
—
5
µs
A/D current stabilization time
tADON
—
100
µs
16-bit timer
Resolution(2)
Input capture pulse width
Input capture pulse period
tRESL
tTLTH
tTLTL
4
250
—
—
—
tCYC
ns
tCYC
tPORL
4064
4064
tCYC
tILIH
250
—
ns
tILIL
(4)
—
tCYC
EEPROM programming voltage fall time
Power-on reset delay
Interrupt pulse width low (edge-triggered)
Interrupt pulse period (see Figure 30)
(3)
1. For bus frequencies less than 1MHz, the internal RC oscillator should be used when programming the EEPROM.
2. Since the 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the
timer resolution.
3. The minimum period tTLTL should not be less than the number of cycles it takes to execute the capture interrupt service
routine plus 24 tCYC.
4. The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine
plus 21 tCYC.
MC68HC05E6 — Rev. 1.0
7-elec
Electrical Specifications
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Electrical SpeciÞcations
Table 24 AC electrical characteristics for 3.3V operation
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal
External clock
fOSC
fOSC
—
dc
2.1
2.1
MHz
MHz
Internal operating frequency
Crystal (fOSC /2)
External clock (fOSC /2)
fOP
fOP
—
dc
1.05
1.05
MHz
MHz
Processor cycle time
tCYC
1000
—
ns
Ceramic resonator start-up time
tOCOV
—
20
ms
Ceramic resonator STOP recovery start-up time
tICCH
—
20
ms
OSC1 pulse width
tOH, tOL
200
—
ns
RESET pulse width
tRL
1.5
—
tCYC
EEPROM byte erase time
tEBYT
—
20
ms
EEPROM block erase time
tEBLOCK
—
100
ms
EEPROM bulk erase time
tEBULK
—
200
ms
EEPROM byte program time
tEEPGM
—
20
ms
tFPV
—
10
µs
RC oscillator stabilization (EEPROM, A/D)(1)
tADRC
—
5
µs
A/D current stabilization time
tADON
—
100
µs
16-bit timer
Resolution(2)
Input capture pulse width
Input capture pulse period
tRESL
tTLTH
tTLTL
4
500
—
—
—
tCYC
ns
tCYC
tPORL
4064
4064
tCYC
tILIH
250
—
ns
tILIL
(4)
—
tCYC
EEPROM programming voltage fall time
Power-on reset delay
Interrupt pulse width low (edge-triggered)
Interrupt pulse period (see Figure 30)
(3)
1. For bus frequencies less than 1MHz, the internal RC oscillator should be used when programming the EEPROM.
2. Since the 2-bit prescaler in the timer must count four external cycles (tCYC), this is the limiting factor in determining the
timer resolution.
3. The minimum period tTLTL should not be less than the number of cycles it takes to execute the capture interrupt service
routine plus 24 tCYC.
4. The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus
21 tCYC.
MC68HC05E6 — Rev. 1.0
8-elec
Electrical Specifications
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Electrical Specifications
AC electrical characteristics
IRQ
tILIH
tILIL
Edge-sensitive trigger — The minimum tILIH is either 125ns (VDD =5V) or 250ns (VDD =3.3V). The minimum period tILIL
should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 tCYC.
Edge and level sensitive trigger — If IRQ remains low after the initial interrupt is serviced, the MCU recognises the
interrupt until the IRQ line returns to a high level.
Freescale Semiconductor, Inc...
Figure 30 External interrupt timing
MC68HC05E6 — Rev. 1.0
9-elec
Electrical Specifications
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Electrical SpeciÞcations
A/D converter electrical characteristics
Table 25 A/D converter electrical characteristics for 5V operation
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Freescale Semiconductor, Inc...
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by A/D converter
8
—
Bits
Non-linearity
Maximum deviation from best straight line through
the A/D transfer characteristics
(VRH = VDD and VRL = 0V)
—
±0.5
LSB
Quantization error
Uncertainty due to converter resolution
—
±0.5
LSB
Absolute accuracy
Difference between the actual input voltage and the
full-scale equivalent of the binary output code for all
errors
—
±1.5
LSB
Conversion range
Analog input voltage range
VRL
VRH
V
VRH
Maximum analog reference voltage
VRL
VDD + 0.1
V
Conversion time
Total time to perform a single analog to digital
conversion
Bus clock
Internal RC oscillator
—
—
32
32
tCYC
µs
Monotonicity
Conversion result never decreases with an increase
in input voltage and has no missing codes
Zero input reading
Conversion result when VIN = VRL
$00
—
Hex
Full scale reading
Conversion result when VIN = VRH
—
$FF
Hex
Sample acquisition
time(1)
Analog input acquisition sample time
Bus clock
Internal RC oscillator
—
—
12
12
tcyc
µs
Sample/hold
capacitance
Input capacitance during sample ADIN
—
12
pF
Input leakage(2)
Input leakage on A/D pins ADIN and VREFH
—
1
µA
Guaranteed
1. Source impedances greater than 10 kΩ will adversely affect internal RC charging time during input sampling.
2. The external system error caused by input leakage current is approximately equal to the product of RSOURCE and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 17).
MC68HC05E6 — Rev. 1.0
10-elec
Electrical Specifications
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Electrical Specifications
A/D converter electrical characteristics
Table 26 A/D converter electrical characteristics for 3.3V operation
(VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH)
Freescale Semiconductor, Inc...
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by A/D converter
8
—
Bits
Non-linearity
Maximum deviation from best straight line through
the A/D transfer characteristics
(VRH = VDD and VRL = 0V)
—
±0.5
LSB
Quantization error
Uncertainty due to converter resolution
—
±0.5
LSB
Absolute accuracy
Difference between the actual input voltage and the
full-scale equivalent of the binary output code for all
errors
—
±1.5
LSB
Conversion range
Analog input voltage range
VRL
VRH
V
VRH
Maximum analog reference voltage
VRL
VDD + 0.1
V
Conversion time
Total time to perform a single analog to digital
conversion
Bus clock
Internal RC oscillator
—
—
32
32
tCYC
µs
Monotonicity
Conversion result never decreases with an increase
in input voltage and has no missing codes
Zero input reading
Conversion result when VIN = VRL
$00
—
Hex
Full scale reading
Conversion result when VIN = VRH
—
$FF
Hex
Sample acquisition
time(1)
Analog input acquisition sample time
Bus clock
Internal RC oscillator
—
—
12
12
tCYC
µs
Sample/hold
capacitance
Input capacitance during sample ADIN
—
12
pF
Input leakage(2)
Input leakage on A/D pins ADIN and VRH
—
1
µA
Guaranteed
1. Source impedances greater than 10 kΩ will adversely affect internal RC charging time during input sampling.
2. The external system error caused by input leakage current is approximately equal to the product of RSOURCE and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 17).
MC68HC05E6 — Rev. 1.0
11-elec
Electrical Specifications
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Electrical SpeciÞcations
MC68HC05E6 — Rev. 1.0
12-elec
Electrical Specifications
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Mechanical Data
Mechanical Data
Contents
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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Introduction
Both the MC68HC05E6 and the MC68HC705E6 are available in a
28-pin SOIC package and a 44-pin QFP package. The pinout diagrams
and associated mechanical drawings are illustrated in this chapter.
MC68HC05E6 — Rev. 1.0
1-mech
Mechanical Data
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Mechanical Data
IRQ/VPP
1
28
VSS
RESET
2
27
VDD
OSC1
3
26
PA0
OSC2
4
25
PA1
LVI
5
24
PA2
PG0/AD0
6
23
PA3
VREFH
7
22
PA4
PB4
8
21
PA5
PB3
9
20
PA6
PB2
10
19
PA7
PB1
11
18
PC0/TCAP
PB0
12
17
PC1/TCMP
PC5
13
16
PC2
PC4
14
15
PC3
44
43
42
41
40
39
38
37
36
35
34
LVI
PB7
OSC2
OSC1
RESET
IRQ/VPP
VSS
VDD
PA0
PD0
PA1
Figure 31 28-pin SOIC pinout
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
PA2
PD1
PA3
PD2
PA4
PD3
PA5
PD4
PA6
PD5
PA7
PB0
PC7
PC6
PC5
PC4
PC3
PD7
PC2
PC1
PD6
PC0
12
13
14
15
16
17
18
19
20
21
22
PB6
PG0/AD0
PG1/AD1
PG2/AD2
PG3/AD3
VREFH
PB5
PB4
PB3
PB2
PB1
Figure 32 44-pin QFP pinout
MC68HC05E6 — Rev. 1.0
2-mech
Mechanical Data
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Mechanical Data
Introduction
–A–
–B–
Freescale Semiconductor, Inc...
Case 751F-03
P
0.25
M B M
14 PL
1
R x 45°
G
J
C
0.25
Dim.
A
B
C
D
F
G
Min.
Max.
17.80 18.05
7.40
7.60
2.35
2.65
0.35
0.49
0.41
0.90
1.27 BSC
M
Seating
plane
K
D 28 PL
–T–
M
F
T B S
A S
Notes
Dim. Min.
J
0.229
1.Dimensions ‘A’ and ‘B’ are datums and ‘T’ is a datum surface. K
0.127
2.Dimensioning and tolerancing per ANSI Y14.5M, 1982.
M
0°
3.All dimensions in mm.
P
10.05
4.Dimensions ‘A’ and ‘B’ do not include mould protrusion.
R
0.25
5.Maximum mould protrusion is 0.15 mm per side.
—
—
Max.
0.317
0.292
8°
10.55
0.75
—
Figure 33 28-pin SOIC mechanical dimensions
MC68HC05E6 — Rev. 1.0
3-mech
Mechanical Data
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Mechanical Data
Case No. 824A-01
44 lead QFP
L
B
P
22
-A-
-B-
L
B
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Detail “A”
44
12
1
V
- A, B, D -
0.20 M H A – B S D S
23
0.05 A – B
33
34
0.20 M C A – B S D S
B
Detail “A”
F
N
J
11
-D-
Base
metal
D
A
0.20 M C A – B S D S
Section B–B
0.05 A – B
0.20 M C A – B S D S
S
0.20 M H A – B S D S
U
T
Detail “C”
M
E
Q
C
-CSeating
plane
R
Datum
-H- plane
H
G
M
K
W
X
Dim.
A
B
C
D
E
F
G
H
J
K
Min. Max.
9.90 10.10
9.90 10.10
2.10
2.45
0.30
0.45
2.00
2.10
0.30
0.40
0.80 BSC
—
0.250
0.130 0.230
0.65
0.95
L
8.00 REF
Notes
Dim. Min. Max.
1.Datum plane –H– is located at bottom of lead and is coincident
M
5°
10°
with the lead where the lead exits the plastic body at the bottom of N
0.130 0.170
the parting line.
Q
0°
7°
2.Datums A–B and –D to be determined at datum plane –H–.
R
0.13
0.30
3.Dimensions S and V to be determined at seating plane –C–.
S
12.95
13.45
4.Dimensions A and B do not include mould protrusion. Allowable
T
0.13
—
mould protrusion is 0.25mm per side. Dimensions A and B do
include mould mismatch and are determined at datum plane –H–. U
0°
—
5.Dimension D does not include dambar protrusion. Allowable
V
12.95 13.45
dambar protrusion shall be 0.08 total in excess of the D dimension W
0.40
—
at maximum material condition. Dambar cannot be located on the
X
1.6 REF
lower radius or the foot.
6.Dimensions and tolerancing per ANSI Y 14.5M, 1982.
7.All dimensions in mm.
Figure 34 44-pin QFP mechanical dimensions
MC68HC05E6 — Rev. 1.0
4-mech
Mechanical Data
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Ordering Information
Ordering Information
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Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
EPROMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Verification media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Introduction
This section describes the information needed to order the
MC68HC05E6 or MC68HC705E6.
To initiate a ROM pattern for the MCU, it is necessary to contact your
local field service office, local sales person or Motorola representative.
Please note that you will need to supply details such as mask option
selections, temperature range, oscillator frequency, package type,
electrical test requirements and device marking details so that an order
can be processed, and a customer specific part number allocated. Refer
to Table 27 for appropriate part numbers.
NOTE:
When making a decision about packaging for the MC68HC05E6 or
MC68HC705E6, it is important to remember that not all pins are bonded
out in the 28-pin package and therefore some of the I/O ports of the
device are not available to the user. Modes of Operation and Pin
Descriptions shows the pin-out diagrams for each package option.
MC68HC05E6 — Rev. 1.0
1-ord
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Table 27 MC order numbers
Device title
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MC68HC05E6
MC68HC705E6
Package type
Temperature
Part number
28-pin plastic SOIC
0 to +70°C
MC68HC05E6DW
44-pin QFP
0 to +70°C
MC68HC05E6FB
28-pin plastic SOIC
–40 to +85°C
MC68HC05E6CDW
44-pin QFP
–40 to +85°C
MC68HC05E6CFB
28-pin plastic SOIC
–40 to +105°C
MC68HC05E6VDW
44-pin QFP
–40 to +105°C
MC68HC05E6VFB
28-pin plastic SOIC
–40 to +125°C
MC68HC05E6MDW
44-pin QFP
–40 to +125°C
MC68HC05E6MFB
28-pin plastic SOIC
0 to +70°C
MC68HC705E6DW
44-pin QFP
0 to +70°C
MC68HC705E6FB
28-pin plastic SOIC
–40 to +85°C
MC68HC705E6CDW
44-pin QFP
–40 to +85°C
MC68HC705E6CFB
28-pin plastic SOIC
–40 to +105°C
MC68HC705E6VDW
44-pin QFP
–40 to +105°C
MC68HC705E6VFB
28-pin plastic SOIC
–40 to +125°C
MC68HC705E6MDW
44-pin QFP
–40 to +125°C
MC68HC705E6MFB
MC68HC05E6 — Rev. 1.0
2-ord
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EPROMS
EPROMS
An 8K byte EPROM programmed with the customer’s software (positive
logic for address and data) should be submitted for pattern generation.
All unused bytes should be programmed to $00.
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The EPROM should be clearly labelled, placed in a conductive IC carrier
and securely packed.
Verification media
All original pattern media (EPROMs) are filed for contractual purposes
and are not returned. A computer listing of the ROM code will be
generated and returned with a listing verification form. The listing should
be thoroughly checked and the verification form completed, signed and
returned to Motorola. The signed verification form constitutes the
contractual agreement for creation of the custom mask. If desired,
Motorola will program blank EPROMs (supplied by the customer) from
the data file used to create the custom mask, to aid in the verification
process.
MC68HC05E6 — Rev. 1.0
3-ord
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Ordering Information
MC68HC05E6 — Rev. 1.0
4-ord
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Glossary
Glossary
$xxxx — The digits following the’$’ are in hexadecimal format.
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%xxxx — The digits following the ’%’ are in binary format.
A — See “accumulator (A).”
accumulator (A) — An 8-bit general-purpose register in the CPU08. The CPU08 uses the
accumulator to hold operands and results of arithmetic and logic operations.
acquisition mode — A mode of PLL operation during startup before the PLL locks on a
frequency. Also see "tracking mode."
A/D, ADC — Analog-to-digital (converter).
address bus — The set of wires that the CPU or DMA uses to read and write memory locations.
addressing mode — The way that the CPU determines the operand address for an instruction.
The M68HC08 CPU has 16 addressing modes.
ALU — See “arithmetic logic unit (ALU).”
arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform
arithmetic, logic, and manipulation operations on operands.
asynchronous — Refers to logic circuits and operations that are not synchronized by a common
reference signal.
baud rate — The total number of bits transmitted per unit of time.
BCD — See “binary-coded decimal (BCD).”
binary — Relating to the base 2 number system.
binary number system — The base 2 number system, having two digits, 0 and 1. Binary
arithmetic is convenient in digital circuit design because digital circuits have two
permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to
correspond to the two digital voltage levels.
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binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10
decimal digits and that retains the same positional structure of a decimal number. For
example,
234 (decimal) = 0010 0011 0100 (BCD)
bit — A binary digit. A bit has a value of either logic 0 or logic 1.
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Bootstrap mode — In this mode the device automatically loadsits internal memory from an
external source on reset and then allows this program to be executed.
branch instruction — An instruction that causes the CPU to continue processing at a memory
location other than the next sequential address.
break module — A module in the M68HC08 Family. The break module allows software to halt
program execution at a programmable point in order to enter a background routine.
breakpoint — A number written into the break address registers of the break module. When a
number appears on the internal address bus that is the same as the number in the break
address registers, the CPU executes the software interrupt instruction (SWI).
break interrupt — A software interrupt caused by the appearance on the internal address bus
of the same value that is written in the break address registers.
bus — A set of wires that transfers logic signals.
bus clock — The bus clock is derived from the CGMOUT output from the CGM. The bus clock
frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by
four.
byte — A set of eight bits.
C — The carry/borrow bit in the condition code register. The CPU08 sets the carry/borrow bit
when an addition operation produces a carry out of bit 7 of the accumulator or when a
subtraction operation requires a borrow. Some logical operations and data manipulation
instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and
shifts and rotates).
CCR — See “condition code register.”
central processor unit (CPU) — The primary functioning unit of any computer system. The
CPU controls the execution of instructions.
CERQUAD — A ceramic package type, principally used for EPROM and high temperature
devices.
CGM — See “clock generator module (CGM).”
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Glossary
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Glossary
clear — To change a bit from logic 1 to logic 0; the opposite of set.
clock — A square wave signal used to synchronize events in a computer.
clock generator module (CGM) — A module in the M68HC08 Family. The CGM generates a
base clock signal from which the system clocks are derived. The CGM may include a
crystal oscillator circuit and or phase-locked loop (PLL) circuit.
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comparator — A device that compares the magnitude of two inputs. A digital comparator defines
the equality or relative differences between two binary numbers.
computer operating properly module (COP) — A counter module in the M68HC08 Family that
resets the MCU if allowed to overflow.
condition code register (CCR) — An 8-bit register in the CPU08 that contains the interrupt
mask bit and five bits that indicate the results of the instruction just executed.
control bit — One bit of a register manipulated by software to control the operation of the
module.
control unit — One of two major units of the CPU. The control unit contains logic functions that
synchronize the machine and direct various operations. The control unit decodes
instructions and generates the internal control signals that perform the requested
operations. The outputs of the control unit drive the execution unit, which contains the
arithmetic logic unit (ALU), CPU registers, and bus interface.
COP — See "computer operating properly module (COP)."
counter clock — The input clock to the TIM counter. This clock is the output of the TIM
prescaler.
CPU — See “central processor unit (CPU).”
CPU08 — The central processor unit of the M68HC08 Family.
CPU clock — The CPU clock is derived from the CGMOUT output from the CGM. The CPU
clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by
four.
CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing
a crystal oscillator source by two or more so the high and low times will be equal. The
length of time required to execute an instruction is measured in CPU clock cycles.
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CPU registers — Memory locations that are wired directly into the CPU logic instead of being
part of the addressable memory map. The CPU always has direct access to the
information in these registers. The CPU registers in an M68HC08 are:
•
A (8-bit accumulator)
•
H:X (16-bit index register)
•
SP (16-bit stack pointer)
•
PC (16-bit program counter)
•
CCR (condition code register containing the V, H, I, N, Z, and C bits)
CSIC — customer-specified integrated circuit
cycle time — The period of the operating frequency: tCYC = 1/fOP.
decimal number system — Base 10 numbering system that uses the digits zero through nine.
direct memory access module (DMA) — A M68HC08 Family module that can perform data
transfers between any two CPU-addressable locations without CPU intervention. For
transmitting or receiving blocks of data to or from peripherals, DMA transfers are faster
and more code-efficient than CPU interrupts.
DMA — See "direct memory access module (DMA)."
DMA service request — A signal from a peripheral to the DMA module that enables the DMA
module to transfer data.
duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is
usually represented by a percentage.
EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of
memory that can be electrically reprogrammed.
EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can
be erased by exposure to an ultraviolet light source and then reprogrammed.
exception — An event such as an interrupt or a reset that stops the sequential execution of the
instructions in the main program.
external interrupt module (IRQ) — A module in the M68HC08 Family with both dedicated
external interrupt pins and port pins that can be enabled as interrupt pins.
fetch — To copy data from a memory location into the accumulator.
firmware — Instructions and data programmed into nonvolatile memory.
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Glossary
free-running counter — A device that counts from zero to a predetermined number, then rolls
over to zero and begins counting again.
full-duplex transmission — Communication on a channel in which data can be sent and
received simultaneously.
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H — The upper byte of the 16-bit index register (H:X) in the CPU08.
H — The half-carry bit in the condition code register of the CPU08. This bit indicates a carry from
the low-order four bits of the accumulator value to the high-order four bits. The half-carry
bit is required for binary-coded decimal arithmetic operations. The decimal adjust
accumulator (DAA) instruction uses the state of the H and C bits to determine the
appropriate correction factor.
hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A
through F.
high byte — The most significant eight bits of a word.
illegal address — An address not within the memory map
illegal opcode — A nonexistent opcode.
I — The interrupt mask bit in the condition code register of the CPU08. When I is set, all interrupts
are disabled.
index register (H:X) — A 16-bit register in the CPU08. The upper byte of H:X is called H. The
lower byte is called X. In the indexed addressing modes, the CPU uses the contents of
H:X to determine the effective address of the operand. H:X can also serve as a temporary
data storage location.
input/output (I/O) — Input/output interfaces between a computer system and the external world.
A CPU reads an input to sense the level of an external signal and writes to an output to
change the level on an external signal.
instructions — Operations that a CPU can perform. Instructions are expressed by programmers
as assembly language mnemonics. A CPU interprets an opcode and its associated
operand(s) and instruction.
interrupt — A temporary break in the sequential execution of a program to respond to signals
from peripheral devices by executing a subroutine.
interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to
execute a subroutine.
I/O — See “input/output (I/0).”
IRQ — See "external interrupt module (IRQ)."
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Glossary
jitter — Short-term signal instability.
latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power
is applied to the circuit.
latency — The time lag between instruction completion and data movement.
least significant bit (LSB) — The rightmost digit of a binary number.
logic 1 — A voltage level approximately equal to the input power voltage (VDD).
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logic 0 — A voltage level approximately equal to the ground voltage (VSS).
low byte — The least significant eight bits of a word.
low voltage inhibit module (LVI) — A module in the M68HC08 Family that monitors power
supply voltage.
LVI — See "low voltage inhibit module (LVI)."
M68HC08 — A Motorola family of 8-bit MCUs.
mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.
mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used
in integrated circuit fabrication to transfer an image onto silicon.
mask option — A optional microcontroller feature that the customer chooses to enable or
disable.
mask option register (MOR) — An EPROM location containing bits that enable or disable
certain MCU features.
MCU — Microcontroller unit. See “microcontroller.”
memory location — Each M68HC08 memory location holds one byte of data and has a unique
address. To store information in a memory location, the CPU places the address of the
location on the address bus, the data information on the data bus, and asserts the write
signal. To read information from a memory location, the CPU places the address of the
location on the address bus and asserts the read signal. In response to the read signal,
the selected memory location places its data onto the data bus.
memory map — A pictorial representation of all memory locations in a computer system.
microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,
memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.
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Glossary
modulo counter — A counter that can be programmed to count to any number from zero to its
maximum possible modulus.
monitor ROM — A section of ROM that can execute commands from a host computer for testing
purposes.
MOR — See "mask option register (MOR)."
most significant bit (MSB) — The leftmost digit of a binary number.
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multiplexer — A device that can select one of a number of inputs and pass the logic level of that
input on to the output.
N — The negative bit in the condition code register of the CPU08. The CPU sets the negative bit
when an arithmetic operation, logical operation, or data manipulation produces a negative
result.
nibble — A set of four bits (half of a byte).
object code — The output from an assembler or compiler that is itself executable machine code,
or is suitable for processing to produce executable machine code.
opcode — A binary code that instructs the CPU to perform an operation.
open-drain — An output that has no pullup transistor. An external pullup device can be
connected to the power supply to provide the logic 1 output voltage.
operand — Data on which an operation is performed. Usually a statement consists of an
operator and an operand. For example, the operator may be an add instruction, and the
operand may be the quantity to be added.
oscillator — A circuit that produces a constant frequency square wave that is used by the
computer as a timing and sequencing reference.
OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that
cannot be reprogrammed.
overflow — A quantity that is too large to be contained in one byte or one word.
page zero — The first 256 bytes of memory (addresses $0000–$00FF).
parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.
In a system that uses odd parity, every byte is expected to have an odd number of logic
1s. In an even parity system, every byte should have an even number of logic 1s. In the
transmitter, a parity generator appends an extra bit to each byte to make the number of
logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts
the number of logic 1s in each byte. The parity checker generates an error signal if it finds
a byte with an incorrect number of logic 1s.
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Glossary
PC — See “program counter (PC).”
peripheral — A circuit not under direct CPU control.
phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is
synchronized to a reference signal.
PLL — See "phase-locked loop (PLL)."
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pointer — Pointer register. An index register is sometimes called a pointer register because its
contents are used in the calculation of the address of an operand, and therefore points to
the operand.
polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different
voltage levels, VDD and VSS.
polling — Periodically reading a status bit to monitor the condition of a peripheral device.
port — A set of wires for communicating with off-chip devices.
prescaler — A circuit that generates an output signal related to the input signal by a fractional
scale factor such as 1/2, 1/8, 1/10 etc.
program — A set of computer instructions that cause a computer to perform a desired operation
or operations.
program counter (PC) — A 16-bit register in the CPU08. The PC register holds the address of
the next instruction or operand that the CPU will use.
pull — An instruction that copies into the accumulator the contents of a stack RAM location. The
stack RAM address is in the stack pointer.
pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage
of the power supply.
pulse-width — The amount of time a signal is on as opposed to being in its off state.
pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a
signal with a constant frequency.
push — An instruction that copies the contents of the accumulator to the stack RAM. The stack
RAM address is in the stack pointer.
PWM period — The time required for one complete cycle of a PWM waveform.
RAM — Random access memory. All RAM locations can be read or written by the CPU. The
contents of a RAM memory location remain valid until the CPU writes a different value or
until power is turned off.
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RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.
read — To copy the contents of a memory location to the accumulator.
register — A circuit that stores a group of bits.
reserved memory location — A memory location that is used only in special factory test modes.
Writing to a reserved location has no effect. Reading a reserved location returns an
unpredictable value.
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reset — To force a device to a known condition.
ROM — Read-only memory. A type of memory that can be read but cannot be changed (written).
The contents of ROM must be specified before manufacturing the MCU.
SCI — See "serial communication interface module (SCI)."
serial — Pertaining to sequential transmission over a single line.
serial communications interface module (SCI) — A module in the M68HC08 Family that
supports asynchronous communication.
serial peripheral interface module (SPI) — A module in the M68HC08 Family that supports
synchronous communication.
set — To change a bit from logic 0 to logic 1; opposite of clear.
shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to
them and that can shift the logic levels to the right or left through adjacent circuits in the
chain.
signed — A binary number notation that accommodates both positive and negative numbers.
The most significant bit is used to indicate whether the number is positive or negative,
normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the
magnitude of the number.
software — Instructions and data that control the operation of a microcontroller.
software interrupt (SWI) — An instruction that causes an interrupt and its associated vector
fetch.
SPI — See "serial peripheral interface module (SPI)."
stack — A portion of RAM reserved for storage of CPU register contents and subroutine return
addresses.
stack pointer (SP) — A 16-bit register in the CPU08 containing the address of the next available
storage location on the stack.
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start bit — A bit that signals the beginning of an asynchronous serial transmission.
status bit — A register bit that indicates the condition of a device.
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stop bit — A bit that signals the end of an asynchronous serial transmission.
subroutine — A sequence of instructions to be used more than once in the course of a program.
The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each
place in the main program where the subroutine instructions are needed, a jump or branch
to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the
flow of the main program to execute the instructions in the subroutine. When the RTS
instruction is executed, the CPU returns to the main program where it left off.
synchronous — Refers to logic circuits and operations that are synchronized by a common
reference signal.
TIM — See "timer interface module (TIM)."
timer interface module (TIM) — A module used to relate events in a system to a point in time.
timer — A module used to relate events in a system to a point in time.
toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.
tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a
frequency. Also see "acquisition mode."
two’s complement — A means of performing binary subtraction using addition techniques. The
most significant bit of a two’s complement number indicates the sign of the number (1
indicates negative). The two’s complement negative of a number is obtained by inverting
each bit in the number and then adding 1 to the result.
unbuffered — Utilizes only one register for data; new data overwrites current data.
unimplemented memory location — A memory location that is not used. Writing to an
unimplemented location has no effect. Reading an unimplemented location returns an
unpredictable value. Executing an opcode at an unimplemented location causes an illegal
address reset.
V —The overflow bit in the condition code register of the CPU08. The CPU08 sets the V bit when
a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE,
and BLT use the overflow bit.
variable — A value that changes during the course of program execution.
VCO — See "voltage-controlled oscillator."
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vector — A memory location that contains the address of the beginning of a subroutine written
to service an interrupt or reset.
voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a
frequency that is controlled by a dc voltage applied to a control input.
waveform — A graphical representation in which the amplitude of a wave is plotted against time.
wired-OR — Connection of circuit outputs so that if any output is high, the connection point is
high.
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word — A set of two bytes (16 bits).
write — The transfer of a byte of data from the CPU to a memory location.
X — The lower byte of the index register (H:X) in the CPU08.
Z — The zero bit in the condition code register of the CPU08. The CPU08 sets the zero bit when
an arithmetic operation, logical operation, or data manipulation produces a result of $00.
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